SGM48520 [SGMICRO]
5V, 6A/4A, Low-Side GaN and MOSFET Driver with 1ns Pulse Width;
| 型号： | SGM48520 |
| 厂家： | 
Shengbang Microelectronics Co, Ltd |
| 描述： | 5V, 6A/4A, Low-Side GaN and MOSFET Driver with 1ns Pulse Width |
| 文件： | 总17页 (文件大小：791K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SGM48520
5V, 6A/4A, Low-Side GaN and
MOSFET Driver with 1ns Pulse Width
GENERAL DESCRIPTION
FEATURES
The high-speed, single-channel low-side driver
SGM48520 is designed to drive GaN FETs and logic
level MOSFETs. Application areas include LiDAR, time
of flight, facial recognition, and power converters using
low-side drivers. The SGM48520 provides 6A source
and 4A sink output current capability. Split output
configuration allows individual turn-on and turn-off time
optimization depending on FET. Package and pinout
with minimum parasitic inductances reduce the rise and
fall time and limit the ringing. Additionally, the 2.3ns
propagation delay with minimized tolerances and
variations allows efficient operation at high frequencies.
● 5V Supply Voltage
● 6A Peak Source and 4A Peak Sink Currents
● Ultra-Fast, Low-side Gate Driver for GaN and Si
FETs
● Minimum Input Pulse Width: 1ns
● Up to 60MHz Operation
● Propagation Delay: 2.3ns (TYP)
● Rise Time: 550ps (TYP)
● Fall Time: 480ps (TYP)
● Protection Features:
Under-Voltage Lockout (UVLO)
Over-Temperature Protection (OTP)
● Available in Green WLCSP-0.88×1.28-6B and
TDFN-2×2-6AL Packages
The driver has internal under-voltage lockout and
over-temperature protection against overload and fault
events.
APPLICATIONS
The SGM48520 is available in Green WLCSP-0.88×
1.28-6B and TDFN-2×2-6AL packages.
Laser Distance Measuring System
5G RF Communication System
Wireless Charging System
GaN DC/DC Conversion System
TYPICAL APPLICATION
VBUS
R1
5V
VDD
IN+
IN-
OUTH
SGM48520
GaN
R2
PWM
nEN
OUTL
GND
Figure 1. Typical Application Circuit
SG Micro Corp
www.sg-micro.com
DECEMBER 2022 – REV. A
5V, 6A/4A, Low-Side GaN and
SGM48520
MOSFET Driver with 1ns Pulse Width
PACKAGE/ORDERING INFORMATION
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESCRIPTION
ORDERING
NUMBER
PACKAGE
MARKING
PACKING
OPTION
MODEL
XXX
MBY
WLCSP-0.88×1.28-6B
TDFN-2×2-6AL
SGM48520XG/TR
SGM48520XTDI6G/TR
Tape and Reel, 3000
Tape and Reel, 3000
-40℃ to +125℃
-40℃ to +125℃
SGM48520
G3M
XXXX
MARKING INFORMATION
NOTE: XXX = Date Code and Trace Code. XXXX = Date Code and Trace Code.
WLCSP-0.88×1.28-6B TDFN-2×2-6AL
Date Code - Year
Serial Number
Y Y Y
X X X X
Trace Code
Trace Code
Date Code - Year
X X X
Y Y Y
Serial Number
Green (RoHS & HSF): SG Micro Corp defines "Green" to mean Pb-Free (RoHS compatible) and free of halogen substances. If
you have additional comments or questions, please contact your SGMICRO representative directly.
OVERSTRESS CAUTION
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed in Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods
may affect reliability. Functional operation of the device at any
conditions beyond those indicated in the Recommended
Operating Conditions section is not implied.
Supply Voltage, VDD......................................................5.75V
IN+, IN- Pin Voltage, VINx ................................ -0.3V to 5.75V
OUTH Pin Voltage, VOUTH ........................-0.3V to VDD + 0.3V
OUTL Pin Voltage, VOUTL ................................ -0.3V to 5.75V
Package Thermal Resistance
WLCSP-0.88×1.28-6B, θJA ...................................... 133℃/W
TDFN-2×2-6AL, θJA.................................................... 63℃/W
Junction Temperature.................................................+150℃
Storage Temperature Range.......................-65℃ to +150℃
Lead Temperature (Soldering, 10s)............................+260℃
ESD Susceptibility
ESD SENSITIVITY CAUTION
This integrated circuit can be damaged if ESD protections are
not considered carefully. SGMICRO recommends that all
integrated circuits be handled with appropriate precautions.
Failureto observe proper handlingand installation procedures
can cause damage. ESD damage can range from subtle
performance degradation tocomplete device failure. Precision
integrated circuits may be more susceptible to damage
because even small parametric changes could cause the
device not to meet the published specifications.
HBM.............................................................................4000V
CDM ............................................................................1500V
RECOMMENDED OPERATING CONDITIONS
Supply Voltage, VDD........................................4.75V to 5.25V
IN+, IN- Pin Voltage, VINx .....................................0V to 5.25V
Operating Junction Temperature Range......-40℃ to +125℃
DISCLAIMER
SG Micro Corp reserves the right to make any change in
circuit design, or specifications without prior notice.
SG Micro Corp
www.sg-micro.com
DECEMBER 2022
2
5V, 6A/4A, Low-Side GaN and
SGM48520
MOSFET Driver with 1ns Pulse Width
PIN CONFIGURATIONS
(TOP VIEW)
(TOP VIEW)
1
2
IN+
GND
VDD
IN-
1
2
3
6
5
4
VDD
OUTH
A
B
C
GND
OUTL
OUTH
GND
IN+
OUTL
IN-
WLCSP-0.88×1.28-6B
TDFN-2×2-6AL
FUNCTION
PIN DESCRIPTION
PIN
NAME
I/O
WLCSP-0.88×1.28-6B TDFN-2×2-6AL
Input Voltage Supply. Bypass to GND with a low inductance
ceramic capacitor.
A1
A2
B1
B2
C1
C2
—
3
VDD
OUTH
GND
OUTL
IN+
I
O
—
O
I
Pull-Up Gate Drive Output. Connect it to the gate of the target
transistor with an optional resistor.
4
2
Ground.
Pull-Down Gate Drive Output. Connect it to the gate of the target
transistor with an optional resistor.
5
1
Non-Inverting Logic Input.
Inverting Logic Input.
6
IN-
I
Exposed Pad. It is internally connected to GND through substrate.
Connect this pad to large copper area, generally a ground plane.
Exposed Pad
GND
—
NOTE: I: input, O: output.
FUNCTION TABLE
IN- Pin
IN+ Pin
OUTH Pin
Open
H
OUTL Pin
L
L
L
H
L
L
Open
L
H
H
Open
Open
H
L
SG Micro Corp
DECEMBER 2022
www.sg-micro.com
3
5V, 6A/4A, Low-Side GaN and
SGM48520
MOSFET Driver with 1ns Pulse Width
ELECTRICAL CHARACTERISTICS
(VDD = 5V, TJ = +25℃, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC Characteristics
VDD Quiescent Current
VDD Operating Current
IVDDQ
VIN+ = VIN- = 0V
75
µA
fSW = 30MHz, no load
34
52
IVDD_OP
mA
fSW = 30MHz, 100pF load
Under-Voltage Lockout
VDD_UVLO VDD rising
3.92
4.15
78
4.33
V
mV
℃
UVLO Hysteresis
ΔVDD_UVLO
TOTP
Over-Temperature Shutdown, Rising Edge Threshold
Over-Temperature Hysteresis
Input DC Characteristics
175
26
ΔTOTP
℃
VDD = 4.75V to 5.25V,
IN+, IN- High Threshold
IN+, IN- Low Threshold
IN+, IN- Hysteresis
VIH
VIL
1.7
1.1
0.4
2.6
1.8
1
V
V
V
TJ = -40℃ to +125℃
VDD = 4.75V to 5.25V,
TJ = -40℃ to +125℃
VDD = 4.75V to 5.25V,
TJ = -40℃ to +125℃
VHYS
Positive Input Pull-Down Resistance
Negative Input Pull-Up Resistance
Input Pin Capacitance
Output DC Characteristics
OUTL Voltage
RIN+
RIN-
CIN
To GND
To VDD
To GND
100
100
200
200
5
250
250
kΩ
kΩ
pF
VOL
IOUTL = 100mA, VIN+ = VIN- = 0V
45
52
mV
mV
A
OUTH Voltage
VDD - VOH IOUTH = 100mA, VIN+ = 3V, VIN- = 0V
Peak Source Current
IOH
IOL
VOUTH = 0V, VIN+ = 3V, VIN- = 0V
VOUTL = 5V, VIN+ = VIN- = 0V
6
4
Peak Sink Current
A
SWITCHING CHARACTERISTICS
(VDD = 5V, TJ = +25℃, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
IN- = GND, IN+ = VDD,
VDD rising to 4.4V to OUTH rising
Startup Time, VDD Rising above UVLO
tSTART
50
78
µs
IN- = GND, IN+ = VDD,
VDD falling below 3.9V to OUTH falling
ULVO Falling
tSHUTOFF
0.7
2.5
3.5
µs
Turn-on Propagation Delay
Turn-off Propagation Delay
tPDR
tPDF
VIN- = 0V, IN+ to OUTH, 100pF load
VIN- = 0V, IN+ to OUTL, 100pF load
2.1
2.3
200
660
550
680
480
1
ns
ns
ps
ps
ps
ps
ps
ns
Pulse Positive Distrortion (tPDF - tPDR
)
ΔtPD
TDFN-2×2-6AL
Output Rise Time
tRISE
0Ω series 100pF load (1)
WLCSP-0.88×1.28-6B
TDFN-2×2-6AL
Output Fall Time
tFALL
tMIN
0Ω series 100pF load (1)
0Ω series 100pF load (1)
WLCSP-0.88×1.28-6B
Minimum Input Pulse Width
NOTE:
1. Rise and fall are calculated as a 20% to 80%.
SG Micro Corp
www.sg-micro.com
DECEMBER 2022
4
5V, 6A/4A, Low-Side GaN and
SGM48520
MOSFET Driver with 1ns Pulse Width
TYPICAL PERFORMANCE CHARACTERISTICS
VDD Operating Current vs. Temperature
Quiescent Current vs. Temperature
VDD = 5V
55
54
53
52
51
50
65
60
55
50
45
40
VDD = 5V, fSW = 30MHz,
2Ω in Series 100pF Load
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (℃)
Temperature (℃)
Propagation Delay vs. Temperature
VDD = 5V, 100pF Load,
Propagation Delay vs. Temperature
VDD = 5V, 100pF Load,
2.5
2.4
2.3
2.2
2.1
2.0
1.9
2.5
2.4
2.3
2.2
2.1
2.0
1.9
TDFN-2×2-6AL Package
WLCSP-0.88×1.28-6B Package
tPDF
tPDR
tPDF
tPDR
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (℃)
Temperature (℃)
Rise and Fall Time vs. Temperature
VDD = 5V, 100pF Load,
Rise and Fall Time vs. Temperature
VDD = 5V, 100pF Load,
800
750
700
650
600
550
700
650
600
550
500
450
400
TDFN-2×2-6AL Package
WLCSP-0.88×1.28-6B Package
tFALL
tRISE
tFALL
tRISE
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (℃)
Temperature (℃)
SG Micro Corp
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DECEMBER 2022
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5V, 6A/4A, Low-Side GaN and
SGM48520
MOSFET Driver with 1ns Pulse Width
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VDD Operating Current vs. Frequency
100
VDD = 5V, 2Ω in Series 100pF Load
80
T = +125℃
60
40
20
0
T = +85℃
T = +25℃
T = 0℃
T = -40℃
20
0
10
30
40
50
60
Frequency (MHz)
SG Micro Corp
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DECEMBER 2022
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5V, 6A/4A, Low-Side GaN and
SGM48520
MOSFET Driver with 1ns Pulse Width
FUNCTIONAL BLOCK DIAGRAM
SGM48520
VDD
OUTH
Over-Temperature
Protection (OTP)
Under-Voltage
Lockout (UVLO)
IN+
OUTL
200kΩ
VDD
200kΩ
IN-
GND
Figure 2. Functional Block Diagram
SG Micro Corp
www.sg-micro.com
DECEMBER 2022
7
5V, 6A/4A, Low-Side GaN and
SGM48520
MOSFET Driver with 1ns Pulse Width
DETAILED DESCRIPTION
The high-speed, single-channel low-side driver
SGM48520 is designed to drive GaN FETs and logic
level MOSFETs. Application areas include LiDAR, time
of flight, facial recognition, and power converters using
low-side drivers.
as much as possible reduces the stress on the driver
and switch device, which is very important for
high-performance applications and reliability of GaN
FETs. In order to prevent the device CISS from turning
the FET on by mistake, the OUTL pin will be pulled low
in under-voltage conditions.
SGM48520 provides the lowest propagation delay of
2.3ns from the driver to the power transistor.
SGM48520 adopts small WLCSP package with very
small parasitic inductance. This package reduces
ringing and increases current drive capability in high
frequency applications when driving power transistors.
VDD and Under-Voltage Lockout
The rated working voltage of SGM48520 is 5V ± 0.25V,
and the maximum power supply voltage of the part is
5.75V. In the application, the error of the power supply
of the driver chip needs to be ensured within 0.25V, and
the transient overshoot voltage of the power supply
cannot exceed the maximum voltage of the part. In the
VDD Overshoot Solution section, there are more
specific design details.
Input Stage
There are two Schmitt triggers at the input pins IN+ and
IN- to improve noise immunity. In order to prevent the
output from accidentally turning on when the input is in
the floating state, IN+ is internally connected to a
pull-down resistor, and IN- is internally connected to a
pull-up resistor. The output signal depends on the logic
voltage levels on the IN+ and IN- pins (which are not a
differential input pair).
SGM48520 provides under-voltage lockout (UVLO)
function to protect the circuit in the event of a fault
condition. The UVLO trigger point is set at 4.15V, and
the hysteresis voltage is 78mV. This UVLO level
ensures that the GaN FET operates in the low RDSON
region. When UVLO is triggered, the output is low.
Output Stage
Over-Temperature Protection (OTP)
SGM48520 provides 6A peak source and 4A sink
currents, and the outputs are separated to allow
custom pull-up and pull-down drive strength to suit the
application. Each of OUTH and OUTL pins can be
connected to transistor gates with separate drive
resistors, adjusting the driving speed of turning on and
off to control the slew rate and EMI of the driving signal
and the ringing on the gate signal. Controlling ringing
The SGM48520 provides an over-temperature
protection (OTP) function with a trigger point of +175°C.
The hysteresis temperature is 26°C. If the OTP is
triggered, switching action is stopped with OUTL held
low. Then when the junction temperature of the device
falls below +149°C, normal operation resumes.
SG Micro Corp
www.sg-micro.com
DECEMBER 2022
8
5V, 6A/4A, Low-Side GaN and
SGM48520
MOSFET Driver with 1ns Pulse Width
APPLICATION INFORMATION
Since the output of the PWM controller cannot often
provide the voltage required by the gate of the power
device, a high-performance gate driver is usually
required between the PWM output of the controller and
the gate of the GaN transistor, so that the GaN
transistor can operate at correct gate voltages. In
addition, the gate driver can reduce switching losses
and maximize the performance of GaN transistors in
high-frequency applications. Especially in the field of
digital power control, it is common for the PWM signal
of the digital controller to be a 3.3V logic signal, and
GaN transistors cannot work optimally with this gate
voltage. The gate driver boosts the 3.3V signal to the
preferred gate drive voltage of 5V, which fully turns on
the power device and minimizes conduction losses.
resistors. If it is not necessary to adjust the turn-on
and turn-off speeds separately, OUTH and OUTL may
be connected directly together (with a single gate
drive resistor added if necessary).
In order to avoid voltage overstress caused by the
parasitic inductance of the drive circuit, SGMICRO
recommends the use of at least 2Ω resistors at OUTH
and OUTL.
For applications requiring a smaller resistance value,
please contact SGMICRO E2E for guidance.
Design Requirements
There are some key factors to consider when designing
with the SGM48520 gate driver and GaN power FETs,
especially for high MHz frequency (or nanosecond
pulse) applications. These factors include circuit layout,
PCB trace design, passive component selection, and
maximum operating frequency.
The good noise immunity of the SGM48520 gate driver
also minimizes the effects of high frequency switching
noise when the driver is placed near the power switch.
Adding a gate driver also transfers the gate charge
power loss from the controller to the driver, effectively
reducing the power consumption and thermal stress in
the controller.
Detailed Design Procedure
Handling Ground Bounce
Place the ground pin of the SGM48520 as close as
possible to the source of the low-side FET to get the
smallest gate current loop, the smallest parasitic
inductance, and maximize the switching performance.
However, this can cause ground bounce on the
SGM48520, resulting in incorrect switching logic at the
input and wrong level at the output.
SGM48520 is a low-side high-speed gate driver with a
maximum operating frequency of 60MHz and an
operating voltage of 5V. It is optimized to drive GaN
FETs. The output has an independent configuration
architecture, which can flexibly adjust the turn-on and
turn-off speed, while providing a strong current sinking
and sourcing capabilities.
In order to eliminate this effect, SGM48520 has built-in
Schmitt triggers on the input terminals to increase the
input hysteresis. Equation 1 shows the relationship
between the input hysteresis and the maximum
allowable di/dt:
The SGM48520 is primarily used to drive GaN
transistors, which are used in various power converters,
LiDAR, wireless chargers, and synchronous rectifiers.
The SGM48520 can be used as a driver for high-speed
pulsed laser diodes.
di
dt
VHYS
LP
(1)
=
Typical Application
where
LP: Parasitic inductance between source and Ground.
HYS: Hysteresis voltage of the input port.
di/dt: Current slew rate.
A typical application circuit for the SGM48520 is
shown in Figure 1, with a single-channel, 5V drive
voltage, which is specifically designed to drive GaN
transistors or logic-level Si FETs. The output has a
separated structure, so that the turn-on and turn-off
speeds can be controlled separately by driving
V
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5V, 6A/4A, Low-Side GaN and
SGM48520
MOSFET Driver with 1ns Pulse Width
APPLICATION INFORMATION (continued)
Assuming that the parasitic inductance is 0.7nH and
the hysteresis voltage is 0.7V, the maximum allowable
current slew rate is 1A/ns by calculation. If the current
slew rate generated in the application is higher than
1A/ns, this exceeds the hysteresis voltage range and
causes the output signal to be unstable. Using the
inverting input to accept the PWM signal and
connecting the non-inverting input to VDD reduce the
possibility of false pulses or oscillations and improve
stability. High di/dt produces high transient voltage
spikes that affect the input of the SGM48520. In order
to protect the device from a large current spike at IN-, a
100Ω current limiting resistor can be placed before the
IN- input.
the application circuit with current sense resistor shown
in Figure 3, the ground of the SGM48520 is connected
to the source of the GaN FET, and one side of the
current sense resistor is connected to the controller
ground. In the case of high-speed switching and large
current, the potential rebound due to the parasitic
inductance of the current detection resistor will cause
the circuit to turn on/off by mistake, and in severe cases
may cause damage to the device. Figure 5 shows the
solution for this situation: Use a common mode choke
between the controller output and the SGM48520 input.
When the pulse width is not extremely narrow, a
resistor can also be added to the signal output line
before SGM48520 to form an RC filter as a supplement.
Although the circuit of Figure 4 improves the ground
bounce problem by connecting the GND of the driver to
the signal ground after the current sense resistor, this
circuit is not recommended. The drawback of this circuit
is that the voltage drop across the current sense
resistor and its parasitic inductance reduce the
transient and DC gate drive voltage to the FET, thus
reducing the efficiency. In severe cases, the voltage
ringing caused by the inductance of the sense resistor
path can even cause the FET to spuriously turn on and
off. For these reasons, the circuit of Figure 5 is the
preferred solution to ground bounce problems.
If the current slew rate is not too high, and the pulse
width is not very short (for example, 1ns range), the
extra delay can be accepted. The parasitic capacitance
of the SGM48520 input can be used to good advantage
to create an RC filter to reduce high-frequency noise by
adding a resistor in series with the input pin. The
SGM48520 has stable input capacitance of about 5pF
at the input pins, which is convenient for this purpose.
If the environment is more severe, using a common
mode choke coil can increase the stability of the
system.
In applications that use current sensing resistors, the
ground bounce phenomenon is particularly serious. In
R1
R1
OUTH
OUTH
SGM48520
GaN
RS
SGM48520
GaN
RS
R2
R2
OUTL
OUTL
GND
GND
Figure 3. RS Current Sense A Configuration
Figure 4. RS Current Sense B Configuration
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5V, 6A/4A, Low-Side GaN and
SGM48520
MOSFET Driver with 1ns Pulse Width
APPLICATION INFORMATION (continued)
R1
R2
5V
VDD
OUTH
OUTL
GND
RC Filter
SGM48520
GaN
IN+
IN-
RS
Common Mode Choke
Controller
Figure 5. Filtering For Ground Bounce Noise Handling with SGM48520
Creating Nanosecond Pulse with SGM48520
SGM48520 can provide a minimum 1ns pulse width
output to capacitive load. However, outputting such a
small equivalent pulse width requires a very powerful
digital driver and also needs to consider the influence of
parasitic parameters from the digital output to the
SGM48520 input. Using the two inputs of SGM48520
and the AND gate can get a method of generating short
pulses at the output. As shown in Figure 6, connect one
digital signal to IN+, and the other delayed digital signal
to IN-, so that a narrow pulse will appear at the output,
the width of which is equal to the delay time of the two
digital signals. The digital controller only needs to
control the delay time in the range of nanoseconds,
which reduces the requirement for the SGM48520 input
signal. If the digital signal has only one output, an RC
low-pass filter can be used to generate a signal with an
adjustable delay time, which is related to the RC time
constant.
IN+
IN-
OUT
Figure 6. Timing Diagram of Creating Short Pulses
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DECEMBER 2022
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5V, 6A/4A, Low-Side GaN and
SGM48520
MOSFET Driver with 1ns Pulse Width
APPLICATION INFORMATION (continued)
0.5V, the maximum error voltage of the power supply
VDD Overshoot Solution
cannot exceed 5.25V (5% accuracy). Therefore, if the
overshoot voltage is large, a power supply with higher
accuracy is necessary.
Due to the existence of PCB parasitic inductance,
inductance ringing and transient overshoot voltage are
prone to occur under high current switching conditions.
In the PCB design process, it is necessary to evaluate
and control the overshoot caused by the ringing, so as
not to exceed the stress of the device. The strength of
the overshoot voltage and the percentage of the
overshoot duration to the switching time are
parameters that affect the stress. Keeping the
overshoot below maximum allowable pin voltage is the
best solution. The parasitic inductance can be
decreased by optimizing PCB layout. To limit the
voltage overshoot, low ESL components and series
resistance can be helpful as well. If the overshoot is too
large, the accuracy of the power supply needs to be
considered. For example, if the overshoot voltage is
Applications at High Frequencies
SGM48520 has a rise/fall time of 550ps/480ps, and
provides a minimum output capability of 1ns pulse
width and a maximum operating frequency of 60MHz.
According to the capacitive load, different output modes
and frequencies can be selected. Under the working
condition of high-frequency pulse, in order to prevent
the device from overheating, a high-frequency pulse
train with a certain interval time can be used. This can
increase the transient frequency and keep the effective
value of the output current unchanged. At this time, a
larger decoupling capacitor is needed to charge the
capacitive load at a high frequency.
Application Curves
Startup Time
Shutdown Time
VOUT
VDD
VDD
VOUT
Time (5μs/div)
Time (20μs/div)
Input Pulse Width and Propagation Delays
Rise and Fall Time
665ps
1.3ns
625ps
VIN+
VOUT
VIN+
VOUT
VOUT
2.6ns
4ns
Time (2ns/div)
Time (1ns/div)
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5V, 6A/4A, Low-Side GaN and
SGM48520
MOSFET Driver with 1ns Pulse Width
APPLICATION INFORMATION (continued)
the resistor power of a small package to meet the
requirements of gate drive power loss.
Power Supply Recommendations
In order to provide high peak current when the FET is
turned on and improve the stability of the VDD pin
supply voltage, a low ESR/ESL ceramic capacitor
needs to be used as a bypass capacitor placed as
close as possible to the IC's VDD and GND pins. To
avoid ringing at the IC pins as much as possible, the
decoupling capacitors need to be placed on the same
side as the IC, and vias cannot be used.
Drive Loop Inductance and Grounding
SGM48520 should be placed as close to the GaN FET
as possible, and the trace of the gate drive circuit
should be as wide as possible to reduce parasitic
inductance.
To achieve minimum drive loop inductance, it is
recommended to use the second layer of the PCB as
the source loop of the GaN FET, near the bottom of the
device (top layer). Both the vias that are connected to
the GND pin and the source of the FET are connected
to this layer with minimal impedance. Please note that
the coupling of the ground plane will be decreased only
when the GND plane is connected to the source power
plane at the FET.
In order to achieve the best transient performance,
SGMICRO recommends choosing a three-terminal
capacitor and a capacitor with a larger capacitance in
parallel. The three-terminal capacitor needs to be
placed close to the VDD and GND pins of the IC, and
the other capacitor is placed close to the three-terminal
capacitor. The three-terminal capacitor has the lowest
ESL, and the larger capacitor provides enough drive
peak current. Under normal circumstances, it is
recommended to use 0.1µF 0402 or through-core
capacitors in parallel with 1µF 0603 capacitors.
Bypass Capacitor
The VDD pin requires a bypass capacitor connected to
GND, placed as close to the pins of the SGM48520 as
physically possible. The capacitor should be connected
to VDD and GND power planes, which should be large
and as close to the top layer of the PCB as possible.
Due to the high operating frequency of the IC, the
inductance of the bypass capacitor is critical, so the
value of the bypass capacitor should be between 0.1µF
and 1µF, and the material should be X7R or better. The
best capacitors for the application are low inductance
chip capacitors (LICC), interdigital capacitors (IDC),
feedthrough and LGA capacitors. Finally, in order to
meet the demand of driving peak current, an extra 1μF
capacitor between VDD and GND should be added in
parallel close to the IC.
Layout Guidelines
Proper PCB layout is extremely important in a
high-current,
fast-switching
circuit
to
provide
appropriate device operation and design robustness.
SGM48520 provides WLCSP ball grid array package,
which can reduce the parasitic inductance in the
connection line with BGA type GaN FET.
In order to achieve the best performance, a PCB with at
least four routing layers is recommended to minimize
the parasitic inductance. Using resistors and capacitors
in a smaller package (0201) can also minimize
inductance and PCB space. It is necessary to calculate
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (DECEMBER 2022) to REV.A
Page
Changed from product preview to production data.............................................................................................................................................All
SG Micro Corp
www.sg-micro.com
DECEMBER 2022
13
PACKAGE INFORMATION
PACKAGE OUTLINE DIMENSIONS
WLCSP-0.88×1.28-6B
0.22
6 × Φ
D
0.20
A1 CORNER
0.40
E
0.40
TOP VIEW
RECOMMENDED LAND PATTERN (Unit: mm)
2
1
6 × Φd
A
B
C
e
C
A
A1
SEATING PLANE
ccc
C
e
SIDE VIEW
BOTTOM VIEW
Dimensions In Millimeters
Symbol
MIN
MOD
0.580
MAX
A
A1
D
0.535
0.190
0.845
1.245
0.238
0.625
0.230
0.905
1.305
0.278
0.210
0.875
E
1.275
d
0.258
e
0.400 BSC
0.050
ccc
NOTE: This drawing is subject to change without notice.
SG Micro Corp
TX00281.000
www.sg-micro.com
PACKAGE INFORMATION
PACKAGE OUTLINE DIMENSIONS
TDFN-2×2-6AL
D
e
N6
L
D1
E1
E
N3
N1
b
BOTTOM VIEW
TOP VIEW
1.60
0.55
1.00
2.60
A
A1
A2
SIDE VIEW
0.30
0.65
RECOMMENDED LAND PATTERN (Unit: mm)
Dimensions
In Millimeters
Dimensions
In Inches
Symbol
MIN
MAX
0.800
0.050
MIN
MAX
0.031
0.002
A
A1
A2
D
0.700
0.000
0.028
0.000
0.203 REF
0.008 REF
1.900
1.500
1.900
0.900
0.250
2.100
1.700
2.100
1.100
0.350
0.075
0.059
0.075
0.035
0.010
0.083
0.067
0.083
0.043
0.014
D1
E
E1
b
e
0.650 BSC
0.026 BSC
L
0.174
0.326
0.007
0.013
NOTE: This drawing is subject to change without notice.
SG Micro Corp
TX00132.000
www.sg-micro.com
PACKAGE INFORMATION
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
P2
P0
W
Q2
Q4
Q2
Q4
Q2
Q4
Q1
Q3
Q1
Q3
Q1
Q3
B0
Reel Diameter
P1
A0
K0
Reel Width (W1)
DIRECTION OF FEED
NOTE: The picture is only for reference. Please make the object as the standard.
KEY PARAMETER LIST OF TAPE AND REEL
Reel Width
Reel
Diameter
A0
B0
K0
P0
P1
P2
W
Pin1
Package Type
W1
(mm)
(mm) (mm) (mm) (mm) (mm) (mm) (mm) Quadrant
WLCSP-0.88×1.28-6B
TDFN-2×2-6AL
7″
7″
9.5
9.5
0.99
2.30
1.38
2.30
0.69
1.10
4.0
4.0
4.0
4.0
2.0
2.0
8.0
8.0
Q1
Q1
SG Micro Corp
TX10000.000
www.sg-micro.com
PACKAGE INFORMATION
CARTON BOX DIMENSIONS
NOTE: The picture is only for reference. Please make the object as the standard.
KEY PARAMETER LIST OF CARTON BOX
Length
(mm)
Width
(mm)
Height
(mm)
Reel Type
Pizza/Carton
7″ (Option)
7″
368
442
227
410
224
224
8
18
SG Micro Corp
www.sg-micro.com
TX20000.000
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