SGM48524A_技术文档

SGM48523/SGM48524A

SGM48525/SGM48526

Dual 5A, High-Speed, Low-Side Gate Drivers

with Negative Input Voltage Capability

GENERAL DESCRIPTION

FEATURES

The SGM48523/4A/5/6 are dual high-speed low-side

gate drivers for MOSFET and IGBT power switches.

They have rail-to-rail driving capability and can sink and

source up to 5A peak current with capacitive loads. The

propagation delays are very short and well matched

between the two channels that make the device very fit

for applications that need accurate dual gate driving

such as synchronous rectifiers. The matched

propagation delays also allow for paralleling the two

channels when higher driving current is required for

example for paralleled switches. The input voltage

thresholds are fixed, independent of supply voltage

(V_DD) and are compatible with low voltage TTL and

CMOS logic. Noise immunity is excellent due to the

wide hysteresis window between the input low and high

thresholds. The devices have internal pull-up/pull-down

resistors on the input pins to ensure low state on the

driver outputs when the inputs are floating.

● Two Independent Gate Drive Channels

● 4.5V to 18V Single Supply Range (V_DD)

● 5A Peak Source/Sink Pulse Current Drive

● Independent Enable Pin for Each Channel

● TTL and CMOS Compatible Logic Threshold

● Logic Levels Independent of Supply Voltage

● Hysteretic Input Logic for High Noise Immunity

● Outputs are Logic Low when Inputs are Floating

● Negative Voltage Handling Capability:

 -8V DC at Inputs

 -2V, 200ns Pulse for Outputs (OUTx)

● Glitch-Free Operation at Power-Up and Power-

Down: Outputs Pulled Low during Supply UVLO

● Fast Propagation Delays: 18ns (TYP)

● Fast Rise Time: 8ns (TYP)

● Fast Fall Time: 8ns (TYP)

● Delay Matching between Two Channels: 1ns (TYP)

● Channels can be Paralleled for Higher Drive Current

● -40℃ to +140℃ Operating Temperature Range

● Packaging:

The SGM48523/4A/5 offer 3 logic options: dual inverting

(SGM48523), dual non-inverting (SGM48524A), and

one inverting and one non-inverting (SGM48525). They

have independent enable pins (ENA and ENB) for each

channel with active-high logic that can be left open for

normal operation because of internal pull-up to VDD.

The SGM48526 offers a flexible dual input design

which can be configured as inverting (-INx) or

non-inverting (+INx) for each channel. Both inputs

(+INx or -INx) can control the output state. Typically,

one input is used for gate pulse and the other one is

used for enable/disable function.

 SGM48523/4A/5 Available in Green SOIC-8,

MSOP-8 (Exposed Pad) and TDFN-3×3-8L

Packages

 SGM48526 Available in a Green TDFN-3×3-8L

Package

APPLICATIONS

Power MOSFETs

IGBT Driving for Power Supplies

DC/DC Converters

Solar Power, Motor Drivers

Gate Drive for Emerging Wide Bandgap Devices

The SGM48523/4A/5 are available in SOIC-8, MSOP-8

(Exposed Pad) and TDFN-3×3-8L packages. The

SGM48526 is available in a Green TDFN-3×3-8L

package. They operate over a temperature range of

-40℃ to +140℃.

SG Micro Corp

JANUARY2022–REV. A

www.sg-micro.com

SGM48523/SGM48524A

SGM48525/SGM48526

Dual 5A, High-Speed, Low-Side Gate Drivers

with Negative Input Voltage Capability

PACKAGE/ORDERING INFORMATION

SPECIFIED

TEMPERATURE

RANGE

PACKAGE

DESCRIPTION

ORDERING

NUMBER

PACKAGE

MARKING

PACKING

OPTION

MODEL

SGM

48523XS8

XXXXX

SGM48523

XPMS8

XXXXX

SGM

48523DB

XXXXX

SGM

CM9XS8

XXXXX

SGMR67

XPMS8

XXXXX

SGM

R66DB

XXXXX

SGM

48525XS8

XXXXX

SGM48525

XPMS8

XXXXX

SGM

48525DB

XXXXX

SGM

SOIC-8

SGM48523XS8G/TR

Tape and Reel, 4000

-40℃ to +140℃

MSOP-8

(Exposed Pad)

SGM48523

SGM48523XPMS8G/TR

SGM48523XTDB8G/TR

SGM48524AXS8G/TR

SGM48524AXPMS8G/TR

SGM48524AXTDB8G/TR

SGM48525XS8G/TR

TDFN-3×3-8L

SOIC-8

MSOP-8

(Exposed Pad)

SGM48524A

TDFN-3×3-8L

SOIC-8

MSOP-8

(Exposed Pad)

SGM48525

SGM48526

SGM48525XPMS8G/TR

SGM48525XTDB8G/TR

SGM48526XTDB8G/TR

TDFN-3×3-8L

48526DB

XXXXX

MARKING INFORMATION

NOTE: XXXXX = Date Code, Trace Code and Vendor Code.

X X X X X

Vendor Code

Trace Code

Date Code - Year

Green (RoHS & HSF): SG Micro Corp defines "Green" to mean Pb-Free (RoHS compatible) and free of halogen substances. If

you have additional comments or questions, please contact your SGMICRO representative directly.

SG Micro Corp

www.sg-micro.com

JANUARY 2022

2

SGM48523/SGM48524A

SGM48525/SGM48526

Dual 5A, High-Speed, Low-Side Gate Drivers

with Negative Input Voltage Capability

OVERSTRESS CAUTION

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed in Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to

absolute maximum rating conditions for extended periods

may affect reliability. Functional operation of the device at any

conditions beyond those indicated in the Recommended

Operating Conditions section is not implied.

Supply Voltage, V_DD........................................... -0.3V to 20V

INA, INB, ENA, ENB Voltage................................ -8V to 20V

OUTA, OUTB Voltage (DC) .....................-0.3V to V_DD+ 0.3V

OUTA, OUTB Voltage (Pulse < 200ns).......-2V to V_DD+ 0.3V

Package Thermal Resistance

SOIC-8, θ^JA.............................................................. 121℃/W

MSOP-8 (Exposed Pad), θJA...................................... 55℃/W

TDFN-3×3-8L, θ^JA...................................................... 70℃/W

Junction Temperature.................................................+150℃

Storage Temperature Range.......................-65℃ to +150℃

Lead Temperature (Soldering, 10s)............................+260℃

ESD Susceptibility

ESD SENSITIVITY CAUTION

This integrated circuit can be damaged if ESD protections are

not considered carefully. SGMICRO recommends that all

integrated circuits be handled with appropriate precautions.

Failureto observe proper handlingand installation procedures

can cause damage. ESD damage can range from subtle

performance degradation tocomplete device failure. Precision

integrated circuits may be more susceptible to damage

because even small parametric changes could cause the

device not to meet the published specifications.

HBM.............................................................................4000V

CDM ............................................................................1000V

RECOMMENDED OPERATING CONDITIONS

Supply Voltage Range.........................................4.5V to 18V

Input Voltage, INA, INB......................................... -2V to 18V

Enable Voltage, ENA and ENB............................. -2V to 18V

Operating Junction Temperature Range......-40℃ to +140℃

DISCLAIMER

SG Micro Corp reserves the right to make any change in

circuit design, or specifications without prior notice.

SG Micro Corp

www.sg-micro.com

JANUARY 2022

3

SGM48523/SGM48524A

SGM48525/SGM48526

Dual 5A, High-Speed, Low-Side Gate Drivers

with Negative Input Voltage Capability

PIN CONFIGURATIONS

SGM48523 (TOP VIEW)

SGM48524A (TOP VIEW)

ENA

INA

1

2

3

4

8

7

6

5

ENB

ENA

INA

1

2

3

4

8

7

6

5

ENB

OUTA

VDD

OUTA

VDD

GND

INB

GND

INB

OUTB

SOIC-8

SGM48525 (TOP VIEW)

SGM48523/4A/5 (TOP VIEW)

ENA

INA

1

2

3

4

8

7

6

5

ENB

1

2

3

4

8

7

6

5

ENB

ENA

OUTA

VDD

INA

GND

INB

OUTA

GND

INB

VDD

OUTB

SOIC-8

MSOP-8 (Exposed Pad)

SGM48526 (TOP VIEW)

SGM48523/4A/5 (TOP VIEW)

ENA

INA

1

2

3

4

8

7

6

5

ENB

-INA

-INB

1

2

3

4

8

7

6

5

+INA

OUTA

VDD

+INB

OUTA

VDD

GND

INB

GND

OUTB

TDFN-3×3-8L

SG Micro Corp

www.sg-micro.com

JANUARY 2022

4

SGM48523/SGM48524A

SGM48525/SGM48526

Dual 5A, High-Speed, Low-Side Gate Drivers

with Negative Input Voltage Capability

PIN DESCRIPTIONS

Table 1. Pin Functions of SGM48523, SGM48524A and SGM48525

1

NAME

ENA

INA

I/O

I

FUNCTION

Channel A Enable Input. Pull ENA high or leave it floating to enable OUTA output. Pull ENA low to

disable OUTA output, ignoring INA state.

Channel A Input. Inverting configuration in SGM48523/5 and non-inverting configuration in

SGM48524A. OUTA is logic low if INA is unbiased or left floating.

2

I

3

GND

INB

―

I

Ground. Reference pin for all signals.

Channel B Input. Inverting configuration in SGM48523 and non-inverting configuration in

SGM48524A/5. OUTB is logic low if INB is unbiased or left floating.

4

5

OUTB

VDD

OUTA

ENB

GND

O

I

Channel B Output.

Power Supply Input.

Channel A Output.

6

7

O

I

Channel B Enable Input. Pull ENB high or leave it floating to enable OUTB output. Pull ENB low to

disable OUTB output, ignoring INB state.

8

Exposed

Pad

―

Exposed Pad. It should be soldered to PCB board and connected to GND.

Table 2. Pin Function of SGM48526

1

NAME

-INA

I/O

I

FUNCTION

Channel A Inverting Input. When +INA is used as a non-inverting input, pull -INA down to GND to

enable OUTA output. OUTA is logic low if -INA is unbiased or left floating.

Channel B Inverting Input. When +INB is used as a non-inverting input, pull -INB down to GND to

enable OUTB output. OUTB is logic low if -INB is unbiased or left floating.

2

-INB

I

3

GND

OUTB

VDD

―

O

I

Ground. Reference pin for all signals.

Channel B Output.

4

5

Power Supply Input.

6

OUTA

+INB

+INA

GND

O

I

Channel A Output.

Channel B Non-Inverting Input. When -INB is used as an inverting input, pull +INB up to VDD to

enable OUTB output. OUTB is logic low if +INB is unbiased or left floating.

7

Channel A Non-Inverting Input. When -INA is used as an inverting input, pull +INA up to VDD to

enable OUTA output. OUTA is logic low if +INA is unbiased or left floating.

8

I

Exposed

Pad

―

Exposed Pad. It should be soldered to PCB board and connected to GND.

NOTE: I: input, O: output.

SG Micro Corp

www.sg-micro.com

JANUARY 2022

5

SGM48523/SGM48524A

SGM48525/SGM48526

Dual 5A, High-Speed, Low-Side Gate Drivers

with Negative Input Voltage Capability

FUNCTION TABLE

Table 3. Device Logic Table (SGM48523, SGM48524A and SGM48525)

SGM48523/4A/5 SGM48523

SGM48524A

SGM48525

ENA

ENB

INA

INB

OUTA

OUTB

OUTA

OUTB

OUTA

OUTB

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

Any

L

Any

Floating

L

Floating

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

Table 4. Device Logic Table (SGM48526)

+INx (x = A or B)

-INx (x = A or B)

OUTx (x = A or B)

L

H

L

H

L

H

Floating

Any

Floating

SG Micro Corp

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JANUARY 2022

6

SGM48523/SGM48524A

SGM48525/SGM48526

Dual 5A, High-Speed, Low-Side Gate Drivers

with Negative Input Voltage Capability

TYPICAL APPLICATION CIRCUITS

Enable Channel B

SGM48523/4A/5

1

8

7

6

5

Enable Channel A

Channel A Input

ENA

ENB

OUTA

VDD

To Load

R_G1

2

3

4

INA

GND

INB

R_G2

Channel B Input

OUTB

C_VDD

Figure 1. SGM48523/4A/5 Typical Application

SGM48526

1

2

3

4

8

7

6

5

Non-Inverting

Input

-INA

-INB

GND

+INA

To Load

R_G1

Non-Inverting

Input

+INB

OUTA

R_G2

OUTB

VDD

C_VDD

Figure 2. SGM48526 with Channel A and Channel B in Non-Inverting Configuration

SGM48526

1

2

3

4

8

7

6

5

Inverting Input

-INA

-INB

GND

+INA

To Load

R_G1

+INB

OUTA

R_G2

OUTB

VDD

C_VDD

Figure 3. SGM48526 with Channel A and Channel B in Inverting Configuration

SG Micro Corp

www.sg-micro.com

JANUARY 2022

7

SGM48523/SGM48524A

SGM48525/SGM48526

Dual 5A, High-Speed, Low-Side Gate Drivers

with Negative Input Voltage Capability

ELECTRICAL CHARACTERISTICS

(V_DD= 12V, C_VDD= 1µF, TJ = -40℃ to +140℃, typical values are at TJ = +25℃, unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Power Supplies

VDD Supply Voltage

VDD Start-Up Current

V_DD

4.5

18

119

65

V

_DD= 3.4V, V_INA= V_INB= 0V

74

36

38

56

57

49

38

56

4.2

SGM48523

SGM48524A

SGM48525

V_DD= 3.4V, V_INA= V_INB= V_DD

V_DD= 3.4V, V_INA= V_INB= 0V

V_DD= 3.4V, V_INA= V_INB= V_DD

V_DD= 3.4V, V_INA= V_INB= 0V

V_DD= 3.4V, V_INA= V_INB= V_DD

V_DD= 3.4V, V_+INA= V_+INB= 0V

V_DD= 3.4V, V_+INA= V_+INB= V_DD

70

102

98

I_{DD_OFF}

μA

82

70

SGM48526

102

4.5

4.7

3.8

3.7

TJ = +25℃

Supply Start Threshold

V_ON

V

TJ = -40℃ to +140℃

Minimum Operating VDD Voltage after Supply

is Started

V_OFF

3.4

0.2

3.85

0.35

4.3

0.5

V

VDD Supply Voltage Hysteresis

V_{DD_HYS}

Input Pins (INA, INB, +INA, -INA, +INB, -INB)

Output high for non-inverting input pins

Output low for inverting input pins

Output low for non-inverting input pins

Output high for inverting input pins

Input Signal High Threshold

Input Signal Low Threshold

V_{IN_H}

1.8

2

2.2

V

V_{IN_L}

1.0

0.6

1.2

0.8

1.4

1.0

V

Input Hysteresis

V_{IN_HYS}

Enable Pins (ENA, ENB)

Enable Signal High Threshold

Enable Signal Low Threshold

Enable Hysteresis

V_{EN_H}

V_{EN_L}

Output high for non-inverting input pins

Output low for non-inverting input pins

1.8

1.0

0.6

2

2.2

1.4

1.0

V

1.2

0.8

V_{EN_HYS}

Output Pins (OUTA, OUTB)

High Level Output Voltage

Low Level Output Voltage

Output Pull-Up Resistance ⁽¹⁾

Output Pull-Down Resistance

V_OH

V_OL

V_OH= V_DD- V_OUT, I_OUT= -10mA

I_OUT= 10mA

0.061

0.009

6.1

V

Ω

A

R_OH

I_OUT= -10mA

4

0.5

5

R_OL

I_OUT= 10mA

0.9

I_{PK_SOURCE}

Peak Output Current

C_L= 0.22μF, f_SW= 1kHz

I_{PK_SINK}

5

Protection Circuits

Thermal Shutdown Temperature

Thermal Shutdown Temperature Hysteresis

T_TSD

T_HYS

165

15

℃

NOTE:

1. R_OHrepresents constant pull-up resistance only.

SG Micro Corp

www.sg-micro.com

JANUARY 2022

8

SGM48523/SGM48524A

SGM48525/SGM48526

Dual 5A, High-Speed, Low-Side Gate Drivers

with Negative Input Voltage Capability

SWITCHING CHARACTERISTICS

(V_DD= 12V, C_VDD= 1µF, TJ = -40℃ to +140℃, typical values are at TJ = +25℃, unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

8

MAX

UNITS

ns

Rise Time ⁽¹⁾

Fall Time ⁽¹⁾

t_R

t_F

C_L= 1.8nF

8

ns

INA = INB, OUTA and OUTB at 50%

transition point

Delay Matching between Two Channels

t_M

1

ns

Minimum Input Pulse Width that Changes the Output State

t_PW

t_D1

t_D2

t_D3

t_D4

t_D5

t_D6

15

11

18

11

18

14

16

C_L= 1.8nF, 5V input pulse

C_L= 1.8nF, 5V enable pulse

C_L= 1.8nF, 5V input pulse

Non-Inverting Input to Output Propagation Delay ⁽¹⁾

Enable to Output Propagation Delay ⁽¹⁾

Inverting Input to Output Propagation Delay ⁽¹⁾

NOTE:

ns

1. See timing diagrams as shown in Figure 4 through Figure 7.

TIMING DIAGRAMS

High

Input

Low

High

Enable

Low

High

Enable

Low

90%

Output

10%

90%

Output

10%

t_D1t_R

t_D2t_F

t_D3t_R

t_D4t_F

Figure 4. Non-Inverting Configuration

Figure 5. Enable Function (For Non-Inverting Configuration)

High

Input

Low

High

Enable

Low

High

Enable

Low

90%

Output

10%

90%

Output

10%

t_D5t_F

t_D6t_R

t_D3t_R

t_D4t_F

Figure 6. Inverting Configuration

Figure 7. Enable Function (For Inverting Configuration)

SG Micro Corp

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JANUARY 2022

9

SGM48523/SGM48524A

SGM48525/SGM48526

Dual 5A, High-Speed, Low-Side Gate Drivers

with Negative Input Voltage Capability

TYPICAL PERFORMANCE CHARACTERISTICS

Start-Up Current vs. Temperature

V_DD= 3.4V, SGM48524A only

Operating Supply Current vs. Temperature (Outputs Switching)

100

80

60

40

20

0

10

9

V_DD= 12V, f_SW= 500kHz, C_L= 500pF,

both channels switching

V_INx= V_ENx= V_DD

8

7

V_INx= V_ENx= 0V

6

5

-50 -25

0

25

50

75 100 125 150

-50 -25

0

25

50

75 100 125 150

Temperature (℃)

Supply Current vs. Temperature (Outputs in DC On/Off Condition)

Input Threshold Voltage vs. Temperature

V_DD= 12V

1000

2.5

2.0

1.5

1.0

0.5

0.0

V_DD= 12V

V_INx= V_ENx= 4V

800

600

400

200

0

Input High Threshold

V_INx= V_ENx= 0V

Input Low Threshold

-50 -25

0

25

50

75 100 125 150

-50 -25

0

25

50

75 100 125 150

Temperature (℃)

Enable Threshold Voltage vs. Temperature

V_DD= 4.5V

Enable Threshold Voltage vs. Temperature

V_DD= 12V

2.5

2.0

1.5

1.0

0.5

0.0

2.5

2.0

1.5

1.0

0.5

0.0

Enable High Threshold

Enable Low Threshold

Enable High Threshold

Enable Low Threshold

-50 -25

0

25

50

75 100 125 150

-50 -25

0

25

50

75 100 125 150

Temperature (℃)

SG Micro Corp

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JANUARY 2022

10

SGM48523/SGM48524A

SGM48525/SGM48526

Dual 5A, High-Speed, Low-Side Gate Drivers

with Negative Input Voltage Capability

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Output Pull-Up Resistance vs. Temperature

V_DD= 12V, I_OUT= -10mA

Output Pull-Down Resistance vs. Temperature

V_DD= 12V, I_OUT= 10mA

6

5

4

3

2

1

0.8

0.7

0.6

0.5

0.4

0.3

-50 -25

0

25

50

75 100 125 150

-50 -25

0

25

50

75 100 125 150

Temperature (℃)

Rise Time vs. Temperature

V_DD= 12V, C_L= 1.8nF

Fall Time vs. Temperature

V_DD= 12V, C_L= 1.8nF

10

9

10

9

8

7

6

5

-50 -25

0

25

50

75 100 125 150

-50 -25

0

25

50

75 100 125 150

Temperature (℃)

Non-Inverting Input to Output Propagation Delay vs. Temperature

Inverting Input to Output Propagation Delay vs. Temperature

25

V_DD= 12V, C_L= 1.8nF

20

15

10

5

Inverting Input to Output High Delay, t_D6

Non-Inverting Input to Output Low Delay, t_D2

Non-Inverting Input to Output High Delay, t_D1

15

10

5

Inverting Input to Output Low Delay, t_D5

0

-50 -25

0

25

50

75 100 125 150

-50 -25

0

25

50

75 100 125 150

Temperature (℃)

SG Micro Corp

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JANUARY 2022

11

SGM48523/SGM48524A

SGM48525/SGM48526

Dual 5A, High-Speed, Low-Side Gate Drivers

with Negative Input Voltage Capability

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Enable to Output Propagation Delay vs. Temperature

V_DD= 12V, C_L= 1.8nF

UVLO Threshold Voltage vs. Temperature

25

20

15

10

5

5.0

4.5

4.0

3.5

3.0

2.5

V_ON

Enable to Output Low Delay, t_D4

Enable to Output High Delay, t_D3

V_OFF

0

-50 -25

0

25

50

75 100 125 150

-50 -25

0

25

50

75 100 125 150

Temperature (℃)

Rise Time vs. Supply Voltage

C_L= 1.8nF

Fall Time vs. Supply Voltage

C_L= 1.8nF

12

11

10

9

10

9

8

7

8

6

7

5

4

6

8

10

12

14

16

18

4

6

8

10

12

14

16

18

Supply Voltage (V)

Propagation Delays vs. Supply Voltage

C_L= 1.8nF

Operating Supply Current vs. Frequency

C_L= 1.8nF, both channels switching

25

20

15

10

5

60

50

40

30

20

10

0

V_DD= 15V

V_DD= 12V

— Non-Inverting Input to Output High Delay, t_D1

— Non-Inverting Input to Output Low Delay, t_D2

— Enable to Output High Delay, t_D3

— Enable to Output Low Delay, t_D4

— Inverting Input to Output Low Delay, t_D5

— Inverting Input to Output High Delay, t_D6

V_DD= 4.5V

0

4

6

8

10

12

14

16

18

0

200

400

600

800

1000

Supply Voltage (V)

Frequency (kHz)

SG Micro Corp

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JANUARY 2022

12

SGM48523/SGM48524A

SGM48525/SGM48526

Dual 5A, High-Speed, Low-Side Gate Drivers

with Negative Input Voltage Capability

FUNCTIONAL BLOCK DIAGRAMS

V_DD

200kΩ

ENA

1

Filter

ENA

1

Filter

V_DD

200kΩ

INA

GND

INB

2

3

4

Logic A

7

6

5

OUTA

INA

GND

INB

2

3

4

Filter

Logic A

7

6

5

OUTA

400kΩ

UVLO

VDD

UVLO

VDD

Thermal

Shutdown

Thermal

Shutdown

V_DD

200kΩ

Filter

Logic B

OUTB

Filter

400kΩ

Logic B

OUTB

V_DD

200kΩ

ENB

8

Filter

ENB

8

Filter

Figure 8. SGM48523 Block Diagram

Figure 9. SGM48524A Block Diagram

V_DD

200kΩ

+INA

8

Filter

ENA

1

Filter

V_DD

400kΩ

V_DD

200kΩ

V_DD

-INA

GND

-INB

1

3

2

Filter

Logic A

6

5

4

OUTA

INA

GND

INB

2

3

4

Logic A

7

6

5

OUTA

UVLO

VDD

Thermal

Shutdown

UVLO

VDD

V_DD

Thermal

Shutdown

V_DD

200kΩ

V_DD

Filter

Logic B

OUTB

Filter

400kΩ

Logic B

OUTB

V_DD

200kΩ

+INB

7

Filter

400kΩ

ENB

8

Filter

Figure 10. SGM48525 Block Diagram

Figure 11. SGM48526 Block Diagram

SG Micro Corp

www.sg-micro.com

JANUARY 2022

13

SGM48523/SGM48524A

SGM48525/SGM48526

Dual 5A, High-Speed, Low-Side Gate Drivers

with Negative Input Voltage Capability

DETAILED DESCRIPTION

The SGM48523/4A/5/6 dual-channel, low-side, high-

speed gate drivers are among the top level devices in

the market featuring a 5A source/sink current capability

and industry best-in-class switching characteristics.

They have several other prominent features as listed in

Table 5 assuring that they are reliable and efficient gate

driving solutions for power switches in high frequency

applications.

Table 5. Prominent Features and Benefits

Feature

Benefit

Best-in-class propagation delays (18ns, TYP).

Excellent delay matching between channels (1ns, TYP).

Wide supply voltage range (V_DDfrom 4.5V to 18V).

Wide operating temperature range (-40℃ to +140℃).

UVLO protection on VDD.

Very low delay and distortion in pulse transmission.

Allows paralleling of the channel outputs for double current driving

capability. It is especially useful for driving paralleled power switches.

Design Flexibility.

Wider system operating temperature range and smaller cooling system.

Driver outputs are logic low in UVLO condition to ensure controlled and

glitch-free driving during power-up and power-down.

This safety feature prevents unexpected gate pulses during abnormal

situations such as the conditions tested in the safety certification.

Outputs are logic low when inputs (INx) are floating.

Outputs are enabled when enable inputs (ENx) are floating.

This feature provides pin-to-pin compatibility with other similar products

in those designs where pin 1 and 8 are floating.

Wide hysteresis CMOS/TTL compatible input and enable thresholds. Improved noise immunity while compatible with digital logic (3.3V, 5V).

Input/enable pins voltage levels are not restricted by V_DD.

Ability to handle -8V V_DC(MAX) at input pins.

Simplified system especially in the auxiliary bias supply architecture.

Increased robustness in noisy environments.

superimposed noise or other fluctuations. The safe low

voltage (less than 5V) operating capability along with

the excellent switching characteristics makes the

device well suited for driving GaN power switches.

Under-Voltage Lockout for VDD

The internal under-voltage lockout (UVLO) protection

keeps the outputs in low state when the VDD supply

voltage is insufficient for proper operation of the chip. If

V_DDrises but its voltage does not reach UVLO

threshold, the outputs are logic low, ignoring the state

of the inputs. The UVLO rising threshold voltage is 4.2V

(TYP) and has a 350mV (TYP) hysteresis band to

prevent output from chattering when V_DDhas large

If the enable pin is active or floating during power-up,

the output remains low until V_DDexceeds the UVLO

threshold. Then the output is controlled by the input

signal with a magnitude that follows V_DD(see Figure 12

for non-inverting and Figure 13 for inverting channels).

VDD Threshold

VDD

Enable

Input

Enable

Input

Output

Figure 12. Power-up in a Non-Inverting Driver Channel

Figure 13. Power-up in an Inverting Driver Channel

SG Micro Corp

www.sg-micro.com

JANUARY 2022

14

SGM48523/SGM48524A

SGM48525/SGM48526

Dual 5A, High-Speed, Low-Side Gate Drivers

with Negative Input Voltage Capability

DETAILED DESCRIPTION (continued)

Because VDD pin is the supply source for the device

internal circuits, it is recommended to use two V_DD

surface mount bypass capacitors to prevent noise

problems caused by high speed switching. A small

100nF ceramic capacitor must be soldered as close

between the VDD and GND pins as possible. In

addition, a larger low ESR capacitor (a few μF) must be

placed in parallel and close to the same pins for

delivery of the high peak driving currents with sharp rise

time. The low impedance characteristic provided by

these capacitors allows high frequency and high

current driving of the outputs. Avoid using vias for

connecting bypass capacitors to the device pins.

An important safety feature of the drivers is that if any

of the input pins floats, the corresponding channel

output will be held in the low state. This feature is

implemented by the GND pull-down resistors on the

non-inverting inputs and VDD pull-up resistors on the

inverting inputs as shown in Figure 8 through Figure 11.

The SGM48526 has two input pins in each channel to

control the output. The SGM48526 offers the flexibility

to use either a non-inverting input (+INx) or an inverting

input (-INx) to drive the output on each channel. The

output state depends on both +INx and -INx pins (x = A

or B). When one input pin is chosen to drive the output,

the other unused input cannot be left floating and must

be biased to allow output control by the other pin. As

explained before if an input is floating, the channel

output is disabled by the internal pull-up or pull-down

resistors for safety. The unused input pin can function

as enable/disable input. In summary, the SGM48526

output is only driven high when +INx pin is high and

-INx is low. The details are provided in the function

table and the application diagrams given in Figure 2

and Figure 3.

Operating Supply Current

The SGM48523/4A/5/6 consume a very low quiescent

current. The lowest quiescent I_DDvalue is reached

when the device is fully powered (not in UVLO), and the

outputs are in a low or high DC static state and the

internal pull-up inputs (enable inputs) are in high or float

state. During normal operation, the total I_DDcurrent is

the sum of three components: the quiescent current,

the average I_OUTcurrent due to switching and the

internal pull-up resistor currents (on enable inputs and

inverting inputs). Clearly if an inverting input pin that

has an internal pull-up resistor is externally pulled low,

a small additional current is drawn from V_DDthrough the

internal pull-up resistor (see Figure 8 through Figure 11).

Usually the main portion of the supply current is for

driving the outputs and the other two can be ignored.

For driving MOSFETs with a frequency of f_SWand gate

The input driving signal must have short rise or fall time.

This condition is normally satisfied when the input

signals are generated by a PWM controller or logic gate

(with transition times < 200ns). If the input transition is

too slow, the output may chatter several times (at high

frequency) before going to its new stable state. The

wide input hysteresis of these devices minimizes the

concern for such problem even for other logic

thresholds. However, the designer should make sure

the implementation satisfies the driver input

requirements. To limit the rise or fall time of the gate

pulse on the output, it is recommended to use an

external series resistance between the driver output

and the gate of the power device. This resistor reduces

the switching gate charge losses in the driver output

stage because a portion of the loss will dissipate in the

resistor.

charge of Q_g, the average driver output current is I_OUT

Q_g⨯ f_SW

=

.

Input Stage

The SGM48523/4A/5/6 input pins are compatible with

TTL and CMOS logic thresholds and are independent

of the supply voltage (V_DD). The logic high threshold is

typically around 2V and the low threshold is around 1.2V.

Therefore the inputs can be easily driven by a 3.3V or 5V

digital controller. The noise immunity is enhanced due

to the relatively wide hysteresis band (2V - 1.2V = 0.8V,

TYP) compared to the traditional TTL logic in which the

hysteresis is typically less than 0.5V. The input voltage

thresholds of the SGM48523/4A/5/6 are tightly

controlled to simplify the system design and assure

stable operation against wide temperature variations.

Also the devices are designed with very low parasitic

input pin capacitances to allow high speed switching.

Enable

The enable function is very useful in some applications

that need to block gate pulses depending on the

system operating conditions. For example, in a

synchronous rectifier and in light load conditions, it may

be necessary to disable gate signal to avoid negative

current in the device for improving efficiency or to

prevent boosting in a buck converter.

SG Micro Corp

www.sg-micro.com

JANUARY 2022

15

SGM48523/SGM48524A

SGM48525/SGM48526

Dual 5A, High-Speed, Low-Side Gate Drivers

with Negative Input Voltage Capability

DETAILED DESCRIPTION (continued)

The SGM48523/4A/5 devices have an independent

active-high enable pin (ENx). Similar to the driver

inputs, the enable pins are independent of the supply

voltage with tightly controlled thresholds and are

compatible with TTL or CMOS logic. They can be

directly controlled by the popular 3.3V and 5V

microcontrollers. The ENx pins (x = A or B) are internally

pulled up to VDD by pull-up resistors and the output

channel x is enabled if ENx input is floating. Therefore

the SGM48523/4A/5 are pin-to-pin compatible with

SGMICRO’s previous gate driver. Note that if two

channels in a device are paralleled, the enable signals

should also be tied together.

applications, for example, in the synchronous rectifier

applications where both SR MOSFETs are driven with

one driver. Moreover, the delays between the two

channels are extremely well matched with 1ns (TYP)

difference. This feature is critically important when

accurate timing between dual gate drives is required.

For example, in some PFC applications, two paralleled

MOSFETs may be needed to be driven independently

using each output channel and with the same input

pulses. The matching gate drivers ensure that they are

driven simultaneously with the minimum turn-on or

turn-off delay differences. The tight matching also

allows for paralleling the two channels to increase

current driving capability. The INA and INB pins are tied

together as input and OUTA and OUTB pins are tied

together as output. Caution must be exercised that any

delay between triggering of the two channels can lead

to a shoot-through between outputs. Note that as

described in Figure 14, the input signals must also be

well matched and with fast rise or fall time. Due to the

small differences between the input thresholds, a pulse

with slow rise or fall time may add extra delay between

signals. Therefore, it is recommended to use very fast

input pulses (20V/µs or greater) when inputs are

paralleled. Also, the tie point for inputs must be as close

as possible to the chip. If possible, adding external

series gate resistors between the outputs will also help.

Considering small 0Ω series output resistors in the

layout is recommended to allow future adjustment in

the design if needed.

The SGM48526 device does not have specified enable

pins. However, the unused input pin can be used to

enable or disable the device. Either pulling +INx down

to GND or pulling -INx up to VDD disables the output.

Therefore, +INx pin is used as an active high enable pin,

while -INx is used as an active low enable pin. Note that

while the ENA and ENB pins in SGM48523/4A/5 are

allowed to be floating during normal operation and the

outputs will be enabled. The unused input pins in

SGM48526 are not allowed to be floating.

Tightly Matched and Low Propagation

Delays

The SGM48523/4A/5/6 drivers offer very low

propagation delays (18ns, TYP), and pulse transmission

distortion between input and output. Such low distortion

is important in the industry for high frequency switching

V_DD

200kΩ

ENA

INA

1

Filter

V_DD

2

3

4

Filter

Logic A

7

6

5

OUTA

I_{SHOOT-THROUGH}

400kΩ

Slow Signal

V_{INB_H}

V_{INA_H}

GND

INB

UVLO

VDD

Thermal

Shutdown

V_DD

Filter

400kΩ

Logic B

OUTB

V_DD

200kΩ

ENB

8

Filter

Figure 14. When channels are paralleled for higher drive current, slow rise or fall time of the input pulse can cause

shoot-through between device outputs. Inputs with dv/dt higher than 20V/µs are recommended

SG Micro Corp

www.sg-micro.com

JANUARY 2022

16

SGM48523/SGM48524A

SGM48525/SGM48526

Dual 5A, High-Speed, Low-Side Gate Drivers

with Negative Input Voltage Capability

APPLICATION INFORMATION

In order to achieve fast switching and to reduce losses

in the power switches, high current gate drivers with

sufficient drive voltage are required. Such function

cannot be directly provided by logic controllers usually

operating at low power and low voltages such as 3.3V.

Even traditional buffer drivers like totem-pole NPN/PNP

configurations, are not useful as they are not capable

for voltage level shifting. A gate driver device provides

other advantages in the system such as reduction of

the high frequency noise by placing the high current

driver close to the power switch, and reduction of power

dissipation and thermal stress in controllers because

gate-charge power losses are handled by the driver.

Moreover, with the emerging of wide band-gap power

devices such as GaN based switches that are capable

for operating at very high frequency, new gate driving

requirements are imposed on the driver devices. Such

requirements include operating at low supply voltages

(5V or less), low propagation delays and excellent

delay matching, and compact layout with low

inductance and enhanced thermal capability.

Drive Current and Power Dissipation

MOSFETs are widely used as power switches in many

high frequency applications. The SGM48523/4A/5/6

can source and sink 5A at 12V for a pulse width of

several hundred nanoseconds for driving MOSFETs.

High peak driving current is usually needed for a quick

turn on and usually the same amount of current in

opposite direction is also needed for switch turn off.

The sourcing and sinking actions repeat at the

switching frequency and for each transition some

energy is dissipated in the driver device.

The amount of power dissipation in the device depends

on the following:

•

Switching frequency.

Gate charge required to turn the MOSFET on or off.

Size of the external gate resistors used (if any).

Gate charge is usually a function of the V_GSdrive

voltage. The drive voltage is V_GS≈ V_DD(the dropout of

the driver, V_OH, is normally very low). Note that due to

the low quiescent current and the internal bias power,

the loss in the driver is effectively equal to the output

driving losses caused by drive currents.

In summary, gate driver devices simplify the system

design and provide better performance, lower cost,

lower component count and require less space on the

board.

Using a discrete capacitor (C_g) as a similar switch gate

load for testing, the loss in the driver can be easily

estimated. The energy that is needed to charge the

capacitor to the supply voltage V_DDis given by (1):

Supply Voltage V_DD

The supply voltage is selected based on the power

switch and driving requirements. Some power switches,

need positive gate voltage for turn-on and negative for

turn-off and for some other types, it is reversed. In both

cases the differential drive voltage is equal to V_DDthat

can be selected in a wide range from 4.5V to 18V. This

gate driver can be used for driving of a variety of power

switches. Typically for Si MOSFETs, the driving V_GSis

chosen to be 4.5V, 10V or 12V depending on the

application and switch class. For IGBTs, a V_GEof 15V

or 18V is commonly used.

1

2

(1)

E_G= C_gV_DD

2

It can be proved that the same amount of energy is

dissipated in the driver output stage resistances. Also,

the same amount of energy is dissipated if the

capacitor is discharged by the driver. Therefore, with a

switching frequency of f_SW, the total power loss (in one

channel) is:

P_G= C_gV_D²_Df_SW

(2)

Propagation Delay

The propagation delays depend on the operating

switching frequency and the permissible pulse

distortion. All devices present very short 18ns (TYP)

propagation delays. Switching characteristics with more

details are provided to illustrate the propagation and

switching performance.

As an example, with V_DD= 12V, C_g= 10nF and f_SW

200kHz the driver loss is calculated as:

=

(3)

P_G= 10nF×12V ×12V × 200kHz = 288mW

SG Micro Corp

www.sg-micro.com

JANUARY 2022

17

SGM48523/SGM48524A

SGM48525/SGM48526

Dual 5A, High-Speed, Low-Side Gate Drivers

with Negative Input Voltage Capability

APPLICATION INFORMATION (continued)

The test is implemented on MOSFETs to find the

equivalent gate capacitance to determine the gate

charge required for switching the device. The gate

charge includes the impact of the input gate-source and

drain-gate capacitances. The drain-gate capacitance

also needs current for charge and discharge due to the

voltage swing of the drain voltage when the power

device is turning on and off. Usually the typical and

maximum gate charges (Q_g) are provided by

manufacturers for switching the device under specified

conditions. Because Q_g= C_gV_DD, the power loss in the

driver can be calculated from (4) too:

effective resistance of the internal pull-up structure to

VDD (in the SGM48523/4A/5/6).

To find the total loss in the device, the quiescent current

losses (P_Q= I_DD,Q× V_DD) should be added. Due to small

quiescent current (I_DD,Q≤ 0.6mA) of the device, this loss

is small and can be ignored. With V_DD= 12V the

quiescent loss is P_Q= 0.6mA ×12V = 7.2mW.

The actual driver supply current can be calculated as:

P_G

V_DD

I_DD

≈

(7)

With P_G= 0.6W and V_DD= 12V the device supply

current will be I_DD= 50mA.

P_G= C_gV_D²_Df_SW= Q_gV_DDf_SW

(4)

Power Supply Recommendation

For example, for driving a power MOSFET with 50nC of

gate charge (Q_g= 50nC) at 500kHz with V_DD= 12V, the

driver loss due to gate charge will be 0.3W. For this

driver that includes two channels, the total loss related

to gate charge is doubled when driving similar

MOSFETs:

The supply voltage ranges (V_DD) for SGM48523/4A/5/6

are between 4.5V and 18V. The absolute maximum

stress that the device tolerates is 20V. Considering a

2V margin for transient spikes, the maximum range is

set to 18V. The minimum limit is dictated by the UVLO

protection. In UVLO condition, the outputs are logic low,

ignoring the input states. UVLO has an almost 0.35V

hysteresis and an operating driver will not shut down

unless V_DDfalls below V_OFF= 3.85V (TYP). Therefore, it

is important to make sure that for the designed system,

the supply ripple or voltage drops do not fall below

UVLO lower threshold that triggers device shutdown. A

100nF low ESR ceramic capacitor with another

surface-mount capacitor of few microfarads between

VDD and GND are necessary to prevent V_DDtransient

drops. Similarly, at start-up, the device starts operation

when the VDD pin voltage exceeds the V_ONthreshold

(4.2V, TYP).

(5)

P_G= 2×50nC×12V ×0.5MHz = 0.6W

When an external series gate resistor, R_g, is used for

MOSFET or IGBT, a portion the P_Gloss will dissipate on

R_gand not inside the driver. With a simplified analysis,

the gate driving loss inside each channel can be

calculated by (6):





R_OFF

_OFF+ R_g

R_ON

_ON+ R_g

(6)

P_G= 0.5×Q_g× V_DD× f_SW

×

+









R

Where R_OFF= R_OLis the effective pull-down resistance

from the channel output to the ground and R_ONis the

REVISION HISTORY

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (JANUARY 2022) to REV.A

Page

Changed from product preview to production data.............................................................................................................................................All

SG Micro Corp

www.sg-micro.com

JANUARY 2022

18

PACKAGE INFORMATION

PACKAGE OUTLINE DIMENSIONS

SOIC-8

0.6

D

e

2.2

E1

E

5.2

b

1.27

RECOMMENDED LAND PATTERN (Unit: mm)

L

A

A1

c

θ

A2

Dimensions

In Millimeters

Dimensions

In Inches

Symbol

MIN

MAX

1.750

0.250

1.550

0.510

0.250

5.100

4.000

6.200

MIN

MAX

0.069

0.010

0.061

0.020

0.010

0.200

0.157

0.244

A

A1

A2

b

1.350

0.100

1.350

0.330

0.170

4.700

3.800

5.800

0.053

0.004

0.053

0.013

0.006

0.185

0.150

0.228

c

D

E

E1

e

1.27 BSC

0.050 BSC

L

0.400

0°

1.270

8°

0.016

0°

0.050

8°

θ

SG Micro Corp

www.sg-micro.com

TX00010.000

PACKAGE INFORMATION

PACKAGE OUTLINE DIMENSIONS

MSOP-8 (Exposed Pad)

D1

1.80

E1

E

E2

1.55 4.8

1.02

b

e

0.65

0.41

RECOMMENDED LAND PATTERN (Unit: mm)

D

L

A

c

A1

θ

A2

Dimensions

In Millimeters

Dimensions

In Inches

Symbol

MIN

MAX

MIN

MAX

0.043

0.006

0.037

0.015

0.009

0.122

0.075

A

A1

A2

b

0.820

0.020

0.750

0.250

0.090

2.900

1.700

1.100

0.150

0.950

0.380

0.230

3.100

1.900

0.032

0.001

0.030

0.010

0.004

0.114

0.067

c

D

D1

e

0.65 BSC

0.026 BSC

E

2.900

4.750

1.450

0.400

0°

3.100

5.050

1.650

0.800

6°

0.114

0.187

0.057

0.016

0°

0.122

0.199

0.065

0.031

6°

E1

E2

L

θ

SG Micro Corp

www.sg-micro.com

TX00016.000

PACKAGE INFORMATION

PACKAGE OUTLINE DIMENSIONS

TDFN-3×3-8L

D

e

N8

D1

k

E

E1

N4

N1

L

b

BOTTOM VIEW

TOP VIEW

2.3

1.5 2.725

A

A1

A2

0.675

SIDE VIEW

0.65

0.24

RECOMMENDED LAND PATTERN (Unit: mm)

Dimensions

In Millimeters

Dimensions

In Inches

Symbol

MIN

MAX

0.800

0.050

MIN

0.028

0.000

MAX

0.031

0.002

A

A1

A2

D

0.700

0.000

0.203 REF

0.008 REF

2.900

2.200

2.900

1.400

3.100

2.400

3.100

1.600

0.114

0.087

0.114

0.055

0.122

0.094

0.122

0.063

D1

E

E1

k

0.200 MIN

0.650 TYP

0.008 MIN

0.026 TYP

b

0.180

0.375

0.300

0.575

0.007

0.015

0.012

0.023

e

L

SG Micro Corp

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TX00058.000

PACKAGE INFORMATION

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

P2

P0

W

Q2

Q4

Q2

Q4

Q2

Q4

Q1

Q3

Q1

Q3

Q1

Q3

B0

Reel Diameter

P1

A0

K0

Reel Width (W1)

DIRECTION OF FEED

NOTE: The picture is only for reference. Please make the object as the standard.

KEY PARAMETER LIST OF TAPE AND REEL

Reel Width

Reel

Diameter

A0

B0

K0

P0

P1

P2

W

Pin1

Package Type

W1

(mm)

(mm) (mm) (mm) (mm) (mm) (mm) (mm) Quadrant

SOIC-8

13″

12.4

6.40

5.20

3.35

5.40

3.30

3.35

2.10

1.50

1.13

4.0

8.0

2.0

12.0

Q1

MSOP-8

(Exposed Pad)

TDFN-3×3-8L

SG Micro Corp

TX10000.000

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PACKAGE INFORMATION

CARTON BOX DIMENSIONS

NOTE: The picture is only for reference. Please make the object as the standard.

KEY PARAMETER LIST OF CARTON BOX

Length

(mm)

Width

(mm)

Height

(mm)

Reel Type

Pizza/Carton

13″

386

280

370

5

SG Micro Corp

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型号：	SGM48524A
厂家：	Shengbang Microelectronics Co, Ltd
描述：	Dual 5A, High-Speed, Low-Side Gate Driver with Negative Input Voltage Capability 栅
文件：	总23页 (文件大小：963K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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