SGM5352-16 [SGMICRO]
16-Bit, 4 Channels, Voltage-Output Digital-to-Analog Converter;
| 型号： | SGM5352-16 |
| 厂家： | 
Shengbang Microelectronics Co, Ltd |
| 描述： | 16-Bit, 4 Channels, Voltage-Output Digital-to-Analog Converter |
| 文件： | 总23页 (文件大小：1522K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SGM5352-16
16-Bit, 4 Channels, Voltage-Output
Digital-to-Analog Converter
GENERAL DESCRIPTION
FEATURES
The SGM5352-16 is a low power, 4 channels, 16-bit,
voltage-output DAC. It operates from a 2.7V to 5.5V
supply and the monotonicity is guaranteed by design.
● Power Supply Range: 2.7V to 5.5V
● 16-Bit DAC, Monotonicity Guaranteed by Design
● 6LSB (TYP) Relative Accuracy
● Low Power Operation: 0.4mA at 2.7V
● Power-On Reset to Zero-Scale
● 10μs (TYP) Settling Time
The SGM5352-16 sets the output range of each DAC
channel by using an external reference voltage. It
incorporates a power-on reset circuit that ensures the
DAC output powers to 0V.
● -100dB (TYP) AC Crosstalk
● Simultaneous or Sequential Output Update and
Power-Down
The SGM5352-16 uses a 3-wire serial SPI interface.
● 1.8V to 5.5V Logic Interface
The SGM5352-16 is available in Green TSSOP-16 and
WLCSP-1.64×1.62-16B packages. It operates over an
ambient temperature range of -40℃ to +125℃.
● Available in Green WLCSP-1.64×1.62-16B and
TSSOP-16 Packages
APPLICATIONS
Industrial Instrumentation
Factory Automation
Process Control
Servo-Control
Data Acquisition Systems
SG Micro Corp
DECEMBER 2021–REV. A
www.sg-micro.com
16-Bit, 4 Channels, Voltage-Output
Digital-to-Analog Converter
SGM5352-16
PACKAGE/ORDERING INFORMATION
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESCRIPTION
ORDERING
NUMBER
PACKAGE
MARKING
PACKING
OPTION
MODEL
OUA
XXXX
WLCSP-1.64×1.62-16B -40℃ to +125℃
TSSOP-16
SGM5352-16XG/TR
Tape and Reel, 3000
Tape and Reel, 4000
SGM5352-16
SGM535216
XTS16
-40℃ to +125℃ SGM5352-16XTS16G/TR
XXXXX
MARKING INFORMATION
NOTE: XXXX = Date Code and Trace Code. XXXXX = Date Code, Trace Code and Vendor Code.
WLCSP-1.64×1.62-16B
TSSOP-16
Serial Number
Y Y Y
X X X X
X X X X X
Vendor Code
Trace Code
Trace Code
Date Code - Year
Date Code - Year
Green (RoHS & HSF): SG Micro Corp defines "Green" to mean Pb-Free (RoHS compatible) and free of halogen substances. If
you have additional comments or questions, please contact your SGMICRO representative directly.
OVERSTRESS CAUTION
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed in Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods
may affect reliability. Functional operation of the device at any
conditions beyond those indicated in the Recommended
Operating Conditions section is not implied.
Input Voltage Range............................................ -0.3V to 6V
Digital Input Voltage Range.................. -0.3V to AVDD + 0.3V
Output Voltage Range .......................... -0.3V to AVDD + 0.3V
Package Thermal Resistance
WLCSP-1.64×1.62-16B, θJA................................... 107℃/W
WLCSP-1.64×1.62-16B, θJC..................................... 41℃/W
TSSOP-16, θJA......................................................... 94℃/W
TSSOP-16, θJC......................................................... 37℃/W
Junction Temperature.................................................+150℃
Storage Temperature Range.......................-65℃ to +150℃
Lead Temperature (Soldering, 10s)............................+260℃
ESD Susceptibility
ESD SENSITIVITY CAUTION
This integrated circuit can be damaged if ESD protections are
not considered carefully. SGMICRO recommends that all
integrated circuits be handled with appropriate precautions.
Failureto observe proper handlingand installation procedures
can cause damage. ESD damage can range from subtle
performance degradation tocomplete device failure. Precision
integrated circuits may be more susceptible to damage
because even small parametric changes could cause the
device not to meet the published specifications.
HBM.............................................................................4000V
CDM ............................................................................1000V
RECOMMENDED OPERATING CONDITIONS
Operating Temperature Range....................-40℃ to +125℃
DISCLAIMER
SG Micro Corp reserves the right to make any change in
circuit design, or specifications without prior notice.
SG Micro Corp
www.sg-micro.com
DECEMBER 2021
2
16-Bit, 4 Channels, Voltage-Output
Digital-to-Analog Converter
SGM5352-16
PIN CONFIGURATIONS
(TOP VIEW)
(TOP VIEW)
1
2
3
4
A
nENABLE
LDAC
VOUTB
VREFH
VOUTA
VOUTB
VREFH
AVDD
VREFL
GND
VOUTC
VOUTD
1
2
3
4
5
6
7
8
16 LDAC
15 nENABLE
14 A1
A1
A0
VOUTA
VOUTD
VOUTC
AVDD
VREFL
GND
B
C
13 A0
12 IOVDD
11 DIN/OUT
10 SCLK
IOVDD
SCLK
DIN/OUT
9
nSYNC
nSYNC
D
TSSOP-16
WLCSP-1.64×1.62-16B
PIN DESCRIPTION
PIN
NAME
FUNCTION
WLCSP-
1.64×1.62-16B
TSSOP-16
1
2
3
4
5
6
7
8
B3
A3
A4
B4
C4
D4
D3
C3
VOUTA
VOUTB
VREFH
AVDD
VREFL
GND
Analog Output DAC A.
Analog Output DAC B.
Positive Reference Voltage Pin.
Power Supply Pin. It can be operated from 2.7V to 5.5V.
Negative Reference Voltage Pin.
Ground Pin.
VOUTC
VOUTD
Analog Output DAC C.
Analog Output DAC D.
Frame Synchronization Input Pin. Active low. When this pin goes low, data can be
transferred into the input shift register, or transferred out of the DAC register or data
buffer.
9
D2
D1
C2
nSYNC
SCLK
10
11
Serial Clock Input Pin. The data transfer rate is up to 50MHz.
Serial Data Input/Output Pin. When used as the input pin, data is clocked into the
24-bit input shift register on the falling edge of SCLK; when used as the output pin,
data is clocked out of the DAC register or data buffer on the rising edge of SCLK.
DIN/OUT
12
13
14
15
16
C1
B2
B1
A1
A2
IOVDD
A0
Digital I/O Power Supply.
Device Address 0.
A1
Device Address 1.
nENABLE Enable Pin. Active low. Connect the SPI interface to the serial port.
LDAC
Load DAC Registers Pin. When rising edge triggered, all DAC registers are loaded.
SG Micro Corp
www.sg-micro.com
DECEMBER 2021
3
16-Bit, 4 Channels, Voltage-Output
Digital-to-Analog Converter
SGM5352-16
ELECTRICAL CHARACTERISTICS
(AVDD = 2.7V to 5.5V, Full = -40℃ to +125℃, typical values are at TA = +25℃, unless otherwise noted.)
PARAMETER
Static Performance (1)
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
16
Bits
LSB
LSB
mV
Relative Accuracy
Differential Nonlinearity
Zero-Code Error
Measured by line passing through codes 485 and 64741
16-bit monotonic
6
0.5
0.42
4
14
1
Measured by line passing through codes 485 and 64741
3
Zero-Code Error Drift
μV/℃
Measured by line passing through codes 485 and 64741,
(AVDD = 5.5V, VREF = 5.4V) and (AVDD = 2.7V,
VREF = 2.5V)
% of
FSR
Full-Scale Error
0.06
0.01
0.3
0.2
Measured by line passing through codes 485 and 64741,
(AVDD = 5.5V, VREF = 5.4V) and (AVDD = 2.7V,
VREF = 2.5V)
% of
FSR
Gain Error
ppm of
Gain Temperature Coefficient
1
FSR/℃
Power Supply Rejection Ratio
Output Characteristics (2)
Output Voltage Range
Output Voltage Settling Time
Slew Rate
PSRR
RL = 2kΩ, CL = 200pF
RL = 2kΩ, CL = 500pF
0.1
mV/V
0
VREFH
V
μs
10
1
V/μs
RL = ∞
2
Capacitive Load Stability
nF
RL = 2kΩ
10
20
0.1
Code Change Glitch Impulse
Digital Feedthrough
1LSB change around major carry
nV-s
nV-s
Full-scale swing on adjacent channel,
AVDD = 5V, VREF = 4.096V
DC Crosstalk
0.05
LSB
AC Crosstalk
1kHz sine wave
At mid-point input
AVDD = 5V
-100
0.3
37
dB
DC Output Impedance
Ω
Short-Circuit Current
Power-Up Time
mA
AVDD = 3V
35
AVDD = 5V
Coming out of power-down mode
AVDD = 3V
15
μs
13
AC Performance
BW = 20kHz, AVDD = 5V, fOUT = 1kHz,
Signal-to-Noise Ratio
SNR
THD
54
-62
66
dB
dB
dB
dB
1st 19 harmonics removed for SNR calculation
BW = 20kHz, AVDD = 5V, fOUT = 1kHz,
Total Harmonic Distortion
1st 19 harmonics removed for SNR calculation
BW = 20kHz, AVDD = 5V, fOUT = 1kHz,
1st 19 harmonics removed for SNR calculation
Spurious-Free Dynamic Range
Signal-to-Noise and Distortion
SFDR
SINAD
BW = 20kHz, AVDD = 5V, fOUT = 1kHz,
53
1st 19 harmonics removed for SNR calculation
Reference Input
VREFH Voltage
VREFL Voltage
0
AVDD
V
V
0
VREFL = GND, VREFH = AVDD = 5V
VREFL = GND, VREFH = AVDD = 3V
VREFL < VREFH
85
50
59
110
70
Reference Input Current
μA
kΩ
Reference Input Impedance
SG Micro Corp
www.sg-micro.com
DECEMBER 2021
4
16-Bit, 4 Channels, Voltage-Output
Digital-to-Analog Converter
SGM5352-16
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = 2.7V to 5.5V, Full = -40℃ to +125℃, typical values are at TA = +25℃, unless otherwise noted.)
PARAMETER
Logic Inputs (2)
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
IOVDD = 5.5V
IOVDD = 1.8V
IOVDD = 5.5V
IOVDD = 1.8V
1.2
0.4
Input Low Voltage
Input High Voltage
VIL
VIH
V
2.1
1.3
V
Pin Capacitance
Power Requirements
Supply Voltage
2
pF
AVDD
2.7
1.8
5.5
5.5
V
V
Digital Input-Output Supply
Voltage
IOVDD
IOIDD
no load, reference current not included, AVDD = 5.5V
0.03
0.45
0.4
1
0.7
0.6
4
μA
Normal mode, input code = 32768,
mA
V
IH = IOVDD and VIL = GND
Supply Current
IDD
AVDD = 2.7V
AVDD = 5.5V
AVDD = 2.7V
0.45
0.32
All power-down modes,
IH = IOVDD and VIL = GND
μA
V
4
Power Efficiency
IOUT/IDD Power Efficiency
IL = 2mA, AVDD = 5V
95
%
NOTES:
1. Linearity calculated using a reduced codes range of 485 to 64741; output unloaded.
2. Specified by design and characterization; not production tested.
SG Micro Corp
www.sg-micro.com
DECEMBER 2021
5
16-Bit, 4 Channels, Voltage-Output
Digital-to-Analog Converter
SGM5352-16
TIMING CHARACTERISTICS
(AVDD = 2.7V to 5.5V, Full = -40℃ to +125℃, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
IOVDD = AVDD = 2.7V to 3.6V
IOVDD = AVDD = 3.6V to 5.5V
IOVDD = AVDD = 2.7V to 3.6V
IOVDD = AVDD = 3.6V to 5.5V
IOVDD = AVDD = 2.7V to 3.6V
IOVDD = AVDD = 3.6V to 5.5V
IOVDD = AVDD = 2.7V to 3.6V
IOVDD = AVDD = 3.6V to 5.5V
IOVDD = AVDD = 2.7V to 3.6V
IOVDD = AVDD = 3.6V to 5.5V
IOVDD = AVDD = 2.7V to 3.6V
IOVDD = AVDD = 3.6V to 5.5V
IOVDD = AVDD = 2.7V to 3.6V
IOVDD = AVDD = 3.6V to 5.5V
IOVDD = AVDD = 2.7V to 3.6V
IOVDD = AVDD = 3.6V to 5.5V
IOVDD = AVDD = 2.7V to 5.5V
IOVDD = AVDD = 2.7V to 5.5V
IOVDD = AVDD = 2.7V to 5.5V
MIN
20
20
10
10
10
10
0
TYP
MAX UNITS
SCLK Cycle Time (3)
SCLK High Time
SCLK Low Time
t1
ns
t2
t3
t4
t5
t6
t7
t8
ns
ns
ns
ns
ns
ns
ns
nSYNC Falling Edge to SCLK Rising Edge Setup
Time
0
5
Data Setup Time
5
5
Data Hold Time
5
0
24th SCLK Falling Edge to nSYNC Rising Edge
0
20
20
100
15
0
Minimum nSYNC High Time
24th SCLK Falling Edge to nSYNC Falling Edge
DIN/OUT Tri-State to Driven
24th SCLK Falling Edge to DIN/OUT Tri-State
t9
ns
ns
ns
t10
t11
NOTES:
1. All input signals are specified with tR = tF = 3ns (10% to 90% of AVDD) and timed from a voltage level of (VIL + VIH)/2.
2. Refer to Figure 1 and Figure 2.
3. Maximum SCLK frequency is 50MHz at IOVDD = AVDD = 2.7V to 5.5V.
t1
t9
SCLK
1
5
24
t2
t8
t7
t3
t4
nSYNC
t6
t5
DIN/OUT
DB[23]
DB[20]
0
DB[18]
DB[0]
DB[23]
NOTE: 1. When DB[19] = 0, this is a write operation, the data DB[18:0] is locked into DAC on each falling edge of SCLK.
Figure 1. Serial Write Operation
t1
t9
24
SCLK
1
9
t2
t8
t7
t3
t4
nSYNC
t6
(1)
(2)
t10
t11
t5
DIN/OUT
DB[23]
DB[15]
DB[20]
1
DB[16]
DB[0]
DB[23]
NOTES:
1. When DB[19] = 1, this is a read operation, the data DB[15:0] is read from DAC. On the rising edge of 9th of SCLK, the DIN/OUT is
switched from input to output, the data of internal register is put on the bus on each rising edge of SCLK.
2. On the 24th falling edge of SCLK, the DIN/OUT is turned off to Hi-Z.
Figure 2. Serial Read Operation
SG Micro Corp
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DECEMBER 2021
6
16-Bit, 4 Channels, Voltage-Output
Digital-to-Analog Converter
SGM5352-16
TYPICAL PERFORMANCE CHARACTERISTICS
TA = +25℃, unless otherwise noted.
INL vs. Digital Input Code (Channel A)
INL vs. Digital Input Code (Channel B)
INL vs. Digital Input Code (Channel C)
DNL vs. Digital Input Code (Channel A)
AVDD = 5V
DNL vs. Digital Input Code (Channel B)
AVDD = 5V
DNL vs. Digital Input Code (Channel C)
AVDD = 5V
SG Micro Corp
www.sg-micro.com
DECEMBER 2021
7
16-Bit, 4 Channels, Voltage-Output
Digital-to-Analog Converter
SGM5352-16
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
TA = +25℃, unless otherwise noted.
INL vs. Digital Input Code (Channel D)
DNL vs. Digital Input Code (Channel D)
AVDD = 5V
Zero-Scale Error vs. Temperature
AVDD = 5V, VREF = 4.99V
Full-Scale Error vs. Temperature
AVDD = 5V, VREF = 4.99V
1.5
1
6
4
CHD
CHB
CHD
0.5
0
2
CHA
CHB
CHC
0
-0.5
-1
-2
-4
-6
CHC
CHA
-1.5
-50
-25
0
25
50
75
100 125
-50
-25
0
25
50
75
100 125
Temperature (℃)
Temperature (℃)
Source Current Capability (All Channels)
AVDD = 5.5V, VREF = 5.49V
Supply Current vs. Logic Input Voltage
6.0
5.6
5.2
4.8
4.4
4.0
210
180
150
120
90
IOVDD = AVDD = VREF = 5V, TA = +25℃,
SYNC Input (All other inputs = GND),
CHA Powered Up (All other channels in
power-down), Reference Current Included
DAC Loaded with FFFFh
60
30
0
0
2
4
6
8
10
0
1
2
3
4
5
ISOURCE (mA)
Logic Input Voltage (V)
SG Micro Corp
www.sg-micro.com
DECEMBER 2021
8
16-Bit, 4 Channels, Voltage-Output
Digital-to-Analog Converter
SGM5352-16
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
TA = +25℃, unless otherwise noted.
Full-Scale Settling Time, 5V Rising Edge
Trigger Pulse 5V/div
Full-Scale Settling Time, 5V Falling Edge
Trigger Pulse 5V/div
AVDD = 5V
REF = 4.096V
V
From Code: FFFF
To Code: 0000
AVDD = 5V
Falling Edge 1V/div
V
REF = 4.096V
Rising Edge 1V/div
From Code: 0000
To Code: FFFF
Time (2μs/div)
Time (2μs/div)
Half-Scale Settling Time, 5V Rising Edge
Trigger Pulse 5V/div
Half-Scale Settling Time, 5V Falling Edge
Trigger Pulse 5V/div
Falling Edge 1V/div
AVDD = 5V
Rising Edge 1V/div
AVDD = 5V
V
REF = 4.096V
VREF = 4.096V
From Code: 4000
To Code: CFFF
From Code: CFFF
To Code: 4000
Time (2μs/div)
Time (2μs/div)
Glitch Energy: 5V, 1LSB Step, Rising Edge
Glitch Energy: 5V, 1LSB Step, Falling Edge
VOUT
VOUT
AVDD = 5V
REF = 4.096V
AVDD = 5V
REF = 4.096V
V
V
From Code: 7FFF
To Code: 8000
From Code: 8000
To Code: 7FFF
Time (2μs/div)
Time (2μs/div)
SG Micro Corp
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DECEMBER 2021
9
16-Bit, 4 Channels, Voltage-Output
Digital-to-Analog Converter
SGM5352-16
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
TA = +25℃, unless otherwise noted.
Glitch Energy: 5V, 16LSB Step, Rising Edge
Glitch Energy: 5V, 16LSB Step, Falling Edge
VOUT
VOUT
AVDD = 5V
REF = 4.096V
AVDD = 5V
REF = 4.096V
V
V
From Code: 8000
To Code: 8010
From Code: 8010
To Code: 8000
Time (2μs/div)
Time (2μs/div)
Glitch Energy: 5V, 256LSB Step, Rising Edge
Glitch Energy: 5V, 256LSB Step, Falling Edge
VOUT
VOUT
AVDD = 5V
REF = 4.096V
AVDD = 5V
REF = 4.096V
V
V
From Code: 8000
To Code: 80FF
From Code: 80FF
To Code: 8000
Time (500ns/div)
Time (500ns/div)
Output Noise Density
270
250
230
210
190
170
150
130
110
90
AVDD = 5V
70
100
1000
10000
100000
Frequency (Hz)
SG Micro Corp
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DECEMBER 2021
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16-Bit, 4 Channels, Voltage-Output
Digital-to-Analog Converter
SGM5352-16
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
TA = +25℃, unless otherwise noted.
INL vs. Digital Input Code (Channel A)
INL vs. Digital Input Code (Channel B)
INL vs. Digital Input Code (Channel C)
DNL vs. Digital Input Code (Channel A)
AVDD = 2.7V
DNL vs. Digital Input Code (Channel B)
AVDD = 2.7V
DNL vs. Digital Input Code (Channel C)
AVDD = 2.7V
SG Micro Corp
www.sg-micro.com
DECEMBER 2021
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16-Bit, 4 Channels, Voltage-Output
Digital-to-Analog Converter
SGM5352-16
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
TA = +25℃, unless otherwise noted.
INL vs. Digital Input Code (Channel D)
DNL vs. Digital Input Code (Channel D)
AVDD = 2.7V
Zero-Scale Error vs. Temperature
AVDD = 2.7V, VREF = 2.69V
Full-Scale Error vs. Temperature
1.5
1
6
4
AVDD = 2.7V, VREF = 2.69V
CHB
CHD
CHC
CHA
2
0.5
0
CHA
0
CHD
CHB
-2
-4
-6
-0.5
-1
CHC
-1.5
-50
-25
0
25
50
75
100 125
-50
-25
0
25
50
75
100 125
Temperature (℃)
Temperature (℃)
Source Current Capability (All Channels)
AVDD = 2.7V, VREF = 2.69V
Supply Current vs. Logic Input Voltage
3.0
2.7
2.4
2.1
1.8
1.5
60
45
30
15
0
IOVDD = AVDD = VREF = 2.7V, TA = +25℃,
SYNC Input (All other inputs = GND),
CHA Powered Up (All other channels in
power-down), Reference Current Included
DAC Loaded with FFFFh
0
2
4
6
8
10
0
0.6
1.2
1.8
2.4
3
ISOURCE (mA)
Logic Input Voltage (V)
SG Micro Corp
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DECEMBER 2021
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16-Bit, 4 Channels, Voltage-Output
Digital-to-Analog Converter
SGM5352-16
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
TA = +25℃, unless otherwise noted.
Full-Scale Settling Time: 2.7V Rising Edge
Trigger Pulse 2.7V/div
Full-Scale Settling Time: 2.7V Falling Edge
Trigger Pulse 2.7V/div
AVDD = 2.7V
REF = 2.5V
V
From Code: FFFF
To Code: 0000
AVDD = 2.7V
V
REF = 2.5V
From Code: 0000
To Code: FFFF
Rising Edge 0.5V/div
Falling Edge 0.5V/div
Time (2μs/div)
Time (2μs/div)
Half-Scale Settling Time: 2.7V Rising Edge
Trigger Pulse 2.7V/div
Half-Scale Settling Time: 2.7V Falling Edge
Trigger Pulse 2.7V/div
AVDD = 2.7V
AVDD = 2.7V
Rising Edge 0.5V/div
Falling Edge 0.5V/div
V
REF = 2.5V
V
REF = 2.5V
From Code: 4000
To Code: CFFF
From Code: CFFF
To Code: 4000
Time (2μs/div)
Time (2μs/div)
Glitch Energy: 2.7V, 1LSB Step, Rising Edge
Glitch Energy: 2.7V, 1LSB Step, Falling Edge
VOUT
VOUT
AVDD = 2.7V
REF = 2.5V
AVDD = 2.7V
VREF = 2.5V
V
From Code: 7FFF
To Code: 8000
From Code: 8000
To Code: 7FFF
Time (2μs/div)
Time (2μs/div)
SG Micro Corp
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DECEMBER 2021
13
16-Bit, 4 Channels, Voltage-Output
Digital-to-Analog Converter
SGM5352-16
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
TA = +25℃, unless otherwise noted.
Glitch Energy: 2.7V, 16LSB Step, Rising Edge
Glitch Energy: 2.7V, 16LSB Step, Falling Edge
VOUT
VOUT
AVDD = 2.7V
REF = 2.5V
AVDD = 2.7V
REF = 2.5V
V
V
From Code: 8000
To Code: 8010
From Code: 8010
To Code: 8000
Time (2μs/div)
Time (2μs/div)
Glitch Energy: 2.7V, 256LSB Step, Rising Edge
Glitch Energy: 2.7V, 256LSB Step, Falling Edge
VOUT
VOUT
AVDD = 2.7V
REF = 2.5V
AVDD = 2.7V
VREF = 2.5V
V
From Code: 8000
To Code: 80FF
From Code: 80FF
To Code: 8000
Time (500ns/div)
Time (500ns/div)
Sink Current Capability (All Channels)
Supply Current vs. Digital Input Code
Reference Current Included
0.12
900
750
600
450
300
150
0
VREF = AVDD - 10mV,
DAC Loaded with 0000h
0.10
0.08
0.06
0.04
0.02
0.00
AVDD = VREF = 5V
AVDD = 2.7V
AVDD = VREF = 2.7V
AVDD = 5.5V
0
2
4
6
8
10
0
16384
32768
49152
65536
Digital Input Code
I/SINK (mA)
SG Micro Corp
www.sg-micro.com
DECEMBER 2021
14
16-Bit, 4 Channels, Voltage-Output
Digital-to-Analog Converter
SGM5352-16
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
TA = +25℃, unless otherwise noted.
Supply Current vs. Temperature
AVDD = VREF = 5V
Supply Current vs. Supply Voltage
600
500
400
300
200
100
0
600
550
500
450
400
350
300
AVDD = VREF, , All DACs Powered,
Reference Current Included, No Load
AVDD = VREF = 2.7V
Reference Current Included
-50
-25
0
25
50
75
100 125
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
Supply Voltage (V)
Temperature (℃)
SG Micro Corp
www.sg-micro.com
DECEMBER 2021
15
16-Bit, 4 Channels, Voltage-Output
Digital-to-Analog Converter
SGM5352-16
FUNCTIONAL BLOCK DIAGRAM
AVDD
IOVDD
DAC
VREFH
Data
VOUTA
VOUTB
VOUTC
VOUTD
DAC A
DAC D
Buffer A
Register A
Data
Buffer D
DAC
Register D
nSYNC
SCLK
Logic Control Unit
Output Control
Network
DIN/OUT
A0 A1 LDAC nENABLE
VREFL
Figure 3. Block Diagram
SG Micro Corp
www.sg-micro.com
DECEMBER 2021
16
16-Bit, 4 Channels, Voltage-Output
Digital-to-Analog Converter
SGM5352-16
DETAILED DESCRIPTION
DAC Section
Input Shift Register
The SGM5352-16 is a 16-bit resistor string DAC, and it has
output buffer amplifier. The input code is unipolar straight
binary, so the ideal output voltage can be calculated based on
the following equation:
Data input register is shown in Figure 4. DB[23:22] are chip
address bits, and they must be matched by the setting of
hardware address pins A1 and A0. If there is no match, the
operation command is ignored. Address matching can be
overridden by the broadcast update. DB[19] is write/read
selection bit. When DB[19] = 0, it means this is a write
operation. When DB[19] = 1, it means this is a read operation.
DB[18:17] are DAC channel select bits. See more details in
Table 2 and Table 3.
DIN
VOUTX = VREFH − VREFL
×
(
)
(1)
65536
Where:
DIN = Decimal equivalent of the binary code, which is loaded
to the DAC register. The range is 0 to 65535.
Table 1. Power-Down Modes
Serial Interface
PD2
PD1
PD0
Operating Mode
(DB[16]) (DB[15]) (DB[14])
The 3-wire serial interface (nSYNC, SCLK, and DIN/OUT) is
compatible with SPI interface standard. The SGM5352-16
supports 3-wire SPI read and write operation. See Figure 1
for an example of a write sequence, and see Figure 2 for an
example of a read sequence.
1
1
1
1
0
0
1
1
0
1
0
1
Output high-impedance
Output typically 1kΩ to GND
Output typically 100kΩ to GND
Output high-impedance
DB[23] DB[22] DB[21] DB[20] DB[19] DB[18] DB[17] DB[16] DB[15] DB[14] DB[13] DB[12] DB[11] DB[10] DB[9] DB[8] DB[7] DB[6] DB[5] DB[4] DB[3] DB[2] DB[1] DB[0]
Channel
Selection
Power-
Down
Address
A1 A0
R/W
RW
MSB
Input Data Signal
D8 D7
LSB
D0
D15/
PD1
D14/
PD0
LD1
LD0
DAC_S[1:0]
PD2
D13
D12
D11
D10
D9
D6
D5
D4
D3
D2
D1
Figure 4. Data Input Register Format
Table 2. Input Register Details
BITS
BIT NAME
DESCRIPTION
COMMENT
DB[23]
DB[22]
A1
A0
Address Bit 1
Address Bit 0
A1 must be matched with the hardware address pin 14.
A0 must be matched with the hardware address pin 13.
Output Load Selection Configuration Bits
00 = Write to DAC buffer and don't load DAC output
01 = Write to DAC buffer and load selected channel
DAC output
DB[21:20]
LD[1:0]
10 = Write to DAC buffer and load all channels DACs
outputs simultaneously
11 = Broadcast modes, see Table 3
When DB[21:20] = "00" and "01", chip corresponds to DB[19]
setting to do write or read operation.
When DB[21:20] = "10" and "11", the operation is only write
command ignoring the DB[19].
Read or Write Operation Selection Bit
0 = It's a write operation to chip
1 = It's a read operation to chip
DB[19]
RW
DAC Channel Selection Bits
00 = DAC channel A
01 = DAC channel B
10 = DAC channel C
11 = DAC channel D
When there is a broadcast command (DB[21:20] = "11"),
these bits are not for DAC channel selection. Details see
Table 3.
DAC_S[1:0]
DB[18:17]
Power-Down Control Bit
0 = Not power-down
1 = Power-down
When there is a broadcast command (DB[21:20] = "11"), this
bit is not dedicated for power-down. Details see Table 3.
DB[16]
PD2
DB[15] is Most Significant Bit (MSB).
DB[15:0]
Data[15:0]
DB[0] is Least Significant Bit (LSB).
When DB[16] = 1, DB[15:14] meanings see Table 1.
SG Micro Corp
www.sg-micro.com
DECEMBER 2021
17
16-Bit, 4 Channels, Voltage-Output
Digital-to-Analog Converter
SGM5352-16
DETAILED DESCRIPTION (continued)
Table 3. Broadcast Modes Description
DB[23] DB[22] DB[21] DB[20] DB[19] DB[18] DB[17] DB[16]
DB[15:0]
Description
Simultaneously update all channels of all
devices in the system with data stored in each
channels temporary register.
X
X
X
X
X
1
1
1
1
1
1
X
X
X
0
1
1
X
X
X
0
0
1
X
Write to all devices and load all DACs with
shifted in data.
Data
Write to all devices and load all DACs with
power-down command in DB[16:14]. See
details in Table 1.
X
X
DB[15:14]
0
X
X
1
1
1
1
X
X
0
0
X
X
1
1
1
0
X
X
X
X
Enable SPI output function.
Disable SPI output function.
X
nSYNC Interrupt
LDAC Functionality
In a normal write/read sequence, the nSYNC line must be
kept low for at least 24 falling edges of SCLK and the DAC is
updated on the 24th falling edge. However, if nSYNC goes
high before the 24th falling edge, this write/read operation is
invalid and ignored. An example is shown in Figure 5.
The SGM5352-16 provides two update functions: software
update mode and hardware update mode.
In software update mode, the LDAC pin must be connected to
GND. The SGM5352-16 data updates are synchronized with
the falling edge of the 24th SCLK cycle (there is a
corresponded LD[1:0] setting), which follows a falling edge of
nSYNC.
Power-On Reset
The SGM5352-16 has a power-on reset circuit, which can
control the output voltage during power-up. On power-up, the
DAC output voltages are 0V.
In hardware update mode, the LDAC pin is used as a positive
edge triggered signal for DAC updates. With a low-to-high
LDAC transition, all DACs are updated with corresponding
DAC register data.
Power-Down Modes
The SGM5352-16 provides flexible power-down modes. It
can be a broadcast power-down command to all the DAC
channels, or it can power down a selected channel and still
update data on other channels. When a channel data is
updated, it exits power-down automatically. Please see Table
2 and Table 3 for power-down operation details.
nENABLE Pin
In normal operation, the enable pin must be set low. When the
enable pin goes high, the SGM5352-16 is not response to
any operation.
24th Falling Edge
SCLK
1
2
nSYNC
Invalid Write/Read nSYNC, nSYNC goes High
before the 24th Falling Edge
DB[23]
DB[22]
DB[0]
DIN/OUT
Figure 5. An Example of Invalid Write/Read nSYNC Timing
SG Micro Corp
www.sg-micro.com
DECEMBER 2021
18
16-Bit, 4 Channels, Voltage-Output
Digital-to-Analog Converter
SGM5352-16
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (DECEMBER 2021) to REV.A
Page
Changed from product preview to production data.............................................................................................................................................All
SG Micro Corp
www.sg-micro.com
DECEMBER 2021
19
PACKAGE INFORMATION
PACKAGE OUTLINE DIMENSIONS
WLCSP-1.64×1.62-16B
0.25
0.19
D
0.4
16 × Φ
A1 CORNER
E
0.4
TOP VIEW
RECOMMENDED LAND PATTERN (Unit: mm)
16 × Φd
3
2
1
4
A
B
C
D
A
e
A1
e
SIDE VIEW
BOTTOM VIEW
Dimensions In Millimeters
Symbol
MIN
MOD
0.580
MAX
0.618
0.214
1.670
1.650
0.288
A
A1
D
E
0.542
0.174
1.620
1.600
0.248
0.194
1.645
1.625
d
0.268
e
0.400 BSC
NOTE: This drawing is subject to change without notice.
SG Micro Corp
TX00231.000
www.sg-micro.com
PACKAGE INFORMATION
PACKAGE OUTLINE DIMENSIONS
TSSOP-16
D
E1
E
5.94
1.78
0.42
e
b
0.65
RECOMMENDED LAND PATTERN (Unit: mm)
L
A
A1
θ
H
c
A2
Dimensions
In Millimeters
Dimensions
In Inches
Symbol
MIN
MAX
MIN
MAX
0.047
0.006
0.041
0.012
0.008
0.201
0.177
0.260
A
A1
A2
b
1.200
0.150
1.050
0.300
0.200
5.100
4.500
6.600
0.050
0.800
0.190
0.090
4.860
4.300
6.200
0.002
0.031
0.007
0.004
0.191
0.169
0.244
c
D
E
E1
e
0.650 BSC
0.25 TYP
0.026 BSC
0.01 TYP
L
0.500
1°
0.700
7°
0.02
1°
0.028
7°
H
θ
NOTES:
1. Body dimensions do not include mode flash or protrusion.
2. This drawing is subject to change without notice.
SG Micro Corp
TX00020.001
www.sg-micro.com
PACKAGE INFORMATION
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
P2
P0
W
Q2
Q4
Q2
Q4
Q2
Q4
Q1
Q3
Q1
Q3
Q1
Q3
B0
Reel Diameter
P1
A0
K0
Reel Width (W1)
DIRECTION OF FEED
NOTE: The picture is only for reference. Please make the object as the standard.
KEY PARAMETER LIST OF TAPE AND REEL
Reel Width
Reel
Diameter
A0
B0
K0
P0
P1
P2
W
Pin1
Package Type
W1
(mm)
(mm) (mm) (mm) (mm) (mm) (mm) (mm) Quadrant
WLCSP-1.64×1.62-16B
TSSOP-16
7″
9.5
1.81
6.90
1.81
5.60
0.76
1.20
4.0
4.0
4.0
8.0
2.0
2.0
8.0
Q1
Q1
13″
12.4
12.0
SG Micro Corp
TX10000.000
www.sg-micro.com
PACKAGE INFORMATION
CARTON BOX DIMENSIONS
NOTE: The picture is only for reference. Please make the object as the standard.
KEY PARAMETER LIST OF CARTON BOX
Length
(mm)
Width
(mm)
Height
(mm)
Reel Type
Pizza/Carton
7″ (Option)
368
442
386
227
410
280
224
224
370
8
18
5
7″
13″
SG Micro Corp
www.sg-micro.com
TX20000.000
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