SGM58031 [SGMICRO]
Ultra-Small, Low-Power, 16-Bit Analog-to-Digital Converter with Internal Reference;
| 型号： | SGM58031 |
| 厂家： | 
Shengbang Microelectronics Co, Ltd |
| 描述： | Ultra-Small, Low-Power, 16-Bit Analog-to-Digital Converter with Internal Reference |
| 文件： | 总27页 (文件大小：980K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SGM58031
Ultra-Small, Low-Power, 16-Bit
Analog-to-DigitalConverterwithInternalReference
GENERAL DESCRIPTION
FEATURES
The SGM58031 is a low-power, 16-bit, precision,
delta-sigma (ΔΣ) analog-to-digital converter (ADC). It
operates from a 3V to 5.5V supply.
● Single-Supply Voltage Range: 3V to 5.5V
I2C Bus Voltage Range: 3V to 5.5V
● Low Quiescent Current:
Continuous Mode: 255μA (TYP)
Power-Down Mode: 0.8μA (TYP)
The SGM58031 contains an on-chip reference and
oscillator. It has an I2C-compatible interface, and it can
select four I2C slave addresses. The data rate of the
filter is up to 960SPS. The SGM58031 has an on-chip
PGA, which can provide input ranges to as low as
±256mV from the power supply.
● Selectable Data Rates: 6.25SPS to 960SPS
● Input Multiplexer
4 Single-Ended Inputs or 2 Differential Inputs
● Internal Programmable Gain Amplifier (PGA)
● Internal Voltage Reference and Oscillator
● Selectable Digital Comparator
● I2C-Compatible Serial Interface
● Available in Green MSOP-10 and TDFN-3×3-10L
Packages
The input multiplexer supports 4 single-ended inputs or
2 differential inputs configuration.
The SGM58031 is available in Green MSOP-10 and
TDFN-3×3-10L packages. It operates over an ambient
temperature range of -40℃ to +125℃.
APPLICATIONS
Portable Devices
Process Control
Battery Monitoring System
Temperature Measurement
SG Micro Corp
MAY 2023 – REV. A. 3
www.sg-micro.com
Ultra-Small, Low-Power, 16-Bit
SGM58031
Analog-to-Digital Converter with Internal Reference
PACKAGE/ORDERING INFORMATION
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESCRIPTION
ORDERING
NUMBER
PACKAGE
MARKING
PACKING
OPTION
MODEL
SGM58031
XMS10
XXXXX
MSOP-10
-40℃ to +125℃
-40℃ to +125℃
SGM58031XMS10G/TR
Tape and Reel, 4000
Tape and Reel, 4000
SGM58031
SGM
58031D
XXXXX
TDFN-3×3-10L
SGM58031XTD10G/TR
MARKING INFORMATION
NOTE: XXXXX = Date Code, Trace Code and Vendor Code.
X X X X X
Vendor Code
Trace Code
Date Code - Year
Green (RoHS & HSF): SG Micro Corp defines "Green" to mean Pb-Free (RoHS compatible) and free of halogen substances. If
you have additional comments or questions, please contact your SGMICRO representative directly.
OVERSTRESS CAUTION
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed in Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods
may affect reliability. Functional operation of the device at any
conditions beyond those indicated in the Recommended
Operating Conditions section is not implied.
Voltage Range (with Respect to GND)
V
DD .................................................................. -0.3V to 5.5V
Analog Input Voltage....................................... -0.3V to 5.5V
SDA, SCL, ADDR, ALERT/RDY Voltage ........ -0.3V to 5.5V
Input Current (Momentary)..........................................100mA
Input Current (Continuous) ...........................................10mA
Junction Temperature.................................................+150℃
Storage Temperature Range........................-65℃ to +150℃
Lead Temperature (Soldering, 10s)............................+260℃
ESD Susceptibility
ESD SENSITIVITY CAUTION
This integrated circuit can be damaged if ESD protections are
not considered carefully. SGMICRO recommends that all
integrated circuits be handled with appropriate precautions.
Failureto observe proper handlingand installation procedures
can cause damage. ESD damage can range from subtle
performance degradation tocomplete device failure. Precision
integrated circuits may be more susceptible to damage
because even small parametric changes could cause the
device not to meet the published specifications.
HBM.............................................................................4000V
CDM ............................................................................1000V
RECOMMENDED OPERATING CONDITIONS
Operating Temperature Range.....................-40℃ to +125℃
DISCLAIMER
SG Micro Corp reserves the right to make any change in
circuit design, or specifications without prior notice.
SG Micro Corp
www.sg-micro.com
MAY 2023
2
Ultra-Small, Low-Power, 16-Bit
SGM58031
Analog-to-Digital Converter with Internal Reference
PIN CONFIGURATIONS
(TOP VIEW)
(TOP VIEW)
1
2
3
4
5
10
9
ADDR
ALERT/RDY
GND
SCL
ADDR
ALERT/RDY
GND
1
2
3
4
5
10 SCL
SDA
9
8
7
6
SDA
8
VDD
EP
VDD
AIN3/VREFIN
AIN2
AIN0
7
AIN0
AIN3/VREFIN
AIN2
AIN1
6
AIN1
MSOP-10
TDFN-3×3-10L
FUNCTION
PIN DESCRIPTION
PIN
NAME
TYPE (1)
MSOP-10
TDFN-3×3-10L
1
2
3
1
2
3
ADDR
DI
DO
G
I2C Address Selection Pin.
ALERT/RDY
GND
Digital Comparator Output/Conversion Ready Pin.
Ground.
Positive Input of Differential Channel
Single-Ended Channel 1.
1
or Input of
or Input of
or Input of
or Input of
4
5
6
7
4
5
6
7
AIN0
AIN1
AI
AI
AI
AI
Negative Input of Differential Channel
Single-Ended Channel 2.
1
Positive Input of Differential Channel
Single-Ended Channel 3.
2
AIN2
Negative Input of Differential Channel
Single-Ended Channel 4, or External Reference Input.
2
AIN3/VREFIN
8
9
8
9
VDD
SDA
SCL
P
DIO
DI
Power Supply Pin. It can be operated from 3V to 5.5V.
Serial Data Pin.
10
10
Serial Clock Input Pin.
Exposed pad should be soldered to PCB board and
connected to GND.
‒
Exposed Pad
EP
‒
NOTE:
1. AI = Analog Input, DI = Digital Input, DO = Digital Output, DIO = Digital Input and Output, P = Power, G = Ground.
SG Micro Corp
www.sg-micro.com
MAY 2023
3
Ultra-Small, Low-Power, 16-Bit
SGM58031
Analog-to-Digital Converter with Internal Reference
ELECTRICAL CHARACTERISTICS
(VDD = 3.3V, Full-Scale (FS) = ±2.048V, maximum and minimum specifications apply from TA = -40℃ to +125℃, typical values
are at TA = +25℃, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Analog Input
Full-Scale Input Voltage (1)
Analog Input Voltage
Differential Input Impedance
System Performance
Resolution
VIN = AINP - AINN
±4.096/PGA
See Table 1
V
V
AINP or AINN to GND
GND
VDD
No missing codes
All data rates
16
-6
Bits
SPS
%
Data Rate
DR
INL
See Table 5
Data Rate Variation
Output Noise
6
See Table 6 and Table 7
DR = 8SPS, FS = ±2.048V,
best fit (99% of full-scale)
Integral Nonlinearity
Offset Error
1
1
4
5
LSB
LSB
differential inputs
single-ended inputs
FS = ±2.048V
2
0.005
1.2
0.03
30
8.5
Offset Drift
FS = ±2.048V
FS = ±2.048V
0.06
LSB/℃
LSB/V
%
Offset Power-Supply Rejection
Gain Error (2)
0.3
70
FS = ±2.048V at +25℃
FS = ±0.256V
Gain Drift (3)
FS = ±2.048V
30
ppm/℃
FS = ±6.144V (1)
30
Gain Power-Supply Rejection
PGA Gain Match (2)
Gain Match
50
200
0.28
0.08
8.5
ppm/V
%
Match between any two PGA gains
Match between any two inputs
Match between any two gains
FS = ±2.048V
0.1
0.01
1
%
Offset Match
LSB
dB
50/60Hz Rejection
95
At DC and FS = ±2.048V, differential or
single-ended inputs adjacent channels
Channel-to-Channel Crosstalk
90
dB
At DC and FS = ±0.256V
At DC and FS = ±2.048V
At DC and FS = ±6.144V (1)
110
110
110
Common-Mode Rejection Ratio
CMRR
dB
Internal Clock
Frequency
386
410
434
kHz
NOTES:
1. The full-scale range of the ADC scaling. In any event, it should not exceed VDD + 0.3V be applied to this device.
2. It includes all errors from on-chip PGA and reference.
3. Gain temperature drift is defined as the maximum change of gain error measured over the specified temperature range. The
gain error drift is calculated using the box method, as described by Equation: Gain Error Drift = (GEMAX - GEMIN)/(TMAX - TMIN).
Where:
• GEMAX and GEMIN are the maximum and minimum gain errors, respectively.
• TMAX and TMIN are the maximum and minimum temperatures, respectively, over the temperature range -40℃ to +125℃.
SG Micro Corp
www.sg-micro.com
MAY 2023
4
Ultra-Small, Low-Power, 16-Bit
SGM58031
Analog-to-Digital Converter with Internal Reference
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, Full-Scale (FS) = ±2.048V, maximum and minimum specifications apply from TA = -40℃ to +125℃, typical values
are at TA = +25℃, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Reference
Internal Reference
External Reference
2.048
V
V
0.5
2.5
External Reference Input
Current
VREFIN = 2.5V, continuous mode
0.45
μA
Digital Input/Output
High Input Voltage (4)
Low Input Voltage (4)
VIH
VIL
VOL
IIH
0.7 × VBUS
V
V
0.3 × VBUS
Low Output Voltage
IOL = 3mA
VIH = 5.5V
VIL = GND
0.07
0.1
0.4
1
V
High Input Leakage Current (5)
Low Input Leakage Current (5)
Power-Supply Requirements
Power-Supply Voltage
μA
μA
IIL
0.1
1
VDD
3
5.5
1
V
(6)
Power-down current at +25℃
0.8
1.8
(6)
Power-down current up to +125℃
Operating current at +25℃
3.8
320
340
Supply Current
IDD
VDD = 5.5V
μA
255
270
1.05
0.6
Operating current up to +125℃
VDD = 5V
Power Dissipation
NOTES:
PD
mW
VDD = 3.3V
4. There are 2 scenarios: VDD = 5V, VBUS can be 3V to 5V; VDD = 3.3V, VBUS should be 3.3V. Note that VBUS = 3V may cause
leakage in some extreme conditions, and it's better to make it higher than 3.1V. For VBUS = VDD, VIL/VIH = 30%/70% of VBUS. For
V
BUS = 3.3V and VDD = 5V, VIL/VIH = 20%/80% of VBUS.
5. Meet the "loss of VDD" requirement of I2C fast mode. When VDD is lost, the leakage drawn from the pin is controlled.
6. Power-down current increases to 2.3μA at +25℃ and 3.5μA at +125℃ when Config1 BUS_FLEX bit is set to '1'.
SG Micro Corp
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MAY 2023
5
Ultra-Small, Low-Power, 16-Bit
SGM58031
Analog-to-Digital Converter with Internal Reference
TIMING CHARACTERISTICS
STANDARD MODE
FAST MODE
HIGH-SPEED MODE
PARAMETER
SYMBOL
fSCL
t1
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
SCL Operating Frequency
0.01
0.1
0.01
0.4
0.01
3.4
MHz
ns
Bus Free Time between START and STOP
Condition
4700
4000
600
600
160
160
Hold Time after Repeated START Condition.
After This Period, the First Clock is Generated
t2
ns
SCL Clock Low Time
t3
t7
t9
4700
4000
4700
4000
0
1300
600
600
600
0
160
60
ns
ns
ns
ns
ns
ns
ns
ns
SCL Clock High Time
Repeated START Condition Setup Time
Stop Condition Setup Time
Data Hold Time
160
160
0
t10
t5
t8
Data Setup Time
Clock/Data Fall Time (1)
250
100
10
t6
300
300
300
160
160
Clock/Data Rise Time
t4
1000
NOTE:
1. t6 (MIN) for SDA output is 20ns for normal/fast mode and 10ns for high-speed mode. Glitch filter capability is 50ns for
normal/fast mode and 10ns for high-speed mode.
S
S
P
t8
t3
t6
t2
SCL
SDA
t7
t9
t4
t10
t2
t5
t1
Figure 1. I2C Timing Diagram
SG Micro Corp
www.sg-micro.com
MAY 2023
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Ultra-Small, Low-Power, 16-Bit
SGM58031
Analog-to-Digital Converter with Internal Reference
TYPICAL PERFORMANCE CHARACTERISTICS
TA = +25℃, VDD = 3.3V, Data Rate = 200SPS and Full-Scale (FS) = ±2.048V, unless otherwise noted.
Gain Error Histogram
Offset Error Histogram
2500
2000
1500
1000
500
3500
3000
2500
2000
1500
1000
500
3926 Units From
a Production Lot
FS = ±2.048V,
Differential Inputs
3926 UnitsFrom a Production Lot
FS = ±2.048V
0
0
-5 -4 -3 -2 -1
0
1
2
3
4
5
Offset Error (LSB)
Gain Error (%)
Operating Current vs. Temperature
Power-Down Current vs. Temperature
300
250
200
150
100
50
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
VDD = 3V
VDD = 3V
V
V
DD = 3.3V
DD = 5.5V
V
V
DD = 3.3V
DD = 5.5V
0
-50 -35 -20 -5 10 25 40 55 70 85 100 115 130
-50 -35 -20 -5 10 25 40 55 70 85 100 115 130
Temperature (℃)
Temperature (℃)
Single-Ended Offset Error vs. Temperature
VDD = 3.3V
Differential Offset Error vs. Temperature
0.5
0.0
0.5
0.0
V
DD = 5V
-0.5
-1.0
-1.5
-2.0
-0.5
-1.0
-1.5
-2.0
VDD = 3.3V
DD = 5V
V
-50 -35 -20 -5 10 25 40 55 70 85 100 115 130
-50 -35 -20 -5 10 25 40 55 70 85 100 115 130
Temperature (℃)
Temperature (℃)
SG Micro Corp
MAY 2023
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7
Ultra-Small, Low-Power, 16-Bit
SGM58031
Analog-to-Digital Converter with Internal Reference
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
TA = +25℃, VDD = 3.3V, Data Rate = 200SPS and Full-Scale (FS) = ±2.048V, unless otherwise noted.
INL vs. Temperature
Internal Oscillator Frequency vs. Temperature
412.5
412.0
411.5
411.0
410.5
410.0
409.5
409.0
408.5
2.0
1.5
1.0
0.5
0.0
VDD = 3.3V
VDD = 3.3V
DD = 5V
CVDD = 100nF
IN = 100nF
V
C
-40 -20
0
20 40 60 80 100 120 140
-50 -35 -20 -5 10 25 40 55 70 85 100 115 130
Temperature (℃)
Temperature (℃)
Gain Error vs. Temperature
Filter Response
Data Rate = 6.25
0
0.45
0.4
FS = ±2.048V
CVDD = 100nF
-20
-40
0.35
0.3
CIN = 100nF
0.25
0.2
-60
0.15
0.1
-80
0.05
0
-100
-120
VDD = 3.3V
DD = 5V
V
-0.05
-40 -20
0
20 40 60 80 100 120 140
0
10 20 30 40 50 60 70 80 90 100
Temperature (℃)
Frequency (Hz)
Filter Response
Data Rate = 12.5
Filter Response
Data Rate = 25
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
10 20 30 40 50 60 70 80 90 100
0
10 20 30 40 50 60 70 80 90 100
Frequency (Hz)
Frequency (Hz)
SG Micro Corp
MAY 2023
www.sg-micro.com
8
Ultra-Small, Low-Power, 16-Bit
SGM58031
Analog-to-Digital Converter with Internal Reference
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
TA = +25℃, VDD = 3.3V, Data Rate = 200SPS and Full-Scale (FS) = ±2.048V, unless otherwise noted.
Filter Response
0
Data Rate = 50
-20
-40
-60
-80
-100
-120
0
20 40 60 80 100 120 140 160 180 200
Frequency (Hz)
SG Micro Corp
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MAY 2023
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Ultra-Small, Low-Power, 16-Bit
SGM58031
Analog-to-Digital Converter with Internal Reference
FUNCTIONAL BLOCK DIAGRAM
VDD
Comparator
Oscillator
MUX
ALERT/RDY
AIN0
AIN1
Gain = 2/3, 1, 2, 4, 8
or 16
ADDR
SCL
I2C
Interface
16-Bit ΔΣ
ADC
PGA
SDA
AIN2
AIN3/VREFIN
Voltage
Reference
SGM58031
GND
Figure 2. Functional Block Diagram
SG Micro Corp
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MAY 2023
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Ultra-Small, Low-Power, 16-Bit
SGM58031
Analog-to-Digital Converter with Internal Reference
DETAILED DESCRIPTION
For example, writing to the configuration register 0x01 sets
the SGM58031 to continuous conversion mode, we need the
following order:
Overview
The SGM58031 is a low-power, 16-bit, delta-sigma (ΔΣ)
analog-to-digital converter (ADC).
1. First byte, 0b1001000 (first 7-bit is I2C address), the 8th bit
is read/write bit which is low writing now
The SGM58031 supports both differential inputs and
single-ended inputs.
2. Second byte, 0b00000001 (points to Config register 0x01)
3. Third byte, 0b10000100 (MSB of the Config register to be
written, Bit[8] = 0 means the continuous mode)
The SGM58031 has two working modes: single-shot mode
and continuous conversion mode.
In single-shot mode, the ADC performs one conversion and
gives full settled data, no data needs to be discarded. Once
ADC completes the conversion, it then goes to low-power
shutdown mode.
4. Fourth byte, 0b10000011 (LSB of the Config register to be
written, Bit[7:5] = '100' means data rate 100Hz)
For example, to read the conversion result from SGM58031,
the following order can be followed:
In continuous modes, the ADC begins a new conversion
automatically after a previous conversion is completed. Every
conversion result is given out. The data rate is equal to the
configured data rate.
1. First byte, 0b1001000 (first 7-bit is I2C address), the 8th bit
is read/write bit which is low writing now
2. Second byte, 0b00000000 (points to Conversion register
0x00)
3. Third byte, 0b10010001 (first 7-bit is I2C address), the 8th
bit is read/write bit which is high reading now
4. Fourth byte, the SGM58031 answer with the MSB of the
Conversion register
Quickstart Guide
The basic connection of ADC is shown in Figure 3. The
communication interface is I2C compatible. The SGM58031
works in slave mode. The I2C address is configured as
0b1001000 (ADDR is connected to GND).
5. Fifth byte, the SGM58031 answer with the LSB of the
Conversion register
Figure 4 and Figure 5 show a demo read and write operation
sequence.
+3.3V
VDD
100nF
+3.3V
GND
ADDR
AIN0
AIN1
I2C-Capable Master
+3.3V
10kΩ 10kΩ
10kΩ
SGM58031
AIN2
VDD
SCL
SDA
SCL
100nF
AIN3/VREFIN
SDA
GND
ALERT/RDY
INT (Optional)
Figure 3. Basic Hardware Configuration
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Ultra-Small, Low-Power, 16-Bit
SGM58031
Analog-to-Digital Converter with Internal Reference
DETAILED DESCRIPTION (continued)
Frame 1
Frame 2
1
9
1
0
9
SCL
SDA
1
0
0
1
0
A1(1) A0(1)
0
0
0
0
P2
P1
P0
W
Byte#2 I2C Point Address Byte
ACK by
Device
STOP by
Master
Byte#1 I2C Slave Address Byte
ACK by
Device
START by
Master
Frame 3
Frame 4
1
1
9
1
9
SCL
(Continued)
0
0
1
0
A1(1) A0(1)
D15 D14 D13 D12 D11 D10 D9
D8
SDA
(Continued)
R
START by
Master
Byte#3 I2C Slave Address Byte
Byte#4 Data Byte 1 from Device
ACK by
Master (2)
ACK by
Device
Frame 5
1
9
SCL
(Continued)
SDA
(Continued)
D7
D6
D5
D4
D3
D2
D1
D0
Byte#5 Data Byte 2 from Device
ACK by
STOP by
Master
Master (3)
NOTES:
1. The A0 and A1 values depend on the ADDR pin.
2. SDA can be set high by master to terminate a single-byte read operation.
3. SDA can be set high by master to terminate a two-byte read operation.
Figure 4. Timing Diagram for Read Word Register
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Ultra-Small, Low-Power, 16-Bit
SGM58031
Analog-to-Digital Converter with Internal Reference
DETAILED DESCRIPTION (continued)
Frame 1
Frame 2
1
9
1
0
9
SCL
SDA
1
0
0
1
0
A1(1) A0(1)
0
0
0
0
P2
P1
P0
W
Byte#2 I2C Point Address Byte
ACK by
Device
Byte#1 I2C Slave Address Byte
START by
Master
ACK by
Device
Frame 3
Frame 4
1
9
1
9
SCL
(Continued)
SDA
(Continued)
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Byte#3 Data Byte 1 to
SGM58031 Register
ACK by
Device
Byte#4 Data Byte 2 to
SGM58031 Register
ACK by
Device
STOP by
Master
NOTE:
1. The A0 and A1 values depend on the ADDR pin.
Figure 5. Timing Diagram for Write Word Register
S1
Multiplexer
The SGM58031 has a flexible input multiplexer. It can be
AINP
S
Equivalent
Circuit
2
AINP
configured as 2 differential inputs or 4 single-ended inputs.
ZDIFF
CB
AINN
2
fCLK = 61.4kHz
Whether the input is configured as differential inputs or
single-ended inputs, the absolute voltage on any inputs pin
S
AINN
S1
must be in the range from GND to VDD
.
Figure 6. Simplified Analog Input Circuit
Table 1. Differential Input Impedance
Analog Inputs
The SGM58031 has a switched capacitor input stage. There
FS (V)
±6.144V (1)
±4.096V (1)
±2.048V
±1.024V
±0.512V
±0.256V
Differential Input Impedance
are charge and discharge current when ADC is working. The
37.5MΩ
25MΩ
equal effective input impedance can be estimated by REFF
VIN/IAVERAGE
=
.
12.5MΩ
6.25MΩ
6.25MΩ
6.25MΩ
The differential input impedance is ZDIFF in Figure 6. Table 1
shows the typical differential input impedance.
NOTE:
1. FS = Full-scale range of the ADC scaling. In any event, it should
not exceed VDD + 0.3V be applied to this device.
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MAY 2023
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Ultra-Small, Low-Power, 16-Bit
SGM58031
Analog-to-Digital Converter with Internal Reference
DETAILED DESCRIPTION (continued)
Full-Scale Input
Aliasing
The SGM58031 has an internal PGA. The PGA can be set to
gains of 2/3, 1, 2, 4, 8 or 16. Table 2 and Table 3 show the
corresponding full-scale (FS) ranges.
For some applications, an RC external filtering is recommended.
Operating Modes
The SGM58031 has two working modes, continuous mode
Analog input voltages can never exceed the analog input
voltage limits.
and single-shot mode.
In continuous mode, the ADC begins a new conversion
automatically after a previous conversion is completed. Every
conversion result is given out.
Table 2. PGA Gain Full-Scale Range with Internal Reference
PGA Setting
FS (V)
±6.144V (1)
±4.096V (1)
±2.048V
±1.024V
±0.512V
±0.256V
2/3
1
In single-shot mode, if OS bit is written to '1', a single-shot
conversion is started, during the conversion process, the OS
bit is kept '0', and the chip doesn't response to OS bit
operation. If conversion data is ready, the OS bit is set to '1'
and the chip goes power-down automatically, and user can
write '1' to OS bit to call a single-shot conversion again.
2
4
8
16
NOTE:
Power-Up and Reset
When the SGM58031 is powered up, all registers are reset to
1. FS = Full-scale range of the ADC scaling. In any event, it should
not exceed VDD + 0.3V be applied to this device.
default values.
The SGM58031 supports I2C general call reset command.
Details see I2C General Call section.
Table 3. PGA Gain Full-Scale Range with External Reference
PGA Setting
FS (V)
±3×VREF
±2×VREF
±VREF
2/3
1
Duty Cycling for Low Power
In some power sensitive application, the SGM58031 can work
in sampling and power-down mode periodically. The duty
cycle of working time and power-down time can be controlled
by microcontroller flexibly.
2
4
±VREF/2
±VREF/4
±VREF/8
8
16
For example, if the SGM58031 is configured as sample data
rate at 960Hz, we can operate it with 125ms duty cycle. It
means that we call the chip do single-shot conversion every
125ms, it will take the chip 3.2ms for sampling and then stay
in power-down mode for 121.8ms. Under this working mode,
it will reduce 39/40 power consumption compare with 960Hz
operation in continuous mode.
Data Format
The SGM58031 conversion result data is in binary two's
complement format.
Table 4 shows the ideal output codes for different input
signals.
Table 4. Ideal Output Code for Different Input Signals
Input Signal VIN (AINP - AINN)
Ideal Output Code (1)
≥ FS (215 - 1)/215
7FFFh
0001h
0
+FS/215
0
-FS/215
≤ -FS
FFFFh
8000h
NOTE:
1. Except for effects of INL, noise, offset, and gain errors.
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Ultra-Small, Low-Power, 16-Bit
SGM58031
Analog-to-Digital Converter with Internal Reference
DETAILED DESCRIPTION (continued)
Input
Signal
Data Rate
Table 5. ADC Output Data Rate (SPS)
High_Threshold
Low_Threshold
DR_SEL Bit in Config1 Register
DR[2:0] Bits
in Config Register
DR_SEL = 0
6.25Hz
12.5Hz
25Hz
DR_SEL = 1
Time
000
001
010
011
100
101
110
111
7.5Hz
SMBus Alert
Response
Completed
15Hz
Latching
Comparator
Output
30Hz
50Hz
60Hz
100Hz
200Hz
400Hz
800Hz
120Hz
240Hz
480Hz
960HZ
Time
Non-Latching
Comparator
Output
Comparator
The SGM58031 has an inside comparator that can be used to
check ADC conversion results with high threshold and low
threshold. When the result exceeds the limited setting, the
chip can give an alert on the ALERT/RDY pin.
Time
Figure 7. Alert Pin Timing Diagram when Configured as A
Traditional Comparator
The comparator has two workings modes: traditional mode
and window comparator mode. These modes are
configurable. Under both working modes, the comparator can
be configured as latch output or no-latch output (COMP_LAT
bit in Config register). In latch output mode, the latched
comparator output can be cleared by issuing an SMBus alert
response or by reading the Conversion register. The
ALERT/RDY pin output active polarity (low or high) can be
configured by COMP_POL bit in Config register. Demos are
shown in Figure 7 and Figure 8.
Input
Signal
High_Threshold
Low_Threshold
Time
SMBus Alert
Response
Completed
SMBus Alert
Response
Completed
Latching
Comparator
Output
The comparator output trigger waiting times can be set by
COMP_QUE[1:0] in Config register. It means comparator
output can wait until the ADC results beyond the threshold
configured times (which can be one, two, or four times).
Details see Config Register section.
Time
Non-Latching
Comparator
Output
Time
Figure 8. Alert Pin Timing Diagram when Configured as A
Window Comparator
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Ultra-Small, Low-Power, 16-Bit
SGM58031
Analog-to-Digital Converter with Internal Reference
DETAILED DESCRIPTION (continued)
ADC Noise
Table 6. ADC Noise with Internal Reference (RMS in μV)
DR
800
400
200
100
50
25
12.5
6.25
FS
6.144
4.096
2.048
1.024
0.512
0.256
187.5
125
187.5
125
187.5
125
187.5
125
187.5
125
187.5
125
187.5
125
187.5
125
62.5
62.5
62.5
62.5
62.5
62.5
62.5
62.5
31.25
15.62
7.81
31.25
15.62
7.81
31.25
15.62
7.81
31.25
15.62
7.81
31.25
15.62
7.81
31.25
15.62
7.81
31.25
15.62
7.81
31.25
15.62
7.81
Table 7. ADC ENOB (ENOB = (20log (FS/Noise_RMS) - 1.76)/6.02)
DR
800
400
200
100
50
25
12.5
6.25
FS
6.144
4.096
2.048
1.024
0.512
0.256
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Conversion Ready Pin
60, 50, 30, 25, 15, 12.5, 7.5 and 6.25, the device uses a
third-order Sinc filter (Sinc3). When data rate is configured as
200, 240, 400, 480, 800 and 960, the device uses a
fourth-order Sinc filter (Sinc4).
If ALERT/RDY pin is used as a conversion ready pin, we need
the following operations, firstly set the MSB (Most Significant
Bit) of the high threshold register to '1', secondly set the MSB of
the low threshold register to '0', and select COMP_QUE[1:0] in
'00' mode. It should be noted that COMP_QUE[1:0] can
disable this pin function. COMP_MODE and COMP_LAT have
no affection on this function.
When ALERT/RDY is used as the conversion completed
indication pin, its default logic state is high (pulled up by the
external resistor) during the conversion. When the device
works in continuous mode, the ALERT/RDY pin will go low
and remain low for about 8μs, generating an 8μs logic low
pulse at the end of each conversion cycle. When the device
works in single-shot mode and the Sinc3 filter is used, the
ALERT/RDY pin will go logic low after the third data
conversion is finished and remain low until the device begins
the next new conversion (OS bit is set to '1' again), and the
ALERT/RDY pin goes logic high again during the new
conversion. When the device works in single-shot mode and
the Sinc4 filter is used, the ALERT/RDY pin will go low after
the fourth data conversion is finished and remain low until the
device begins the next new conversion (OS bit is set to '1'
again), and the ALERT/RDY pin goes logic high again during
the new conversion. Please see ALERT/RDY examples in
Figure 9 and Figure 10.
The ALERT/RDY pin is an open-drain output, it needs a pull-up
resistor outside.
When the SGM58031 works in continuous mode, the
ALERT/RDY pin gives a pulse (~8μs) at the end of every
conversion completion.
When the SGM58031 works in single-shot mode, the
ALERT/RDY pin goes low (COMP_POL is set to '0') when the
conversion data is ready, and keeps low until the next
conversion starts. Please see demos in Figure 9 and Figure 10.
Digital Filter
The devices offer digital filter for filtering the digital data
stream coming from the delta-sigma modulator. The
implementation of the digital filter is determined by the ADC
data rate setting. When data rate is configured as 120, 100,
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Ultra-Small, Low-Power, 16-Bit
SGM58031
Analog-to-Digital Converter with Internal Reference
DETAILED DESCRIPTION (continued)
SMBus Alert Response
In a multiple I2C devices system, two scenarios about clearing
an alert on ALERT/RDY pin need to be noted. The first
scenario is, when clearing an alert on ALERT/RDY pin of
SGM58031 by sending a SMBus alert command (0x19), it
must be committed that there is only one SGM58031 device
in the system, meanwhile make sure that SGM58031 keeps
the lowest address. Another scenario is, when clearing an
alert on ALERT/RDY pin of SGM58031 by reading data
register (0x00) of SGM58031, it needs to be committed that
there are multiple SGM58031 chips in the system
(SGM58031s' data registers need to be read one by one) or
only one SGM58031 chip in the system.
The ALERT/RDY pin can output as an SMBus alert. When it’s
in latch mode, COMP_LAT is set to '1'. If an ADC result is
above the upper threshold or below the lower threshold, this
pin is set (active low or active high). And the pin output is
latched, it can be cleared by reading ADC conversion data, or
by issuing an SMBus alert response (reading the alerting
device I2C address).
The ALERT/RDY pin is an open-drain output, it needs a
pull-up resistor.
If an alert is output at the ALERT/RDY pin and latched, the
master controller accepts the alert, it sent an SMBus alert
command (0b00011001) to I2C bus. Any SGM58031 on the
bus will response with their own address, the lowest I2C
address chip will occupy the bus and it will clear itself
ALERT/RDY pin, the chip which loses I2C bus will keep alert
on ALERT/RDY pin. The master will repeat SMBus alert
command until all salve chips clear their alert.
When ALERT/RDY pin is configured as window comparator
mode, if ADC result is higher than upper threshold or ADC
result is below the lower threshold, the pin is set (active low or
active high).
Timing diagram for SMBus alert response is shown in Figure
11.
1 conversion cycle
RDY
8μs
Figure 9. RDY in Continuous Mode
3 or 4 Conversion Cycles
RDY
Previous data is ready
New conversion start
and 'OS' is set to '1'
Data is ready
Figure 10. RDY in Single-Shot Mode
ALERT
Frame 1
Frame 2
1
9
1
1
9
SCL
SDA
0
0
0
1
1
0
0
0
0
1
0
A1
A0 Status
R/W
Byte#1 SMBus Alert Response Address Byte
ACK by
Device
START by
Master
Byte#2 Slave Address from Device
NACK by
Master
STOP by
Master
NOTE: 1. The A0 and A1 values depend on the ADDR pin.
Figure 11. Timing Diagram for SMBus Alert Response
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Ultra-Small, Low-Power, 16-Bit
SGM58031
Analog-to-Digital Converter with Internal Reference
DETAILED DESCRIPTION (continued)
I2C Interface
I2C General Call
The SGM58031 communication interface is an I2C interface.
The SGM58031 can only act as slave devices. An I2C timing
diagram is shown in Figure 1.
The SGM58031 supports I2C general call address (0000000)
and the eighth bit must be '0'. The device acknowledges the
general call address. And if the second byte is 00000110
(06h), the SGM58031 resets all registers and goes to
power-down.
I2C Address Selection
The SGM58031 has a separate address setting pin ADDR,
which can be connected to GND, VDD, SDA and SCL. Table 8
shows the four available addresses.
I2C Speed Modes
The I2C bus operation supports three speed modes: Standard
mode, fast mode, and high-speed mode. See more details in
Electrical Characteristics section.
Table 8. ADDR Pin Connection and Corresponding Slave
Address
To enter standard and fast mode, it needs no special
operation.
ADDR Pin
GND
Slave Address
1001000
To enter high-speed mode, send a special address byte of
00001XXX following the I2C start condition. The SGM58031
doesn't give an ACK (acknowledge) to this byte, the
SGM58031 switches to high-speed mode after receiving this
byte. The SGM58031 quits high-speed mode with the next
STOP condition.
VDD
1001001
SDA
1001010
SCL
1001011
Slave Mode Operations
The SGM58031 works in slave mode and doesn't drive the
SCL line.
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Ultra-Small, Low-Power, 16-Bit
SGM58031
Analog-to-Digital Converter with Internal Reference
REGISTER MAPS
Table 9. Register Address
Register Address
The SGM58031 has seven pointer registers. Table 9 and
Table 10 shows these register maps. Figure 4 shows how to
access this pointer registers.
Address
0x0
Register
Conversion Register
0x1
Config Register
0x2
Low_Thresh Register
High_Thresh Register
Config1 Register
0x3
0x4
0x5
Chip_ID Register
0x6
GN_Trim1 Register for EXT_REF
Pointer Register
Table 10. Pointer Register Byte (Write-Only)
MSB
LSB
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
0
0
0
0
0
Register Address
Conversion Register
The ADC conversion result is 16-bit two's complement format. Table 11 shows the data format. Its reset default value is '0'.
Table 11. 16-Bit Conversion Register (Read-Only)
MSB
LSB
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NOTE: Default Value = 0000h.
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Ultra-Small, Low-Power, 16-Bit
SGM58031
Analog-to-Digital Converter with Internal Reference
REGISTER MAPS (continued)
Config Register
The configuration register (Config Register) is shown in Table 12.
Table 12. Config Register Details (Read/Write)
DEFAULT
VALUE
BITS
NAME
DESCRIPTION
COMMENT
Working Status/Single-Shot Conversion Start
For a write status:
0 = No effect
1 = Start a single conversion (when in single-shot
mode)
This bit reports the status of the chip.
This bit can only be written when the chip is in
power-down.
D[15]
OS
For a read status:
0 = The chip is doing a conversion
1 = The chip isn’t doing a conversion
Input Multiplexer (MUX) Configuration
000 = AINP = AIN0 and AINN = AIN1 (default)
001 = AINP = AIN0 and AINN = AIN3
010 = AINP = AIN1 and AINN = AIN3
011 = AINP = AIN2 and AINN = AIN3
100 = AINP = AIN0 and AINN = GND
101 = AINP = AIN1 and AINN = GND
110 = AINP = AIN2 and AINN = GND
111 = AINP = AIN3 and AINN = GND
Programmable Gain Amplifier (PGA) Configuration
000 = FS = ±6.144V (1)
D[14:12]
MUX[2:0]
000
001 = FS = ±4.096V (1)
010 = FS = ±2.048V (default)
011 = FS = ±1.024V
D[11:9]
PGA[2:0]
010
100 = FS = ±0.512V
101 = FS = ±0.256V
110 = FS = ±0.256V
111 = FS = ±0.256V
Device Operating Mode
D[8]
D[7:5]
D[4]
MODE
0 = Continuous conversion mode
1 = Power-down single-shot mode (default)
1
100
0
These bits control the data rate setting.
See Table 5.
DR[2:0]
Data Rate
Comparator Mode
COMP_MODE 0 = A traditional comparator with hysteresis (default)
1 = A window comparator
Comparator Polarity
0 = Active low (default)
1 = Active high
This bit sets the active polarity of the
ALERT/RDY pin.
D[3]
D[2]
COMP_POL
0
0
This bit sets whether the ALERT/RDY pin
latches once its outputs sets or resets when
ADC conversion result is within the upper and
lower threshold limitations.
Latching Comparator
0 = Non-latching comparator (default)
1 = Latching comparator
COMP_LAT
Comparator Queue and Disable Function
00 = Assert after one conversion
D[1:0] COMP_QUE[1:0] 01 = Assert after two conversions
10 = Assert after four conversions
These bits can disable the comparator.
These bits can set the required times of
successive ADC conversion beyond the
threshold before an alert output on
ALERT/RDY pin.
11
11 = Disable comparator (default)
NOTES:
1. Default Value = 8583h.
2. This is a theoretical full-scale range of the ADC scaling. The real input must be within the electrical limitation (0V ~ VDD + 0.3V).
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Ultra-Small, Low-Power, 16-Bit
SGM58031
Analog-to-Digital Converter with Internal Reference
REGISTER MAPS (continued)
Low_Thresh and High_Thresh Registers
The lower (Low_Thresh) and upper (High_Thresh) threshold registers are in 16-bit two's complement format. Table 13 shows
these two register format.
Table 13. Low_Thresh and High_Thresh Registers (Read/Write)
Low_Thresh Register
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 2
Bit 9
Bit 1
Bit 8
Bit 0
Low_Thresh[15:8]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Low_Thresh[7:0]
High_Thresh Register
Bit 15
Bit 7
Bit 14
Bit 6
Bit 13
Bit 5
Bit 12
Bit 11
Bit 10
Bit 2
Bit 9
Bit 1
Bit 8
Bit 0
High_Thresh[15:8]
Bit 4
Bit 3
High_Thresh[7:0]
NOTE: Low_Thresh Default Value = 8000h, High_Thresh Default Value = 7FFFh.
Config1 Register
Table 14. 16-Bit Config1 Register Details
DEFAULT
VALUE
BITS
NAME
DESCRIPTION
COMMENT
D[15:9]
N/A
Writing '1' to PD powers down this part, and this PD bit is automatically cleared
internally. Another continuous/single conversion can be carried out again without
the need to clear this bit.
D[8]
D[7]
PD
0
0
0 = DR[2:0] = 000 ~ 111 for conversion rate of 6.25Hz, 12.5Hz, 25Hz, 50Hz, 100Hz,
200Hz, 400Hz and 800Hz (default)
1 = DR[2:0] = 000 ~ 111 for conversion rate of 7.5Hz, 15Hz, 30Hz, 60Hz, 120Hz,
240Hz, 480Hz and 960Hz
DR_SEL
0 = No current sourced (default)
1 = Source a pair of 2μA current to selected pair of AINs
D[6]
D[5]
BURNOUT
Reserved
0
0
0 = Disable leakage blocking circuit for the scenario that I2C bus voltage is lower
than VDD of the part. The I2C interface is still functional but VDD sees leakage when
D[4]
BUS_FLEX
V
BUS < VDD - 0.3V (default)
0
0
1 = Bus voltage can be lower than VDD without causing leakage. The VDD range is
3V to 5.5V and the I2C bus voltage should be limited to 3V to 5.5V
0 = None (default)
1 = Use AIN3 as external reference for ADC
D[3]
EXT_REF
N/A
D[2:0]
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Ultra-Small, Low-Power, 16-Bit
SGM58031
Analog-to-Digital Converter with Internal Reference
REGISTER MAPS (continued)
Chip_ID Register
Table 15. 16-Bit Chip_ID Register for Identifying Chip ID and Its Subversions (Read-Only)
Bit 15
N/A
0
Bit 14
N/A
Bit 13
N/A
0
Bit 12
Bit 11
Bit 10
ID[4:0]
0
Bit 9
Bit 8
0
0
Bit 4
N/A
0
0
Bit 3
N/A
0
0
Bit 1
N/A
0
0
Bit 0
N/A
0
Bit 7
Bit 6
VER[2:0]
0
Bit 5
Bit 2
N/A
0
1
0
GN_Trim1 Register (When Using EXT_REF)
ADC gain coefficient for user selecting Config1 register EXT_REF bit as reference. We provide a default value and user is
responsible for writing proper value to the register if they want to compensate external reference error. This register does not take
effect when EXT_REF = 0 and internal reference is selected.
Table 16. GN_Trim1 Format
Bit 15
N/A
0
Bit 14
N/A
0
Bit 13
N/A
0
Bit 12
N/A
0
Bit 11
N/A
0
Bit 10
GN10
0
Bit 9
GN9
1
Bit 8
GN8
1
Bit 7
GN7
1
Bit 6
GN6
1
Bit 5
GN5
1
Bit 4
GN4
1
Bit 3
GN3
1
Bit 2
GN2
0
Bit 1
GN1
1
Bit 0
GN0
0
ADC GN_Trim1 register is an unsigned value. Default value used for final trimming is 1.3333 to compensate default ADC gain of
3/4. The value of GN[10:0] adds a constant to get the final gain trimming value.
GN_Trim1 + CONST = GN_Trim. The binary value of CONST is 1010011010110000, corresponding to a gain factor of 1.30225.
After adding the default value of GN_Trim1 register (01111111010), the final default gain trimming value is 1.3333. The MAX final
gain trimming value is 1.3547 when trimming register is all '1'; MIN value is 1.30225 when register is all '0'. This gives GN
trimming a ±3% range and 32ppmFS step.
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Ultra-Small, Low-Power, 16-Bit
SGM58031
Analog-to-Digital Converter with Internal Reference
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
MAY 2023 ‒ REV.A.2 to REV.A.3
Page
Updated Detailed Description section................................................................................................................................................................17
JUNE 2022 ‒ REV.A.1 to REV.A.2
Page
Updated Detailed Description section................................................................................................................................................................16
MARCH 2020 ‒ REV.A to REV.A.1
Page
Updated Detailed Description section................................................................................................................................................................12
Changes from Original (DECEMBER 2019) to REV.A
Page
Changed from product preview to production data.............................................................................................................................................All
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23
PACKAGE INFORMATION
PACKAGE OUTLINE DIMENSIONS
MSOP-10
b
E1
E
4.8
1.02
0.3
e
0.5
RECOMMENDED LAND PATTERN (Unit: mm)
D
L
A
A1
c
θ
A2
Dimensions
In Millimeters
Dimensions
In Inches
Symbol
MIN
MAX
1.100
0.150
0.950
0.280
0.230
3.100
3.100
5.050
MIN
MAX
0.043
0.006
0.037
0.011
0.009
0.122
0.122
0.199
A
A1
A2
b
0.820
0.020
0.750
0.180
0.090
2.900
2.900
4.750
0.032
0.001
0.030
0.007
0.004
0.114
0.114
0.187
c
D
E
E1
e
0.500 BSC
0.020 BSC
L
0.400
0°
0.800
6°
0.016
0°
0.031
6°
θ
NOTES:
1. Body dimensions do not include mode flash or protrusion.
2. This drawing is subject to change without notice.
SG Micro Corp
TX00015.000
www.sg-micro.com
PACKAGE INFORMATION
PACKAGE OUTLINE DIMENSIONS
TDFN-3×3-10L
D
e
N10
D1
k
E
E1
N5
N1
b
L
BOTTOM VIEW
TOP VIEW
2.4
1.7 2.8
A
A1
A2
0.6
SIDE VIEW
0.24
0.5
RECOMMENDED LAND PATTERN (Unit: mm)
Dimensions
In Millimeters
Dimensions
In Inches
Symbol
MIN
MAX
0.800
0.050
MIN
0.028
0.000
MAX
0.031
0.002
A
A1
A2
D
0.700
0.000
0.203 REF
0.008 REF
2.900
2.300
2.900
1.500
3.100
2.600
3.100
1.800
0.114
0.091
0.114
0.059
0.122
0.103
0.122
0.071
D1
E
E1
k
0.200 MIN
0.500 TYP
0.008 MIN
0.020 TYP
b
0.180
0.300
0.300
0.500
0.007
0.012
0.012
0.020
e
L
NOTE: This drawing is subject to change without notice.
SG Micro Corp
TX00060.000
www.sg-micro.com
PACKAGE INFORMATION
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
P2
P0
W
Q2
Q4
Q2
Q4
Q2
Q4
Q1
Q3
Q1
Q3
Q1
Q3
B0
Reel Diameter
P1
A0
K0
Reel Width (W1)
DIRECTION OF FEED
NOTE: The picture is only for reference. Please make the object as the standard.
KEY PARAMETER LIST OF TAPE AND REEL
Reel Width
Reel
Diameter
A0
B0
K0
P0
P1
P2
W
Pin1
Package Type
W1
(mm)
(mm) (mm) (mm) (mm) (mm) (mm) (mm) Quadrant
MSOP-10
13″
13″
12.4
12.4
5.20
3.35
3.30
3.35
1.50
1.13
4.0
4.0
8.0
8.0
2.0
2.0
12.0
12.0
Q1
Q1
TDFN-3×3-10L
SG Micro Corp
TX10000.000
www.sg-micro.com
PACKAGE INFORMATION
CARTON BOX DIMENSIONS
NOTE: The picture is only for reference. Please make the object as the standard.
KEY PARAMETER LIST OF CARTON BOX
Length
(mm)
Width
(mm)
Height
(mm)
Reel Type
Pizza/Carton
13″
386
280
370
5
SG Micro Corp
www.sg-micro.com
TX20000.000
相关型号：
SGM58031B
Ultra-Small, Low-Power, 16-Bit Analog-to-Digital Converter with Internal Reference
SGMICRO
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