SGM6060 [SGMICRO]
55V, 2A High Frequency Buck Converter;
| 型号： | SGM6060 |
| 厂家： | 
Shengbang Microelectronics Co, Ltd |
| 描述： | 55V, 2A High Frequency Buck Converter |
| 文件： | 总20页 (文件大小：1260K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SGM6060
55V, 2A High Frequency Buck Converter
GENERAL DESCRIPTION
FEATURES
The SGM6060 is a high voltage and high frequency
Buck converter with 2A maximum output current and
integrated high-side power MOSFET. It implements
peak current mode control to simplify external
compensation design.
● 3.8V to 55V Wide Input Voltage Range
● Adjustable Output Voltage
● Up to 95% Efficiency
● PFM Mode at Light Loads
● Quiescent Current: 126μA (TYP)
● Less than 18μA Shutdown Current
● Internal HS Power MOSFET RDSON: 220mΩ (TYP)
● Adjustable Switching Frequency: 200kHz to 2MHz
● Internal Soft-Start Circuit
With a wide input voltage range of 3.8V to 55V, it is
suitable for a broad range of applications such as
industry equipment.
The SGM6060 operates at fixed frequency and enters
PFM (Pulse Frequency Modulation) mode automatically
at light loads to maintain high efficiency. During startup
and thermal shutdown, the frequency foldback
technique is used to avoid inductor current runaway for
reliable and fault tolerant operation. The current limit
foldback technique is used for reducing power
consumption during output shorted and suppressing
output voltage overshot during recovery.
● Accurate EN Input Threshold
● Stable with Ceramic Capacitor
● Available in Green TDFN-3×3-10L and SOIC-8
(Exposed Pad) Packages
APPLICATIONS
Industrial and Commercial Power Systems
Distributed Power Systems
Switching frequency can be set as high as 2MHz. It
minimizes the EMI noise issues that could interfere with
nearby systems such as AM radio or ADSL modems.
Aftermarket Automotive Accessories
The SGM6060 is available in Green TDFN-3×3-10L
and SOIC-8 (Exposed Pad) packages.
TYPICAL APPLICATION
C5
VIN
L1
VOUT
BOOT
VIN
EN
SW
D1
R5
R1
C7
SGM6060
FB
C1
C2
C3
C4
C9
C10
FREQ
GND COMP
R2
C8
R3
R6
R4
C6
Figure 1. Typical Application Circuit
SG Micro Corp
DECEMBER 2022 – REV. A
www.sg-micro.com
SGM6060
55V, 2A High Frequency Buck Converter
PACKAGE/ORDERING INFORMATION
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESCRIPTION
ORDERING
NUMBER
PACKAGE
MARKING
PACKING
OPTION
MODEL
SGM
6060D
XXXXX
SGM
6060XPS8
XXXXX
TDFN-3×3-10L
SGM6060XTD10G/TR
Tape and Reel, 4000
Tape and Reel, 4000
-40℃ to +125℃
-40℃ to +125℃
SGM6060
SOIC-8 (Exposed Pad)
SGM6060XPS8G/TR
MARKING INFORMATION
NOTE: XXXXX = Date Code, Trace Code and Vendor Code.
TDFN-3×3-10L/SOIC-8 (Exposed Pad)
X X X X X
Vendor Code
Trace Code
Date Code - Year
Green (RoHS & HSF): SG Micro Corp defines "Green" to mean Pb-Free (RoHS compatible) and free of halogen substances. If
you have additional comments or questions, please contact your SGMICRO representative directly.
ABSOLUTE MAXIMUM RATINGS
OVERSTRESS CAUTION
Supply Voltage Range, VIN ................................ -0.3V to 60V
Switch Voltage Range, VSW ......................-0.5V to VIN + 0.5V
BOOT to SW........................................................ -0.3V to 5V
EN Pin Voltage Range, VEN ......................-0.3V to VIN + 0.3V
All Other Pins....................................................... -0.3V to 5V
Package Thermal Resistance
Stresses beyond those listed in Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods
may affect reliability. Functional operation of the device at any
conditions beyond those indicated in the Recommended
Operating Conditions section is not implied.
TDFN-3×3-10L, θJA.................................................... 77℃/W
SOIC-8 (Exposed Pad), θJA ....................................... 53℃/W
unction Temperature...................................................+150℃
Storage Temperature Range.......................-65℃ to +150℃
Lead Temperature (Soldering, 10s)............................+260℃
ESD Susceptibility
ESD SENSITIVITY CAUTION
This integrated circuit can be damaged if ESD protections are
not considered carefully. SGMICRO recommends that all
integrated circuits be handled with appropriate precautions.
Failureto observe proper handlingand installation procedures
can cause damage. ESD damage can range from subtle
performance degradation tocomplete device failure. Precision
integrated circuits may be more susceptible to damage
because even small parametric changes could cause the
device not to meet the published specifications.
HBM.............................................................................3000V
CDM ............................................................................1000V
RECOMMENDED OPERATING CONDITIONS
Supply Voltage Range, VIN ..................................3.8V to 55V
Operating Junction Temperature Range......-40℃ to +125℃
DISCLAIMER
SG Micro Corp reserves the right to make any change in
circuit design, or specifications without prior notice.
SG Micro Corp
www.sg-micro.com
DECEMBER 2022
2
SGM6060
55V, 2A High Frequency Buck Converter
PIN CONFIGURATION
(TOP VIEW)
(TOP VIEW)
SW
EN
1
2
3
4
8
7
6
5
BST
SW
SW
1
2
3
4
5
10 BOOT
9
8
7
6
VIN
VIN
EN
GND
VIN
GND
COMP
FB
FREQ
GND
COMP
FB
FREQ
GND
TDFN-3×3-10L
SOIC-8 (Exposed Pad)
PIN DESCRIPTION
PIN
NAME
FUNCTION
SOIC-8
TDFN-3×3-10L
(Exposed Pad)
1, 2
3
1
2
SW
EN
Switching Node of the Converter.
Active High Enable Input Pin. It has a weak internal pull-up current source. Pull it below
1.12V to disable the device. Leave EN pin floating when unused. When EN pin is directly
connected to VIN pin or external signal source, a resistor greater than 10kΩ is necessary.
Transconductance Error Amplifier Output. Use a compensation network between COMP
and GND pins to compensate the internal loop.
4
5
3
4
COMP
FB
Inverting Input of the Error Amplifier.
Ground Pin.
6
5
GND
FREQ
VIN
Adjustable Switching Frequency Pin. Connect an external resistor between FREQ and GND
pins to adjust the switching frequency.
7
6
8, 9
10
—
7
Power Supply Input Pin.
Power Supply of the Internal MOSFET Gate Driver. Connect a 0.1µF bootstrap capacitor
between BOOT and SW pins.
8
BOOT
—
Exposed Pad Exposed Pad. It should be soldered to the ground plane for enhanced heat dissipation.
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SGM6060
55V, 2A High Frequency Buck Converter
ELECTRICAL CHARACTERISTICS
(VIN = 12V, VEN = 2V, TJ = +25℃, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
0.792
0.783
TYP
MAX
0.814
0.820
270
UNITS
VIN = 12V
0.803
Feedback Voltage
VFB
V
TJ = -40℃ to +125℃
VBOOT - VSW = 5V
220
Switch On-Resistance
RDSON
mΩ
430
TJ = -40℃ to +125℃
VEN = 0V, VSW = 0V
Switch Leakage Current
ILKG
ILIM
1
μA
A
Current Limit
3.08
3.79
5.85
80
4.38
COMP to Sensed Current Transconductance
Error Amplifier Voltage Gain (1)
Error Amplifier Transconductance
Error Amplifier Source Current
Error Amplifier Sink Current
GCS
A/V
dB
AEA
GEA
ICOMP = ±3µA
120
9
µA/V
µA
ISOURCE
ISINK
VFB = 0.7V, VCOMP = 1V
VFB = 0.9V, VCOMP = 1V
-9
µA
2.87
2.70
3.16
3.48
3.70
VIN Under-Voltage Lockout Threshold (UVLO)
VUVLO
V
TJ = -40℃ to +125℃
VIN Under-Voltage Lockout Hysteresis
Soft-Start Time (1)
VUVLOHYS
tSS
0.61
0.55
V
From 10% to 90% × VOUT (set)
R4 = 89kΩ
ms
0.900
0.890
0.985
1.100
1.105
18
Switching Frequency
fSW
MHz
R4 = 89kΩ, TJ = -40℃ to +125℃
VIN = 12V, VEN < 0.2V
No load, VFB = 0.86V
Shutdown Supply Current
Quiescent Supply Current
Thermal Shutdown Temperature
Thermal Shutdown Temperature Hysteresis
Minimum Off Time (1)
ISD
IQ
13
126
155
20
µA
µA
℃
℃
ns
ns
TSD
THYS
tOFF_MIN
tON_MIN
100
100
1.58
Minimum On Time (1)
1.40
1.35
1.75
1.85
EN Rising Threshold
VENR
V
TJ = -40℃ to +125℃
EN Threshold Hysteresis
VENHYS
460
mV
NOTE: 1. Guaranteed by design.
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SGM6060
55V, 2A High Frequency Buck Converter
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 12V, VOUT = 3.3V, CIN = 10μF, COUT = 22μF, L1 = 10μH, DCR = 15.3mΩ, unless otherwise noted.
Startup
Shutdown
ILOAD = 0.1A
ILOAD = 1A
ILOAD = 2A
ILOAD = 0.1A
ILOAD = 1A
ILOAD = 2A
VEN
VEN
VOUT
VOUT
VSW
VSW
IL
IL
Time (2ms/div)
Startup
Time (1ms/div)
Shutdown
VEN
VEN
VOUT
VOUT
VSW
IL
VSW
IL
Time (2ms/div)
Startup
Time (200μs/div)
Shutdown
VEN
VEN
VOUT
VOUT
VSW
IL
VSW
IL
Time (2ms/div)
Time (200μs/div)
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SGM6060
55V, 2A High Frequency Buck Converter
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3.3V, CIN = 10μF, COUT = 22μF, L1 = 10μH, DCR = 15.3mΩ, unless otherwise noted.
Output Ripple
Short-Circuit Entry
ILOAD = 0.1A
AC Coupled
ILOAD = 0.1A to short
VOUT
VOUT
\
VSW
VSW
IL
IL
Time (1μs/div)
Time (1ms/div)
Output Ripple
Short-Circuit Recovery
ILOAD = 1A
ILOAD = short to 0.1A
AC Coupled
VOUT
VOUT
VSW
IL
VSW
IL
Time (1μs/div)
Time (500μs/div)
Output Ripple
Short-Circuit Steady State
ILOAD = 2A
AC Coupled
VOUT
VOUT
VSW
IL
VSW
IL
Time (1μs/div)
Time (20μs/div)
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SGM6060
55V, 2A High Frequency Buck Converter
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3.3V, CIN = 10μF, COUT = 22μF, L1 = 10μH, DCR = 15.3mΩ, unless otherwise noted.
Efficiency vs. Output Current
Efficiency vs. Output Current
100
80
60
40
20
0
100
80
60
40
20
0
VIN = 12V
IN = 55V
VIN = 12V
IN = 55V
V
V
VOUT = 5V, L1 = 15μH, fSW = 500kHz
VOUT = 3.3V, L1 = 10μH, fSW = 500kHz
0
0.4
0.8
1.2
1.6
2
0
0.4
0.8
1.2
1.6
2
Output Current (A)
Output Current (A)
Efficiency vs. Output Current
R4 Resistance vs. Switching Frequency
100
80
60
40
20
0
500
400
300
200
100
0
VIN = 24V
IN = 55V
V
VOUT = 12V, L1 = 33μH, fSW = 500kHz
0
0.4
0.8
1.2
1.6
2
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Switching Frequency (MHz)
Output Current (A)
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SGM6060
55V, 2A High Frequency Buck Converter
FUNCTIONAL BLOCK DIAGRAM
VIN
VDD
1μA
BOOT
Charger
VDD
Reference
EN
Internal
Regulators
BOOT
UVLO
_
ISW
Logic
+
Internal
Soft-Start
VSS
Current
Limit
SW
_
FB
COMP
Oscillator
VSS
0.8V
Slope
Compensation
+
COMP
GND
FREQ
Figure 2. SGM6060 Functional Block Diagram
DETAILED DESCRIPTION
Overview
Internal 2.8V Regulator
The SGM6060 is a 3.8V to 55V, 2A non-synchronous
Buck converter with integrated high-side N-channel
MOSFET. It is a perfect solution for efficient single
stage Buck applications. The integrated functions
include precision current limiting, automatically
switched PWM and PFM modes, soft-start circuit and
wide range switching frequency, which can meet
different requirements. Peak current mode control is
implemented to provide fast load transient response
and simple compensation.
An internal 2.8V regulator powers most of the device
internal circuits. The 2.8V output is fully regulated when
VIN exceeds 3.16V. It will drop if VIN falls below 3.16V.
Enable Input
The EN pin is an active high input to enable or disable
the device. The EN rising threshold voltage VENR is
1.58V (TYP) and has a 460mV (TYP) hysteresis.
A 1μA internal current source pulls the EN pin up to
approximately 3.0V. Therefore the device will be
enabled when the EN pin is left floating. To disable the
device, pull the EN pin down below 1.12V with at least
1µA sink capability.
VIN Under-Voltage Lockout (UVLO)
The SGM6060 integrates VIN under-voltage lockout
(UVLO) feature to protect the device from
malfunctioning when the input voltage is insufficient to
properly power up the internal circuits. The UVLO rising
threshold is 3.16V (TYP) and has a 0.61V (TYP)
hysteresis.
When VEN falls below 1.12V, the device is disabled and
enters low shutdown current mode. When VEN exceeds
0V and does not reach VENR, the device is still disabled
but with slightly higher shutdown current.
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SGM6060
55V, 2A High Frequency Buck Converter
DETAILED DESCRIPTION
Startup and Shutdown
PWM Comparator and Current Limit
If both VIN and VEN exceed their thresholds, the device
is enabled and starts operation. First, the bandgap
circuit starts working to generate stable reference
voltage and bias current. Then two internal regulators
are established to provide supply voltage for internal
analog and digital circuit respectively. About 30µs later,
bootstrap capacitor voltage is charged above UVLO
threshold. Then the output starts to rise slowly during
soft-start.
For peak current mode, a signal represent of high-side
current is used as the input of PWM comparator, which
is accurately sampled by internal sensing circuit. After
100ns typical blanking time, the signal is compared with
COMP to determine switching state of high-side
MOSFET. The cycle-by-cycle current limit threshold is
approximately 3.79A.
Note that the measured peak current limits in the
closed-loop and open-loop test conditions are slightly
different, mainly caused by the propagation delay.
The device is disabled when any of invalid EN voltage,
VIN UVLO and thermal shutdown events occurs. Once
the device is disabled, the high-side switch is turned off
immediately to avoid any other fault triggering.
Short-Circuit Protection and Recovery
If the output is shorted to the ground, the switching
frequency is reduced. The foldback current limit is
reduced by half to lower the power consumption.
During output shorted condition, VSS is pulled down to
about 0.1V above VFB to reduce the overshot of short
recovery. The current limit resumes its normal value
when VFB exceeds 0.4V.
Soft-Start and Ramp
Every time the device is enabled (after power-up,
pulling EN high), the output voltage is gradually
increased to its regulation value with a ramp (after a
brief 50µs hold). Soft-start is needed to prevent
triggering of current limit or short-circuit protections or
to avoid output overshooting during startup. Without a
soft-start, the inrush currents of the output capacitors or
the load can cause over-current and the protection
procedure results in non-monotonic startup or even
instability. Overshooting may also occur during startup
after short-circuit recovery. The internal soft-start
voltage (VSS) and reference (VREF) are both sent to the
error amplifier and the lower value of them is the actual
reference that is compared with the feedback voltage
(VFB).
Bootstrap Floating MOSFET Driver
The power of the high-side MOSFET driver is provided
by an external capacitor between BOOT and SW pins.
An internal bootstrap regulator keeps the bootstrap
capacitor charged and regulated to approximately 4.5V.
The bootstrap voltage is detected by internal BOOT
UVLO circuit with 2.4V rising threshold and 250mV
hysteresis. If the bootstrap voltage falls below its UVLO
threshold, the power MOSFET is turned off immediately.
An internal transistor is used to pull down the SW node
to make sure BOOT capacitor is charged sufficiently.
This design can obviously reduce the output voltage
ripple at small input/output voltage difference and no
load. When the bootstrap voltage is charged above
threshold, the pull-down transistor is turned off and
high-side MOSFET is able to be turned on again.
PWM Operation Mode
In the moderate to heavy load conditions, the
SGM6060 runs at fixed frequency with peak current
control mode. The high-side MOSFET is turned on at
the leading edge of internal clock until the sensing
current ramp signal reaches the COMP voltage. If the
switch current does not reach the reference value
(conversion from VC) in a cycle, the switch will also be
turned off for tOFF_MIN (100ns, TYP) before the next
clock.
Except for BOOT UVLO condition, the external circuit
connected to the SW serves as the return path to GND
for the charge current. Enough voltage headroom
should be left to facilitate the charging. When the
external freewheeling diode is on, bootstrap charging
starts until the regulated voltage.
PFM Mode
In the light load condition, the frequency is reduced
depending on the load to minimize the switching and
gate driving losses and keep the efficiency high.
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SGM6060
55V, 2A High Frequency Buck Converter
DETAILED DESCRIPTION (continued)
The converter operates in PFM Mode at no load or light
load, to minimize switching losses and keep the output
regulated. In this mode, the available time for
refreshing the BOOT voltage is reduced, bootstrap
voltage will drop below the regulated voltage (4.5V).
The maximum charged voltage is equal to VIN - VOUT. If
the difference of VIN - VOUT is too small, BOOT UVLO
can be triggered. The internal charging circuit charges
the bootstrap capacitor by the set frequency, until
BOOT UVLO is released.
Adjustable Switching Frequency
The switching frequency is adjusted by connecting an
external resistor (R4) between the FREQ and GND.
Use Equation 2 to calculate R4 resistance:
94581
(2)
R4(kΩ) =
- 7.24
fSW (kHz)
For Example, to get 500kHz switching frequency, the
required R4 resistor is 180kΩ.
An internal frequency foldback technique is designed
by monitoring the FB voltage. It can effectively avoid
the inductor current runaway during startup or
restarting in certain situation.
The designer should make sure that the SW node
bleeding current is higher than the quiescent current of
the floating driver (approximately 20µA). Usually the
feedback resistors (R1 and R2) are selected such that
the R1 + R2 value is small enough to provide that
current:
Error Amplifier (EA)
The output voltage is sensed by a resistor divider
through the FB pin and is compared with the internal
reference. The EA generates an output current that is
proportional to the voltage difference (error). This
current is fed into the external compensation network to
generate the VC voltage on the COMP pin, which sets
the reference value for the peak current that controls
the on time of the power MOSFET.
VOUT
(1)
IOUT _MIN
+
> 20μA
(R1 + R2 )
External Bootstrap Diode
To improve the efficiency, using an external boot diode
supplied from a 5V rail (in Figure 3) is recommended in
the following cases:
The operating voltage range of COMP (VC) is between
0.75V and 2.0V in normal conditions. COMP is pulled
down to the ground when the device shuts down. The
COMP voltage must not be pulled higher than 2.8V.
A 5V rail is available.
VIN is less than 5V.
VOUT is between 3.3V and 5V.
High duty cycle applications (VOUT/VIN > 65%).
A low-cost diode like IN4148 or BAT54 can be used.
Thermal Shutdown
To protect the device from damage due to overheating,
a thermal shutdown feature is implemented to disable
the device when the die temperature exceeds +155℃
(TYP). The chip is automatically enabled when the
temperature falls below +135℃ (20℃ hysteresis, TYP).
5V
BOOT
0.1μF
SGM6060
SW
Figure 3. External Bootstrap Diode
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SGM6060
55V, 2A High Frequency Buck Converter
APPLICATION INFORMATION
In this section, power supply design with the SGM6060 non-synchronous Buck converter and selection of the
external component will be explained based on the typical application that is applicable for various input and output
voltage combinations.
C5
0.1μF
L1
10μH
VIN = 8V to 55V
VOUT = 3.3V
BOOT
VIN
EN
SW
R5
100kΩ
R1
100kΩ
C7
NS
D1
SGM6060
C2
10μF
100V
C3
0.1μF
100V
C4
0.1μF
100V
C9
EC
NS
C1
NS
C10
NS
+
FB
1
22μF
25V
FREQ
GND COMP
R2
32.4kΩ
C8
R6
24.9kΩ
R4
180kΩ
1.5nF
C6
15pF
R3
24.9kΩ
NOTE: EC1 and C1 are optional. If the input voltage is far away from the VIN of SGM6060, EC1 and C1 should be installed.
Figure 4. SGM6060 Application Example with 3.3V/2A Output
off time limits of the converter. In this design, fSW
=
Design Requirements
500kHz is chosen as a tradeoff. From Equation 2, the
nearest standard resistor for this frequency is R4 =
180kΩ.
In this example, a high frequency regulator with
ceramic output capacitors will be designed using
SGM6060 and the details will be reviewed. The design
requirements are typically determined at the system
level. The known requirements are summarized in
Table 1.
Inductor Design
Equation 3 is conventionally used to calculate the
output inductance of a Buck converter. Generally, a
smaller inductor is preferred to allow larger bandwidth
and smaller size. The ratio of inductor current ripple (∆IL)
to the maximum output current (IOUT) is represented as
KIND factor (∆IL/IOUT). The inductor ripple current is
bypassed and filtered by the output capacitor and the
inductor DC current is passed to the output. Inductor
ripple is selected based on a few considerations. The
peak inductor current (IOUT + ∆IL/2) must have a safe
margin from the saturation current of the inductor in the
worst-case conditions especially if a hard-saturation
core type inductor (such as ferrite) is chosen. During
power-up with large output capacitor, over-current,
output shorted or load transient conditions, the actual
peak current of inductor can be greater than ILPEAK
calculated in Equation 6. For peak current mode
converter, selecting an inductor with saturation current
above the switch current limit is sufficient. Typically, a
20% to 40% ripple is selected (KIND = 0.2 ~ 0.4).
Choosing a higher KIND value reduces the selected
inductance.
Table 1. Design Parameters
Design Parameter
Output Voltage
Example Value
3.3V
Maximum Output Current
2A
ΔVOUT = 7%
12V nominal, 8V to 55V
33mVP-P
Load Transient Response of 1A - 2A Step
Input Voltage Range
Maximum Output Voltage Ripple
Turn-On Input Voltage (Rising VIN)
Turn-Off Input Voltage (Falling VIN)
7.9V
5.6V
Switching Frequency (fSW
)
500kHz
Operating Frequency
Usually the first parameter to design is the switching
frequency (fSW). Higher switching frequencies allow
smaller solution size and smaller filter inductors and
capacitors, and the bandwidth of the converter can be
increased for faster response. It is also easier to filter
noises because they also shift to higher frequencies.
The drawbacks are increased switching and gate
driving losses that result in lower efficiency and tighter
thermal limits. Also the duty cycle range and step-down
ratio will be limited due to the minimum on time and/or
V
- VOUT
VOUT
VINMAX × fSW
INMAX
(3)
L1 =
×
IOUT ×KIND
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SGM6060
55V, 2A High Frequency Buck Converter
APPLICATION INFORMATION (continued)
In this example, KIND = 0.3 is chosen and the
two or more cycles for the loop to detect the output
inductance is calculated to be 10.34μH. In this example,
change and respond (change the duty cycle). It may
also be expressed as the maximum output voltage drop
or rise when the full load is connected or disconnected
(100% load step). Equation 7 can be used to calculate
the minimum output capacitance that is needed to
supply or absorb a current step (ΔIOUT) for at least 2
cycles until the control loop responds to the load
change with a maximum allowed output transient of
ΔVOUT (overshoot or undershoot).
the nearest standard value 10μH is selected. The ripple,
RMS and peak inductors current calculations are
summarized in Equations 4, 5 and 6 respectively.
V
- VOUT
VOUT
INMAX
(4)
∆IL =
×
L1
IOUT
ILPEAK = IOUT
V
INMAX × fSW
2
∆IL
12
2
ILRMS
=
+
(5)
(6)
∆IL
2
2× ∆IOUT
+
(7)
COUT
>
fSW × ∆VOUT
The ripple, RMS, and peak inductor currents are
calculated as 0.62A, 2.01A and 2.31A respectively. A
10μH inductor from Sunlord SWPA8040S100MT with
4.1A saturation and 3.3A RMS current ratings is selected.
For example, if the acceptable transient to a 1A load
step is 7%, by inserting ΔVOUT = 0.07 × 3.3V = 0.231V
and ΔIOUT = 1A, the minimum required capacitance will
be 17.3μF. Generally, the ESR of ceramic capacitors is
small enough. The impact of output capacitor ESR on
the transient is not taken into account in Equation 7.
External Diode (D)
The SGM6060 adopts non-synchronous architecture.
Therefore an external diode is required to place
between SW and GND pins. A Schottky diode is
recommended due to the characteristics of fast
recovery and small forward conduction voltage drop,
which can help improve the efficiency and reduce the
rising edge ring of SW node.
Equation 8 can be used for the output ripple criteria and
finding the minimum output capacitance needed.
VORIPPLE is the maximum acceptable ripple. In this
example, the allowed ripple is 33mV that results in
minimum capacitance of 4.7μF.
1
∆IL
(8)
COUT
>
×
8× fSW VORIPPLE
For main parameters of diode, the maximum reverse
voltage rating of the selected diode must be greater
than the maximum applicable input voltage. The peak
current rating must be greater than the current limit,
and the average forward current should be greater than
typical load current with enough margin.
Note that the impact of output capacitor ESR on the
ripple is not considered in Equation 8. Use Equation 9
to calculate the maximum acceptable ESR of the output
capacitor to meet the output voltage ripple requirement.
In this example, the ESR must be less than
33mV/0.62A = 53.2mΩ.
In this example, a B380-13-F from Diodes Inc. with 80V
reverse voltage and 3A forward current is selected.
VORIPPLE
(9)
RESR
<
∆IL
Output Capacitor Design
Three primary criteria must be considered for design of
the output capacitor (COUT): (1) the converter pole
location, (2) the output voltage ripple, (3) the transient
response to a large change in load current. The
selected value must satisfy all of them. The desired
transient response is usually expressed as maximum
overshoot, maximum undershoot, or maximum recovery
time of VOUT in response to a large load step. Transient
response is usually the more stringent criteria in low
output voltage applications. The output capacitor must
provide the increased load current or absorb the
excess inductor current (when the load current steps
down) until the control loop can re-adjust the current of
the inductor to the new load level. Typically, it requires
Higher nominal capacitance value must be chosen due
to aging, temperature, and DC bias derating of the
output capacitors. In this example, a 22μF/25V ceramic
capacitor with X7R dielectric and 3mΩ ESR is selected.
There is a limit to the amount of ripple current that a
capacitor can handle without damage or overheating.
The inductor ripple is bypassed through the output
capacitor. Equation 10 calculates the RMS current that
the output capacitor must support. In this example, it is
179mA.
∆IL
ICORMS
=
(10)
12
SG Micro Corp
www.sg-micro.com
DECEMBER 2022
12
SGM6060
55V, 2A High Frequency Buck Converter
APPLICATION INFORMATION (continued)
VSTARTUP - VENR
Input Capacitor Design
A high-quality ceramic capacitor (X5R or X7R or better
(13)
R5 = R6 ×
VENR
dielectric grade) must be used for input decoupling of
the SGM6060. If input power is far away from
SGM6060, additional bulk capacitor is recommended in
parallel to stabilize input voltage. The RMS value of
input capacitor can be calculated from Equation 11 and
the maximum ICIRMS occurs at 50% duty cycle. For this
example, the maximum input RMS current is 1A. The
ripple current rating of input capacitor should be greater
than ICIRMS.
Feedback Resistors
Choosing a 100kΩ value for the upper resistor (R1), the
lower resistor (R2) can be calculated from Equation 14.
The nearest 1% resistor for the calculated value (32kΩ)
is 32.4kΩ. For higher output accuracy, choose resistors
with better tolerance (0.5% or better).
VREF
(14)
R2 =
×R1
VOUT - VREF
Loop Compensation Design
ICIRMS = IOUTMAX × D× 1-D
(
)
(11)
Several techniques are used by engineers to
compensate a DC/DC regulator. In this simplified
method, the effects of the slope compensation are
ignored. Because of this approximation, the actual
cross over frequency is usually lower than the
calculated value.
where D is the duty cycle.
In this example, the voltage rating of capacitor should
have a safe margin from maximum input voltage.
Therefore, a 10μF/100V ceramic capacitor is selected
for VIN to cover all DC bias, thermal and aging
deratings, and two 0.1μF/100V capacitors are selected
for further decoupling of high frequency noise. The
small capacitors should be connected between VIN and
GND pins as close as possible.
First, the converter pole (fP), and ESR zero (fZ) are
calculated from Equations 15 and 16. For COUT, the
worst derated value of 17μF should be used. Equations
17 and 18 can be used to find an estimation for
closed-loop crossover frequency (fCO) as a starting
point (choose the lower value).
The input voltage ripple can be calculated from
Equation 12, and the maximum ripple occurs at 50%
duty cycle.
IOUT
(15)
(16)
fP =
fZ =
2π× VOUT ×COUT
IOUTMAX ×D× 1-D
(
)
(12)
∆V =
1
IN
CIN × fSW
2π×RESR ×COUT
Bootstrap Capacitor Selection
fCO
= fP × fZ
(17)
(18)
A 0.1μF ceramic capacitor with 10V or higher voltage
rating must be connected between the BOOT and SW
pin. X5R or better dielectric types are recommended.
fSW
2
fCO = fP ×
UVLO Setting
For this design, fP = 5.68kHz and fZ = 3.12MHz.
Equation 17 yields 133.1kHz for crossover frequency
and Equation 18 gives 37.7kHz. As the influence of
slope compensation in the actual circuit, a slightly
higher frequency of 40kHz is selected.
The under-voltage lockout (UVLO) can be programmed
by an external voltage divider network. In this design,
the turn-on (enable to start switching) occurs when VIN
rises above 7.9V (VSTARTUP). When the regulator is in
operation, it will not stop switching (disabled) until the
input falls below 5.6V (VSHUTDOWN). Use Equation 13 to
calculate the resistors value. In this example, choose
R5 = 100kΩ and R6 = 24.9kΩ.
SG Micro Corp
www.sg-micro.com
DECEMBER 2022
13
SGM6060
55V, 2A High Frequency Buck Converter
APPLICATION INFORMATION (continued)
Having the crossover frequency, the compensation
network (R3 and C8) can be calculated. R3 sets the gain
of the compensated network at the crossover frequency
and can be calculated by Equation 19.
Place the larger input ceramic capacitor and
Schottky diode close to relevant pins for minimizing
the influence of ground bounce.
Use short and wide trace to connect SW node to the
inductor. Minimize the area of switching loop.
Otherwise, large voltage spikes on the SW node and
poor EMI performance are inevitable.
2π× fCO × VOUT ×COUT
GEA × VREF ×GCS
(19)
R3 =
C8 sets the location of the compensation zero along
with R3. To place this zero on the converter pole, use
Equation 20.
Sensitive signal like FB, COMP, EN traces must be
placed away from high dv/dt nodes (such as SW)
and not inside any high di/dt loop (like capacitor or
switch loops). The ground of these signals should be
connected to GND pin and separated with power
ground.
VOUT ×COUT
IOUT ×R3
C8 =
(20)
From Equations 19 and 20, the standard selected
values are R3 = 24.9kΩ and C8 = 1.5nF.
To improve the thermal relief, use a group of thermal
vias under the exposed pad to transfer the heat to
the ground planes in the opposite side of the PCB.
Use small vias (approximately 15mil) such that they
can be filled up during the reflow soldering process to
provide a good metallic heat conduction path from
the IC exposed pad to the other PCB side.
A high frequency pole can also be added by a parallel
capacitor if needed (not used in this example). The pole
frequency can be calculated from Equation 21.
1
fP =
(21)
2π×R3 ×C6
Layout Considerations
Connect VIN, GND and exposed pad pins to large
copper areas to increase heat dissipation and
long-term reliability. Keep SW area small to avoid
emission issue.
PCB layout is critical for stable and high-performance
converter operation. The recommend layout is shown in
Figure 5.
Place the nearest input high frequency decoupling
capacitor (0.1μF) between VIN and GND pins as
close as possible.
SG Micro Corp
www.sg-micro.com
DECEMBER 2022
14
SGM6060
55V, 2A High Frequency Buck Converter
APPLICATION INFORMATION (continued)
TDFN-3×3-10L Top Layer
TDFN-3×3-10L Bottom Layer
SOIC-8 (Exposed Pad) Top Layer
SOIC-8 (Exposed Pad) Bottom Layer
Figure 5. PCB Layout Guide
SG Micro Corp
www.sg-micro.com
DECEMBER 2022
15
SGM6060
55V, 2A High Frequency Buck Converter
ADDITIONAL TYPICAL APPLICATION CIRCUITS
C5
0.1μF
L1
15μH
VIN = 10V to 55V
V
OUT = 5V
BOOT
VIN
SW
R5
100kΩ
R1
180kΩ
C7
NS
D1
SGM6060
C3
0.1μF
100V
C4
0.1μF
100V
C1
10μF
100V
C2
10μF
100V
C9
22μF
25V
C10
22μF
25V
EN
FB
FREQ
GND COMP
R2
34kΩ
C8
1.5nF
R6
20kΩ
R4
180kΩ
C6
15pF
R3
56kΩ
Figure 6. 5V Output Typical Application (NS: not soldered)
C5
0.1μF
L1
33μH
VIN = 24V to 55V
VOUT = 12V
BOOT
VIN
EN
SW
R5
100kΩ
R1
390kΩ
C7
NS
D1
SGM6060
C3
0.1μF
100V
C4
C1
10μF
100V
C2
10μF
100V
C9
C10
FB
0.1μF
100V
22μF
25V
22μF
25V
FREQ
GND COMP
R2
28kΩ
C8
R6
7.5kΩ
R4
180kΩ
1.5nF
C6
15pF
R3
59kΩ
Figure 7. 12V Output Typical Application (NS: not soldered)
C5
0.1μF
L1
47μH
V
IN = 36V to 55V
VOUT = 24V
BOOT
VIN
EN
SW
R5
100kΩ
R1
806kΩ
C7
NS
D1
SGM6060
C3
0.1μF
100V
C4
C1
10μF
100V
C2
10μF
100V
C9
C10
FB
0.1μF
100V
10μF
50V
10μF
50V
FREQ
GND COMP
R2
28kΩ
C8
R6
4.7kΩ
R4
180kΩ
820pF
C6
15pF
R3
91kΩ
Figure 8. 24V Output Typical Application (NS: not soldered)
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (DECEMBER 2022) to REV.A
Page
Changed from product preview to production data.............................................................................................................................................All
SG Micro Corp
www.sg-micro.com
DECEMBER 2022
16
PACKAGE INFORMATION
PACKAGE OUTLINE DIMENSIONS
TDFN-3×3-10L
D
e
N10
D1
k
E
E1
N5
N1
b
L
BOTTOM VIEW
TOP VIEW
2.4
1.7 2.8
A
A1
A2
0.6
SIDE VIEW
0.24
0.5
RECOMMENDED LAND PATTERN (Unit: mm)
Dimensions
In Millimeters
Dimensions
In Inches
Symbol
MIN
MAX
0.800
0.050
MIN
0.028
0.000
MAX
0.031
0.002
A
A1
A2
D
0.700
0.000
0.203 REF
0.008 REF
2.900
2.300
2.900
1.500
3.100
2.600
3.100
1.800
0.114
0.091
0.114
0.059
0.122
0.103
0.122
0.071
D1
E
E1
k
0.200 MIN
0.500 TYP
0.008 MIN
0.020 TYP
b
0.180
0.300
0.300
0.500
0.007
0.012
0.012
0.020
e
L
NOTE: This drawing is subject to change without notice.
SG Micro Corp
TX00060.000
www.sg-micro.com
PACKAGE INFORMATION
PACKAGE OUTLINE DIMENSIONS
SOIC-8 (Exposed Pad)
D
e
3.22
E1
E
E2
2.33 5.56
1.91
b
D1
1.27
0.61
RECOMMENDED LAND PATTERN (Unit: mm)
L
A
A1
c
θ
A2
Dimensions
In Millimeters
Symbol
MIN
MOD
MAX
1.700
0.150
1.650
0.510
0.250
5.100
3.420
4.000
6.200
2.530
A
A1
A2
b
0.000
1.250
0.330
0.170
4.700
3.020
3.800
5.800
2.130
-
-
-
c
-
D
-
D1
E
-
-
E1
E2
e
-
-
1.27 BSC
L
0.400
0°
-
-
1.270
8°
θ
NOTES:
1. Body dimensions do not include mode flash or protrusion.
2. This drawing is subject to change without notice.
SG Micro Corp
TX00013.002
www.sg-micro.com
PACKAGE INFORMATION
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
P2
P0
W
Q2
Q4
Q2
Q4
Q2
Q4
Q1
Q3
Q1
Q3
Q1
Q3
B0
Reel Diameter
P1
A0
K0
Reel Width (W1)
DIRECTION OF FEED
NOTE: The picture is only for reference. Please make the object as the standard.
KEY PARAMETER LIST OF TAPE AND REEL
Reel Width
Reel
Diameter
A0
B0
K0
P0
P1
P2
W
Pin1
Package Type
W1
(mm)
(mm) (mm) (mm) (mm) (mm) (mm) (mm) Quadrant
TDFN-3×3-10L
13″
13″
12.4
12.4
3.35
6.40
3.35
5.40
1.13
2.10
4.0
4.0
8.0
8.0
2.0
2.0
12.0
12.0
Q1
Q1
SOIC-8
(Exposed Pad)
SG Micro Corp
TX10000.000
www.sg-micro.com
PACKAGE INFORMATION
CARTON BOX DIMENSIONS
NOTE: The picture is only for reference. Please make the object as the standard.
KEY PARAMETER LIST OF CARTON BOX
Length
(mm)
Width
(mm)
Height
(mm)
Reel Type
Pizza/Carton
13″
386
280
370
5
SG Micro Corp
www.sg-micro.com
TX20000.000
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