SGM61130 [SGMICRO]
4.5V to 18V Input, 4A, Synchronous Buck Converter;
| 型号： | SGM61130 |
| 厂家： | 
Shengbang Microelectronics Co, Ltd |
| 描述： | 4.5V to 18V Input, 4A, Synchronous Buck Converter |
| 文件： | 总27页 (文件大小：1174K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SGM61130
4.5V to 18V Input, 4A,
Synchronous Buck Converter
GENERAL DESCRIPTION
FEATURES
The SGM61130 is an efficient, 4A, synchronous Buck
converter with integrated power MOSFETs and a wide
4.5V to 18V input range. This current mode control
device is optimized for high density applications with
minimal number of external components. High
switching frequency, up to 2000kHz, can be chosen to
lessen the solution size by smaller inductor and
capacitors. This device can be used as a standalone or
tracking power supply. The SS/TR pin can be used to
control the output voltage startup ramp or as an input
for tracking.
● Low Integrated RDSON Switches: 46mΩ/34mΩ
● Split Rails for Supply (VIN) and Power (PVIN)
1.8V to 18V Range for PVIN
4.5V to 18V Range for VIN
● 200kHz to 2000kHz Switching Frequency
● External Clock Synchronization
● Voltage Tracking Capability
● 0.8V Internal Reference Voltage
● ±1% Reference Voltage Accuracy
● 3.4μA (TYP) Shutdown Current
● Hiccup Mode Current Limit
● Monotonic Startup with Pre-biased Outputs
● Adjustable Soft-Start Time
● Power Sequencing Capability
● Power Good Output Monitor for Under-Voltage
and Over-Voltage Protections
● Adjustable Input Under-Voltage Lockout (UVLO)
● Thermal Shutdown (+175℃)
Power supply sequencing for two or more power
supplies is possible by using the enable input (EN) and
the open-drain power good output (PG) signals.
The high-side MOSFET current is cycle-by-cycle
limited for overload protection. The low-side MOSFET
sourcing current is also limited to prevent current
runaway. The low-side switch also has a sinking
current limit that turns it off if an excessive reverse
current flows through it.
● Available in a Green TQFN-3.5×3.5-14L Package
APPLICATIONS
Thermal shutdown protection is activated to prevent
damage to the device when the junction temperature is
above the shutdown threshold.
Industrial and Commercial Power Systems
Distributed Power Systems
Server and Storage
The SGM61130 is available in a Green TQFN-3.5×3.5-14L
package.
Communications Equipment
TYPICAL APPLICATION
Efficiency vs. Load Current
100
CBOOT
90
80
70
60
50
40
30
20
BOOT
L1
PVIN
VIN
VOUT
VIN
SW
COUT
CIN
EN
R1
SGM61130
SS/TR
FB
RT/CLK
COMP
PG
R2
R3
C1
GND
CSS RRT C2
VOUT = 3.3V
VIN = 8V
DCR = 15.6mΩ
V
V
IN = 12V
IN = 18V
10
0
f
SW = 480kHz
Figure 1. Typical Application Circuit
0
1
2
3
4
Load Current (A)
SG Micro Corp
www.sg-micro.com
NOVEMBER,2022–REV. A
4.5V to 18V Input, 4A,
SGM61130
Synchronous Buck Converter
PACKAGE/ORDERING INFORMATION
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESCRIPTION
ORDERING
NUMBER
PACKAGE
MARKING
PACKING
OPTION
MODEL
SGM
SGM61130
TQFN-3.5×3.5-14L
SGM61130XTRI14G/TR
61130RI
XXXXX
Tape and Reel, 6000
-40℃ to +125℃
MARKING INFORMATION
NOTE: XXXXX = Date Code, Trace Code and Vendor Code.
X X X X X
Vendor Code
Trace Code
Date Code - Year
Green (RoHS & HSF): SG Micro Corp defines "Green" to mean Pb-Free (RoHS compatible) and free of halogen substances. If
you have additional comments or questions, please contact your SGMICRO representative directly.
OVERSTRESS CAUTION
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed in Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods
may affect reliability. Functional operation of the device at any
conditions beyond those indicated in the Recommended
Operating Conditions section is not implied.
VIN Voltage........................................................ -0.3V to 22V
PVIN Voltage ..................................................... -0.3V to 22V
EN, PG, RT/CLK Voltages................................... -0.3V to 6V
BOOT Voltage ................................................... -0.3V to 29V
FB, COMP, SS/TR Voltages................................ -0.3V to 3V
BOOT to SW.............................................................0V to 7V
SW to GND........................................................... -1V to 22V
SW to GND (10ns Transient)................................ -3V to 22V
Package Thermal Resistance
ESD SENSITIVITY CAUTION
This integrated circuit can be damaged if ESD protections are
not considered carefully. SGMICRO recommends that all
integrated circuits be handled with appropriate precautions.
Failureto observe proper handlingand installation procedures
can cause damage. ESD damage can range from subtle
performance degradation tocomplete device failure. Precision
integrated circuits may be more susceptible to damage
because even small parametric changes could cause the
device not to meet the published specifications.
TQFN-3.5×3.5-14L, θJA.............................................. 42℃/W
Junction Temperature.................................................+150℃
Storage Temperature Range.......................-65℃ to +150℃
Lead Temperature (Soldering, 10s)............................+260℃
ESD Susceptibility
HBM.............................................................................2000V
CDM ............................................................................1000V
RECOMMENDED OPERATING CONDITIONS
Input Voltage Range............................................4.5V to 18V
Power Stage Input Voltage Range.......................1.8V to 18V
Operating Junction Temperature Range......-40℃ to +150℃
DISCLAIMER
SG Micro Corp reserves the right to make any change in
circuit design, or specifications without prior notice.
SG Micro Corp
www.sg-micro.com
NOVEMBER 2022
2
4.5V to 18V Input, 4A,
SGM61130
Synchronous Buck Converter
PIN CONFIGURATION
(TOP VIEW)
RT/CLK
PG
1
14
2
3
4
5
6
13
GND
GND
PVIN
PVIN
VIN
BOOT
12
SW
GND
11
SW
10
EN
9
SS/TR
7
8
FB
COMP
TQFN-3.5×3.5-14L
PIN DESCRIPTION
PIN
NAME
I/O
FUNCTION
Frequency Setting Resistor (RT) or External Clock Input Pin. An input pin for RT programming
resistor or external CLK input (auto select) for setting the switching frequency. In RT mode, an
external timing resistor connected between this pin and GND adjusts the switching frequency.
In CLK mode, an external clock sets the switching frequency.
1
RT/CLK
I
2, 3
4, 5
6
GND
PVIN
VIN
G
P
P
I
Ground Pin.
Power Input for the Power Stage Switches. PVIN voltage can be lower or higher than VIN
voltage.
Power Input for the Control Circuitry.
7
FB
Feedback Input. Inverting Input of the Transconductance Error Amplifier.
Transconductance Error Amplifier Output. Connect the frequency compensation circuit
between this pin and GND.
8
COMP
O
Soft-Start and Tracking Input. Connect a capacitor between the SS and GND pins to set the
rise time of the internal reference voltage. A voltage applied on this pin (TR) overrides the
internal reference and the output will follow that voltage. This feature is used for tracking and
sequencing functions.
9
SS/TR
I/O
Enable Input Pin with Internal Pull-up. Float this pin to enable the device or pull it down to
disable it. The EN input could regulate the input UVLO by a resistor divider from VIN or PVIN.
10
EN
I
11, 12
SW
O
Switching Node Output of the Converter.
Bootstrap Input to Supply the High-side Gate Driver. A bootstrap capacitor (0.1µF) is required
between the BOOT and SW pins. The voltage on this capacitor supplies the gate driver of the
high-side MOSFET.
Power Good Open-Drain Output Pin. PG is released to go high by the external pull-up resistor
if the output is in regulation. It is pulled low during soft-start, when EN is low or during fault
events such as thermal shutdown, dropout or over-voltage.
13
14
BOOT
PG
I
O
Package Exposed Pad and Analog Ground. This pad must be soldered to the ground plane for
proper operation and heat relief. Connect it to a PCB ground on the top layer that is only
connected to the GND pins and use it as reference for RT/CLK, COMP, SS/TR, UVLO setting
and VIN bypass.
Exposed
Pad
—
G
NOTE: I = input, O = output, I/O = input or output, G = ground, P = power.
SG Micro Corp
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NOVEMBER 2022
3
4.5V to 18V Input, 4A,
SGM61130
Synchronous Buck Converter
ELECTRICAL CHARACTERISTICS
(TJ = -40℃ to +125℃, VIN = 4.5V to 18V, VPVIN = 1.8V to 18V, typical values are at TJ = +25℃, unless otherwise noted.)
PARAMETER
Supply Voltage (VIN and PVIN Pins)
PVIN Operating Input Voltage
PVIN OVP
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VPVIN
1.8
18
V
V
VPVIN_OVP VPVIN rising
VPVIN_OVP_HYS VPVIN falling
VIN
24
PVIN OVP Hysteresis
300
mV
V
VIN Operating Input Voltage
VIN Internal UVLO Threshold
VIN Internal UVLO Hysteresis
VIN Shutdown Supply Current
4.5
18
VIN_UVLO
VIN rising
4.0
180
3.4
4.5
V
mV
μA
ISD
VEN = 0V
6.5
1.5
VIN Non-Switching Operating Supply
Current
VFB = 810mV
1.1
mA
Enable and UVLO (EN Pin)
Enable Rising Threshold
Enable Falling Threshold
Input Current
VENRISING Rising
VENFALLING Falling
1.24
1.20
1.15
3.4
1.40
V
V
1.05
IP
IH
VEN = 1.0V
VEN = 1.4V
μA
μA
Hysteresis Current
Reference Voltage
0.792
0.788
0.800
0.808
0.812
Measured at FB, TJ = +25℃
Reference Voltage
VREF
V
Measured at FB
Power MOSFETs
High-side Switch Resistance
High-side Switch Resistance (1)
Low-side Switch Resistance(1)
Error Amplifier
BOOT-SW = 3V
BOOT-SW = 5V
VIN = 12V
48
46
34
84
80
60
RDSON_H
RDSON_L
mΩ
mΩ
Error Amplifier Transconductance (gm)
Error Amplifier DC Gain
Error Amplifier Source/Sink Current
Start Switching Threshold
COMP to ISWITCH gm
gmEA
ADC
-2μA < ICOMP < 2μA, VCOMP = 1V
VFB = 0.8V
1450
10000
±130
0.79
15
μA/V
V/V
μA
VCOMP = 1V, 100mV input overdrive
V
gmPS
A/V
Current Limit
High-side Switch Current Limit Threshold IOC_HS_PK
5.8
4.6
2
7.1
6.3
8.5
7.8
5
A
A
TJ = +25℃
TJ = +25℃
TJ = +25℃
Low-side Switch Sourcing Current Limit
Low-side Switch Sinking Current Limit
Hiccup Wait Time
IOC_LS_SRC
IOC_LS_SNK
3.6
A
512
Cycles
Cycles
Hiccup Time before Restart
Thermal Shutdown
16384
Thermal Shutdown
TSD
175
15
℃
℃
Thermal Shutdown Hysteresis
TSD_HYS
NOTE: 1. Measured at pins.
SG Micro Corp
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NOVEMBER 2022
4
4.5V to 18V Input, 4A,
SGM61130
Synchronous Buck Converter
ELECTRICAL CHARACTERISTICS (continued)
(TJ = -40℃ to +125℃, VIN = 4.5V to 18V, VPVIN = 1.8V to 18V, typical values are at TJ = +25℃, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Timing Resistor and External Clock (RT/CLK Pin)
Minimum Switching Frequency
RRT = 240kΩ (1%)
160
400
210
480
2000
20
240
560
Switching Frequency
fSW
RRT = 100kΩ (1%)
RRT = 21.5kΩ (1%)
kHz
Maximum Switching Frequency
Minimum Pulse Width
1750
2250
ns
V
RT/CLK High Threshold
RT/CLK Low Threshold
2
0.8
V
RT/CLK Falling Edge to SW Rising Edge
Delay
Measured at 500kHz with RT resistor in
series
35
ns
Switching Frequency Range (RT Mode
Set Point and PLL Mode)
200
2000
kHz
SW (SW Pin)
Measured at 90% to 90% of VIN, +25℃,
ISW = 2A
Minimum On-Time
tON
105
0
ns
ns
Minimum Off-Time
tOFF
BOOT-SW ≥ 3V
BOOT (BOOT Pin)
BOOT-SW UVLO
2.5
3
V
Soft-Start and Tracking (SS/TR Pin)
SS Charge Current
ISS
2
μA
SS/TR to FB Matching
Power Good (PG Pin)
VSSOFFSET VSS/TR = 0.4V
42
75
mV
VFB falling (fault)
VFB rising (good)
VFB rising (fault)
VFB falling (good)
VFB = VREF, VPG = 5.5V
IPG = 2mA
91
94
FB Threshold
%VREF
109
106
10
Output High Leakage
Output Low
1000
0.3
nA
V
Minimum VIN for Valid Output
Minimum SS/TR Voltage for PG
VPG < 0.5V at 100μA
1.8
1.3
2.3
V
1.6
V
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4.5V to 18V Input, 4A,
SGM61130
Synchronous Buck Converter
TYPICAL PERFORMANCE CHARACTERISTICS
TA = +25℃, VIN = 12V, unless otherwise noted.
Startup with EN
Load Transient
VIN
AC Coupled
VOUT
EN
IOUT
VOUT
Load Step = 1A to 3A
Slew Rate = 100mA/μs
Time (2ms/div)
Pre-biased Start
Time (200μs/div)
Input Voltage Ripple with Full Load
AC Coupled
VIN
VOUT
SW
VIN
SW
Time (2ms/div)
Time (1μs/div)
Startup with VIN
Output Voltage Ripple with No Load
AC Coupled
VIN
VOUT
VOUT
SW
Time (2ms/div)
Time (1μs/div)
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NOVEMBER 2022
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4.5V to 18V Input, 4A,
SGM61130
Synchronous Buck Converter
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
TA = +25℃, VIN = 12V, unless otherwise noted.
High-side RDSON vs. Temperature
Low-side RDSON vs. Temperature
70
60
50
40
30
55
50
45
40
35
30
25
VIN = 12V
100 125
VIN = 12V
75 100 125
-50
-50
3
-25
0
25
50
75
-50
-25
0
25
50
Junction Temperature (℃)
Junction Temperature (℃)
Reference Voltage vs. Temperature
Oscillator Frequency vs. Temperature
0.805
490.0
487.5
485.0
482.5
480.0
477.5
475.0
0.803
0.801
0.799
0.797
0.795
RRT = 100kΩ
-25
0
25
50
75
100 125
-50
-25
0
25
50
75
100 125
Junction Temperature (℃)
Junction Temperature (℃)
Shutdown Current vs. Input Voltage
Non-Switching Quiescent Current vs. Input Voltage
6
1,200
1,100
1,000
900
VEN = 0V
5
4
3
2
1
TJ = -40℃
TJ = -40℃
TJ = +25℃
TJ = +125℃
TJ = +25℃
TJ = +125℃
800
6
9
12
15
18
3
6
9
12
15
18
Input Voltage (V)
Input Voltage (V)
SG Micro Corp
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NOVEMBER 2022
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4.5V to 18V Input, 4A,
SGM61130
Synchronous Buck Converter
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
TA = +25℃, VIN = 12V, unless otherwise noted.
EN Pin Hysteresis Current vs. Temperature
EN Pin UVLO Threshold vs. Temperature
3.50
3.45
3.40
3.35
3.30
3.25
3.20
1.26
1.25
1.24
1.23
1.22
1.21
VIN = 12V
VEN = 1.4V
VIN = 12V
75 100 125
-50
-50
-50
-25
0
25
50
75
100 125
-50
-25
0
25
50
Junction Temperature (℃)
Junction Temperature (℃)
EN Pin Pull-up Current vs. Temperature
Soft-Start Charge Current vs. Temperature
1.20
1.15
1.10
1.05
1.00
2.20
2.10
2.00
1.90
1.80
VIN = 12V
VEN = 1.0V
-25
0
25
50
75
100 125
-50
-25
0
25
50
75
100 125
Junction Temperature (℃)
Junction Temperature (℃)
(SS/TR - FB) Offset vs. Temperature
PG Threshold vs. Temperature
0.06
0.05
0.04
0.03
0.02
120
110
100
90
FB rising (fault) FB falling (good)
FB rising (good) FB falling (fault)
80
-50
-25
0
25
50
75
100 125
-25
0
25
50
75
100 125
Junction Temperature (℃)
Junction Temperature (℃)
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4.5V to 18V Input, 4A,
SGM61130
Synchronous Buck Converter
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
TA = +25℃, VIN = 12V, unless otherwise noted.
High-side Current Limit Threshold vs. Input Voltage
Minimum Controllable On-Time vs. Temperature
8.0
7.5
7.0
6.5
6.0
5.5
5.0
140
130
120
110
100
90
TJ = -40℃
TJ = +25℃
TJ = +125℃
fsw = 480kHz
75 100 125
4
6
8
10
12
14
16
18
-50
-50
8
-25
0
25
50
Input Voltage (V)
Junction Temperature (℃)
Minimum Controllable Duty Ratio vs. Temperature
BOOT-SW UVLO Threshold vs. Temperature
7.0
6.5
6.0
5.5
5.0
4.5
4.0
2.8
2.7
2.6
2.5
2.4
2.3
2.2
fsw = 480kHz
-50
-25
0
25
50
75
100 125
-25
0
25
50
75
100 125
Junction Temperature (℃)
Junction Temperature (℃)
Load Regulation
Line Regulation
0.3
0.2
0.4
0.3
0.2
0.1
0.1
0.0
0.0
-0.1
-0.2
-0.3
-0.4
-0.1
-0.2
-0.3
VIN = 12V
IOUT = 4A
16 18
0
1
2
3
4
10
12
14
Load Current (A)
Input Voltage (V)
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4.5V to 18V Input, 4A,
SGM61130
Synchronous Buck Converter
FUNCTIONAL BLOCK DIAGRAM
PG
EN
PG
Discharge
IP
IH
VIN
Thermal PVIN
UVLO
Shutdown OVP
UV
OV
Logic
BOOT
Regulator
Regulator
Shutdown
Logic
EN
Threshold
BOOT
PVIN
PVIN
Current
Sense
0.8V Ref
BOOT
UVLO
Detector
ISS
2μA
High-side
Driver
PWM
Modulator
EA
SS/TR
Power Stage
& Deadtime
Control
Logic
SW
FB
Slope
Compensation
SW
Timer
and Stop
Low-side
Driver
SS
Discharge
Overload
Recovery
Detector
Low-side OCP
and
ZCD Detector
OSC and
PLL
GND
GND
COMP
RT/CLK
Figure 2. Block Diagram
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4.5V to 18V Input, 4A,
SGM61130
Synchronous Buck Converter
DETAILED DESCRIPTION
duty cycle operation is possible as long as the boot
capacitor voltage is higher than the 2.5V (TYP)
threshold (preset UVLO level).
Overview
The SGM61130 is a 4.5V to 18V, 4A, synchronous
Buck converter with integrated high-side and low-side
MOSFETs. The minimum achievable output voltage of
this converter is 0.8V, which is equal to the device
internal reference voltage (VREF).
The device contains a power good (PG) pin which
indicates the status of the output voltage by comparing
the FB voltage and the internal reference voltage. PG
pin is connected to the drain of internal MOSFET. The
PG signal is high when VOUT is between 94% and 106%
of its nominal (set) value and goes low if VOUT drops
below 91% or rises above 109% of its nominal value.
SGM61130 can provide fast transient response with a
simple compensation circuit with constant frequency
and peak current mode control. The wide switching
frequency is adjustable from 200kHz to 2000kHz to
allow optimization of the efficiency and size of the
converter. For adjusting the internal switching
frequency, an external resistor RRT is put between the
RT/CLK pin and GND. The device also accepts an
external clock source on this pin to synchronize the
oscillator using the internal phase locked loop (PLL).
The SS/TR (soft-start/tracking) pin can be used to
minimize the inrush currents (soft-start function) with a
small value capacitor, or for power supply sequencing
during power-up with a resistor divider from preceding
voltage rail. It is the input pin for the voltage that is
followed by the output when the power supply is used
in the tracking mode.
This device has a safe and monotonic startup in output
pre-biased conditions. The VIN must exceed the
under-voltage lockout threshold (UVLO, 4.0V TYP) for
device power-up. The UVLO thresholds can be
adjusted (increased) by connecting the EN pin to the
tap point of a resistor divider between the VIN (or PVIN)
pin and GND. The EN internal pull-up current source
and the resistor divider determine the UVLO thresholds.
When the EN is floated or is pulled high, the device is
enabled and the total device current (no switching) is
near 1100μA. Pulling the EN pin low will shut down the
device with 3.4μA (TYP) supply current.
The SGM61130 is protected from output over-voltage,
over-current and over-heating damage. The output
over-voltage transients are effectively minimized by the
over-voltage comparator of the power good circuit.
When an over-voltage occurs, the high-side switch is
forced off and allowed to turn on again if the VOUT drops
below 106% of its nominal value.
High-side MOSFET is naturally protected from sourcing
over-current by peak current mode control. The
low-side MOSFET is also protected bidirectionally
against over-current. This feature helps the control of
the inductor current to avoid current runaway.
The integrated MOSFETs are optimized for higher
efficiency at lower duty cycles. They can efficiently
provide up to 4A continuous output current.
If a die temperature is too high (TJ > TSD), the device
will stop switching and go to shutdown state. It will
automatically recover with a soft-start when the junction
temperature drops 15℃ (TYP) below the shutdown
temperature.
The integrated bootstrap circuit along with the external
boot capacitor provides the bias voltage for the
high-side MOSFET driver. The voltage of the bootstrap
capacitor that is placed between the BOOT and SW
pins is continuously monitored for bootstrap UVLO
(BOOT-SW UVLO) detection. If the boot capacitor
voltage drops below the bootstrap UVLO, the SW pin
will be pulled low to recharge the boot capacitor. 100%
Note that a continued overload condition may cause a
cycling thermal shutdown and recovery. It will depend
on the temperature and the ventilation conditions of the
system.
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4.5V to 18V Input, 4A,
SGM61130
Synchronous Buck Converter
DETAILED DESCRIPTION (continued)
PVIN
Power Input Pins
IH
VIN and PVIN pins can be tied together or separated
depending on the application and minimum input
voltage. The VIN pin supplies the internal circuits of the
device and needs to be above 4.5V, while the PVIN
provides the supply voltage for the switches and can go
down to 1.8V. Therefore, if these pins are tied, the input
voltage range is from 4.5V to 18V. A voltage divider
connected to the EN pin from either VIN or PVIN can be
used to adjust the power supply UVLO. For a
consistent power-up behavior, PVIN is the
recommended source for the UVLO programming.
IP
R11
EN
R12
Figure 4. PVIN UVLO Setting with a Resistor Divider
(VIN ≥ 4.5V)
PVIN
IH
VIN
IP
R11
EN
EN Pin and UVLO Programming
The EN pin is used to turn the device on and off. The
device starts operation when the EN voltage rises
above the enable rising threshold. Pulling the EN
voltage below the enable falling threshold stops
switching and reduces the device current to the very
low quiescent shutdown level. Floating the EN pin will
enable the device due to its internal pull-up current
source. This current source is used for programming
the UVLO threshold. An open-drain or open-collector
output connected to the EN pin can be used to control
the device. An internal UVLO circuit is implemented on
the VIN pin to disable the device and prevent
malfunction when the supply voltage is too low. The
internal VIN UVLO hysteresis is 180mV. To program a
higher UVLO threshold for the VIN or to add a
secondary UVLO on the PVIN that is typically needed
for split-rail applications, the EN pin can be configured
to one of the configurations shown in Figure 3, Figure 4,
or Figure 5. Without external components, the internal
pull-up current (IP) sets the EN pin default state to
enable. When the device is enabled, the second
current source (IH) is activated. IP and IH are used to set
the UVLO.
R12
Figure 5. VIN and PVIN UVLO Setting
The resistor divider can be calculated from Equations 1
and 2 based on the desired UVLO start and stop
thresholds. A 500mV or higher hysteresis (VSTART
VSTOP) is recommended for the UVLO programming.
-
VENFALLING
VENRISING
VSTART
�
ꢀ - VSTOP
R11
=
(1)
(2)
V
IP �1 - ENFALLINGꢀ + IH
VENRISING
R11 × VENFALLING
R12
=
VSTOP - VENFALLING + R11(IP + IH)
where:
• IH = 3.4μA.
• IP = 1.15μA.
• VENRISING = 1.24V.
• VENFALLING = 1.20V.
Soft-Start (SS/TR)
The lower voltage between the internal VREF and the
SS/TR pin is used as the reference to regulate the
output. The soft-start capacitor is connected to the
SS/TR pin and is charged by a 2μA internal current
source to set the soft-start time (tSS).
VIN
IH
IP
R11
EN
R12
Equation 3 can be used to calculate the soft-start time
for a selected soft-start capacitor (CSS).
(
)
CSS nF × VREF (V)
Figure 3. VIN UVLO Setting with a Resistor Divider
tSS (ms) =
(3)
ISS (μA)
where:
• VREF = 0.8V.
• ISS is the soft-start current source (2μA).
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Synchronous Buck Converter
DETAILED DESCRIPTION (continued)
under 1.3V (TYP), or if a fault such as UVLO or thermal
shutdown occurs, PG is also pulled low.
Startup with Pre-biased Output
The low-side switch is prohibited from turning on and
discharging the output if a pre-biased voltage is sensed
on the output before startup. As long as the SS/TR pin
voltage is below VFB, the low-side switch is not allowed
to sink current to have a monotonic startup with
pre-biased output.
A 10kΩ to 100kΩ pull-up resistor connected to a
voltage rail less than 5.5V is recommended for PG. An
option is using the output voltage for PG pull-up. The
state of PG is valid only if the VIN > 1.8V. The current
sinking capability of PG is limited until VIN exceeds the
4.5V at which the full sinking capacity is available.
Reference Voltage (VREF
)
A precise 0.8V reference is internally implemented by
scaling the output of a temperature-stable bandgap
circuit. The reference voltage tolerance over the whole
temperature range is ±1.5%. The actual reference
voltage for output setting is changed during startup or
tracking.
Frequency and Synchronization (RT/CLK)
The device can operate in two modes to adjust
switching frequency.
In the RT mode, a resistor (RRT) is placed between the
RT/CLK and GND pins to set the free running switching
frequency of the PLL. It can be set between 200kHz to
2000kHz by choosing RRT resistor between 240kΩ to
21.5kΩ respectively.
Output Voltage Setting
The output voltage of the device can be adjusted by
resistors R1 and R2 which are connected to the FB pin
(see Figure 1). Use resistors with 1% tolerance or
better for good output accuracy. The values of R1 and
R2 (upper and lower resistors) can be calculated by
In the CLK mode, an external clock drives the RT/CLK
pin and the internal switching clock oscillator is
synchronized to CLK by the PLL. The CLK mode
overrides the RT mode. The device automatically
detects the input clock and switches to the CLK mode.
Equation 4 based on the desired output voltage (VOUT
)
and VREF
.
VOUT - VREF
Constant Frequency PWM
R1 =
× R2
(4)
VREF
The SGM61130 operates at fixed frequency that can be
set by an external resistor or synchronized by external
clock.
where:
• VREF = 0.8V.
It is based on peak current control mode architecture.
The high-side MOSFET is turned on until the sensing
current ramp signal reaches the COMP voltage
determined by the EA. If the switch current does not
reach the reference value that generates from the
COMP voltage at the end of a cycle, the high-side
switch remains on for the next cycle until the current
meets the reference value. A slope compensation block
slightly reduces the sensed high-side switch current
before comparison (depending on the on-time) to avoid
sub-harmonic oscillations.
For example, a 10kΩ resistor can be chosen for R2 and
then R1 is calculated. Do not choose too large resistors
that may cause output errors due to the FB bias current
or make the regulator susceptible to the noises coupled
to the FB input.
The minimal output voltage is determined by the
minimum on-time of the high-side switch. The maximal
output voltage is constrained by the bootstrap voltage.
More details are provided in the Bootstrap Voltage
(BOOT) and Operation with Low Dropout (100% Duty
Cycle) section.
Continuous Current Mode (CCM) Operation
In most load conditions, the device operates in
continuous conduction mode (CCM) (forced PWM). For
light loads, the inductor current can be negative when
the low-side switch is on. However, if the current
reaches the low-side sinking current limit, the low-side
switch will be forced off.
Power Good (PG)
The PG is an open-drain output. It is released if there is
no fault and the FB pin voltage is in regulation. The PG
is pulled low if the FB voltage is lower than 91% or
above 109% of the reference voltage. When the device
is disabled by EN pin or the voltage of SS/TR pin is
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Synchronous Buck Converter
DETAILED DESCRIPTION (continued)
Error Amplifier
Over-Current Protection
The output voltage is sensed by a resistor divider
through the FB pin and is compared with the internal
reference. The error amplifier generates an output
current that is proportional to the voltage difference
(error), and the transconductance is 1450μA/V. The
generated current is then fed into the external
compensation network to generate the voltage on the
COMP pin, which sets the reference value for the peak
current that controls the on-time of the power MOSFET.
COMP is pulled down to the ground when the device
shuts down.
Both high-side and low-side switches are protected
from over-current with cycle-by-cycle current limiting as
will be explained in the next two sections.
High-side Switch Over-Current Protection
Using current mode control, the pulse width (from the
beginning of the cycle until high-side turn-off) is
determined by the compensator output voltage (VCOMP
at COMP pin) in a cycle-by-cycle basis. In each cycle
the high-side switch current is continuously compared
with the current set point determined by compensator
output (VCOMP) and when the high-side current reaches
to that reference (peak current), the high-side switch is
turned off. Considering the internal delay and
inductance current slope, the actual current limit value
will be slightly larger than the value in Electrical
Characteristics section.
Slope Compensation
To avoid sub-harmonic oscillations that result in
unstable PWM pulses,
a
small negative-slope
compensating ramp is added to the measured switch
current before it is used to generate the PWM signal.
The slope compensation has no influence on the peak
current limit which is maintained over full range of duty
cycle.
Low-side MOSFET Over-Current Protection
The current of the low-side switch is continuously
monitored while it is turned on. Normally, the low-side
switch sources current from ground to the load through
the inductor. Before the beginning of a new cycle, the
low-side current is compared to its current limit which is
normally lower than the high-side current limit. Only
when the low-side source current drops below its
current limit, the high-side MOSFET will turn on again
for the new cycle.
Output Over-Voltage Protection (OVP)
The device contains an over-voltage protection circuit
to avoid high overshoots of the output voltage during
operation. Usually an OVP occurs after removal of an
overload condition. When the output voltage is dropped
due to a persisting overload, the error amplifier output
reaches to its maximum and forces the converter to
provide the maximum output current. Upon removal of
the overload condition, the regulator output rises
quickly because the high inductor current charges the
output capacitor rapidly, especially if COUT is small. The
error amplifier will respond and re-adjust itself but not
as fast as the output filter (LC) and an overshoot
occurs.
In some operating conditions, the low-side switch sinks
current from the load to the ground. If the low-side
sinking current exceeds the typical limit of 3.6A, the
low-side switch will immediately turn off and both the
switches will not turn on until the end of the cycle.
Thermal Shutdown
To minimize the overshoots, the device monitors the FB
pin voltage and compares it to the internal OVP
threshold. If the threshold is exceeded, the high-side
MOSFET is turned off to stop feeding current to the
output. When the FB voltage drops below the OVP
threshold, the high-side MOSFET can turn on again in
the next cycle.
To protect the device from damage due to overheating,
a thermal shutdown feature is implemented to disable
the device when the die temperature exceeds +175℃
(TYP).
A
new power-up sequence is initiated
automatically once the temperature falls below +160℃
(15℃ hysteresis, TYP).
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Synchronous Buck Converter
DETAILED DESCRIPTION (continued)
Small Signal Model
Simplified Model for Peak Current Mode
A simplified small signal model to design the frequency
compensation network is given in Figure 7. The power
stage and duty cycle modulator are approximated by a
voltage-controlled current source (VCCS) that is
controlled by the error amplifier output (VCOMP) and
provides current to the output capacitor and the load.
Feedback Loop Small Signal Model
The equivalent small signal model of the control loop
for frequency response and transient analysis is given
in Figure 6.
The compensation network (R3, C1 and C2) is placed in
the output of the transconductance error amplifier (EA).
The EA can be simplified as an ideal voltage controlled
current source with 1450μA/V gain. The ROEA (6.9MΩ)
models the frequency response of the EA. Power
converter is modeled with a pure 15A/V gain. The
inductor dynamics is effectively removed in the
cycle-by-cycle average small signal model, because
with the current mode control the inductor average
current is set by the compensator. The COUT and RESR
model the output capacitance and its parasitic ESR. To
measure the frequency response, the loop is broken at
points ‘a’ and ‘b’ to insert a small signal (e.g. 1mV) AC
source. For small signal frequency response analysis,
the magnitude and phase versus frequency for the
output to input transfer functions of each stage is
plotted. The ‘a/c’ (power stage gain), ‘c/b’
(compensation gain) and ‘a/b’ (loop gain) voltage ratios
are commonly used for the analysis. To simulate or test
the response of the output to load steps in time domain
(dynamic loop response), the load (RL) is replaced with
a stepping current source with proper amplitude,
repetition rate and rate of change (A/µs) depending on
the application. As a common example, stepping
between 25% and 75% of the nominal load with ±1A/µs
slew rate and repeating at 1kHz or 10kHz can be used
for testing and comparison of the power supply
transient response to rapid load changes.
The control-to-output transfer function (VOUT/VCOMP
)
consists of a DC voltage gain (ADC), a dominant pole (fP)
determined by RL × COUT time constant, and a simple
ESR-zero (fZ) determined by RESR × COUT time constant
as given in Equations 5, 6, 7 and 8. The VCCS
transconductance is the ratio of the output current
change to the control voltage (COMP) change. This is
equivalent to the power stage transconductance (gmPS)
that is 15A/V for this device. As indicated in Equation 6,
for resistive loads, the DC voltage gain (ADC) is equal to
the power stage transconductance (gmPS) multiplied by
the load resistance (RL). Therefore, the DC gain drops
with the reduced load resistance. This relationship can
be problematic because it could move the crossover
frequency of the converter in the same way.
VOUT
VCOMP
RESR
ADC
RL
fP
gmPS
COUT
fZ
Figure 7. Simplified Model for Peak Current Mode Control
and Frequency Response
s
(1 +
(1 +
)
)
VOUT (V)
VCOMP
2π × fZ
= ADC
×
(5)
s
SW
VOUT
Power Stage
2π × fP
15A/V
a
ADC = gmPS × RL
(6)
(7)
b
1
fP =
R1
RESR
COUT × RL × 2π
COMP
-
RL
1
c
FB
fZ =
(8)
+
VREF
COUT × RESR × 2π
R3
C1
gmEA
1450μA/V
COUT
R2
ROEA
C2
where:
• gmPS is the gain of the power stage (15A/V).
• RL is the load resistance.
• COUT is the output capacitance.
Figure 6. Small Signal Model for Loop Response
• RESR is the equivalent series resistance of the output
capacitor.
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SGM61130
Synchronous Buck Converter
DETAILED DESCRIPTION (continued)
Fortunately, the dominant pole also moves with load
current as given in Equation 7. As highlighted in Figure
7, the crossover frequency (0dB gain location) is not
affected by the combined effect. With the decrease of
load current, the gain increases and the pole frequency
General Guidelines for Loop Compensation
Design
1. The first step is to determine the crossover frequency,
which is normally set to 1/10th of the switching
frequency.
decreases. Having
simplifies the design of the frequency compensation for
a changing load.
a
fixed crossover frequency
COUT is also initially chosen based on the switching
frequency and ripple requirement.
2. R3 can be determined by:
Small Signal Model for Frequency
Compensation
2π × fC × VOUT × COUT
R3 =
(9)
gmEA × VREF × gmPS
The SGM61130 can easily use the common Type 2 and
3 compensation circuits, as shown in Figure 8.
Compared to Type 2B, the Type 2A compensation has
an extra high-frequency pole (by C2) to attenuate
high-frequency noise and ensure that gain remains
very low at high frequencies against the ESR-zero
effect that tends to increase the gain at higher
frequencies. In the Type 3 compensation, the additional
where:
• gmEA is the gm amplifier gain (1450μA/V).
• gmPS is the power stage gain (15A/V).
• VREF is the reference voltage (0.8V).
3. A compensating zero should be placed at the
dominated pole of the device, which is at
1
fP =
× 2π. C1 can be determined by:
C
×
R
OUT
L
C
10 capacitor is added in parallel to the upper feedback
RL × COUT
C1 =
R3
(10)
resistor divider for phase Boost at the crossover
frequency. An extra resistor may be used in series with
4. C2 is optional and adds a high frequency pole to
cancel the zero created by the output capacitor ESR.
C
10 for more control on the phase Boost. The following
guidelines are provided for designers who prefer to
compensate by the standard loop design method.
These equations are only available for those
applications where the ESR-zero is higher than the
control loop bandwidth (crossover frequency). This
condition is usually valid when ceramic output
capacitors are used. For low frequency ESR-zeros
(capacitors with high ESR) see the Application
Information section for a detailed design procedure.
RESR × COUT
C2 =
(11)
R3
5. C10 can be added for Type 3 compensation that
allows a slightly higher bandwidth and better phase
margin. If C10 is needed, use Equation 12.
1
C10
=
(12)
2π × R1 × fC
VOUT
Type 3
C10
R1
FB
Type 2B
Type 2A
COMP
-
+
VREF
R3
C1
R3
C1
gmEA
R2
ROEA
C2
Figure 8. Types of Frequency Compensation
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Synchronous Buck Converter
DETAILED DESCRIPTION (continued)
RT/CLK
Device Functional Modes
Mode Select
SGM61130
Switching Frequency Setting (RT Mode)
Selection of the switching frequency is generally a
tradeoff between the solution size, efficiency, and the
minimum controllable on-time. The RT resistance can
be designed from Equation 13.
RT/CLK
RRT
52407
fSW (kHz)
RRT (kΩ) =
- 5
(13)
Figure 10. Using RT and CLK Modes Together
250
200
150
100
50
Bootstrap Voltage (BOOT) and Operation with Low
Dropout (100% Duty Cycle)
An integrated bootstrap regulator is used for powering
the high-side MOSFET gate driver. A small 0.1μF
ceramic capacitor (X5R or X7R grade) with at least 10V
rating is required between the BOOT and SW pins to
supply the gate driver. It is recharged from VIN source
through an internal switch every time the SW goes low.
Recharge happens when the BOOT pin voltage is less
than VIN and the BOOT-SW voltage is below the
required regulation for the high-side gate voltage.
0
The SGM61130 has no minimum off-time. It can
operate at 100% duty cycle as long as the BOOT-SW
voltage is higher than its UVLO threshold (2.5V TYP). If
the BOOT-SW voltage drops below its UVLO threshold,
the high-side switch turns off and the low-side switch
turns on to recharge the boot capacitor. If the input
voltage rails are split (separate VIN and PVIN sources),
the 100% duty cycle can be implemented continuously
200 400 600 800 1000 1200 1400 1600 1800 2000
fSW − Oscillator Frequency (kHz)
Figure 9. RT Resistance vs. Switching Frequency
Synchronization (CLK Mode)
The device uses an internal phase locked loop (PLL) to
set or synchronize to an external clock signal with the
200kHz to 2000kHz range. Mode change from RT
mode to CLK mode is allowed.
as long as VIN is at least 4.0V above VPVIN
.
Startup Sequencing (SS/TR)
The SS/TR, EN and PG pins allow the implementation
of common power supply sequencing methods. A
simple sequencing approach is shown in Figure 11 in
which the right side SGM61130 device is powered up
after the left one. The PG of the left device is coupled to
the EN pin of the right. The power supply on the right
side is enabled after the left supply reaches regulation.
For stable synchronization, a square wave clock with
20% to 80% duty cycle must be applied to the RT/CLK
pin. The logic low and high levels of the clock must be
below 0.8V and above 2.0V respectively. The switching
cycle starts with the falling edge of the RT/CLK signal.
If both RT and CLK modes are needed in an application,
configuration shown in Figure 10 can be used. The RT
mode can be overridden by CLK mode when both RRT
and clock are present. Mode switch occurs when the
RT/CLK is pulled above 2.0V for the first time. Once
CLK mode is selected, the PLL is locked to external
CLK and the RT/CLK pin shifts to a high-impedance
state. Going back from CLK mode to RT mode is not
recommended, because by removing clock the
switching frequency drops to around 100kHz first
(waiting for synchronize clock) before recovery to the
free running frequency that is set by RT resistor.
SGM61130
SGM61130
PG
EN
EN
SS/TR
SS/TR
PG
Figure 11. Sequential Startup Sequence
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4.5V to 18V Input, 4A,
SGM61130
Synchronous Buck Converter
DETAILED DESCRIPTION (continued)
In this example, the second power supply output (VOUT2
tracks VOUT1 (the output of the first power supply).
)
Figure 12 shows the ratiometric sequencing of two
converters. The SS/TR and EN inputs of the two
devices are tied together. In this configuration, the ISS
current sources from the SS/TR pins are added
together and 2 × ISS should be considered to calculate
the soft-start capacitor from Equation 3.
By proper selection of RSS1 and RSS2, VOUT2 can ramp
up and reach regulation with the same rate, or a little bit
faster or slower than VOUT1. Note that VOUT2 is tracking
VOUT1 and reaches regulation first. Equations 14 and 15
can be used to calculate the tracking resistors. ∆V is
the desired VOUT1 - VOUT2 difference when VOUT2
reaches regulation. ∆V will be positive when VOUT1
change rate is higher than VOUT2 startup rate. It will be
negative if VOUT2 rate is faster. With simultaneous
sequencing, ∆V is zero. To assure the proper device
operation, make sure that the selected RSS1 is larger
than the value given in Equation 17.
EN
SGM61130
SS/TR
PG
CSS
VOUT2 + ∆V VSSOFFSET
(14)
RSS1
=
×
EN
VREF
ISS
SGM61130
VREF × R1
VOUT2 + ∆V - VREF
(15)
SS/TR
PG
RSS2
=
(16)
(17)
∆V = VOUT1 − VOUT2
RSS1 > 2800× VOUT1 - 180× ∆V
Figure12. Ratiometric Sequencing of Two Devices
Simultaneous ratiometric sequencing can also be
implemented by using a resistor divider as shown in
The VSSOFFSET is the inherent SS/TR to FB offset of the
device (42mV TYP) and ISS is the pull-up current source
(2µA).
Figure 13 by RSS1 and RSS2
.
BOOT
EN
L1
CBOOT1
VOUT1
SW
SGM61130
SS/TR
PG
CSS
BOOT
SW
L2
EN
CBOOT2
VOUT2
SGM61130
RSS1
SS/TR
PG
RSS2
FB
R1
R2
Figure 13. Ratiometric and Simultaneous Startup
Sequence
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4.5V to 18V Input, 4A,
SGM61130
Synchronous Buck Converter
APPLICATION INFORMATION
Typical Application
The schematic of a typical application circuit that is used for SGM61130 evaluation module is given in Figure 14.
C6
0.1μF
C1
4.7μF
C2
4.7μF
C7
22μF
C8
C9
EC1
100μF/35V
22μF 22μF
+
L1
4.7μH
13
BOOT
4
5
11
12
PVIN
PVIN
SW
SW
VIN
8V to 18V
VOUT =3.3V, 4A
C10
NS
R5
31.6kΩ
SGM61130
R7
100kΩ
7
6
VIN
EN
FB
10
R1
59kΩ
9
1
14
8
SS/TR
PG
PG
C3
4.7μF
RT/CLK
GND
COMP
EN
R4
2.4kΩ
2
3 15
R6
10kΩ
R3
100kΩ
R2
11.5kΩ
C11
10nF
C5
150pF
C4
22nF
NOTE: EC1 is optional. If VIN pin is more than 200mm far from the PVIN of SGM61130, or the VIN pin is not connected with the
PVIN of SGM61130, or the input voltage is on/off by air-break switch, EC1 should be installed. Otherwise, the spike voltage over
20V at the input side is caused, which will damage the device.
Figure 14. 3.3V Output Typical Application Circuit
Design Requirements
Operating Frequency
In this example, a high frequency regulator with
ceramic output capacitors will be designed using
SGM61130 and the details will be reviewed. The design
requirements are typically determined at the system
level. In this example, the known parameters are
summarized in Table 1.
Usually the first parameter to design is the switching
frequency (fSW). Higher switching frequencies allow
smaller solution size and smaller filter inductors and
capacitors and the bandwidth of the converter can be
increased for faster response. It is also easier to filter
noises because they also shift to higher frequencies.
The drawbacks are increased switching and gate
driving losses that result in lower efficiency and tighter
thermal limits. Also the duty cycle range and Buck ratio
will be limited due to the minimum on-time and/or
Table 1. Design Parameters
Design Parameter
Output Voltage
Example Value
3.3V
Maximum Output Current
Transient Response 2A Load Step
Input Voltage Range
4A
ΔVOUT = 5%
12V nominal, 8V to 18V
33mVP-P
off-time limits of the converter. In this design, fSW
=
480kHz is chosen as a tradeoff. From Equation 13 the
nearest standard resistor for this frequency is R3 =
100kΩ.
Maximum Output Voltage Ripple
Input Turn-On Voltage (VIN Rising)
Input Turn-Off Voltage (VIN Falling)
7.5V
7.1V
Switching Frequency (fSW
)
480kHz
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4.5V to 18V Input, 4A,
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Synchronous Buck Converter
APPLICATION INFORMATION (continued)
SPM10040T-4R7M with 8A saturation and 7.9A RMS
current ratings is selected for L1.
Inductor Design
Equation 18 is conventionally used to calculate the
output inductance of a Buck converter. Generally, a
smaller inductor is preferred to allow larger bandwidth
and smaller size. The ratio of inductor current ripple (∆IL)
to the maximum output current (IOUT) is represented as
KIND factor (∆IL/IOUT). The inductor ripple current is
bypassed and filtered by the output capacitor and the
inductor DC current is passed to the output. Inductor
ripple is selected based on a few considerations. The
peak inductor current (IOUT + ∆IL/2) must have a safe
margin from the saturation current of the inductor in the
worst-case conditions especially if a hard-saturation
core type inductor (such as ferrite) is chosen. During
power-up with large output capacitor, over-current,
output shorted or load transient conditions, the actual
peak current of inductor can be greater than IL_PEAK
calculated in Equation 21. For peak current mode
converter, selecting an inductor with saturation current
above the switch current limit is sufficient. The ripple
current also affects the output capacitor selection. COUT
RMS current rating must be higher than the inductor
RMS ripple. Typically, a 10% to 30% ripple is selected
(KIND = 0.1 ~ 0.3). Choosing a higher KIND value
reduces the selected inductance.
Output Capacitor Design
Three primary criteria must be considered for design of
the output capacitor (COUT): (1) the converter pole
location, (2) the output voltage ripple, (3) the transient
response to a large change in load current. The
selected value must satisfy all of them. The desired
transient response is usually expressed as maximum
overshoot, maximum undershoot, or maximum
recovery time of VOUT in response to a large load step.
Transient response is usually the more stringent criteria
in low output voltage applications. The output capacitor
must provide the increased load current or absorb the
excess inductor current (when the load current steps
down) until the control loop can re-adjust the current of
the inductor to the new load level. Typically, it requires
two or more cycles for the loop to detect the output
change and respond (change the duty cycle). It may
also be expressed as the maximum output voltage drop
or rise when the full load is connected or disconnected
(100% load step). The minimum output capacitance
can be given by Equation 22, which is needed to supply
or absorb a current step (ΔIOUT) for at least 2 cycles
until the control loop responds to the load change with
V
- VOUT
VOUT
VINMAX × fSW
INMAX
(18)
L1 =
×
a
maximum allowed output transient of ΔVOUT
IOUT ×KIND
(overshoot or undershoot).
In this example, KIND = 0.3 is chosen and the
inductance is calculated to be 4.68μH. The nearest
standard value is 4.7μH. The ripple, RMS and peak
inductors current calculations are summarized in
Equations 19, 20 and 21 respectively.
2× ∆IOUT
fSW × ∆VOUT
(22)
COUT
>
where:
• ΔIOUT is the change in output current.
• fSW is the regulator's switching frequency.
• ΔVOUT is the allowable change in the output voltage.
V
- VOUT
VOUT
VINMAX × fSW
INMAX
(19)
IRIPPLE
=
×
L1
2
For example, if the acceptable transient to a 2A load
step is 5%, by inserting ΔVOUT = 0.05 × 3.3V = 0.165V
and ΔIOUT = 2.0A, the minimum required capacitance
will be 50.5μF. Generally, the ESR of ceramic
capacitors is small enough. The impact of output
capacitor ESR on the transient is not taken into account
in Equation 22.
VOUT ×(V
- VOUT )
1
2
INMAX
(20)
(21)
IL_RMS
=
IOUT
+
×
12
VINMAX ×L1 × fSW
IRIPPLE
2
IL_PEAK = IOUT
+
For this example, the ripple, RMS, and peak inductor
current are calculated as 1.195A, 4.015A and 4.597A
respectively.
A
4.7μH
inductor
from
TDK
SG Micro Corp
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4.5V to 18V Input, 4A,
SGM61130
Synchronous Buck Converter
APPLICATION INFORMATION (continued)
Equation 23 can be used for the output ripple criteria
and finding the minimum output capacitance needed.
VORIPPLE is the maximum acceptable ripple. In this
example, the allowed ripple is 33mV that results in
minimum capacitance of 9.43μF.
current rating of input capacitor should be greater than
ICIRMS.
VOUT ×(VINMIN − VOUT
)
(26)
ICIRMS = IOUT
×
V
INMIN × V
INMIN
1
1
In this example, the voltage rating of capacitor should
have a safe margin from maximum input voltage.
Therefore, two 4.7µF/25V capacitors in parallel are
selected for PVIN to cover all DC bias, thermal and
aging deratings, and a 4.7μF/25V X5R capacitor is
selected for VIN. They are placed in parallel because
the VIN and PVIN inputs are tied together to operate
from a single supply in this design.
(23)
COUT
>
×
VORIPPLE
IRIPPLE
8× fSW
where:
• VORIPPLE is the maximum allowable output voltage
ripple.
• IRIPPLE is the inductor ripple current.
Note that the impact of output capacitor ESR on the
ripple is not considered in Equation 23. Use Equation
24 to calculate the maximum acceptable ESR of the
output capacitor to meet the output voltage ripple
requirement. In this example, the ESR must be less
than 33mV/1.195A = 27.6mΩ.
The input voltage ripple can be calculated from
Equation 27. The maximum ripple occurs at 50% duty
cycle. In this example, the input voltage ripple is
222mV.
IOUTMAX ×D×(1-D)
(27)
ΔV
=
IN
CIN × fSW
VORIPPLE
(24)
RESR
<
IRIPPLE
Soft-Start Capacitor
Higher nominal capacitance value must be chosen due
to aging, temperature and DC bias derating of the
The soft-start capacitor programs the ramp-up time of
the output voltage during power-up. The ramp is
needed in many applications due to limited voltage
slew rate required by the load or limited available input
current to avoid input voltage sag during startup (UVLO)
or to avoid over-current protection that can occur during
output capacitor charging. Soft-start will solve all these
issues by limiting the output voltage slew rate.
output capacitors. In this example, a 3 × 22μF/25V
X7R ceramic capacitor with 3mΩ of ESR is used. The
amount of ripple current that a capacitor can handle
without damage or overheating is limited. The inductor
ripple is bypassed through the output capacitor.
Equation 25 calculates the RMS current that the output
capacitor must support. In this example, it is 345mA.
Equation 28 (with ISS = 2μA and VREF = 0.8V) can be
used to calculate the soft-start capacitor for a required
soft-start time (tSS). In this example, the output
capacitor value is relatively small (51μF) and the
soft-start time is not critical because it does not require
too much charge for 3.3V output voltage. However, it is
better to set a small arbitrary value, like CSS = 10nF that
results in 4ms startup time.
VOUT ×(VINMAX − VOUT
)
(25)
ICORMS
=
12 × VINMAX ×L1 × fSW
Input Capacitor Design
A high-quality ceramic capacitor (X5R or X7R or better
dielectric grade) must be used for input decoupling of
the SGM61130. At least 4.7μF of effective capacitance
(after deratings) is needed on the PVIN input and
similar amount is also needed for the VIN pin. If input
power is far away from this device, additional bulk
capacitor is recommended in parallel to stabilize input
voltage. The RMS value of input capacitor can be
calculated from Equation 26 and the maximum ICIRMS
occurs at 50% duty cycle. For this example, the
maximum input RMS current is 1.97A. The ripple
tSS (ms)×ISS (μA)
(28)
CSS (nF) =
VREF (V)
Bootstrap Capacitor Selection
A 0.1μF ceramic capacitor with 10V or higher voltage
rating must be connected between the BOOT and SW
pins. X5R or better dielectric types are recommended.
SG Micro Corp
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4.5V to 18V Input, 4A,
SGM61130
Synchronous Buck Converter
APPLICATION INFORMATION (continued)
• RDSON_LMIN = Minimum low-side switch RDSON (34mΩ
TYP).
• RL = Output Inductor series resistance.
UVLO Setting
The under-voltage lockout (UVLO) can be programmed
from VIN or PVIN by an external voltage divider
network. In this design, R1 is connected between VIN
and the EN pin and R2 is connected between EN and
GND (see Figure 14). The UVLO has two thresholds
(hysteresis), one for power-up (turn-on) when the input
voltage is rising and one for power-down or brown-out
(turn-off) when the voltage is falling. The turn-on
(enable to start switching) occurs when VIN rises above
7.5V (UVLO rising threshold). When the regulator is
working, it will not stop switching (disabled) until the
input falls below 7.1V (UVLO falling threshold).
Equations 1 and 2 are provided to calculate the
resistors. For this example, choose the resistors as R1
= 59kΩ and R2 = 11.5kΩ.
Loop Compensation Design
Several techniques are used by engineers to
compensate a DC/DC regulator. The recommended
calculation method here is quite simple and yields
results with high phase margins. In most conditions, the
phase margin will be between 60 and 90 degrees. In
this method the effects of the slope compensation are
ignored. Because of this approximation, the actual
cross over frequency is usually lower than the
calculated value.
First, the converter pole (fP) and ESR-zero (fZ) are
calculated from Equations 31 and 32. For COUT, the
worst derated value of 51μF should be used. Equations
33 and 34 can be used to find an estimation for
closed-loop crossover frequency (fC) as a starting point
(choose the lower value).
Feedback Resistors
The feedback resistor divider (see Figure 14, R5 and R6)
is used to set the output voltage. Choosing a 10kΩ
value for the lower resistor (R6), the upper resistor (R5)
can be calculated from Equation 29. The nearest 1%
resistor for the calculated value is 31.6kΩ. For higher
output accuracy, choose resistors with better tolerance
(0.5% or better).
IOUT
(31)
fP =
2π× VOUT ×COUT
1
(32)
fZ =
2π×RESR ×COUT
VOUT - VREF
R5 =
× R6
(29)
(33)
fC = fP × fZ
VREF
fSW
(34)
fC = fP ×
Minimum Output Voltage
2
There is a minimum output voltage limit for any given
input voltage due to the limited minimum switching
on-time of the device. Above the 0.8V minimum
possible output, the lowest achievable voltage is given
by Equation 30.
For this design, fP = 3.78kHz and fZ = 3.12MHz.
Equation 33 yields 108.6kHz for crossover frequency
and Equation 34 gives 30.1kHz. The lower value is
30.1kHz, a slightly higher frequency of 38kHz is
selected for the influence of slope compensation in the
actual circuit.
VOUTMIN = tONMIN × fSWMAX (VINMAX + IOUTMIN (RDSON_HMIN
-
R
DSON_LMIN)) - IOUTMIN (RL + RDSON_HMIN (30)
)
Having the crossover frequency, the compensation
network (R4 and C4) can be calculated. R4 programs
the gain of the compensated network at the crossover
frequency and can be calculated by Equation 35.
where:
• VOUTMIN = Minimum achievable output voltage.
• tONMIN = Minimum controllable on-time (105ns, TYP).
• fSWMAX = Maximum fSW (including tolerance).
• VINMAX = Maximum input voltage.
2π× fC × VOUT ×COUT
(35)
R4 =
gmEA × VREF × gmPS
• IOUTMIN = Minimum load current.
• RDSON_HMIN = Minimum high-side switch RDSON (46mΩ
to 48mΩ TYP).
SG Micro Corp
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NOVEMBER 2022
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4.5V to 18V Input, 4A,
SGM61130
Synchronous Buck Converter
APPLICATION INFORMATION (continued)
C4 sets the location of the compensation zero along
with R4. To place this zero on the converter pole, use
Equation 36.
Use short and wide trace to connect SW node to the
inductor. Minimize the area of switching loop.
Otherwise, large voltage spikes on the SW node and
poor EMI performance are inevitable.
VOUT ×COUT
IOUT ×R4
(36)
C4 =
Sensitive signals like FB, COMP, EN, RT/CLK traces
must be placed away from high dv/dt nodes (such as
SW) and not inside any high di/dt loop (like capacitor
or switch loops). The ground of these signals should
be connected to GND pin and separated with power
ground.
From Equations 35 and 36, the standard selected
values are R4 = 2.4kΩ and C4 = 22nF.
A high frequency pole can also be added by a parallel
capacitor if needed (not used in this example). The pole
frequency can be calculated from Equation 37.
To improve the thermal relief, use a group of thermal
vias under the exposed pad to transfer the heat to
the ground planes in the opposite side of the PCB.
Use small vias (approximately 15mil) such that they
can be filled up during the reflow soldering process to
provide a good metallic heat conduction path from
the IC exposed pad to the other PCB side.
1
(37)
fP =
2π×R4 ×C5
Layout Guidelines
PCB
layout
is
critical
converter
for
operation.
stable
and
The
high-performance
recommended layout is shown in Figure 15.
Connect PVIN, GND and exposed pad pins to large
copper areas to increase heat dissipation and
long-term reliability. Keep SW area small to avoid
emission issue.
Place the nearest input high frequency decoupling
capacitor between VIN and AGND pins as close as
possible.
The dimension and outline information is for the
Place a larger input ceramic capacitor close to PVIN
and GND pins for minimizing the influence of ground
bounce.
standard TQFN-3.5×3.5-14L package.
Bottom Layer
Top Layer
Figure 15. PCB Layout
SG Micro Corp
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NOVEMBER 2022
23
4.5V to 18V Input, 4A,
SGM61130
Synchronous Buck Converter
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (NOVEMBER 2022) to REV.A
Page
Changed from product preview to production data.............................................................................................................................................All
SG Micro Corp
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NOVEMBER 2022
24
PACKAGE INFORMATION
PACKAGE OUTLINE DIMENSIONS
TQFN-3.5×3.5-14L
D
b1
L1
L
PIN 1#
N1
N14
E
E1
e
D1
e1
DETAIL A
e2
b
k
e3
TOP VIEW
BOTTOM VIEW
0.20
0.70
0.625
2.05
A
0.25
4.10 2.70
2.05
A1
A2
SIDE VIEW
0.50
ALTERNATE A-1 ALTERNATE A-2
0.75
1.50
DETAIL A
0.55
ALTERNATE TERMINAL
CONSTRUCTION
RECOMMENDED LAND PATTERN (Unit: mm)
Dimensions In Millimeters
Symbol
MIN
MOD
0.750
MAX
0.800
0.050
A
A1
A2
D
0.700
0.000
-
0.200 REF
3.500
3.400
3.400
1.950
1.950
0.200
0.150
3.600
3.600
2.150
2.150
0.300
0.250
E
3.500
D1
E1
b
2.050
2.050
0.250
b1
e
0.200
0.500 BSC
0.550 BSC
0.750 BSC
1.500 BSC
0.320
e1
e2
e3
k
0.220
0.300
0.225
0.420
0.500
0.425
L
0.400
L1
0.325
NOTE: This drawing is subject to change without notice.
SG Micro Corp
TX00206.000
www.sg-micro.com
PACKAGE INFORMATION
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
P2
P0
W
Q2
Q4
Q2
Q4
Q2
Q4
Q1
Q3
Q1
Q3
Q1
Q3
B0
Reel Diameter
P1
A0
K0
Reel Width (W1)
DIRECTION OF FEED
NOTE: The picture is only for reference. Please make the object as the standard.
KEY PARAMETER LIST OF TAPE AND REEL
Reel Width
Reel
Diameter
A0
B0
K0
P0
P1
P2
W
Pin1
Package Type
W1
(mm)
(mm) (mm) (mm) (mm) (mm) (mm) (mm) Quadrant
TQFN-3.5×3.5-14L
13″
12.4
3.75
3.75
1.05
4.0
8.0
2.0
12.0
Q2
SG Micro Corp
TX10000.000
www.sg-micro.com
PACKAGE INFORMATION
CARTON BOX DIMENSIONS
NOTE: The picture is only for reference. Please make the object as the standard.
KEY PARAMETER LIST OF CARTON BOX
Length
(mm)
Width
(mm)
Height
(mm)
Reel Type
Pizza/Carton
13″
386
280
370
5
SG Micro Corp
www.sg-micro.com
TX20000.000
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