SGM833A [SGMICRO]
140dB Range (1nA to 10mA) Logarithmic Current-to-Voltage Converter;
| 型号： | SGM833A |
| 厂家： | 
Shengbang Microelectronics Co, Ltd |
| 描述： | 140dB Range (1nA to 10mA) Logarithmic Current-to-Voltage Converter |
| 文件： | 总22页 (文件大小：812K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SGM833A
140dB Range (1nA to 10mA)
Logarithmic Current-to-Voltage Converter
GENERAL DESCRIPTION
FEATURES
The SGM833A is a single-supply logarithmic current-to-
voltage converter for measuring the low frequency
current signals over a large range from 1nA to 10mA.
With capabilities such as photodiode adaptive biasing,
active-shielding (guard driving), output buffer amplifier
conditioning and voltage reference on a single chip, this
device is optimized for measuring the power of optical
signals by using a photodiode operating in the photo
current mode. The measured current is converted and
compressed to a logarithmic voltage by using transistor
I-V characteristics and a compensation circuit.
● Patents Pending Proprietary Circuits
● Seven Full Decades Range
● 3V to 5.5V Single-Supply Operation
● Low Power and Temperature Stable
● Precise Trimmed Scaling
● 10mV/dB Logarithmic Slope at VLOG Pin
● 100pA Basic Logarithmic Intercept
● Simple Slope and Intercept Adjustments
● 15V/μs Slew Rate
● 3.3mA (TYP) Quiescent Current (Enabled)
● 9μA (TYP) Shutdown Current (Disabled)
● Available in a Green TQFN-3×3-16L Package
The SGM833A operates with a single 3V to 5.5V supply
and is equipped with a disable input to shut down the
device. The input current (IPD) is converted to an
internal 40µA/dec logarithmic scaled current that is
injected into an internal 5kΩ resistance to provide an
output voltage with 10mV/dB (or 200mV/dec)
logarithmic slope on the VLOG output pin. This slope
can be reduced by an external shunt resistor. The
intercept point (the output voltage corresponding to the
selected intercept current) and the scale (to change the
slope) can be adjusted by the on-chip buffer amplifier.
APPLICATIONS
High Accuracy Optical Power Measurement
Wide Range Baseband Log Data Compression
Versatile Detector for Automatic Power Control Loops
This device is available in a Green TQFN-3×3-16L
package and is specified over a temperature range of
-40℃ to +85℃.
TYPICAL APPLICATION
VOUT
500mV/dec
VP
10
12
VPS
11
VOUT
RA
15kΩ
RB
VPS
10kΩ
IPD
13
8
2
3
VSUM
BFNG
VLOG
BFIN
CFLT
INPT
200mV/dec
9
C1
470pF
SGM833A
4
5
VSUM
VPDB
10nF
10nF
6
R1
750Ω
VREF
GND
AGND
7
PWDN
16
0.1μF
14, 15
Figure 1. Typical Application Circuit
SG Micro Corp
www.sg-micro.com
MARCH2022–REV. A
140dB Range (1nA to 10mA)
SGM833A
Logarithmic Current-to-Voltage Converter
PACKAGE/ORDERING INFORMATION
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESCRIPTION
ORDERING
NUMBER
PACKAGE
MARKING
PACKING
OPTION
MODEL
833ATQ
XXXXX
SGM833A
TQFN-3×3-16L
Tape and Reel, 4000
-40℃ to +85℃
SGM833AYTQ16G/TR
MARKING INFORMATION
NOTE: XXXXX = Date Code, Trace Code and Vendor Code.
X X X X X
Vendor Code
Trace Code
Date Code - Year
Green (RoHS & HSF): SG Micro Corp defines “Green” to mean Pb-Free (RoHS compatible) and free of halogen substances. If
you have additional comments or questions, please contact your SGMICRO representative directly.
OVERSTRESS CAUTION
ABSOLUTE MAXIMUM RATINGS
Supply Voltage...................................................................6V
Input Current.................................................................20mA
Internal Power Dissipation.........................................270mW
Package Thermal Resistance
Stresses beyond those listed in Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods
may affect reliability. Functional operation of the device at any
conditions beyond those indicated in the Recommended
Operating Conditions section is not implied.
TQFN-3×3-16L, θJA.................................................... 71℃/W
Junction Temperature.................................................+150℃
Storage Temperature Range.......................-65℃ to +150℃
Lead Temperature (Soldering, 10s)............................+260℃
ESD Susceptibility
ESD SENSITIVITY CAUTION
This integrated circuit can be damaged if ESD protections are
not considered carefully. SGMICRO recommends that all
integrated circuits be handled with appropriate precautions.
Failureto observe proper handlingand installation procedures
can cause damage. ESD damage can range from subtle
performance degradation tocomplete device failure. Precision
integrated circuits may be more susceptible to damage
because even small parametric changes could cause the
device not to meet the published specifications.
HBM.............................................................................4000V
CDM ............................................................................1000V
RECOMMENDED OPERATING CONDITIONS
Input Voltage Range ..............................................3V to 5.5V
Operating Ambient Temperature Range........-40℃ to +85℃
Operating Junction Temperature Range......-40℃ to +125℃
DISCLAIMER
SG Micro Corp reserves the right to make any change in
circuit design, or specifications without prior notice.
SG Micro Corp
www.sg-micro.com
MARCH 2022
2
140dB Range (1nA to 10mA)
SGM833A
Logarithmic Current-to-Voltage Converter
PIN CONFIGURATION
(TOP VIEW)
16 15 14 13
NC
VSUM
INPT
1
2
3
4
12 VPS
11 VOUT
10 VPS
VSUM
9
BFIN
5
6
7
8
TQFN-3×3-16L
PIN DESCRIPTION
PIN
NAME
FUNCTION
No Connection. Pin labeled NC can be allowed to float, but it is better to connect this pin to ground.
Avoid routing high-speed signals through this pin because noise coupling may result.
Guard Pins. These pins are located on both sides of the INPT pin and can be connected to the shield
guard of the INPT current signal for active shielding.
Photodiode Current Input. INPT pin is typically connected to the photodiode anode. The photo current
flows into the INPT pin. (The photodiode junction is slightly reverse biased to operate as detector.)
Photodiode Bias Output. VPDB pin can be connected to the photodiode cathode to provide adaptive
bias control. The adaptive bias increases the reverse bias voltage as diode current increases to
compensate the resistive drops inside the diode and keeps a sufficient reverse bias across the
junction, such that the diode current is only determined by the incoming optical power. Otherwise,
leave the pin floating.
1
NC
2, 4
3
VSUM
INPT
5
VPDB
6
7
VREF
AGND
Output of the 2V Internal Voltage Reference. It can be used to set the intercept point for buffer output.
Analog Ground (Return for the output signals and VREF).
Output of The Logarithmic Front-End. Output of the logarithmic converter with an internal shunt
resistance is ROUT = 5kΩ to ground. Provide a logarithmic output voltage with a 100pA intercept and a
fixed 200mV/dec slope (200mV change for each 1-decade change in the input current). The lower
margin of VLOG is less than 0.1V but cannot reach 0V. Therefore, for input currents below 1nA, this
output is saturated (the intercept point is out of range). The VLOG output impedance is 5kΩ.
8
VLOG
9
10, 12
11
BFIN
VPS
Internal Buffer Amplifier Non-Inverting Input (High Impedance).
Positive Supply, VP (3.0V to 5.5V).
VOUT
BFNG
GND
Internal Buffer Amplifier Output (Low Impedance).
Internal Buffer Amplifier Inverting Input.
Power Supply Ground.
13
14, 15
16
Power-Down (Disable) Logic Input. Pulling this pin high will disable the device, and pulling this pin low
will enable the device.
PWDN
Exposed
Pad
—
Connect the exposed pad to the VSUM pins to provide low leakage guard.
SG Micro Corp
MARCH 2022
www.sg-micro.com
3
140dB Range (1nA to 10mA)
SGM833A
Logarithmic Current-to-Voltage Converter
ELECTRICAL CHARACTERISTICS
(VP = 5V, TJ = -40℃ to +85℃, typical values are at TJ = +25℃, unless otherwise noted.)
PARAMETER
Input Interface (INPT, VSUM)
Specified Current Range
CONDITIONS
MIN
TYP
MAX
UNITS
Flows into INPT pin
1nA
0.47
10mA
0.53
0.5
0.5
TJ = +25℃
Input Node Voltage
Internally preset; can be altered
V
0.465
0.535
TJ = -40℃ to +85℃
Temperature Drift
0.02
TJ = -40℃ to +85℃
VIN - VSUM, TJ = +25℃
mV/℃
Input Guard Offset Voltage
Photodiode Bias (1) (Established between VPDB and INPT)
-20
70
20
mV
Minimum Value
100
300
mV
IPD = 1nA, TJ = +25℃
Trans-Resistance
mV/mA
Logarithmic Output (VLOG)
194
192
192
189
70
200
200
200
200
100
207
209
212
214
130
140
1.1 (3)
2 (3)
TJ = +25℃
1μA < IPD < 1mA
1nA < IPD < 1μA
TJ = 0℃ to +70℃
TJ = +25℃
Slope
mV/dec
TJ = 0℃ to +70℃
TJ = +25℃
Intercept (IZ)
pA
dB
60
TJ = 0℃ to +70℃
0.05
0.08
1.6
0.1
5
10nA < IPD < 1mA, peak error, TJ = +25℃
1nA < IPD < 1mA, peak error, TJ = +25℃
Law Conformance Error (2)
Maximum Output Voltage
Minimum Output Voltage
Shunt Output Resistance (ROUT
Reference Output (VREF)
V
V
)
4.95
5.05
kΩ
TJ = +25℃
1.98
1.97
2
2
2.02
2.03
TJ = +25℃
Voltage (Referred to AGND)
Output Resistance
V
TJ = -40℃ to +85℃
0.1
Ω
Output Buffer Amplifier (BFIN, BFNG, VOUT)
Input Offset Voltage
Input Bias Current
-20
20
mV
pA
GΩ
V
TJ = +25℃
Flowing out of BFIN or BFNG pins
20
25
Incremental Input Resistance (dv/di)
Output High Voltage
Output Resistance
Loaded with RL = 1kΩ to ground
VP - 0.1
0.1
Ω
Wide-Band Noise (4)
Small Signal Bandwidth (4)
Slew Rate
IPD > 1μA
1
μV/√Hz
MHz
IPD > 1μA
10
0.2V to 4.8V output swing
15
V/μs
SG Micro Corp
www.sg-micro.com
MARCH 2022
4
140dB Range (1nA to 10mA)
SGM833A
Logarithmic Current-to-Voltage Converter
ELECTRICAL CHARACTERISTICS (continued)
(VP = 5V, TJ = -40℃ to +85℃, typical values are at TJ = +25℃, unless otherwise noted.)
PARAMETER
Power-Down Input (PWDN)
Logic High Level Voltage
Logic Low Level Voltage
Power Supply (VPS)
CONDITIONS
MIN
TYP
MAX
UNITS
2.7V < VP < 5.5V
2
V
V
2.7V < VP < 5.5V
1
Positive Supply Voltage
Quiescent Current (Enabled)
Shutdown Current (Disabled)
3
5
3.3
9
5.5
5
V
mA
μA
TJ = +25℃
NOTES:
1. This bias is internally arranged to track the input voltage at INPT; it is not specified relative to ground.
2. The deviation of VLOG from the ideal relationship expressed as VLOG = Slope × (IPD - IZ) with quantities expressed in
logarithmic (dB) scale.
3. The specified minimum and maximum values are guaranteed by ATE, excluding the reliability shift.
4. Output noise and incremental bandwidth are functions of the input current.
SG Micro Corp
www.sg-micro.com
MARCH 2022
5
140dB Range (1nA to 10mA)
SGM833A
Logarithmic Current-to-Voltage Converter
TYPICAL PERFORMANCE CHARACTERISTICS
TJ = +25℃ and VP = 5V, unless otherwise noted.
VLOG vs. IPD
Logarithmic Conformance (Linearity) for VLOG
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
2.0
1.5
TJ =-40℃
TJ =+25℃
TJ =0℃
TJ =+70℃
TJ =+85℃
TJ = -40℃
TJ = +25℃
TJ = 0℃
TJ = +70℃
TJ = +85℃
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
0.001 0.01 0.1
1
10
100 1000 10000
0.001 0.01 0.1
1
10
100 1000 10000
IPD (μA)
IPD (μA)
Absolute Deviation from Nominal Specified
Value of VLOG for Several Supply Voltages
VSUM vs. IPD
2.0
1.5
0.505
VP = 4.5V
VP = 5V
TJ = -40℃
TJ = +25℃
TJ = +85℃
0.504
0.503
0.502
0.501
0.500
0.499
0.498
0.497
0.496
0.495
V
P = 5.5V
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
0.001 0.01 0.1
1
10
100 1000 10000
0.001 0.01 0.1
1
10
100 1000 10000
IPD (μA)
IPD (μA)
Small Signal AC Response, IPD to VLOG
(5% Sine Modulation of IPD at Frequency)
VPDB vs. IPD
4.0
10
0
TJ = -40℃
TJ = +25℃
TJ = +85℃
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-10
-20
-30
-40
-50
-60
-70
1nA
10nA
100nA
1μA
10μA
100μA
1mA
10mA
0
1
2
3
4
5
6
7
8
9
10
0.1
1
10
100
1000 10000 100000
Frequency (kHz)
IPD (A)
SG Micro Corp
www.sg-micro.com
MARCH 2022
6
140dB Range (1nA to 10mA)
SGM833A
Logarithmic Current-to-Voltage Converter
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
TJ = +25℃ and VP = 5V, unless otherwise noted.
Spot Noise Spectral Density at VLOG vs. IPD
Spot Noise Spectral Density at VLOG vs. Frequency
1000
100
10
1000
100
10
100Hz
1kHz
10kHz
100kHz
1MHz
10MHz
1
1
1nA
10μA
100μA
1mA
10nA
100nA
1μA
0.1
0.1
0.01
10mA
0.01
0.001 0.01 0.1
1
10
100 1000 10000
0.1
1
10
100
1000
10000
IPD (μA)
Frequency (kHz)
Total Wide-Band Noise Voltage at VLOG vs. IPD
Small Signal Response of Buffer
22
20
18
16
14
12
10
8
3
0
-3
-6
6
G = 1
-9
G = 2
4
G = 2.5
G = 5
2
0
-12
0.001 0.01
0.1
1
10
100 1000 10000
0.1
1
10
100
1000 10000 100000
IPD (μA)
Frequency (kHz)
Small Signal Response of Buffer Operating as Two-Pole Filter
Logarithmic Conformance Error Distribution
2
1.5
1
10
TJ = +25℃
fC = 1kHz
0
-10
-20
-30
-40
-50
-60
-70
Mean + 3σ
0.5
0
-0.5
-1
Mean - 3σ
-1.5
-2
0.001 0.01
0.1
1
10
100 1000 10000
0.01
0.1
1
10
100
Frequency (kHz)
IPD (μA)
SG Micro Corp
MARCH 2022
www.sg-micro.com
7
140dB Range (1nA to 10mA)
SGM833A
Logarithmic Current-to-Voltage Converter
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
TJ = +25℃ and VP = 5V, unless otherwise noted.
Logarithmic Conformance Error Distribution
Logarithmic Conformance Error Distribution
5
3
5
3
TJ = -40℃
TJ = +85℃
TJ = 0℃
TJ = +70℃
Mean + 3σ
Mean - 3σ
Mean + 3σ
1
1
-1
-3
-5
-1
-3
-5
Mean - 3σ
0.001 0.01
0.1
1
10
100 1000 10000
0.001 0.01
0.1
1
10
100 1000 10000
IPD (μA)
IPD (μA)
VREF Drift vs. Temperature
Slope Drift vs. Temperature
6
4
15
10
5
Mean + 3σ
Mean + 3σ
2
0
0
-2
-4
-6
-8
-5
-10
-15
-20
Mean - 3σ
Mean - 3σ
-40
-20
0
25
55
85
-40
-20
0
25
55
85
Temperature (℃)
Temperature (℃)
Intercept Drift vs. Temperature
Output Buffer Offset vs. Temperature
8
4
0.4
0.2
0
Mean + 3σ
Mean + 3σ
0
-4
-8
-12
Mean - 3σ
Mean - 3σ
-0.2
-0.4
-40
-20
0
25
55
85
-40
-20
0
25
55
70
85
Temperature (℃)
Temperature (℃)
SG Micro Corp
www.sg-micro.com
MARCH 2022
8
140dB Range (1nA to 10mA)
SGM833A
Logarithmic Current-to-Voltage Converter
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
TJ = +25℃ and VP = 5V, unless otherwise noted.
Distribution of Logarithmic Slope
Distribution of Logarithmic Slope Intercept
20
15
10
5
25
20
15
10
5
1000 Samples
1 Production Lot
1000 Samples
1 Production Lot
0
0
Logarithmic Intercept (pA)
Logarithmic Slope (mV/dec)
Distribution of Input Guard Offset Voltage (VINPT - VSUM
)
20
1000 Samples
1 Production Lot
16
12
8
4
0
Input Guard Offset (mV)
SG Micro Corp
www.sg-micro.com
MARCH 2022
9
140dB Range (1nA to 10mA)
SGM833A
Logarithmic Current-to-Voltage Converter
FUNCTIONAL BLOCK DIAGRAM
VPS
IREF
VOUT
Intercept Point
Reference
Voltage
0.6V
VPDB
-
Buffer
-
+
300Ω
Adaptive
Biasing
Active Shielding
BFNG
BFIN
QM
Q2
-
VSUM
INPT
0.5V
VPS
10kΩ
2V
VREF
VREF
VLOG
PWDN
-
+
C1
470pF
ILOG
VSUM
TCA
Voltage-to-Current
Conversion and
Temp-Compensation
VBE1
Q1
R1
750Ω
5kΩ
BIAS
Logarithmic Raw
Conversion TIA
SGM833A
GND
AGND
Figure 2. Functional Block Diagram
SG Micro Corp
www.sg-micro.com
MARCH 2022
10
140dB Range (1nA to 10mA)
SGM833A
Logarithmic Current-to-Voltage Converter
CHARACTERIZATION TEST SETUP
Triax
Connector*
PWDN GND
VPS
VOUT
BFIN
SGM833A
Keithley 236
INPT
Characterization
Board
VLOG
*Signal: INPT
Guard: VSUM
Shield: Ground
VSUM VPDB VREF
Ribbon
Cable
DC Matrix, DC Supplies, DMM
Figure 3. Primary Characterization Setup
HP 3577A
Network Analyzer
OUTPUT
INPUT
INPUTA
INPUTB
+IN
16
15
14
13
B
A
PWDN GND GND BFNG
AD8318
Evaluation
Board
+VS
1
2
3
4
12
11
10
9
Power
Splitter
NC
VPS
VOUT
VPS
0.1μF
VSUM
INPT
VSUM
SGM833A
BFIN
VPDB VREF AGND VLOG
49.9Ω
5
6
7
8
Figure 4. Buffer Amplifier Bandwidth Measurement
SG Micro Corp
www.sg-micro.com
MARCH 2022
11
140dB Range (1nA to 10mA)
SGM833A
Logarithmic Current-to-Voltage Converter
CHARACTERIZATION TEST SETUP (continued)
HP 3577A
Network
Analyzer
OUTPUT INPUT INPUTA INPUTB
Power
Splitter
16
15
14
13
PWDN GND GND BFNG
+VS
1
2
3
4
12
11
10
9
NC
VPS
VOUT
VPS
0.1μF
+IN
B
A
VSUM
INPT
VSUM
AD8318
Evaluation
Board
SGM833A
R1
750Ω
470pF
BFIN
VPDB VREF AGND VLOG
5
6
7
8
Figure 5. Converter Small Signal Bandwidth Measurement Setup
HP 89410A
SOURCE
15
TRIGGER
CHANNEL 1
CHANNEL 2
16
14
13
PWDN GND GND BFNG
1
2
3
4
12
NC
VPS
VOUT
VPS
11
10
9
VSUM
INPT
VSUM
SGM833A
R1
Alkaline
D Cell
Alkaline
D Cell
750Ω
BFIN
VPDB VREF AGND VLOG
470pF
5
6
7
8
Figure 6. Noise Spectrum Measurement Setup
SG Micro Corp
www.sg-micro.com
MARCH 2022
12
140dB Range (1nA to 10mA)
SGM833A
Logarithmic Current-to-Voltage Converter
DETAILED DESCRIPTION
and temperature dependence, the VBE1 - VBE2 is
Conversion Operating Principle
temperature and process independent at the intercept
point (note that IREF/IZ is a constant).
Figure 2 shows the block diagram of the SGM833A,
including the logarithmic conversion blocks and the
required compensations blocks for law conformance.
The Q1 collector voltage is stabilized at 0.5V by a
closed loop bias circuit. The 0.5V is an optimal voltage
level for biasing the photodiode anode, and provides a
good compromise between the diode ohmic leakage
current errors that are significant at lower currents and
the diode series resistance errors that are significant at
higher currents. The adaptive bias block tries to keep
the reverse bias across the diode junction to almost
stable 0.1V by increasing the bias voltage at higher IPD
currents to compensate the diode bulk resistive drops.
The inherent relationship of the collector current (IC)
and the base-emitter voltage (VBE) in a bipolar
transistor (like Q1) is expressed as:
VBE1 - VBE2 = kT/q × loge(IPD/IREF
)
(3)
However, at other currents, the relationship of VBE1
-
VBE2 to IC is still temperature dependent by a direct
multiplication factor (proportional to T). A current mirror
multiplier and a voltage to current conversion multiplier
are used to compensate the temperature variations and
to convert the VBE1 - VBE2 voltage to a temperature and
IS independent current (ILOG). This current passes
through an internal 5kΩ resistor for current to voltage
conversion that provides the intermediate output
voltage (VLOG = 5kΩ × ILOG) with a fixed 200mV/dec
typical slope (200mV increase per one decade or 10×
increase of IPD). The logarithmic conversion is
represented by:
VBE = VT × loge(IC/IS)
VT = kT/q
(1)
(2)
VLOG = 5kΩ × 40μA × log10(IPD/100pA)
= 0.2V × log10(IPD/100pA)
(4)
(5)
where:
log10 (x)
≈ 0.4343
loge (x)
IS is the saturation current of the transistor,
loge is the natural logarithm operator,
VT is the thermal voltage,
log10 is more convenient than loge for per decade units
used for the slope. IZ = 100pA is the SGM833A
intercept current.
k is the Boltzmann constant (~1.38×10-23J/K),
T is the absolute temperature in Kelvin (K),
q is the electron charge in Coulomb (~1.6×10-19C).
Optical Power Measurement
The photodiode sensitivity defined by quantum
efficiency is the number of electrons emitted as a result
of the received photonic irradiation. Because the
electron velocity is stable in a given electric field, the
number of electrons (photo current) will be proportional
to the incoming optical power. So, the IPD can be
measured and calibrated as an equivalent quantity with
the optical power.
Equation 1 provides the raw logarithmic principle that is
used to convert the diode IPD current flowing in the Q1
collector to the logarithmic voltage VBE1. Note that the
fundamental relationship between VBE and IC can be
scaled by both IS and VT. The IC = IS determines the VBE
= 0 intercept point. The IS and the intercept point are
highly temperature and process dependent and have to
be compensated such that the output is independent of
the IS and T. To compensate the IS variations, an
identical dummy transistor (Q2) with the same
geometrics and process as Q1 is implemented in the
device to generate the reference voltage (VBE2) for the
intercept point by setting its collector current to an
stable and accurate reference current (IREF). The IREF
has an input referenced equalization stabilized around
1μA that is 10000 times higher than the intercept
current (IZ = 100pA typical).
The logarithmic current to voltage conversion facilitates
optical measurement in decibel scaling, in which the
optical power is measured as a ratio to a given
reference power, such as dBm that is the ratio to a
1mW reference. If the system is calibrated such that a
1mW optical power results in 1V output, then if a
measurement reading is 1.2V, the optical power is
calculated from 200mV × log10(P/1mW) = (1.2V - 1V)
equation that results in P/1mW = 10 or P = 10dBm.
Because Q1 and Q2 have the same saturation currents
SG Micro Corp
www.sg-micro.com
MARCH 2022
13
140dB Range (1nA to 10mA)
SGM833A
Logarithmic Current-to-Voltage Converter
DETAILED DESCRIPTION (continued)
Available Output Range
The low margin for the VLOG output for proper
trimming and cancellation is limited (0.1V, TYP). So,
when the actual input is very close to the intercept point
(IZ = 100pA), the output is saturated to the low limit
because VLOG cannot reach to zero. However, from
almost a decade higher (1nA), the output is valid. The
VLOG output impedance is 5kΩ. The adaptive biasing
and compensation block are fully functional over the
whole 3V to 5.5V supply range that helps in lowering
the errors caused by diode resistive drops that could
limit the effective high output range. The buffer amplifier
PPK (dB) power peak, results in a realistic PPK - 3dB
average power if the signal is averaged before
conversion. However, if the converter output is
averaged, the result will be a meaningless average
value of PPK/2 (dB) and also depends on 0dB
reference.
Bandwidth and Noise
Even though the AC transfer function is meaningless
for the nonlinear conversion circuit, the bandwidth data
can help the evaluation of the output settling time. This
is an important factor for reading and sampling the
output with high accuracy and fast rate. The Q1 acts as
a feedback path in the trans-impedance amplifier (TIA)
conversion (IPD to VBE). With low IPD values, the
trans-conductance (trans-linear) is very high and the
loop gain is low that limits the bandwidth. It means the
settling time will be long at low currents and short at
higher currents due to the large variation of the loop
gain. The bandwidth of TIA and the compensation
network are both increased when the IPD current goes
high. It is necessary to stabilize the loop gain and the
bandwidth. To this end, the external R1-C1 network is
shunted with the Q1. This will reduce the low current
bandwidth even further. By using the buffer amplifier,
the large bandwidth at higher currents is also limited by
the buffer bandwidth.
provides
a
much smaller (0.1Ω, TYP) output
impedance. With a 1kΩ load, this output can swing up
to VP - 0.1V. If the output is near VP - 0.1V, the law
conformance might have been lost already, because it
shows that the input current is above the guaranteed
operating range.
DC and AC Components
The logarithmic conversion is valid for the steady state
(settled DC) component of the input signal. The high
frequency AC component of the IPD should be filtered
and blocked from entering into the INPT pin. Otherwise,
large measurement errors are expected. Compared to
the averaging before conversion, the signal averaging
at the output of the converter adds much more error.
For example, a 50% duty cycle input pulse signal with
SG Micro Corp
www.sg-micro.com
MARCH 2022
14
140dB Range (1nA to 10mA)
SGM833A
Logarithmic Current-to-Voltage Converter
DETAILED DESCRIPTION (continued)
Active Shielding and Adaptive Biasing
The INPT voltage level is kept at 0.5V as shown in
Figure 2. The same voltage is connected to VSUM pins
that are located on the two sides of the INPT pin. It is
recommended to surround the photodiode anode
copper stripe that connects to the INPT pin, with the
same voltage that is available on VSUM pins to
minimize the IPD leakage by creating a zero voltage
difference between the INPT and the surrounding
guard.
The Reference and Buffer
A 2V reference and a buffer operational amplifier (OPA)
are integrated on the chip. The OPA can be used for
VLOG conditioning or as a conventional op-amp or
comparator.
RINREF
ROUT
VINREF
A
VOUT
+
VIN
VOUTREF
ROUTREF
RIN
The QM is a current mirror to Q1 and its current is
proportional to the Q1 current. The QM current flows into
a current to voltage amplifier with a 0.6V offset to
generate an adaptive bias for the photodiode. The
photodiode bias increases from 100mV (= 0.6V - 0.5V)
minimum up to 300mV/mA × IPD (mA), or the headroom
limit, whichever is less. The reverse bias voltage is
increased at higher currents to compensate the
resistive drops in the photodiode. Note that for higher
range of the input current, the supply voltage needs to
be high enough for proper operation of the adaptive
bias. For example, with a 10mA input, the supply
voltage must be at least 3.7V, otherwise the VPDB
output will be saturated that may cause measurement
error. An external bias can be applied to VSUM if the
INPT voltage needs to be changed from 0.5V.
Figure 7. Re-scaling and Level-Shifting by an OPA
Figure 7 shows how the buffer can be used to shift the
VIN signal that is referenced to VINREF to a re-scaled
VOUT output signal referenced to the VOUTREF voltage.
The gain and level-shift are set by the four resistors.
Chip Enable
Pulling up the PWDN pin to logic high level will power
down and disable the device. In this mode, the supply
current drops to 9μA (TYP).
SG Micro Corp
www.sg-micro.com
MARCH 2022
15
140dB Range (1nA to 10mA)
SGM833A
Logarithmic Current-to-Voltage Converter
APPLICATION INFORMATION
Shielding, guarding, filtering and proper diode biasing
are critical factors to minimize the noise voltage
coupled to the INPT, especially when the diode current
is low and the feedback signal through Q1 is high. The
diode resistive leakage (dark current) along with the
multiplication and self-demodulation in the compensation
multipliers can increase the errors significantly.
Therefore, proper shielding, filtering and diode bias are
essential before feeding the current signal for
conversion.
negative feedback loop. Setting the corner frequency of
external R1-C1 network to smaller values will cause
slower settling at lower IPD currents but quicker settling
at high currents. So the span of the desired operating
range and the stability (or settling) of the converter
need to be compromised depending on the application
requirements.
Figure 9 shows some additional circuits for the
photodiode bias and IPD signal filtering. The CPDB-RPDB
low pass R-C network reduces the bandwidth of the
adaptive biasing loop and helps the stability at high
currents. The CPD-RPD RC low pass filter network
averages the IPD before feeding it to the converter to
suppress the error caused by the multiplication
self-demodulation at low bit rate data communication
applications.
Figure 8 shows how the parasitic leakage and R1-C1
network can cause delay in the negative feedback loop.
It also shows how the active shielding loop provides
positive feedback (bootstrap) at high IPD currents by
increasing the diode bias. The advantage of active
shielding is insulating the INPT from ground leakage
through the parasitic CPG and RPG elements and also
from EMI pick-up. However, the penalty of shielding is
larger parasitic CPS that increases the delay in the
Note that VLOG output filtering is not helpful for error
suppression.
0.6V
-
VPDB
300Ω
QM
0.5V
10kΩ
EMI
INPT
CPS
RPS
-
+
C1
VSUM
CS
TCA
Q1
R1
GND
CPG
RPG
Figure 8. Conversion Loop and Active Shielding Loop
RPDB
VPDB
VPDB
CPDB
RPD
CPD
INPT
INPT
C1
C1
R1
VSUM
CS
VSUM
CS
R1
GND
GND
Figure 9. Filtering the VPDB and IPD
SG Micro Corp
www.sg-micro.com
MARCH 2022
16
140dB Range (1nA to 10mA)
SGM833A
Logarithmic Current-to-Voltage Converter
APPLICATION INFORMATION (continued)
VLOG Output Conditioning
The following equation can be used for calculating the
resistors when a lower intercept point is desired:
The on-chip buffer amplifier and voltage reference can
be used for adjusting the output intercept point and the
scaling needed to match the desired signal level of the
downstream process. Figure 10 shows the circuits that
can be used for lowering or raising the intercept point.
10
RZ
IPD
IZ
RLOG
VOUT = G V ×
×log
+ V
×
(6)
Y
REF
RZ + RLOG
RLOG + RZ
RA
where: G = 1+
and RLOG = 5kΩ.
VOUT
RB
RZ
VREF
2V
RA
-
Usually it is more useful to raise the intercept point.
Note that raising the intercept point reduces all output
values. Figure 10 (b) shows how the intercept point is
raised by placing the RC between the BFNG and VREF
pins. This arrangement raises the BFNG voltage (with
zero input signal) and pushes the VOUT to lower
values. Note that with the RC connected to the BFNG
pin, the gain (G) is also affected, but it can be
compensated and re-adjusted by RA and RB. Use the
following equation for calculating the resistors (Figure
10 (b)):
BFNG
BFIN
Buffer
ILOG
RB
VLOG
VLOG
AGND
5kΩ
(a) Lowering the intercept point
VOUT
RC
VREF
2V
RA
-
BFNG
Buffer
ILOG
BFIN
10
RB
IPD
IZ
RA ||RB
(7)
VLOG
5kΩ
VLOG
AGND
VOUT = G V ×log
- V
×
Y
REF
RA ||RB + RC
RA
RA ×RB
RA + RB
where: G = 1+
and RA ||RB =
(b) Raising the intercept point
RB ||RC
.
Figure 10. Adjusting the Intercept Point and Scaling
Table 2. Some Examples for Raising the Intercept
Table 1 lists some examples for selecting resistors for a
few slope scales values while the intercept point is
reduced from the IZ = 100pA. VY in mV/dec is called the
slope voltage.
VY (mV/dec)
300
IZ (nA)
10
RA (kΩ)
7.5
RB (kΩ)
37.4
130
RC (kΩ)
24.9
18.2
25.5
16.2
13.3
24.9
16.5
12.4
300
100
10
8.25
10
400
16.5
25.5
36.5
12.4
16.5
20.0
400
100
500
10
9.76
9.76
12.4
12.4
11.5
Table 1. Some Examples of Lowering the Intercept Point
400
VY (mV/dec)
200
IZ (pA)
1
RA (kΩ)
20.0
10.0
3.01
10.0
8.06
6.65
11.5
9.76
8.66
16.5
14.3
13.0
RB (kΩ)
100
100
100
12.4
12.4
12.4
8.2
RZ (kΩ)
25
500
500
100
500
200
10
50
1
50
500
200
165
25
300
300
10
50
1
50
300
165
25
400
400
10
50
1
8.2
50
400
8.2
165
25
500
8.2
500
10
50
8.2
50
500
8.2
165
SG Micro Corp
www.sg-micro.com
MARCH 2022
17
140dB Range (1nA to 10mA)
SGM833A
Logarithmic Current-to-Voltage Converter
APPLICATION INFORMATION (continued)
In most cases, a single-pole filter made by a capacitor
(CFLT) between the VLOG and AGND works well for
output filtering as shown in Figure 1. If a high-
performance measurement system with lower noise is
required, a slightly more complex filter such as a
two-pole Sallen-Key filter can be used as shown in
Figure 11. The precise 5kΩ source impedance is
needed as a part of the Sallen-Key filter network
(considering the Thevenin equivalent of the VLOG
output).
For example, to reduce the cut-off frequency to 100Hz,
CA and CB should be increased by a factor of 10.
The values of RD, G, and CA/CB ratio should not deviate
from the suggested values in Table 3 to maintain the
shape of the filter response.
Table 3. Filter Parameters for 1kHz Cut-off Frequency
RA
(kΩ)
RB
(kΩ)
VY
(V/dec)
RD
(kΩ)
CA
(nF)
CB
(nF)
G
0
open
10
8
1
2
0.2
0.4
0.5
1.0
11.3
6.02
12.1
10.0
12
33
33
33
12
22
18
18
10
12
24
2.5
5
VOUT
6
CB
RA
2V
VREF
BFNG
-
SGM833A Evaluation Board
CA
Buffer
BFIN
An evaluation board is available for the SGM833A with
the schematic provided in Figure 12. The EVB can be
configured for a wide variety of experiments. By default,
the EVB is factory-set for a diode detector in
photoconductive mode with a buffer gain of unity,
10mV/dB slope, and 100pA intercept point. By
configuring the EVB resistors and capacitors, all
application circuits and options presented in this
datasheet can be evaluated as summarized in Table 4.
RD
ILOG
VLOG
VLOG
AGND
RB
5kΩ
AGND
Figure 11. Using Sallen-Key Filter to Improve Settling
Some starting points for selecting the filter components
for a few gain (G) examples and 1kHz cut-off frequency
are provided in Table 3. The cut-off frequency can be
increased or decreased by scaling the capacitor values.
J1
VPOS
FB1
0.0Ω
C3
100nF
C4
4.7μF
SW1
J2
AGND
R10
10kΩ
Enable
R1
10kΩ
C2
1nF
R5
R7
NP NP
S1 VSUM
3
1
R8
C12
NP
0.1μF
C13
100pF
12
11
10
9
1
2
R2
20kΩ
NC
VPS
R13
0.0Ω
Buffer OUT
1
VSUM
INPT
VSUM
VOUT
VPS
C8
NP
J6
R16
0.0Ω
SGM833A
INPT
1
3
4
C7
R12
NP
NP
J4
C11
R15
750Ω
R11
470pF
0.0Ω
BFIN
R6
NP
C6
10nF
R14
10kΩ
VPDB
1
C9
10nF
LOG OUT
J7
1
J5
C10
0.1μF
R4 NP
3 NP
C5
NP
R
NOTE: NP = Not Populated in default Configuration
Figure 12. SGM833A Evaluation Board Schematic
SG Micro Corp
www.sg-micro.com
MARCH 2022
18
140dB Range (1nA to 10mA)
SGM833A
Logarithmic Current-to-Voltage Converter
APPLICATION INFORMATION (continued)
Table 4. Evaluation Board Configuration Options
Component
VPOS, AGND
SW1, R10
Function
Default Condition
Positive Supply and Ground Pins.
Device Enable: With SW1 switch in the “0” position, the PWDN pin is grounded and the SW1 = Installed
SGM833A operates in normal mode. R10 = 10kΩ
Buffer Amplifier Gain/Slope Adjustment: The logarithmic slope of the SGM833A can be R1 = 10kΩ
NA
R1, R2
changed by gain-setting resistors (R1 and R2) of the buffer amplifier.
R2 = 20kΩ
R3 = NP
Intercept Adjustment: These resistors can apply DC offset to the buffer amplifier inputs to
adjust the effective logarithmic intercept.
R3, R4
R4 = NP
R5 = R6 = NP
R7 = R8 = NP
C2 = 1nF
C3 = 0.1μF
C4 = 4.7μF
C9 = 10nF
R5, R6, R7, R8
C2, C3, C4, C9
Bias Adjustment: The VSUM and INPT voltages can be set by these resistors.
Power Supply, VREF and PWDN Decoupling Capacitors.
Photodiode Bias Output Decoupling Capacitor: Provides high frequency decoupling for the
adaptive bias output at pin VPDB pin.
C10
C12
C10 = 0.1μF
VSUM Decoupling Capacitor.
C12 = 0.1μF
C5 = NP
C6 =10nF
C5, C6, C7, C8, R11, Output Filter Configuration: These components can be used to implement a variety of filter C7 = C8 = NP
R12, R13, R14
configurations, from a simple low-pass RC filter to a three-pole Sallen-Key filter.
R11 = R13 = 0Ω
R12 = NP
R14 = 10kΩ
R15 = 750Ω
C11 = 470pF
R15, C11
Input Filtering: This RC network sets the essential HF compensation at the input pin (INPT).
Guard/Shield Options: The shells of the SMA input connectors for the photodiode and bias
can be either connected to active shield driver on the VSUM pin or connected to ground.
S1
C13
R16
S1= Installed
C13 = 100pF
R16 = 0Ω
Feed-Forward Capacitor.
Isolation Jumper.
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (MARCH 2022) to REV.A
Page
Changed from product preview to production data.............................................................................................................................................All
SG Micro Corp
www.sg-micro.com
MARCH 2022
19
PACKAGE INFORMATION
PACKAGE OUTLINE DIMENSIONS
TQFN-3×3-16L
D
e
N16
PIN 1#
N1
L
D1
E
E1
k
N5
b
BOTTOM VIEW
TOP VIEW
1.7
0.7
SEATING PLANE
eee
C
A
3.6 2.2 1.7
C
A2
A1
SIDE VIEW
0.5
0.24
RECOMMENDED LAND PATTERN (Unit: mm)
Dimensions
In Millimeters
Dimensions
In Inches
Symbol
MIN
MAX
0.800
0.050
MIN
0.028
0.000
MAX
0.031
0.002
A
A1
A2
D
0.700
0.000
0.203 REF
0.008 REF
2.900
1.600
2.900
1.600
3.100
1.800
3.100
1.800
0.114
0.063
0.114
0.063
0.122
0.071
0.122
0.071
D1
E
E1
k
0.200 MIN
0.500 TYP
0.080
0.008 MIN
0.020 TYP
0.003
b
0.180
0.300
0.300
0.500
0.007
0.012
0.012
0.020
e
L
eee
NOTE: This drawing is subject to change without notice.
SG Micro Corp
TX00081.001
www.sg-micro.com
PACKAGE INFORMATION
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
P2
P0
W
Q2
Q4
Q2
Q4
Q2
Q4
Q1
Q3
Q1
Q3
Q1
Q3
B0
Reel Diameter
P1
A0
K0
Reel Width (W1)
DIRECTION OF FEED
NOTE: The picture is only for reference. Please make the object as the standard.
KEY PARAMETER LIST OF TAPE AND REEL
Reel Width
Reel
Diameter
A0
B0
K0
P0
P1
P2
W
Pin1
Package Type
W1
(mm)
(mm) (mm) (mm) (mm) (mm) (mm) (mm) Quadrant
TQFN-3×3-16L
13″
12.4
3.35
3.35
1.13
4.0
8.0
2.0
12.0
Q2
SG Micro Corp
TX10000.000
www.sg-micro.com
PACKAGE INFORMATION
CARTON BOX DIMENSIONS
NOTE: The picture is only for reference. Please make the object as the standard.
KEY PARAMETER LIST OF CARTON BOX
Length
(mm)
Width
(mm)
Height
(mm)
Reel Type
Pizza/Carton
13″
386
280
370
5
SG Micro Corp
www.sg-micro.com
TX20000.000
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明