LH28F320BFHG-PTTLZK [SHARP]
32M (x16) Flash Memory; 32M ( X16 )快闪记忆体型号: | LH28F320BFHG-PTTLZK |
厂家: | SHARP ELECTRIONIC COMPONENTS |
描述: | 32M (x16) Flash Memory |
文件: | 总36页 (文件大小:902K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Date
Mar. 19. 2003
32M (x16) Flash Memory
LH28F320BFHG-PTTLZK
LHF32FDJ
• Handle this document carefully for it contains material protected by international copyright law. Any reproduction,
full or in part, of this material is prohibited without the express written permission of the company.
• When using the products covered herein, please observe the conditions written herein and the precautions outlined in
the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly
adhere to these conditions and precautions.
(1) The products covered herein are designed and manufactured for the following application areas. When using the
products covered herein for the equipment listed in Paragraph (2), even for the following application areas, be sure
to observe the precautions given in Paragraph (2). Never use the products for the equipment listed in Paragraph
(3).
• Office electronics
• Instrumentation and measuring equipment
• Machine tools
• Audiovisual equipment
• Home appliance
• Communication equipment other than for trunk lines
(2) Those contemplating using the products covered herein for the following equipment which demands high
reliability, should first contact a sales representative of the company and then accept responsibility for
incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring
reliability and safety of the equipment and the overall system.
• Control and safety devices for airplanes, trains, automobiles, and other transportation equipment
• Mainframe computers
• Traffic control systems
• Gas leak detectors and automatic cutoff devices
• Rescue and security equipment
• Other safety devices and safety equipment, etc.
(3) Do not use the products covered herein for the following equipment which demands extremely high performance
in terms of functionality, reliability, or accuracy.
• Aerospace equipment
• Communications equipment for trunk lines
• Control equipment for the nuclear power industry
• Medical equipment related to life support, etc.
(4) Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a sales
representative of the company.
• Please direct all queries regarding the products covered herein to a sales representative of the company.
Rev. 2.44
LHF32FDJ
1
CONTENTS
PAGE
0.75mm pitch 48-Ball CSP (7mm×7mm) Pinout....... 3
Pin Descriptions.......................................................... 4
PAGE
Extended Status Register Definition......................... 15
Partition Configuration Register Definition.............. 16
Partition Configuration ............................................. 16
1 Electrical Specifications......................................... 17
1.1 Absolute Maximum Ratings ........................... 17
1.2 Operating Conditions...................................... 17
1.2.1 Capacitance.............................................. 18
1.2.2 AC Input/Output Test Conditions ............ 18
1.2.3 DC Characteristics ................................... 19
Simultaneous Operation Modes
Allowed with Four Planes .................................. 5
Memory Map.............................................................. 6
Identifier Codes and OTP Address
for Read Operation ............................................. 7
Identifier Codes and OTP Address for
Read Operation on Partition Configuration........ 7
OTP Block Address Map for OTP Program............... 8
Bus Operation............................................................. 9
Command Definitions .............................................. 10
Functions of Block Lock and Block Lock-Down..... 12
1.2.4 AC Characteristics
- Read-Only Operations......................... 21
1.2.5 AC Characteristics
- Write Operations ................................. 25
Block Locking State Transitions upon
Command Write................................................ 12
1.2.6 Reset Operations ...................................... 27
Block Locking State Transitions upon
1.2.7 Block Erase, Full Chip Erase,
(Page Buffer) Program and
WP# Transition................................................. 13
OTP Program Performance.................... 28
Status Register Definition......................................... 14
2 Related Document Information.............................. 29
Rev. 2.44
LHF32FDJ
2
LH28F320BFHG-PTTLZK
32Mbit (2Mbit×16)
Page Mode Dual Work Flash MEMORY
32M density with 16Bit I/O Interface
Flexible Blocking Architecture
• Eight 4K-word Parameter Blocks
• Sixty-three 32K-word Main Blocks
• Top Parameter Location
High Performance Reads
• 80/35ns 8-Word Page Mode
Configurative 4-Plane Dual Work
• Flexible Partitioning
• Read operations during Block Erase or (Page Buffer)
Program
Enhanced Data Protection Features
• Individual Block Lock and Block Lock-Down with
Zero-Latency
• All blocks are locked at power-up or device reset.
• Absolute Protection with VPP≤VPPLK
• Status Register for Each Partition
• Block Erase, Full Chip Erase, (Page Buffer) Word
Program Lockout during Power Transitions
Low Power Operation
• 2.7V Read and Write Operations
• VCCQ for Input/Output Power Supply Isolation
• Automatic Power Savings Mode Reduces ICCR
in Static Mode
Automated Erase/Program Algorithms
• 3.0V Low-Power 11µs/Word (Typ.)
Programming
• 12V No Glue Logic 9µs/Word (Typ.)
Production Programming and 0.5s Erase (Typ.)
Enhanced Code + Data Storage
• 5µs Typical Erase/Program Suspends
Cross-Compatible Command Support
• Basic Command Set
• Common Flash Interface (CFI)
OTP (One Time Program) Block
• 4-Word Factory-Programmed Area
• 4-Word User-Programmable Area
Extended Cycling Capability
• Minimum 100,000 Block Erase Cycles
High Performance Program with Page Buffer
• 16-Word Page Buffer
• 5µs/Word (Typ.) at 12V VPP
0.75mm pitch 48-Ball CSP (7mm×7mm)
ETOXTM* Flash Technology
Operating Temperature -40°C to +85°C
CMOS Process (P-type silicon substrate)
Not designed or rated as radiation hardened
The product, which is 4-Plane Page Mode Dual Work (Simultaneous Read while Erase/Program) Flash memory, is a low
power, high density, low cost, nonvolatile read/write storage solution for a wide range of applications. The product can
operate at VCC=2.7V-3.6V and VPP=1.65V-3.6V or 11.7V-12.3V. Its low voltage operation capability greatly extends
battery life for portable applications.
The product provides high performance asynchronous page mode. It allows code execution directly from Flash, thus
eliminating time consuming wait states. Furthermore, its newly configurative partitioning architecture allows flexible dual
work operation.
The memory array block architecture utilizes Enhanced Data Protection features, and provides separate Parameter and Main
Blocks that provide maximum flexibility for safe nonvolatile code and data storage.
Fast program capability is provided through the use of high speed Page Buffer Program.
Special OTP (One Time Program) block provides an area to store permanent code such as a unique number.
* ETOX is a trademark of Intel Corporation.
Rev. 2.44
LHF32FDJ
3
1
2
3
4
5
6
7
8
A
B
C
D
E
F
A
13
14
15
A
A
A
11
A
8
V
PP WP#
A
19
A
7
5
3
A
4
2
1
0
A
A
A
10 WE# RST#
NC
A
18
A
17
A
A
A
A
A
0.75mm pitch
48-BALL CSP
PINOUT
7mm x 7mm
TOP VIEW
12
A
9
A
6
A
20
16 DQ14 DQ5 DQ11 DQ2 DQ8 CE#
VCCQ DQ15 DQ6 DQ12 DQ3 DQ9 DQ0 GND
GND DQ7 DQ13 DQ4 VCC DQ10 DQ1 OE#
Figure 1. 0.75mm pitch 48-Ball CSP (7mm×7mm) Pinout
Rev. 2.44
LHF32FDJ
4
Table 1. Pin Descriptions
Symbol
A0-A20
Type
Name and Function
ADDRESS INPUTS: Inputs for addresses. 32M: A0-A20
INPUT
DATA INPUTS/OUTPUTS: Inputs data and commands during CUI (Command User
Interface) write cycles, outputs data during memory array, status register, query code,
identifier code and partition configuration register code reads. Data pins float to high-
impedance (High Z) when the chip or outputs are deselected. Data is internally latched
during an erase or program cycle.
INPUT/
OUTPUT
DQ0-DQ15
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and sense
amplifiers. CE#-high (VIH) deselects the device and reduces power consumption to
standby levels.
CE#
INPUT
INPUT
RESET: When low (VIL), RST# resets internal automation and inhibits write operations
which provides data protection. RST#-high (VIH) enables normal operation. After
power-up or reset mode, the device is automatically set to read array mode. RST# must
be low during power-up/down.
RST#
OE#
INPUT
INPUT
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of CE# or WE# (whichever goes high first).
WE#
WRITE PROTECT: When WP# is VIL, locked-down blocks cannot be unlocked. Erase
WP#
INPUT
or program operation can be executed to the blocks which are not locked and not locked-
down. When WP# is VIH, lock-down is disabled.
MONITORING POWER SUPPLY VOLTAGE: VPP is not used for power supply pin.
With VPP≤VPPLK, block erase, full chip erase, (page buffer) program or OTP program
cannot be executed and should not be attempted.
Applying 12V 0.3V to VPP provides fast erasing or fast programming mode. In this
mode, VPP is power supply pin. Applying 12V 0.3V to VPP during erase/program can
only be done for a maximum of 1,000 cycles on each block. VPP may be connected to
VPP
INPUT
12V 0.3V for a total of 80 hours maximum. Use of this pin at 12V beyond these limits
may reduce block cycling capability or cause permanent damage.
DEVICE POWER SUPPLY (2.7V-3.6V): With VCC≤VLKO, all write attempts to the
flash memory are inhibited. Device operations at invalid VCC voltage (see DC
Characteristics) produce spurious results and should not be attempted.
VCC
SUPPLY
INPUT/OUTPUT POWER SUPPLY (2.7V-3.6V): Power supply for all input/output
pins.
VCCQ
SUPPLY
SUPPLY
GND
NC
GROUND: Do not float any ground pins.
NO CONNECT: Lead is not internally connected; it may be driven or floated.
Rev. 2.44
LHF32FDJ
5
Table 2. Simultaneous Operation Modes Allowed with Four Planes(1, 2)
THEN THE MODES ALLOWED IN THE OTHER PARTITION IS:
Page
IF ONE
PARTITION IS:
Block
Erase
Suspend
Read Read
Read Read
Word
OTP
Block FullChip Program
Buffer
Array ID/OTP Status Query Program
Program Erase
Erase Suspend
Program
Read Array
Read ID/OTP
Read Status
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Read Query
Word Program
Page Buffer
Program
X
X
X
X
X
OTP Program
Block Erase
X
X
X
X
X
X
Full Chip Erase
Program
Suspend
X
X
X
X
X
X
X
X
X
Block Erase
Suspend
X
X
X
NOTES:
1. "X" denotes the operation available.
2. Configurative Partition Dual Work Restrictions:
Status register reflects partition state, not WSM (Write State Machine) state - this allows a status register for each
partition. Only one partition can be erased or programmed at a time - no command queuing.
Commands must be written to an address within the block targeted by that command.
Rev. 2.44
LHF32FDJ
6
BLOCK NUMBER ADDRESS RANGE
70 4K-WORD
69 4K-WORD
68 4K-WORD
67 4K-WORD
66 4K-WORD
65 4K-WORD
64 4K-WORD
63 4K-WORD
62 32K-WORD
61 32K-WORD
60 32K-WORD
59 32K-WORD
58 32K-WORD
57 32K-WORD
56 32K-WORD
55 32K-WORD
54 32K-WORD
53 32K-WORD
52 32K-WORD
51 32K-WORD
50 32K-WORD
1FF000H - 1FFFFFH
1FE000H - 1FEFFFH
1FD000H - 1FDFFFH
1FC000H - 1FCFFFH
1FB000H - 1FBFFFH
1FA000H - 1FAFFFH
1F9000H - 1F9FFFH
1F8000H - 1F8FFFH
1F0000H - 1F7FFFH
1E8000H - 1EFFFFH
1E0000H - 1E7FFFH
1D8000H - 1DFFFFH
1D0000H - 1D7FFFH
1C8000H - 1CFFFFH
1C0000H - 1C7FFFH
1B8000H - 1BFFFFH
1B0000H - 1B7FFFH
1A8000H - 1AFFFFH
1A0000H - 1A7FFFH
198000H - 19FFFFH
190000H - 197FFFH
BLOCK NUMBER ADDRESS RANGE
31 32K-WORD
30 32K-WORD
29 32K-WORD
28 32K-WORD
27 32K-WORD
26 32K-WORD
25 32K-WORD
24 32K-WORD
23 32K-WORD
22 32K-WORD
21 32K-WORD
20 32K-WORD
19 32K-WORD
18 32K-WORD
17 32K-WORD
16 32K-WORD
0F8000H - 0FFFFFH
0F0000H - 0F7FFFH
0E8000H - 0EFFFFH
0E0000H - 0E7FFFH
0D8000H - 0DFFFFH
0D0000H - 0D7FFFH
0C8000H - 0CFFFFH
0C0000H - 0C7FFFH
0B8000H - 0BFFFFH
0B0000H - 0B7FFFH
0A8000H - 0AFFFFH
0A0000H - 0A7FFFH
098000H - 09FFFFH
090000H - 097FFFH
088000H - 08FFFFH
080000H - 087FFFH
49 32K-WORD
48 32K-WORD
188000H - 18FFFFH
180000H - 187FFFH
47 32K-WORD
46 32K-WORD
45 32K-WORD
44 32K-WORD
43 32K-WORD
42 32K-WORD
41 32K-WORD
40 32K-WORD
39 32K-WORD
38 32K-WORD
37 32K-WORD
36 32K-WORD
35 32K-WORD
34 32K-WORD
33 32K-WORD
32 32K-WORD
178000H - 17FFFFH
170000H - 177FFFH
168000H - 16FFFFH
160000H - 167FFFH
158000H - 15FFFFH
150000H - 157FFFH
148000H - 14FFFFH
140000H - 147FFFH
138000H - 13FFFFH
130000H - 137FFFH
128000H - 12FFFFH
120000H - 127FFFH
118000H - 11FFFFH
110000H - 117FFFH
108000H - 10FFFFH
100000H - 107FFFH
15 32K-WORD
14 32K-WORD
13 32K-WORD
12 32K-WORD
11 32K-WORD
10 32K-WORD
078000H - 07FFFFH
070000H - 077FFFH
068000H - 06FFFFH
060000H - 067FFFH
058000H - 05FFFFH
050000H - 057FFFH
048000H - 04FFFFH
040000H - 047FFFH
038000H - 03FFFFH
030000H - 037FFFH
028000H - 02FFFFH
020000H - 027FFFH
018000H - 01FFFFH
010000H - 017FFFH
008000H - 00FFFFH
000000H - 007FFFH
9
8
7
6
5
4
3
2
1
0
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
32K-WORD
Figure 2. Memory Map (Top Parameter)
Rev. 2.44
LHF32FDJ
7
Table 3. Identifier Codes and OTP Address for Read Operation
Address
Data
[DQ15-DQ0]
Code
Notes
[A15-A0]
Manufacturer Code
Device Code
Manufacturer Code
0000H
0001H
00B0H
00B4H
DQ0 = 0
1
1, 2
3
Top Parameter Device Code
Block is Unlocked
Block Lock Configuration
Code
Block
Address
+ 2
Block is Locked
DQ0 = 1
DQ1 = 0
DQ1 = 1
3
3
Block is not Locked-Down
Block is Locked-Down
3
Device Configuration Code
OTP
Partition Configuration Register
0006H
0080H
PCRC
OTP-LK
OTP
1, 4
1, 5
1, 6
OTP Lock
OTP
0081-0088H
NOTES:
1. The address A20-A16 are shown in below table for reading the manufacturer code, device code,
device configuration code and OTP data.
2. Top parameter device has its parameter blocks in the plane3 (The highest address).
3. Block Address = The beginning location of a block address within the partition to which
the Read Identifier Codes/OTP command (90H) has been written.
DQ15-DQ2 are reserved for future implementation.
4. PCRC=Partition Configuration Register Code.
5. OTP-LK=OTP Block Lock configuration.
6. OTP=OTP Block data.
Table 4. Identifier Codes and OTP Address for Read Operation on Partition Configuration(1) (32M-bit device)
Partition Configuration Register (2)
Address (32M-bit device)
[A20-A16]
PCR.10
PCR.9
PCR.8
0
0
0
1
0
1
1
1
0
0
1
0
1
1
0
1
0
1
0
0
1
0
1
1
00H
00H or 08H
00H or 10H
00H or 18H
00H or 08H or 10H
00H or 10H or 18H
00H or 08H or 18H
00H or 08H or 10H or 18H
NOTES:
1. The address to read the identifier codes or OTP data is dependent on the partition which is selected
when writing the Read Identifier Codes/OTP command (90H).
2. Refer to Table 12 for the partition configuration register.
Rev. 2.44
LHF32FDJ
8
[A20-A ]
0
000088H
Customer Programmable Area
Factory Programmed Area
000085H
000084H
000081H
000080H
Reserved for Future Implementation
(DQ15-DQ2)
Customer Programmable Area Lock Bit (DQ
Factory Programmed Area Lock Bit (DQ
1
)
0
)
Figure 3. OTP Block Address Map for OTP Program
(The area outside 80H~88H cannot be used.)
Rev. 2.44
LHF32FDJ
9
Table 5. Bus Operation(1, 2)
Mode
Read Array
Output Disable
Standby
Notes RST#
CE#
VIL
VIL
VIH
X
OE#
VIL
VIH
X
WE#
VIH
VIH
X
Address
VPP
X
DQ0-15
DOUT
6
VIH
VIH
VIH
VIL
X
X
X
X
X
High Z
High Z
High Z
X
Reset
3
6
X
X
X
See
Table 3 and
Table 4
See
Table 3 and
Table 4
Read Identifier
Codes/OTP
VIH
VIL
VIL
VIH
X
See
Appendix
See
Appendix
VIH
VIH
VIL
VIL
VIL
VIH
VIH
VIL
Read Query
6,7
X
X
Write
4,5,6
X
DIN
NOTES:
1. Refer to DC Characteristics. When VPP≤VPPLK, memory contents can be read, but cannot be altered.
2. X can be VIL or VIH for control pins and addresses, and VPPLK or VPPH1/2 for VPP. See DC Characteristics for VPPLK
and VPPH1/2 voltages.
3. RST# at GND 0.2V ensures the lowest power consumption.
4. Command writes involving block erase, full chip erase, (page buffer) program or OTP program are reliably executed
when VPP=VPPH1/2 and VCC=2.7V-3.6V.
5. Refer to Table 6 for valid DIN during a write operation.
6. Never hold OE# low and WE# low at the same timing.
7. Refer to Appendix of LH28F320BF series for more information about query code.
Rev. 2.44
LHF32FDJ
10
Table 6. Command Definitions(11)
First Bus Cycle
Bus
Second Bus Cycle
Command
Cycles Notes
Req’d
Oper(1)
Addr(2)
Oper(1)
Addr(2)
Data(3)
Data
Read Array
1
Write
Write
Write
Write
Write
Write
Write
PA
PA
PA
PA
PA
BA
X
FFH
90H
98H
70H
50H
20H
30H
Read Identifier Codes/OTP
Read Query
≥ 2
≥ 2
2
4
4
Read
Read
Read
IA or OA ID or OD
QA
PA
QD
Read Status Register
Clear Status Register
Block Erase
SRD
1
2
5
Write
Write
BA
X
D0H
D0H
Full Chip Erase
Program
2
5,9
40H or
10H
2
≥ 4
1
5,6
5,7
8,9
Write
Write
Write
WA
WA
PA
Write
Write
WA
WA
WD
N-1
Page Buffer Program
E8H
Block Erase and (Page Buffer)
Program Suspend
B0H
Block Erase and (Page Buffer)
Program Resume
1
8,9
Write
PA
D0H
Set Block Lock Bit
2
2
2
2
2
Write
Write
Write
Write
Write
BA
BA
60H
60H
60H
C0H
60H
Write
Write
Write
Write
Write
BA
BA
01H
D0H
2FH
OD
Clear Block Lock Bit
Set Block Lock-down Bit
OTP Program
10
9
BA
BA
OA
OA
Set Partition Configuration Register
PCRC
PCRC
04H
NOTES:
1. Bus operations are defined in Table 5.
2. All addresses which are written at the first bus cycle should be the same as the addresses which are written at the second
bus cycle.
X=Any valid address within the device.
PA=Address within the selected partition.
IA=Identifier codes address (See Table 3 and Table 4).
QA=Query codes address. Refer to Appendix of LH28F320BF series for details.
BA=Address within the block being erased, set/cleared block lock bit or set block lock-down bit.
WA=Address of memory location for the Program command or the first address for the Page Buffer Program command.
OA=Address of OTP block to be read or programmed (See Figure 3).
PCRC=Partition configuration register code presented on the address A0-A15.
3. ID=Data read from identifier codes. (See Table 3 and Table 4).
QD=Data read from query database. Refer to Appendix of LH28F320BF series for details.
SRD=Data read from status register. See Table 10 and Table 11 for a description of the status register bits.
WD=Data to be programmed at location WA. Data is latched on the rising edge of WE# or CE# (whichever
goes high first) during command write cycles.
OD=Data within OTP block. Data is latched on the rising edge of WE# or CE# (whichever goes high first)
during command write cycles.
N-1=N is the number of the words to be loaded into a page buffer.
4. Following the Read Identifier Codes/OTP command, read operations access manufacturer code, device code, block lock
configuration code, partition configuration register code and the data within OTP block (See Table 3 and Table 4).
The Read Query command is available for reading CFI (Common Flash Interface) information.
5. Block erase, full chip erase or (page buffer) program cannot be executed when the selected block is locked. Unlocked
block can be erased or programmed when RST# is VIH.
6. Either 40H or 10H are recognized by the CUI (Command User Interface) as the program setup.
7. Following the third bus cycle, input the program sequential address and write data of "N" times. Finally, input the any
valid address within the target block to be programmed and the confirm command (D0H). Refer to Appendix of
Rev. 2.44
LHF32FDJ
11
LH28F320BF series for details.
8. If the program operation in one partition is suspended and the erase operation in other partition is also suspended, the
suspended program operation should be resumed first, and then the suspended erase operation should be resumed next.
9. Full chip erase and OTP program operations can not be suspended. The OTP Program command can not be accepted while
the block erase operation is being suspended.
10. Following the Clear Block Lock Bit command, block which is not locked-down is unlocked when WP# is VIL. When
WP# is VIH, lock-down bit is disabled and the selected block is unlocked regardless of lock-down configuration.
11. Commands other than those shown above are reserved by SHARP for future device implementations and should not be
used.
Rev. 2.44
LHF32FDJ
12
Table 7. Functions of Block Lock(5) and Block Lock-Down
Current State
Erase/Program Allowed (2)
(1)
(1)
State
[000]
WP#
State Name
Unlocked
DQ1
DQ0
0
0
0
0
0
1
Yes
No
[001](3)
[011]
Locked
0
1
1
1
0
0
1
0
1
Locked-down
Unlocked
Locked
No
Yes
No
[100]
[101](3)
[110](4)
[111]
1
1
1
1
0
1
Lock-down Disable
Lock-down Disable
Yes
No
NOTES:
1. DQ0=1: a block is locked; DQ0=0: a block is unlocked.
DQ1=1: a block is locked-down; DQ1=0: a block is not locked-down.
2. Erase and program are general terms, respectively, to express: block erase, full chip erase and
(page buffer) program operations.
3. At power-up or device reset, all blocks default to locked state and are not locked-down, that is,
[001] (WP#=0) or [101] (WP#=1), regardless of the states before power-off or reset operation.
4. When WP# is driven to VIL in [110] state, the state changes to [011] and the blocks are
automatically locked.
5. OTP (One Time Program) block has the lock function which is different from those described
above.
Table 8. Block Locking State Transitions upon Command Write(4)
Current State
DQ1 DQ0
Result after Lock Command Written (Next State)
Set Lock(1)
Clear Lock(1)
No Change
[000]
Set Lock-down(1)
State WP#
[011](2)
[011]
[000]
[001]
0
0
0
0
0
1
[001]
No Change(3)
No Change
[101]
[011]
[100]
0
1
1
0
1
0
No Change
No Change
No Change
[111](2)
[111]
[101]
[110]
1
1
0
1
1
0
No Change
[111]
[100]
[111](2)
No Change
[111]
1
1
1
No Change
[110]
No Change
NOTES:
1. "Set Lock" means Set Block Lock Bit command, "Clear Lock" means Clear Block Lock Bit
command and "Set Lock-down" means Set Block Lock-Down Bit command.
2. When the Set Block Lock-Down Bit command is written to the unlocked block (DQ0=0), the
corresponding block is locked-down and automatically locked at the same time.
3. "No Change" means that the state remains unchanged after the command written.
4. In this state transitions table, assumes that WP# is not changed and fixed VIL or VIH.
Rev. 2.44
LHF32FDJ
13
Table 9. Block Locking State Transitions upon WP# Transition(4)
Current State
Result after WP# Transition (Next State)
Previous State
WP#=0→1(1)
WP#=1→0(1)
DQ1
DQ0
State
WP#
-
-
[000]
[001]
0
0
0
0
0
1
[100]
[101]
[110]
-
-
-
[110](2)
[011]
0
1
1
Other than [110](2)
[111]
-
-
-
-
[100]
[101]
[110]
1
1
1
0
0
1
0
1
0
-
-
-
[000]
[001]
[011](3)
[011]
-
[111]
1
1
1
-
NOTES:
1. "WP#=0→1" means that WP# is driven to VIH and "WP#=1→0" means that WP# is driven to
VIL.
2. State transition from the current state [011] to the next state depends on the previous state.
3. When WP# is driven to VIL in [110] state, the state changes to [011] and the blocks are
automatically locked.
4. In this state transitions table, assumes that lock configuration commands are not written in
previous, current and next state.
Rev. 2.44
LHF32FDJ
14
Table 10. Status Register Definition
R
15
R
14
R
R
R
11
R
10
R
9
R
8
13
BEFCES
5
12
PBPOPS
4
WSMS
7
BESS
6
VPPS
3
PBPSS
2
DPS
1
R
0
SR.15 - SR.8 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
NOTES:
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
Status Register indicates the status of the partition, not WSM
(Write State Machine). Even if the SR.7 is "1", the WSM may
be occupied by the other partition when the device is set to 2,
3 or 4 partitions configuration.
1 = Ready
0 = Busy
SR.6 = BLOCK ERASE SUSPEND STATUS (BESS)
1 = Block Erase Suspended
Check SR.7 to determine block erase, full chip erase, (page
buffer) program or OTP program completion. SR.6 - SR.1 are
invalid while SR.7="0".
0 = Block Erase in Progress/Completed
SR.5 = BLOCK ERASE AND FULL CHIP ERASE
STATUS (BEFCES)
If both SR.5 and SR.4 are "1"s after a block erase, full chip
erase, (page buffer) program, set/clear block lock bit, set
block lock-down bit, set partition configuration register
attempt, an improper command sequence was entered.
1 = Error in Block Erase or Full Chip Erase
0 = Successful Block Erase or Full Chip Erase
SR.4 = (PAGE BUFFER) PROGRAM AND
OTP PROGRAM STATUS (PBPOPS)
SR.3 does not provide a continuous indication of VPP level.
The WSM interrogates and indicates the VPP level only after
Block Erase, Full Chip Erase, (Page Buffer) Program or OTP
Program command sequences. SR.3 is not guaranteed to
1 = Error in (Page Buffer) Program or OTP Program
0 = Successful (Page Buffer) Program or OTP Program
report accurate feedback when VPP≠VPPH1, VPPH2 or VPPLK
.
SR.3 = VPP STATUS (VPPS)
1 = VPP LOW Detect, Operation Abort
0 = VPP OK
SR.1 does not provide a continuous indication of block lock
bit. The WSM interrogates the block lock bit only after Block
Erase, Full Chip Erase, (Page Buffer) Program or OTP
Program command sequences. It informs the system,
depending on the attempted operation, if the block lock bit is
set. Reading the block lock configuration codes after writing
the Read Identifier Codes/OTP command indicates block
lock bit status.
SR.2 = (PAGE BUFFER) PROGRAM SUSPEND
STATUS (PBPSS)
1 = (Page Buffer) Program Suspended
0 = (Page Buffer) Program in Progress/Completed
SR.1 = DEVICE PROTECT STATUS (DPS)
1 = Erase or Program Attempted on a
Locked Block, Operation Abort
0 = Unlocked
SR.15 - SR.8 and SR.0 are reserved for future use and should
be masked out when polling the status register.
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
Rev. 2.44
LHF32FDJ
15
Table 11. Extended Status Register Definition
R
15
R
14
R
R
13
R
R
12
R
R
11
R
R
10
R
R
9
R
8
SMS
7
R
1
R
0
6
5
4
3
2
XSR.15-8 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
NOTES:
After issue a Page Buffer Program command (E8H),
XSR.7="1" indicates that the entered command is accepted.
If XSR.7 is "0", the command is not accepted and a next Page
Buffer Program command (E8H) should be issued again to
check if page buffer is available or not.
XSR.7 = STATE MACHINE STATUS (SMS)
1 = Page Buffer Program available
0 = Page Buffer Program not available
XSR.15-8 and XSR.6-0 are reserved for future use and
should be masked out when polling the extended status
register.
XSR.6-0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
Rev. 2.44
LHF32FDJ
16
Table 12. Partition Configuration Register Definition
R
15
R
R
14
R
R
13
R
R
12
R
R
11
R
PC2
10
R
PC1
9
PC0
8
R
R
7
6
5
4
3
2
1
0
PCR.15-11 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
111 = There are four partitions in this configuration.
Each plane corresponds to each partition respec-
tively. Dual work operation is available between any
two partitions.
PCR.10-8 = PARTITION CONFIGURATION (PC2-0)
000 = No partitioning. Dual Work is not allowed.
001 = Plane1-3 are merged into one partition.
(default in a bottom parameter device)
PCR.7-0 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
010 = Plane 0-1 and Plane2-3 are merged into one
partition respectively.
100 = Plane 0-2 are merged into one partition.
(default in a top parameter device)
NOTES:
After power-up or device reset, PCR10-8 (PC2-0) is set to
011 = Plane 2-3 are merged into one partition. There are "001" in a bottom parameter device and "100" in a top
three partitions in this configuration. Dual work parameter device.
operation is available between any two partitions.
110 = Plane 0-1 are merged into one partition. There are
See Figure 4 for the detail on partition configuration.
three partitions in this configuration. Dual work
operation is available between any two partitions.
101 = Plane 1-2 are merged into one partition. There are
PCR.15-11 and PCR.7-0 are reserved for future use and
should be masked out when checking the partition
three partitions in this configuration. Dual work
operation is available between any two partitions.
configuration register.
PC2 PC1PC0
0 0 0
PARTITIONING FOR DUAL WORK
PARTITION0
PC2 PC1PC0
0 1 1
PARTITIONING FOR DUAL WORK
PARTITION2
PARTITION0
PARTITION1
PARTITION1
PARTITION0
PARTITION2 PARTITION1
PARTITION0
0 0 1
0 1 0
1 0 0
1 1 0
1 0 1
1 1 1
PARTITION0
PARTITION1
PARTITION2 PARTITION1 PARTITION0
PARTITION0
PARTITION3 PARTITION2 PARTITION1
PARTITION1
PARTITION0
Figure 4. Partition Configuration
Rev. 2.44
LHF32FDJ
17
*WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent
damage. These are stress ratings only. Operation
beyond the "Operating Conditions" is not
recommended and extended exposure beyond
the "Operating Conditions" may affect device
reliability.
1 Electrical Specifications
*
1.1 Absolute Maximum Ratings
Operating Temperature
During Read, Erase and Program ...-40°C to +85°C (1)
NOTES:
1. Operating temperature is for extended temperature
product defined by this specification.
2. All specified voltages are with respect to GND.
Minimum DC voltage is -0.5V on input/output pins
and -0.2V on VCC and VPP pins. During transitions,
this level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage on input/output pins is
Storage Temperature
During under Bias............................... -40°C to +85°C
During non Bias................................ -65°C to +125°C
Voltage On Any Pin
(except VCC and VPP).............. -0.5V to VCC+0.5V (2)
V
CC+0.5V which, during transitions, may overshoot to
VCC+2.0V for periods <20ns.
3. Maximum DC voltage on VPP may overshoot to
+13.0V for periods <20ns.
4. VPP erase/program voltage is normally 2.7V-3.6V.
Applying 11.7V-12.3V to VPP during erase/program
can be done for a maximum of 1,000 cycles on the
main blocks and 1,000 cycles on the parameter blocks.
VCC and VCCQ Supply Voltage .......... -0.2V to +3.9V (2)
VPP Supply Voltage .................... -0.2V to +12.6V (2, 3, 4)
Output Short Circuit Current...........................100mA (5)
V
PP may be connected to 11.7V-12.3V for a total of 80
hours maximum.
5. Output shorted for no more than one second. No more
than one output shorted at a time.
1.2 Operating Conditions
Parameter
Symbol
TA
Min.
-40
Typ.
+25
3.0
3.0
3.0
12
Max.
+85
3.6
Unit
°C
Notes
Operating Temperature
VCC Supply Voltage
VCC
2.7
V
1
1
I/O Supply Voltage
VCCQ
VPPH1
VPPH2
2.7
3.6
V
VPP Voltage when Used as a Logic Control
VPP Supply Voltage
1.65
3.6
V
1
11.7
12.3
V
1, 2
Main Block Erase Cycling: VPP=VPPH1
Parameter Block Erase Cycling: VPP=VPPH1
Main Block Erase Cycling: VPP=VPPH2, 80 hrs.
Parameter Block Erase Cycling: VPP=VPPH2, 80 hrs.
Maximum VPP hours at VPPH2
NOTES:
100,000
100,000
Cycles
Cycles
Cycles
Cycles
Hours
1,000
1,000
80
1. See DC Characteristics tables for voltage range-specific specification.
2. Applying VPP=11.7V-12.3V during a erase or program can be done for a maximum of 1,000 cycles on the main blocks
and 1,000 cycles on the parameter blocks. A permanent connection to VPP=11.7V-12.3V is not allowed and can cause
damage to the device.
Rev. 2.44
LHF32FDJ
18
1.2.1 Capacitance(1) (TA=+25°C, f=1MHz)
Parameter
Symbol
CIN
Condition
VIN=0.0V
Min.
Typ.
Max.
7
Unit
pF
Input Capacitance
4
6
Output Capacitance
COUT
VOUT=0.0V
10
pF
NOTE:
1. Sampled, not 100% tested.
1.2.2 AC Input/Output Test Conditions
VCCQ
INPUT
VCCQ/2
TEST POINTS
VCCQ/2 OUTPUT
0.0
AC test inputs are driven at VCCQ(min) for a Logic "1" and 0.0V for a Logic "0".
Input timing begins, and output timing ends at VCCQ/2. Input rise and fall times (10% to 90%) < 5ns.
Worst case speed conditions are when VCC=VCC(min).
Figure 5. Transient Input/Output Reference Waveform for VCC=2.7V-3.6V
Table 13. Configuration Capacitance Loading Value
CL (pF)
50
Test Configuration
CC=2.7V-3.6V
V
Figure 6. Transient Equivalent Testing Load Circuit
Rev. 2.44
LHF32FDJ
19
1.2.3 DC Characteristics
VCC=2.7V-3.6V
Notes Min.
Symbol
ILI
Parameter
Typ.
Max.
+1.0
Unit
Test Conditions
CC=VCCMax.,
V
Input Load Current
1
-1.0
µA
VCCQ=VCCQMax.,
VIN/VOUT=VCCQ or
GND
ILO
Output Leakage Current
1
-1.0
+1.0
µA
µA
VCC=VCCMax.,
CE#=RST#=
VCCQ 0.2V,
ICCS
VCC Standby Current
1
4
20
WP#=VCCQ or GND
VCC=VCCMax.,
ICCAS
ICCD
VCC Automatic Power Savings Current
1,4
1
4
4
20
20
25
µA
µA
mA
CE#=GND 0.2V,
WP#=VCCQ or GND
VCC Reset Power-Down Current
Average VCC Read
Current
Normal Mode
RST#=GND 0.2V
1,7
15
VCC=VCCMax.,
CE#=VIL,
OE#=VIH,
f=5MHz
ICCR
Average VCC Read
8 Word Read
1,7
5
10
mA
Current
Page Mode
VPP=VPPH1
VPP=VPPH2
VPP=VPPH1
VPP=VPPH2
1,5,7
1,5,7
1,5,7
1,5,7
20
10
10
4
60
20
30
10
mA
mA
mA
mA
ICCW
VCC (Page Buffer) Program Current
VCC Block Erase, Full Chip
Erase Current
ICCE
ICCWS
ICCES
IPPS
IPPR
VCC (Page Buffer) Program or
Block Erase Suspend Current
CE#=VIH
1,2,7
1,6,7
10
2
200
5
µA
µA
VPP Standby or Read Current
VPP≤VCC
VPP=VPPH1
VPP=VPPH2
VPP=VPPH1
VPP=VPPH2
VPP=VPPH1
VPP=VPPH2
VPP=VPPH1
VPP=VPPH2
1,5,6,7
1,5,6,7
1,5,6,7
1,5,6,7
1,6,7
2
10
2
5
30
5
µA
mA
µA
mA
µA
µA
µA
µA
IPPW
VPP (Page Buffer) Program Current
VPP Block Erase, Full Chip
Erase Current
IPPE
5
15
5
2
VPP (Page Buffer) Program
Suspend Current
IPPWS
1,6,7
10
2
200
5
1,6,7
IPPES
VPP Block Erase Suspend Current
1,6,7
10
200
Rev. 2.44
LHF32FDJ
20
DC Characteristics (Continued)
V
CC=2.7V-3.6V
Symbol
VIL
Parameter
Input Low Voltage
Notes Min.
Typ.
Max.
0.4
Unit
V
Test Conditions
5
5
-0.4
2.4
VCCQ
+ 0.4
VIH
Input High Voltage
V
VCC=VCCMin.,
CCQ=VCCQMin.,
OL=100µA
VOL
V
Output Low Voltage
5
5
0.2
V
I
V
V
CC=VCCMin.,
CCQ=VCCQMin.,
VCCQ
-0.2
VOH
Output High Voltage
V
IOH=-100µA
VPP Lockout during Normal
Operations
VPPLK
3,5,6
6
0.4
3.6
V
V
VPP during Block Erase, Full Chip
Erase, (Page Buffer) Program or OTP
Program Operations
VPPH1
1.65
3.0
12
VPP during Block Erase, Full Chip
Erase, (Page Buffer) Program or OTP
Program Operations
VPPH2
6
11.7
1.5
12.3
V
V
VLKO
VCC Lockout Voltage
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values are the reference values at VCC=3.0V and TA=+25°C
unless VCC is specified.
2. ICCWS and ICCES are specified with the device de-selected. If read or (page buffer) program is executed while in block
erase suspend mode, the device’s current draw is the sum of ICCES and ICCR or ICCW. If read is executed while in (page
buffer) program suspend mode, the device’s current draw is the sum of ICCWS and ICCR
.
3. Block erase, full chip erase, (page buffer) program and OTP program are inhibited when VPP≤VPPLK, and not guaranteed
in the range between VPPLK(max.) and VPPH1(min.), between VPPH1(max.) and VPPH2(min.) and above VPPH2(max.).
4. The Automatic Power Savings (APS) feature automatically places the device in power save mode after read cycle
completion. Standard address access timings (tAV QV) provide new data when addresses are changed.
5. Sampled, not 100% tested.
6. VPP is not used for power supply pin. With VPP≤VPPLK, block erase, full chip erase, (page buffer) program and OTP
program cannot be executed and should not be attempted.
Applying 12V 0.3V to VPP provides fast erasing or fast programming mode. In this mode, VPP is power supply pin and
supplies the memory cell current for block erasing and (page buffer) programming. Use similar power supply trace widths
and layout considerations given to the VCC power bus.
Applying 12V 0.3V to VPP during erase/program can only be done for a maximum of 1,000 cycles on each block. VPP
may be connected to 12V 0.3V for a total of 80 hours maximum.
7. The operating current in dual work is the sum of the operating current (read, erase, program) in each plane.
Rev. 2.44
LHF32FDJ
21
(1)
1.2.4 AC Characteristics - Read-Only Operations
V
CC=2.7V-3.6V, TA=-40°C to +85°C
Symbol
tAVAV
Parameter
Notes
Min.
80
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
tAVQV
tELQV
tAPA
Address to Output Delay
CE# to Output Delay
80
80
3
3
Page Address Access Time
OE# to Output Delay
RST# High to Output Delay
35
tGLQV
tPHQV
tEHQZ, tGHQZ
tELQX
tGLQX
tOH
20
150
20
CE# or OE# to Output in High Z, Whichever Occurs First
CE# to Output in Low Z
2
2
2
2
0
0
0
OE# to Output in Low Z
Output Hold from First Occurring Address, CE# or OE# change
Address Setup to CE#, OE# Going Low
for Reading Status Register
tAVEL, tAVGL
tELAX, tGLAX
EHEL, tGHGL
NOTES:
4, 6
5, 6
6
10
30
25
ns
ns
ns
Address Hold from CE#, OE# Going Low
for Reading Status Register
CE#, OE# Pulse Width High for Reading
Status Register
t
1. See AC input/output reference waveform for timing measurements and maximum allowable input slew rate.
2. Sampled, not 100% tested.
3. OE# may be delayed up to tELQV tGLQV after the falling edge of CE# without impact to tELQV
.
4. Address setup time (tAVEL, tAV GL) is defined from the falling edge of CE# or OE# (whichever goes low last).
5. Address hold time (tELAX, tGLAX) is defined from the falling edge of CE# or OE# (whichever goes low last).
6. Specifications tAVEL , tAV GL, tELAX, tGLAX and tEHEL, tGHGL for read operations apply to only status register read
operations.
Rev. 2.44
LHF32FDJ
22
A20-0(A) V
IH
VALID
ADDRESS
tAVAV
VIL
tEHQZ
tGHQZ
tAVQV
tEHEL
VIH
VIL
(E)
CE#
tAVEL
tELAX
tAVGL
tGHGL
tGLAX
OE# (G) V
IH
VIL
tELQV
VIH
VIL
(W)
WE#
tGLQV
tGLQX
tELQX
tOH
tOH
VOH
High Z
VALID
DQ15-0
(D/Q)
OUTPUT
VOL
tPHQV
VIH
VIL
(P)
RST#
Figure 7. AC Waveform for Single Asynchronous Read Operations
from Status Register, Identifier Codes, OTP Block or Query Code
Rev. 2.44
LHF32FDJ
23
A20-3 (A) V
IH
VALID
ADDRESS
tAVAV
VIL
tAVQV
A2-0 (A) V
IH
VALID
ADDRESS
VALID
VALID
VALID
ADDRESS
ADDRESS
ADDRESS
VIL
VIH
VIL
(E)
CE#
tELQV
tEHQZ
tGHQZ
OE# (G) V
IH
VIL
WE# (W) V
IH
tGLQV
VIL
tGLQX
tAPA
tOH
tELQX
VOH
VOL
High Z
VALID
VALID
VALID
VALID
DQ15-0
(D/Q)
OUTPUT OUTPUT
OUTPUT
OUTPUT
tPHQV
VIH
VIL
(P)
RST#
Figure 8. AC Waveform for Asynchronous 4-Word Page Mode
Read Operations from Main Blocks or Parameter Blocks
Rev. 2.44
LHF32FDJ
24
A20-3 (A) V
IH
VALID
ADDRESS
tAVAV
VIL
tAVQV
A2-0 (A) V
IH
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
VALID
VALID
VALID
VALID
ADDRESS ADDRESS ADDRESS ADDRESS
VIL
VIH
VIL
(E)
CE#
tEHQZ
tGHQZ
tELQV
OE# (G) V
IH
VIL
WE# (W) V
IH
tGLQV
VIL
tGLQX
tAPA
tOH
tELQX
VOH
VOL
High Z
tPHQV
VALID VALID VALID
VALID
VALID VALID VALID
VALID
DQ15-0
(D/Q)
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
VIH
VIL
(P)
RST#
Figure 9. AC Waveform for Asynchronous 8-Word Page Mode
Read Operations from Main Blocks or Parameter Blocks
Rev. 2.44
LHF32FDJ
25
(1), (2)
1.2.5 AC Characteristics - Write Operations
VCC=2.7V-3.6V, TA=-40°C to +85°C
Symbol
Parameter
Notes
3
Min.
80
150
0
Max.
Unit
tAVAV
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
PHWL (tPHEL
)
RST# High Recovery to WE# (CE#) Going Low
CE# (WE#) Setup to WE# (CE#) Going Low
WE# (CE#) Pulse Width
t
ELWL (tWLEL
)
tWLWH (tELEH
tDVWH (tDVEH
AVWH (tAVEH
tWHEH (tEHWH
WHDX (tEHDX
tWHAX (tEHAX
tWHWL (tEHEL
SHWH (tSHEH
tVVWH (tVVEH
WHGL (tEHGL
tQVSL
tQVVL
)
4
8
8
55
40
50
0
)
Data Setup to WE# (CE#) Going High
Address Setup to WE# (CE#) Going High
CE# (WE#) Hold from WE# (CE#) High
Data Hold from WE# (CE#) High
t
)
)
t
)
0
)
Address Hold from WE# (CE#) High
WE# (CE#) Pulse Width High
0
)
5
3
3
25
0
t
)
WP# High Setup to WE# (CE#) Going High
VPP Setup to WE# (CE#) Going High
)
200
30
0
t
)
Write Recovery before Read
WP# High Hold from Valid SRD
VPP Hold from Valid SRD
3, 6
3, 6
0
tAVQ V
50
+
tWHR0 (tEHR0
)
WE# (CE#) High to SR.7 Going "0"
3, 7
ns
NOTES:
1. The timing characteristics for reading the status register during block erase, full chip erase, (page buffer) program and
OTP program operations are the same as during read-only operations. Refer to AC Characteristics for read-only
operations.
2. A write operation can be initiated and terminated with either CE# or WE#.
3. Sampled, not 100% tested.
4. Write pulse width (tWP) is defined from the falling edge of CE# or WE# (whichever goes low last) to the rising edge of
CE# or WE# (whichever goes high first). Hence, tWP=tWLWH=tELEH=tWLEH=tELWH
5. Write pulse width high (tWPH) is defined from the rising edge of CE# or WE# (whichever goes high first) to the falling
edge of CE# or WE# (whichever goes low last). Hence, tWPH=tWHWL=tEHEL=tWHEL=tEHWL
.
.
6. VPP should be held at VPP=VPPH1/2 until determination of block erase, full chip erase, (page buffer) program or OTP
program success (SR.1/3/4/5=0).
7. tWHR0 (tEHR0) after the Read Query or Read Identifier Codes/OTP command=tAVQV+100ns.
8. Refer to Table 6 for valid address and data for block erase, full chip erase, (page buffer) program, OTP program or lock bit
configuration.
Rev. 2.44
LHF32FDJ
26
NOTE 1
NOTE 2
NOTE 3
NOTE 4
NOTE 5
A20-0 (A) V
IH
VALID
VALID
ADDRESS
VALID
ADDRESS
ADDRESS
VIL
tAVWH (tAVEH
)
tAVAV
tWHAX
(tEHAX
)
VIH
VIL
NOTES 5, 6
(E)
CE#
tELWL (tWLEL
)
tWHEH (tEHWH
)
tWHGL (tEHGL)
NOTES 5, 6
OE# (G) V
IH
VIL
tPHWL (tPHEL)
tWHWL (tEHEL
)
WE# (W) V
IH
VIL
tWLWH
(tELEH
tWHQV1,2,3 (tEHQV1,2,3)
)
tDVWH (tDVEH
)
t
WHDX (tEHDX)
VIH
VIL
DQ15-0
(D/Q)
VALID
SRD
DATA IN
DATA IN
tWHR0 (tEHR0
)
"1"
"0"
SR.7 (R)
(P) V
IH
RST#
VIL
tSHWH (tSHEH
)
tQVSL
VIH
VIL
WP# (S)
tVVWH (tVVEH
)
tQVVL
VPPH1,2
V
PP (V) VPPLK
VIL
NOTES:
1. VCC power-up and standby.
2. Write each first cycle command.
3. Write each second cycle command or valid address and data.
4. Automated erase or program delay.
5. Read status register data.
6. For read operation, OE# and CE# must be driven active, and WE# de-asserted.
Figure 10. AC Waveform for Write Operations
Rev. 2.44
LHF32FDJ
27
1.2.6 Reset Operations
tPHQV
VIH
(P)
RST#
VIL
tPLPH
VOH
High Z
VALID
OUTPUT
DQ
15-0 (D/Q)
V
OL
(A) Reset during Read Array Mode
SR.7="1"
ABORT
COMPLETE
tPLRH
tPHQV
VIH
VIL
(P)
RST#
tPLPH
VOH
High Z
VALID
OUTPUT
DQ
15-0 (D/Q)
V
OL
(B) Reset during Erase or Program Mode
VCC(min)
GND
VCC
tVHQV
t2VPH
tPHQV
VIH
(P)
RST#
VIL
VOH
High Z
VALID
OUTPUT
DQ
15-0 (D/Q)
V
OL
(C) RST# rising timing
Figure 11. AC Waveform for Reset Operations
Reset AC Specifications (VCC=2.7V-3.6V, TA=-40°C to +85°C)
Symbol
tPLPH
Parameter
Notes
1, 2, 3
Min.
100
Max.
Unit
RST# Low to Reset during Read
(RST# should be low during power-up.)
ns
tPLRH
t2VPH
RST# Low to Reset during Erase or Program
VCC 2.7V to RST# High
1, 3, 4
1, 3, 5
3
22
1
µs
ns
100
tVHQV
NOTES:
VCC 2.7V to Output Delay
ms
1. A reset time, tPHQV, is required from the later of SR.7 going "1" or RST# going high until outputs are valid. Refer to AC
Characteristics - Read-Only Operations for tPHQV
.
2. tPLPH is <100ns the device may still reset but this is not guaranteed.
3. Sampled, not 100% tested.
4. If RST# asserted while a block erase, full chip erase, (page buffer) program or OTP program operation is not executing,
the reset will complete within 100ns.
5. When the device power-up, holding RST# low minimum 100ns is required after VCC has been in predefined range and
also has been in stable there.
Rev. 2.44
LHF32FDJ
28
(3)
1.2.7 Block Erase, Full Chip Erase, (Page Buffer) Program and OTP Program Performance
V
CC=2.7V-3.6V, TA=-40°C to +85°C
Page Buffer
Command is
Used or not
Used
VPP=VPPH1
(In System)
VPP=VPPH2
(In Manufacturing)
Symbol
Parameter
Notes
Unit
Typ.(1) Max.
Typ.(1) Max.
Min.
(2)
(2)
Min.
2
2
2
2
2
2
Not Used
Used
0.05
0.03
0.38
0.24
11
0.3
0.04
0.02
0.31
0.17
9
0.12
s
s
4K-Word Parameter Block
Program Time
tWPB
0.12
2.4
0.06
1.0
0.5
185
90
Not Used
Used
s
32K-Word Main Block
Program Time
tWMB
1.0
s
tWHQV1
tEHQV1
tWHOV1
tEHOV1
tWHQV2
tEHQV2
tWHQV3
tEHQV3
/
/
/
/
Not Used
Used
200
100
µs
µs
Word Program Time
OTP Program Time
7
5
2
2
Not Used
36
400
4
27
185
4
µs
4K-Word Parameter Block
Erase Time
-
-
0.3
0.2
s
32K-Word Main Block
Erase Time
2
2
4
0.6
40
5
5
0.5
33
5
5
s
s
Full Chip Erase Time
350
10
350
10
tWHRH1
tEHRH1
tWHRH2
tEHRH2
/
(Page Buffer) Program Suspend
Latency Time to Read
-
-
µs
/
Block Erase Suspend
Latency Time to Read
4
5
5
20
5
20
µs
µs
Latency Time from Block Erase
Resume Command to Block
Erase Suspend Command
tERES
-
500
500
NOTES:
1. Typical values measured at VCC=3.0V, VPP=3.0V or 12V, and TA=+25°C. Assumes corresponding lock bits
are not set. Subject to change based on device characterization.
2. Excludes external system-level overhead.
3. Sampled, but not 100% tested.
4. A latency time is required from writing suspend command (WE# or CE# going high) until SR.7 going "1".
5. If the interval time from a Block Erase Resume command to a subsequent Block Erase Suspend command is shorter
than tERES and its sequence is repeated, the block erase operation may not be finished.
Rev. 2.44
LHF32FDJ
29
2 Related Document Information(1)
Document No.
FUM00701
Document Name
LH28F320BF series Appendix
NOTE:
1. International customers should contact their local SHARP or distribution sales offices.
Rev. 2.44
i
A-1 RECOMMENDED OPERATING CONDITIONS
A-1.1 At Device Power-Up
AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up.
If the timing in the figure is ignored, the device may not operate correctly.
VCC(min)
VCC
GND
tVR
t2VPH
tPHQV
VIH
(P)
RP#
(RST#)
VIL
VCCWH1/2
(VPPH1/2)
*1
(V)
VCCW
(VPP)
GND
tR or tF
tR or tF
tAVQV
VIH
Valid
Address
ADDRESS (A)
VIL
tR
tF
tELQV
VIH
VIL
VIH
VIL
VIH
VIL
VIH
(E)
CE#
(W)
WE#
tR
tF
tGLQV
(G)
OE#
(S)
WP#
VIL
VOH
High Z
Valid
Output
DATA
(D/Q)
V
OL
*1 To prevent the unwanted writes, system designers should consider the design, which applies VCCW (VPP)
to 0V during read operations and VCCWH1/2 (VPPH1/2) during write or erase operations.
See the application note AP-007-SW-E for details.
Figure A-1. AC Timing at Device Power-Up
For the AC specifications t , t , t in the figure, refer to the next page. See the “ELECTRICAL SPECIFICATIONS“
VR
R
F
described in specifications for the supply voltage range, the operating temperature and the AC specifications not shown in
the next page.
Rev. 1.10
ii
A-1.1.1 Rise and Fall Time
Symbol
Parameter
Notes
1
Min.
0.5
Max.
Unit
t
t
t
V
Rise Time
CC
30000
µs/V
µs/V
µs/V
VR
Input Signal Rise Time
Input Signal Fall Time
1, 2
1, 2
1
1
R
F
NOTES:
1. Sampled, not 100% tested.
2. This specification is applied for not only the device power-up but also the normal operations.
Rev. 1.10
iii
A-1.2 Glitch Noises
Do not input the glitch noises which are below V (Min.) or above V (Max.) on address, data, reset, and control signals,
IH
IL
as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a).
Input Signal
Input Signal
VIH (Min.)
VIH (Min.)
VIL (Max.)
VIL (Max.)
Input Signal
Input Signal
(a) Acceptable Glitch Noises
(b) NOT Acceptable Glitch Noises
Figure A-2. Waveform for Glitch Noises
See the “DC CHARACTERISTICS“ described in specifications for V (Min.) and V (Max.).
IH
IL
Rev. 1.10
iv
(1)
A-2 RELATED DOCUMENT INFORMATION
Document No.
Document Name
AP-001-SD-E
AP-006-PT-E
AP-007-SW-E
Flash Memory Family Software Drivers
Data Protection Method of SHARP Flash Memory
RP#, V Electric Potential Switching Circuit
PP
NOTE:
1. International customers should contact their local SHARP or distribution sales office.
Rev. 1.10
v
A-3 STATUS REGISTER READ OPERATIONS
If AC timing for reading the status register described in specifications is not satisfied, a system processor can check the
status register bit SR.15 instead of SR.7 to determine when the erase or program operation has been completed.
Table A-3-1. Status Register Definition (SR.15 and SR.7)
NOTES:
SR.15 = WRITE STATE MACHINE STATUS: (DQ )
SR.15 indicates the status of WSM (Write State
Machine). If SR.15="0", erase or program operation is in
progress in any partition.
15
1 = Ready in All Partitions
0 = Busy in Any Partition
SR.7 indicates the status of the partition. If SR.7="0",
erase or program operation is in progress in the addressed
partition. Even if the SR.7 is "1", the WSM may be
occupied by the other partition.
SR.7 = WRITE STATE MACHINE STATUS
FOR EACH PARTITION: (DQ )
7
1 = Ready in the Addressed Partition
0 = Busy in the Addressed Partition
Operation to Partition 0
Operation to Partition 2
Address (A) V
IH
VALID ADDRESS
VALID ADDRESS
within PARTITION 0
within PARTITION 2
VIL
VIH
(E)
CE#
VIL
WE# (W) V
IH
VIL
VIH
VIL
VALID
VALID
DQ15-0
(D/Q)
COMMAND
COMMAND
tWHR0 (tEHR0
)
"1"
SR.15
(R)
( Partition 0 )
"0"
"1"
SR.7
( Partition 0 )
(R)
"0"
"1"
SR.15
( Partition 1 )
SR.7
( Partition 1 )
(R)
(R)
"0"
"1"
"0"
"1"
tWHR0 (tEHR0
)
SR.15
( Partition 2 )
SR.7
( Partition 2 )
(R)
(R)
"0"
"1"
"0"
"1"
SR.15
( Partition 3 )
SR.7
( Partition 3 )
(R)
(R)
"0"
"1"
"0"
PARTITION3 PARTITION2 PARTITION1
PARTITION0
Check SR.15 instead of
SR.7 in Partition 0
Check SR.15 instead of
SR.7 in Partition 2
Figure A-3-1. Example of Checking the Status Register
(In this example, the device contains four partitions.)
021211
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