LR38603_技术文档

BACK

LR38603

Digital Signal Processor for

Color CCD Cameras

LR38603

DESCRIPTION

The LR38603 is a CMOS digital signal processor for

color CCD video camera systems of 270 k/320 k/

410 k/470 k-pixel CCDs with complementary color

filters. The video camera system consists of

CDS/PGA/ADC IC (IR3Y48A1), DSP IC (LR38603)

and V driver IC (LR36685) with CCD.

FEATURES

• Designed for 1/4-type 270 k/320 k/410 k/470 k-

pixel color CCDs with Mg, G, CY, and Ye

complementary color filters

• Switchable between NTSC and PAL modes

• Built-in signal generation circuit for driving CCD

and various pulses for TV signals

• Parameters for camera signal processing can be

set

• Built-in auto exposure control

• Built-in auto white balance control

• Built-in auto carrier balance control

• Built-in drive circuit for 2 K-bit EEPROM

• Built-in 9-bit D/A converter

• Built-in mirror image output

• Built-in circuit to reduce line crawl noise

• Built-in auto white detect correction

• YUV digital output (8 bits x 2)

• UYVY digital output (8 bits x 1)

• Analog video output

• External clock input (8 fsc)

• Built-in vertical reset

• Built-in horizontal reset

• Single +3.3 V power supply

• Package :

80-pin LQFP (P-LQFP080-1212) 0.5 mm pin-pitch

In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in

catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.

1

LR38603

PIN CONNECTIONS

80-PIN LQFP

TOP VIEW

ACL

CKI

CKO

V^DD

GND

ADCK

SCK

SDATA

ADI⁹

1

2

3

4

5

6

7

8

9

60 HD

59 Y⁷

58 Y6

57 Y5

56 Y4

55 VDD

54 GND

53 Y³

52 Y2

ADI8 10

ADI7 11

ADI6 12

ADI5 13

ADI4 14

VDD 15

GND 16

ADI³17

ADI2 18

ADI1 19

ADI0 20

51 Y1

50 Y0

49 EXCKI

48 DCK²

47 DCK1

46 VDD

45 GND

44 EEMD³

43 EEMD2

42 EEMD1

41 EEMDS

(P-LQFP080-1212)

2

LR38603

BLOCK DIAGRAM

LUMINANCE

SIGNAL

PROCESS

OB

CLAMPING

4 LINES

DELAY

ADI9-ADI0

VIDEO

Y7-Y0

9-BIT DA

BLKX, CSYNC

HD, VD, ADCLP

OBCP

DCK1, DCK2

EXCKI

SSG

TG

COLOR

SIGNAL

PROCESS

CKI

CKO

EEPSL, EEPFL

EEPCK, EEPDA

FR, FH¹, FH2

V1X-V4X

VH1X, VH3X

AUTOMATIC

CONTROL

EEPROM

CONTROL

EEMD², EEMD3

EEMDS, EEMD1

WB1, WB2, MIR, BLC

FCDS, FS, RS

ADCK

3

LR38603

PIN DESCRIPTION

PIN NO. SYMBOL IO SYMBOL POLARITY

DESCRIPTION

1

2

ACL

CKI

ICSU

OSCI

All reset

Input for reference clock oscillator

Connect to CKO (pin 3) with R.

NTSC : 28.63636 MHz PAL : 28.375 MHz

3

4

5

CKO

VDD

OSCO

Output for reference clock oscillator. The output is the inverse of CKI (pin 2).

Power supply input (+3.3 V)

–

GND

Ground

Clock output for A/D converter

Connect to ADCK of IR3Y48A1.

Clock output for setting parameter of IR3Y48A1

Serial data output for setting parameter of IR3Y48A1

Digital signal input (MSB)

6

ADCK

OBF4M

7

8

9

SCK

OBF4M

SDATA

ADI9

OBF4M

IC

10 ADI8

11 ADI7

12 ADI6

13 ADI5

14 ADI4

15 VDD

IC

Digital signal input

IC

Digital signal input

IC

Digital signal input

IC

Digital signal input

IC

–

Digital signal input

Power supply input (+3.3 V)

16 GND

17 ADI3

18 ADI2

19 ADI1

20 ADI0

21 OBCP

22 ADCLP

23 BLKX

–

Ground

IC

Digital signal input

IC

Digital signal input

IC

Digital signal input

IC

Digital signal input (LSB)

OBF4M

Clamp pulse output for optical black

Clamp pulse output

Blanking pulse output

Data input from EEPROM

Connect to a data output pin of EEPROM.

When setting internal register from an external device, use EEPCK, EEPFL and

EEPSL together with EEPDA. This pin is for serial data input.

Ground

24 EEPDA

IO4MU

25 GND

26 VDD

–

Power supply input (+3.3 V)

Clock output for EEPROM

Connect to clock input of EEPROM.

When setting internal register from external device, this pin is used as serial

clock.

27 EEPCK IO4MSU

Control for setting internal register from an external device

Usually used at H level.

28 EEPFL

29 EEPSL

ICU

ICD

Control for setting internal register from external device

Usually used at L level.

When setting register, set EEPSL at H level.

4

LR38603

PIN NO. SYMBOL IO SYMBOL POLARITY

DESCRIPTION

WB setting. Use together with WB1 and WB2

30 WB1

31 WB2

IO4MD

00 (WB2, WB1) : Auto white balance 01 : WB1 mode 10 : WB2 mode

11 : WB3 mode

These pins are 0 bit (WB1) and 1st-bit (WB2) of UV output in output digital YUV

mode.

Setting for mirroring video output mode

32 MIR

IO4MD

L : Normal H : Mirroring

This pin is 2nd-bit of UV output in output digital YUV mode.

Switching internal register for exposure-standard

This pin is 3rd-bit of UV output in digital output mode.

Ground for internal D/A converter

33 BLC

IO4MD

34 GNDDA

35 VDDDA

–

Power supply for internal D/A converter

Connect to DC 3.3 V power supply (+3.3 V).

DC output of internal D/A converter. Connect to ground pin via capacitor.

DC output of internal D/A converter. Connect to ground pin via register.

DC reference input for internal D/A converter

Connect to DC power supply (+1.0 V).

36 VB

DAO

37 IREF

38 VREF

DAI

39 GNDDA

40 VIDEO

–

Ground for internal D/A converter.

DAO

Analog video output

Switching electronic shutter control

41 EEMDS

42 EEMD1

43 EEMD2

44 EEMD3

IO4MU

Use together with EEMDS, EEMD1, EEMD2 and EEMD3. Refer to "Electronic

Shutter Speed Setting" in AUTOMATIC CAMERA FUNCTION CONTROL.

These pins are 4th to 7th-bit of UV output in digital output mode.

When in line lock mode,

EEMD2 : H reset

EEMD3 : V reset

45 GND

46 VDD

–

Ground

Power supply input (+3.3 V).

Clock output synchronized with digital output

Switchable among CSYNC, CBLK or L level.

ID pulse output of UV signal for digital output

When in analog output, output is KEI or L level.

KEI pulse : At power-on, begin with L level. When shutter speed is 1/60 s (PAL

1/50 s) and PGA gain is more than the value in address 92h, it goes to H level

and becomes stable.

47 DCK1

OBF4M

48 DCK2

OBF4M

49 EXCKI

50 Y0

ICSU

OBF4M

–

Input for external clock

Digital video signal output

Use together with Y7 (MSB) to Y0 (LSB).

UYVY signal or illumination signal output (according to the register).

51 Y1

52 Y2

53 Y3

54 GND

Ground

5

LR38603

PIN NO. SYMBOL IO SYMBOL POLARITY

DESCRIPTION

55 VDD

56 Y4

57 Y5

58 Y6

59 Y7

–

Power supply input (+3.3 V)

Digital video signal output

OBF4M

Use together with Y7 (MSB) to Y0 (LSB).

UYVY signal or illumination signal output (according to the register)

Horizontal drive pulse output

It is able to select horizontal drive pulse for drive timing and video output timing

from BELL pulse, HREF pulse and L level.

60 HD

OBF4M

BELL pulse : The signal that goes to H level 1 time per 1 field.

Vertical drive pulse output

61 VD

OBF4M

It is able to select from VD, CSYNC and VS outputs for drive timing and video

output timing.

62 V1X

63 V2X

64 V3X

65 V4X

66 VDD

67 GND

68 VH1X

69 VH3X

70 OFDX

71 VDD

72 GND

73 FR

OBF4M

–

CCD vertical drive pulse output

Connect each pin to CCD via V driver IC.

Power supply input (+3.3 V)

–

Ground

OBF4M

–

Pulse output for reading charges

Connect each pin to CCD via V driver IC.

OFD pulse output. Connect each pin to CCD via V driver IC.

Power supply input (+3.3 V)

–

Ground

OBF12M

–

Reset pulse output. Connect each pin to CCD via capacitor.

Horizontal transmit pulse output

Connect to CCD.

74 FH1

75 FH2

76 VDD

77 GND

Power supply input (+3.3 V)

–

Ground

Pulse output for sample hold

When using IR3Y48A1, connect to CSN pin for parameter setting.

Pulse output for sample hold

78 RS

OBF4M

79 FS

OBF4M

80 FCDS

IC

: Input pin

DAO

: Output pin for D/A converter

: Output pin for oscillation

ICU

ICD

ICSU

DAI

OSCI

: Input pin with pull-up resistor

: Input pin with pull-down resistor

: Schmidt input pin with pull-up resistor

: Input pin for D/A converter

: Input pin for oscillation

OSCO

IO4MU : Input/output pin with pull-up resistor

IO4MD : Input/output pin with pull-down resistor

IO4MSU : Input/output pin with pull-down resistor (schmidt

input)

OBF4M : Output pin

OBF12M : Output pin

6

LR38603

DSP REGISTER TABLE

ADDRESS

NAME

BIT

CONTENTS

00h

STOP_EEPROM [7 : 0] Stop reading from EEPROM only when EEPROM data is FF.

01h

LPF_TH

[7] H : Luminance signal processing without LPF (when using B/W CCD)

CCD_SEL

[6 : 5] 00 : 270 k pixel CCD (NTSC) 01 : 410 k pixel CCD (NTSC)

10 : 320 k pixel CCD (PAL) 11 : 470 k pixel CCD (PAL)

[4 : 3] Input data timing adjustment

ADTI

00 : Reference 01 : 1 clock delay 10 : 1 clock forward 11 : 2 clocks forward

[2] 1 : Latch with inverted clock

SEL_CDS

NI

[1 : 0] Fixed to 1X (IR3Y48A1)

02h

[6] 0 : Interlace 1 : Non-interlace

MODE_OUT_SIG

Select output mode.

[5 : 3]

000 : Analog video output

001 : Analog video output

EXCKI : Vertical reset pulse input

EXCKI : 8 fsc clock input

EEMD2 : Horizontal reset pulse input

EEMD3 : Vertical reset pulse input

010 : Analog video output

EEMD2 : Horizontal reset pulse input

EEMD3 : Vertical reset pulse input

100 : YUV digital video output : Clock rate of video data pixel-CK

101 : YUV digital video output : Clock rate of video data EXCKI

110 : UYVY digital video output : Clock rate of video data EXCKI

011, 111 are prohibited.

START_EE

AGC_FIX

OB_SEL

[2] Shutter speed at power-on

[1] PGA control

0 : minimum

0 : Auto

1 : maximum

1 : Fixed

[0] Carrier balance control

0 : Auto

1 : Fixed

03h

HD_SEL

[6 : 5] Select output signal from HD pin

00 : HD output (CCD drive timing) 01 : HD output (video output timing)

10 : BELL pulse (in analog video output), HREF (in digital video output)

11 : Fixed to L level

VD_SEL

[4 : 3] Select output signal from VD pin

00 : VD output (CCD drive timing) 01 : VD output (video output timing)

10 : Fixed to L level (in analog video output), VS (in digital video output)

11 : Fixed to L level (in analog video output), CSYNC (in digital video

output)

DCK1_SEL

DCK2_SEL

SW_CTRL

[2 : 1] Select output signal from DCK1 pin (in analog video output)

00 : CSYNC 01 : CBLNK 1X : Fixed to L level

[0] Select output signal from DCK2 pin (in analog video output)

0 : Fluorescent signal 1 : Fixed to L level

04h

[7 : 0] Electronic shutter control (EEMDS, EEMD1, EEME2, EEMD3), mirror video

output (MIR [MSB]), internal register for exposure-standard (BLC) and white

balance (WB2, WB1 [LSB]) are set when selecting digital output mode with

MODE_OUT_SIG (address 02h).

Shutter control of EEMD2 and EEMD3 is set by the register of SW_CTRL

and that of EEMDS and EEMD1 is set by pin 41 and pin 42 when setting

"001" and "010" with MODE_OUT_SIG (address 02h).

7

LR38603

ADDRESS

NAME

MIN_SH_SEL

MAX_SH

BIT

CONTENTS

05h

[7] Select minimum shutter speed 0 : 1/60 s (1/50 s) 1 : 1/100 s (1/120 s)

[6 : 0] Restriction in maximum shutter speed

(When EEMDS, EEMD1, EEMD2, EEMD3 = 4' b1110)

[7 : 0] Reference of exposure

06h

07h

REF_IRIS1

CTLD_AGC

[7 : 0] Outside range of error of exposure reference

(Hysteresis range of IRIS and PGA tweaking range)

[7 : 0] Inside range of error of exposure reference

(Exposure control is stopped in REF_IRIS CTLD_0)

[7 : 0] Exposure reference in condition against light (When BLC = H)

[7 : 0] Ceiling clip in accumulate exposure data

08h

CTLD_0

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

REF_IRIS2

CLIP_IRIS

UW_E1

UW_E2

UW_E3

UW_E4

UW_E5

UW_E6

UW_E7

UW_E8

[7 : 0] Downward weight factor 1 in calculation of exposure. (upper of screen)

[7 : 0] Downward weight factor 2 in calculation of exposure.

[7 : 0] Downward weight factor 3 in calculation of exposure.

[7 : 0] Downward weight factor 4 in calculation of exposure.

[7 : 0] Downward weight factor 5 in calculation of exposure.

[7 : 0] Downward weight factor 6 in calculation of exposure.

[7 : 0] Downward weight factor 7 in calculation of exposure.

[7 : 0] Downward weight factor 8 in calculation of exposure. (lower of screen)

Sum of UW_E1 to UW_E8 must be 256d.

13h

14h

15h

16h

CW_E

[6 : 0] Ratio of downward IRIS against center

CWP_E

CWA_E

EE_DIV_STP

LPFE_O

LPFE_I

[5 : 0] Center point, position of left-upper area.

[5 : 0] Center point, size of area.

[6 : 4] Select dividing value of shutter speed control.

[3 : 2] Select LPF of IRIS data in PGA normal adjustment.

[1 : 0] Select LPF of IRIS data in PGA tweak.

17h

18h

19h

P_HEE

[7 : 0] Ratio of luminance H peak of IRIS data

P_LEE

[7 : 0] Ratio of luminance L peak of IRIS data

MOD8

[4] Select peak accumulation. 0 : Avg. of 8 pixels 1 : Avg. of 4 pixels

[3 : 2] Reduction of IRIS control in normal operation.

IRIS_DLY

00 : Operating always

01 : Operating each 2VD timing

10 : Operating each 4VD timing 11 : Operating each 8VD timing

[1 : 0] Reduction of IRIS control in PGA tweak.

IRIS_DLY

00 : Operating always

01 : Operating each 2VD timing

10 : Operating each 4 VD timing 11 : Operating each 8VD timing

[7 : 5] Select dividing value of PGA control.

1Ah

AG_DIV_STP

AG_GAIN

[4 : 0] Number of steps in PGA gain

1Bh

1Ch

1Dh

1Eh

MAX_AGC

REF_AGC

[7 : 0] Upper limitation of PGA control.

[7 : 0] Lower limitation of PGA control (initial value of PGA at power-on).

[7 : 0] Fixed PGA gain [7 : 0 (LSB) ]

S_38M_GA

S_38M_GA_U

S_38M_MX

[3] Fixed PGA gain when using IR3Y48A1 [8 (MSB)]

IR3Y48A1 minimum gain [1 : 0]

[2 : 0]

00 : 0 01 : +6 dB 10 : +12 dB 11 : –2 dB

8

LR38603

ADDRESS

NAME

BIT

CONTENTS

[7] Offset auto adjustment.

1Fh

S_38M_OFS

0 : Auto 1 : Fixed (when using IR3Y48A1)

[6 : 0] Factor in fixed offset mode

Fixed to 40h when using IR3Y48A1.

20h

21h

22h

23h

24h

CSEPR

CSEPB

CB_R

[7 : 0] R side factor of color separation (positive value)

[7 : 0] B side factor of color separation (positive value)

[7 : 0] R side factor of carrier balance (complement of 2)

[7 : 0] B side factor of carrier balance (complement of 2)

[5 : 3] Select characteristics of color gamma.

[2 : 1] Manner of YL signal production ([2 : 1])

00 : Avg. of 3 lines 01 : Each R, B line 1X : Fixed ratio

[0] Manner of RG signal production

CB_B

C_GAM

YL_SEL

C1_RB_SEL

0 : Use color separation factor (address 20h, 21h)

1 : Use fixed color separation factor.

MODE_MAT

LC_ON_RB

YL_SUB

[7] Matrix factor 0 : Unsigned 1 : Signed

[6] 1 : Operation against line crawl in color processing.

[5] 1 : Set YL to 0 in chrominance generation.

[4] Switch order of UV digital output

25h

UV_CTRL1

SEL_RB

[3] Swap R and B after color separation.

[2] Swap R – Y and B – Y in output

SEL_RB2

SPCTRL

[1] Switch attributes of SP1 and SP2.

IDCO

[0] Switch attribute of color separation HG.

26h

27h

28h

29h

2Ah

MAX_WBR

MIN_WBR

MAX_WBB

MIN_WBB

JMP_OFF

AWB_HIGH

MAX_IQAREA

IQ_LPF

[7 : 0] Upper limit of R side range of AWB gain (9 bits data which includes 1 at LSB)

[7 : 0] Lower limit of R side range of AWB gain (9 bits data which includes 1 at LSB)

[7 : 0] Upper limit of B side range of AWB gain (9 bits data which includes 1 at LSB)

[7 : 0] Lower limit of B side range of AWB gain (9 bits data which includes 1 at LSB)

[4] 0 : Normal 1 : Suppress AWB skipping

[3] 0 : Normal 1 : Force fast processing in small frame

[2] 0 : Address 36h to 3Dh 1 : Fix WB frame to maximum.

[1 : 0] Select LPF of AWB I, Q.

00 : Avg. of 4 V 01 : Avg. of 2 V 1X : Non

2Bh

2Ch

2Dh

2Eh

2Fh

30h

31h

32h

33h

K_WBR_H

K_WBB_H

CMP_CT

AWB_HCL

AWB_LCL

REF_WBPK

K_CL

[7 : 0] R side multiplier of capture speed in AWB fast processing.

[7 : 0] B side multiplier of capture speed in AWB fast processing.

[7 : 0] Number of operations of white balance (each CMP_CT x VD timing)

[7 : 0] Initial value of AWBHCL

[7 : 0] Initial value of AWBLCL

[7 : 0] Reference data in calculation of intercept level of AWB accumulated luminance

[7 : 0] H peak ratio in calculation of intercept level of AWB accumulated luminance

[7 : 0] Multiplier in calculation of intercept level of AWB accumulated luminance

[7] AWB detected data

K_WBCL

INT_I_R_Y

0 : I, Q 1 : R – Y, B – Y

CW_IQ

[6 : 0] Ratio of AWB weighted center and downward.

9

LR38603

ADDRESS

34h

NAME

CWPA_IQ

CTLD_AW0

AWB_IP_L

AWB_IM_L

AWB_QP_L

AWB_QM_L

AWB_IP_S

AWB_IM_S

AWB_QP_S

AWB_QM_S

AWB_IW_L

AWB_QW_L

AWB_IW_S

AWB_QW_S

AWB_C_I

AWB_C_Q

WBR1

BIT

CONTENTS

[7 : 0] Position and area of AWB center.

35h

[7 : 0] Reset range of WB frame (compared with IRIS)

36h

[7 : 0] Outside, I-axis positive of AWB detect area (in fast processing)

[7 : 0] Outside, I-axis negative of AWB detect area (in fast processing)

[7 : 0] Outside, Q-axis positive of AWB detect area (in fast processing)

[7 : 0] Outside, Q-axis negative of AWB detect area (in fast processing)

[7 : 0] Inside, I-axis positive of AWB detect area (in normal processing)

[7 : 0] Inside, I-axis negative of AWB detect area (in normal processing)

[7 : 0] Inside, Q-axis positive of AWB detect area (in normal processing)

37h

38h

39h

3Ah

3Bh

3Ch

3Dh

3Eh

3Fh

[7 : 0] Inside, Q-axis negative of AWB detect area (in normal processing)

[6 : 0] White area, I-axis, outside (for hysteresis).

[6 : 0] White area, Q-axis, outside (for hysteresis).

40h

[7 : 4] White area, I-axis, inside (for targeted white area).

[3 : 0] White area, Q-axis, inside (for targeted white area).

[7 : 4] WB convergence orientation, I-axis coordinate (complement of 2)

[3 : 0] WB convergence orientation, Q-axis coordinate (complement of 2)

[7 : 0] WB1 R side constant (9 bits data which includes 0 at MSB)

[7 : 0] WB1 B side constant (9 bits data which includes 0 at MSB)

[7 : 0] WB2 R side constant (9 bits data which includes 0 at MSB)

[7 : 0] WB2 B side constant (9 bits data which includes 0 at MSB)

[7 : 0] WB3 R side constant (9 bits data which includes 0 at MSB)

[7 : 0] WB3 B side constant (9 bits data which includes 0 at MSB)

41h

42h

43h

44h

45h

46h

47h

48h

WBB1

WBR2

WBB2

WBR3

WBB3

REF_GA_R1M [7 : 0] Chrominance gain of R – Y negative direction when WB1 is fixed or auto-

controlled (present WBR factor ≤ WBR1).

49h

4Ah

4Bh

4Ch

4Dh

4Eh

4Fh

50h

51h

REF_GA_B1M

REF_GA_R1P

REF_GA_B1P

[7 : 0] Chrominance gain of B – Y negative direction when WB1 is fixed or auto-

controlled (present WBR factor ≤ WBR1).

[7 : 0] Chrominance gain of R – Y positive direction when WB1 is fixed or auto-

controlled (present WBR factor ≤ WBR1).

[7 : 0] Chrominance gain of B – Y positive direction when WB1 is fixed or auto-

controlled (present WBR factor ≤ WBR1).

REF_GA_R2M [7 : 0] Chrominance gain of R – Y negative direction when WB2 is fixed or auto-

controlled (present WBR factor ≤ WBR2).

REF_GA_B2M

REF_GA_R2P

REF_GA_B2P

[7 : 0] Chrominance gain of B – Y negative direction when WB2 is fixed or auto-

controlled (present WBR factor ≤ WBR2).

[7 : 0] Chrominance gain of R – Y positive direction when WB2 is fixed or auto-

controlled (present WBR factor ≤ WBR2).

[7 : 0] Chrominance gain of B – Y positive direction when WB2 is fixed or auto-

controlled (present WBR factor ≤ WBR2).

REF_GA_R3M [7 : 0] Chrominance gain of R – Y negative direction when WB3 is fixed or auto-

controlled (present WBR factor ≤ WBR3).

REF_GA_B3M

[7 : 0] Chrominance gain of B – Y negative direction when WB3 is fixed or auto-

controlled (present WBR factor ≤ WBR3).

10

LR38603

ADDRESS

NAME

BIT

CONTENTS

52h

REF_GA_R3P

[7 : 0] Chrominance gain of R – Y positive direction when WB3 is fixed or auto-

controlled (present WBR factor ≤ WBR3).

53h

54h

55h

56h

57h

58h

59h

5Ah

5Bh

5Ch

5Dh

5Eh

5Fh

60h

61h

62h

63h

64h

65h

66h

REF_GA_B3P

K_GA_R1M

K_GA_B1M

K_GA_R1P

K_GA_B1P

K_GA_R2M

K_GA_B2M

K_GA_R2P

K_GA_B2P

[7 : 0] Chrominance gain of B – Y positive direction when WB3 is fixed or auto-

controlled (present WBR factor ≤ WBR3).

[6 : 0] Chrominance gain slope of R – Y negative direction in WB auto control

(WBR1 < present WBR < WBR2)

[6 : 0] Chrominance gain slope of B – Y negative direction in WB auto control

(WBR1 < present WBR < WBR2)

[6 : 0] Chrominance gain slope of R – Y positive direction in WB auto control

(WBR1 < present WBR < WBR2)

[6 : 0] Chrominance gain slope of B – Y positive direction in WB auto control

(WBR1 < present WBR < WBR2)

[6 : 0] Chrominance gain slope of R – Y negative direction in WB auto control

(WBR2 < present WBR < WBR3)

[6 : 0] Chrominance gain slope of B – Y negative direction in WB auto control

(WBR2 < present WBR < WBR3)

[6 : 0] Chrominance gain slope of R – Y positive direction in WB auto control

(WBR2 < present WBR < WBR3)

[6 : 0] Chrominance gain slope of B – Y positive direction in WB auto control

(WBR2 < present WBR < WBR3)

REF_MAT_R1M [5 : 0] Matrix correction factor of R – Y negative direction when WB1 is fixed or

autocontrolled (present WBR factor ≤ WBR1).

REF_MAT_B1M [5 : 0] Matrix correction factor of B – Y negative direction when WB1 is fixed or

autocontrolled (present WBR factor ≤ WBR1).

REF_MAT_R1P [5 : 0] Matrix correction factor of R – Y positive direction when WB1 is fixed or

autocontrolled (present WBR factor ≤ WBR1).

REF_MAT_B1P [5 : 0] Matrix correction factor of B – Y positive direction when WB1 is fixed or

autocontrolled (present WBR factor ≤ WBR1).

REF_MAT_R2M [5 : 0] Matrix correction factor of R – Y negative direction when WB2 is fixed or

autocontrolled (present WBR factor = WBR2).

REF_MAT_B2M [5 : 0] Matrix correction factor of B – Y negative direction when WB2 is fixed or

autocontrolled (present WBR factor = WBR2).

REF_MAT_R2P [5 : 0] Matrix correction factor of R – Y positive direction when WB2 is fixed or

autocontrolled (present WBR factor = WBR2).

REF_MAT_B2P [5 : 0] Matrix correction factor of B – Y positive direction when WB2 is fixed or

autocontrolled (present WBR factor = WBR2).

REF_MAT_R3M [5 : 0] Matrix correction factor of R – Y negative direction when WB3 is fixed or

autocontrolled (present WBR factor = WBR3).

REF_MAT_B3M [5 : 0] Matrix correction factor of B – Y negative direction when WB3 is fixed or

autocontrolled (present WBR factor = WBR3).

REF_MAT_R3P [5 : 0] Matrix correction factor of R – Y positive direction when WB3 is fixed or

autocontrolled (present WBR factor = WBR3).

11

LR38603

ADDRESS

NAME

BIT

CONTENTS

67h

REF_MAT_B3P [5 : 0] Matrix correction factor of B – Y positive direction when WB3 is fixed or

autocontrolled (present WBR factor = WBR3).

68h

69h

6Ah

6Bh

6Ch

6Dh

6Eh

6Fh

70h

K_MAT_R1M

K_MAT_B1M

K_MAT_R1P

K_MAT_B1P

K_MAT_R2M

K_MAT_B2M

K_MAT_R2P

K_MAT_B2P

[7 : 0] Matrix correction slope factor of R – Y negative direction in WB auto control

(WBR1 < present WBR < WBR2)

[7 : 0] Matrix correction slope factor of B – Y negative direction in WB auto control

(WBR1 < present WBR < WBR2)

[7 : 0] Matrix correction slope factor of R – Y positive direction in WB auto control

(WBR1 < present WBR < WBR2)

[7 : 0] Matrix correction slope factor of B – Y positive direction in WB auto control

(WBR1 < present WBR < WBR2)

[7 : 0] Matrix correction slope factor of R – Y negative direction in WB auto control

(WBR2 < present WBR < WBR3)

[7 : 0] Matrix correction slope factor of B – Y negative direction in WB auto control

(WBR2 < present WBR < WBR3)

[7 : 0] Matrix correction slope factor of R – Y positive direction in WB auto control

(WBR2 < present WBR < WBR3)

[7 : 0] Matrix correction slope factor of B – Y positive direction in WB auto control

(WBR2 < present WBR < WBR3)

CKIL_OFF

COL_Y

[6] 1 : Color killer OFF

[5 : 0] Start point of luminance color suppression in maximum PGA gain.

[7 : 0] Start point of low luminance color suppression (PGA gain).

[5 : 0] Low luminance color suppression gain.

71h

72h

73h

74h

75h

COL_S

COL_H

CKI_HCL

CKI_LCL

CKI_HLGA

[7 : 0] Start level of high luminance color suppression.

[7 : 0] Start level of low luminance color suppression.

[7 : 4] High luminance color suppression gain.

[3 : 0] Low luminance color suppression gain.

76h

CKI_HLTI

[5 : 3] Timing adjustment of high luminance color suppression : –2 to +2

[2 : 0] Timing adjustment of low luminance color suppression : –2 to +2

[7 : 0] Start point of horizontal edge color suppression.

[7 : 0] Start point of vertical edge color suppression.

[7 : 4] Gain of horizontal edge color suppression.

77h

78h

79h

CKI_HECL

CKI_EVCL

CKI_EGA

[3 : 0] Gain of vertical edge color suppression.

NSUP_R

[7 : 4] R – Y signal low level suppression

7Ah

7Bh

NSUP_B

[3 : 0] B – Y signal low level suppression

LC_ON_YL

Y_GAM

[7] 1 : Execute measure against line crawl in processing luminance signal.

[6 : 4] Select characteristics of luminance gamma.

[3] Select characteristics of luminance LPF.

SEL_LPF_Y

Y_SEL

[2] Switch luminance signal processing 0 : Use only 1H 1 : 3-line process

[1] 1 : Vertical aperture is OFF

VAPT_OFF

HAPT_OFF

HAPT_SEL

[0] 1 : Horizontal aperture is OFF

[7] Switch characteristics of horizontal aperture.

0 : (–1 + Z1) (1 – Z2) 1 : (–1 + Z1) (1 – Z1)

7Ch

APT_HTIM

APT_HGA

[6 : 5] Timing of horizontal aperture : –1 to +1

[4 : 0] Initial value of APT_HGA (gain of horizontal edge signal)

12

LR38603

ADDRESS

7Dh

7Eh

NAME

APT_HCL

APT_VGA

APT_VCL

APT_S

BIT

CONTENTS

[6 : 0] Suppression level of horizontal edge signal.

[4 : 0] Initial value of APT_VGA (gain of vertical edge signal)

[6 : 0] Suppression level of vertical edge signal.

[7 : 0] Start point of edge signal suppression (PGA gain).

[5 : 0] Gain of edge signal suppression.

7Fh

80h

81h

APT_H

82h

APT_Y

[5 : 0] Start point of edge signal suppression in maximum PGA gained luminance.

[7 : 0] Luminance suppression point of high luminance aperture.

[6] Select level of edge signal, used in internal calculation. 1 : 1/4 times

[5 : 3] Delete timing of horizontal edge : –2 to +2

[2 : 0] Delete timing of vertical edge : –2 to +2

83h

CKI_HCL2

CKI_ETI

84h

85h

86h

87h

88h

LC_K1

LC_K2

LC_MAX

SETUP

[7 : 0] Difference of 0H, 2H signal allowed level, for judgment of line crawl.

[7 : 0] Difference of R, B signal allowed level, for judgment of line crawl.

[7 : 0] Judgment of luminance level, for judgment of line crawl.

[6] Switch CBLK level.

[5 : 0] Adjustment of setup level (complement of 2).

[7] Sign of burst level R – Y 1 : – direction 0 : + direction

[6 : 0] Burst level R – Y.

89h

8Ah

8Bh

BAS_R

BAS_B

OUTGA

[7] Sign of burst level B – Y 1 : – direction 0 : + direction

[6 : 0] Burst level B – Y (sign + absolute value).

[6] 1 : Mute in encoder.

[5] 1 : Stop adding SYNC to analog output.

[4 : 0] Gain of analog output (1 time at 10h).

8Ch

8Dh

SYNCLEV

[7 : 0] Adjustment of SYNC level.

MUTE_OUT

[7] 1 : Disable output mute at power-on.

[6 : 0] Period of mute (MUTE_OUT x 2 vertical period)

8Eh

SEL_FH

[7] Switch attribute of FH

[6] Switch attribute of FR

[5 : 3] ADCK phase adjustment

1 : Inverted

SEL_FR

SEL_ADCK

When using 270 k, 320 k-pixel CCDs 000 : standard to 101 : 300˚ (delayed

from "000" to "101" every 60˚.)

When using 410 k, 470 k-pixel CCDs 000 : standard to 101 : 270˚ (delayed

from "000" to "101" every 45˚.)

SEL_FS

[2 : 0] FS phase adjustment 000 : standard to 111 : 14 ns delay (delayed from

"000" to "111" every 2 ns.)

8Fh

90h

SEL_FH2

SEL_FCDS

SEL_RS

[7 : 6] FH2 phase adjustment

00 : standard 01 : 1 ns delay 10 : 2 ns delay 11 : 3 ns delay

[5 : 3] FCDS phase adjustment 000 : standard to 111 : 14 ns delay (delayed from

"000" to "111" every 2 ns.)

[2 : 0] RS phase adjustment 000 : standard to 111 : 14 ns delay (delayed from

"000" to "111" every 2 ns.)

STANDBY

[6] 1 : Standby

[5 : 0] Period of return from standby (STANDBY x vertical period)

13

LR38603

ADDRESS

NAME

KNEE

BIT

CONTENTS

91h

[7] 1 : Invert OBCP clock

[6] 1 : Invert DCK2

[5] 1 : Invert DCK1

INV_DCK2

INV_DCK1

BUSY_SEL

EI_ON_SEL

HRI_SEL

[4] 1 : Reset auto control factor, when EEPSL is at H.

[3] 1 : Enable KEI pulse function.

[2] 1 : Invert HRES (minus attribute)

[1] 1 : Invert VRES (minus attribute)

[0] Select vertical reset timing.

VRI_SEL

IN_VRES

0 : Reset at CSYNC pulse timing.

1 : Reset at VD pulse timing.

92h

93h

KEI_KEISU

ENCIN_PH

[7 : 0] Gain of PGA which produces KEI pulse.

[3] Latch encoder clock inverted.

[2] 1 : Enable DFF.

VARI_ENC

[1 : 0] Delay adjustment of addition of luminance and color modulation.

(Delay of color signal)

00 : 0 clock delay to 11 : 3 clocks delay (delayed from "00" to "11" every 1

clock .) 1 clock : Original clock

94h

ANA_VARI

[6 : 4] Delay adjustment of addition of luminance and color modulation.

(Delay of luminance signal)

101 : –3 clocks delay to 011 : 3 clocks delay (delayed from "101" to "011"

every 1 clock .)

1 clock : Pixel CK (complement of 2)

VARI_Y

[3 : 0] Timing adjustment of luminance processing.

1001 : –7 clocks delay to 0111 : 7 clocks delay (delayed from "1001" to

"0111" every 1 clock.) 1 clock : Pixel CK (complement of 2)

[7] Output 1/8 of original clock from DCK1.

[6] Test mode. Set 0 in normal operation.

(The LR38603 does not read EEPROM and registers are set by serial data.)

[5] Make D/A converter standby.

95h

BUNSYU8_SEL

TEST

STDBY

CHG_CKIL

CHG_WB

CHG_MTX

CHG_CCD4

HG_YL_SEL

REF_AW

REF_BW

REF_CW

REF_DW

REF_AB

[4] Swap R and B of color killer.

[3] Swap R and B of white balance.

[2] Swap R and B of matrix input.

[1] Swap U and V of digital output.

[0] Swap YL line selection for each R and B.

[7 : 0] Factor for white detect correction

96h

97h

98h

99h

9Ah

9Bh

9Ch

[7 : 0] Factor for white detect correction

[7 : 0] Factor for black detect correction

REF_BB

[7 : 0] Factor for black detect correction

REF_CB

[7 : 0] Factor for black detect correction

14

LR38603

ADDRESS

9Dh

NAME

REF_DB

BIT

CONTENTS

[7 : 0] Factor for black detect correction

9Eh

AWNC_SEL

APT_O_LIM

WN00H

[5 : 0] ON/OFF control signal for each condition.

9Fh

[7 : 0] Limiter of aperture output.

A0h

[7 : 0] Lower bits of horizontal coordinate 1 of white defect.

[7 : 0] Lower bits of vertical coordinate 1 of white defect.

[3 : 0] [3 : 2] Upper bits of vertical coordinate 1 of white defect.

[1 : 0] Upper bits of horizontal coordinate 1 of white defect.

[7 : 0] Lower bits of horizontal coordinate 2 of white defect.

[7 : 0] Lower bits of vertical coordinate 2 of white defect.

[3 : 0] [3 : 2] Upper bits of vertical coordinate 2 of white defect.

[1 : 0] Upper bits of horizontal coordinate 2 of white defect.

[7 : 0] Lower bits of horizontal coordinate 3 of white defect.

[7 : 0] Lower bits of vertical coordinate 3 of white defect.

[3 : 0] [3 : 2] Upper bits of vertical coordinate 3 of white defect.

[1 : 0] Upper bits of horizontal coordinate 3 of white defect.

[7 : 0] Lower bits of horizontal coordinate 4 of white defect.

[7 : 0] Lower bits of vertical coordinate 4 of white defect.

[3 : 0] [3 : 2] Upper bits of vertical coordinate 4 of white defect.

[1 : 0] Upper bits of horizontal coordinate 4 of white defect.

[7 : 0] Lower bits of horizontal coordinate 5 of white defect.

[7 : 0] Lower bits of vertical coordinate 5 of white defect.

[3 : 0] [3 : 2] Upper bits of vertical coordinate 5 of white defect.

[1 : 0] Upper bits of horizontal coordinate 5 of white defect.

[7 : 0] Lower bits of horizontal coordinate 6 of white defect.

[7 : 0] Lower bits of vertical coordinate 6 of white defect.

[3 : 0] [3 : 2] Upper bits of vertical coordinate 6 of white defect.

[1 : 0] Upper bits of horizontal coordinate 6 of white defect.

[7 : 0] Lower bits of horizontal coordinate 7 of white defect.

[7 : 0] Lower bits of vertical coordinate 7 of white defect.

[3 : 0] [3 : 2] Upper bits of vertical coordinate 7 of white defect.

[1 : 0] Upper bits of horizontal coordinate 7 of white defect.

[7 : 0] Lower bits of horizontal coordinate 8 of white defect.

[7 : 0] Lower bits of vertical coordinate 8 of white defect.

[3 : 0] [3 : 2] Upper bits of vertical coordinate 8 of white defect.

[1 : 0] Upper bits of horizontal coordinate 8 of white defect.

[7 : 0] Test address (Set 00h)

A1h

WN00V

A2h

WN00HV

A3h

A4h

A5h

WN01H

WN01V

WN01HV

A6h

A7h

A8h

WN02H

WN02V

WN02HV

A9h

AAh

ABh

WN03H

WN03V

WN03HV

ACh

ADh

AEh

WN04H

WN04V

WN04HV

AFh

B0h

B1h

WN05H

WN05V

WN05HV

B2h

B3h

B4h

WN06H

WN06V

WN06HV

B5h

B6h

B7h

WN07H

WN07V

WN07HV

C0h

C1h

C2h

C3h

C4h

C5h

TST_SEL31

TST_SEL32

TST_SEL33

TST_SEL1A

TST_SEL1B

TST_SEL1C

[7 : 0] Test address (Set 00h)

[0]

Test address (Set 00h)

[7 : 0] Test address (Set 00h)

15

LR38603

ADDRESS

C6h

NAME

BIT

CONTENTS

TST_SEL1D

TST_SEL1V1

TST_SEL1V2

TST_SEL1V3

TST_SEL1V4

TST_C2_OB3

TST_C2_OB4

TST_C2_DL1

TST_C2_DL2

TST_C2_YL

[1 : 0] Test address (Set 00h)

[7 : 0] Test address (Set 00h)

[6 : 0] Test address (Set 00h)

[7 : 0] Test address (Set 00h)

[5 : 0] Test address (Set 00h)

C7h

C8h

C9h

CAh

CBh

CCh

CDh

CEh

CFh

D0h

TST_C2_GAMMA1 [7 : 0] Test address (Set 00h)

TST_SSG_SEL [2] Test address (Set 00h)

TST_C2_GAMMA2 [1 : 0] Test address (Set 00h)

D1h

D2h

D3h

D4h

D5h

D6h

D7h

D8h

D9h

DAh

DBh

DCh

DDh

DEh

DFh

E0h

E1h

E2h

E3h

E4h

E5h

E6h

E7h

E8h

E9h

F0h

F1h

F2h

F3h

TST_C6_00

TST_C6_01

TST_C6_02

TST_C4_IO0

TST_C4_IO1

TST_C4_IO2

TST_C4_S0

TST_C4_S1

TST_C4_S2

TST_C5_T0

TST_C5_T1

TST_C5_T2

TST_SEL71

TST_SEL72

TEST_C8_00

TEST_C8_01

TEST_C8_02

TEST_C8_03

TEST_C8_04

TEST_C8_05

TEST_C8_06

TEST_C8_07

TEST_C8_08

TEST_C8_09

TST_REG1

TST_REG2

TST_REG3

TST_REG4

[7 : 0] Test address (Set 00h)

[6 : 0] Test address (Set 00h)

[7 : 0] Test address (Set 00h)

[4 : 0] Test address (Set 00h)

[7 : 0] Test address (Set 00h)

[0]

Test address (Set 00h)

[7 : 0] Test address (Set 00h)

[5 : 0] Test address (Set 00h)

[7 : 0] Test address (Set 00h)

[1 : 0] Test address (Set 00h)

[7 : 0] Test address (Set 00h)

[6 : 0] Test address (Set 00h)

[7 : 0] Test address (Set 00h)

16

LR38603

ADDRESS

F4h

NAME

TST_REG5

TST_REG6

TST_REG7

TST_REG8

TST_REG9

TST_REGA

TST_REGB

BIT

CONTENTS

[7 : 0] Test address (Set 00h)

[5 : 0] Test address (Set 00h)

[7 : 0] Test address (Set 00h)

F5h

F6h

F7h

F8h

F9h

FAh

FBh

FCh

FDh

FEh

TST_SEL_REG [5 : 0] Test address (Set 00h)

WT_DAT30

WT_DAT31

TST_C5_WT3

[7 : 0] Test address (Set 00h)

[6 : 0] Test address (Set 00h)

[5 : 0] Test address (Set 00h)

17

LR38603

ABSOLUTE MAXIMUM RATINGS

PARAMETER

SYMBOL

RATING

UNIT

V

Supply voltage

VDD

–0.3 to +4.3

Input voltage

VI

–0.3 to VDD + 0.3

–55 to +150

V

Output voltage

Storage temperature

VO

V

TSTG

˚C

RECOMMENDED OPERATING CONDITIONS

SYMBOL MIN.

PARAMETER

TYP. MAX. UNIT

Input voltage

VDD

TOPR

FCK

3.0

3.3

+25

28.6

3.6

V

Output voltage

Input clock

–20

+70

˚C

MHz

ELECTRICAL CHARACTERISTICS 1

(VDD = 3.3 V 10ꢀ, TA = –20 to +70˚C)

PARAMETER

Input "High" voltage

Input "Low" voltage

Input "High" voltage

Input "Low" voltage

Hysteresis voltage

Input "High" current

Input "Low" current

Input "High" current

Input "Low" current

Input "High" current

Input "Low" current

Input "High" current

Input "Low" current

Output "High" voltage

Output "Low" voltage

Output "High" voltage

Output "Low" voltage

Output "High" voltage

Output "Low" voltage

SYMBOL

CONDITIONS

MIN. TYP. MAX. UNIT NOTE

VIH

0.8VDD

0.2

V

1

2

VIL

0.2VDD

VIH

V

VIL

V

VHIS

V

|IIH1|

|IIL1|

|IIH2|

|IIL2|

|IIH3|

|IIL3|

|IIH4|

|IIL4|

VOH1

VOL1

VIN = VDD

VIN = 0 V

1.0

2.0

70

µA

V

3

4

5

6

7

8

9

VIN = VDD

VIN = 0 V

10

33

VIN = VDD

2.0

300

70

VIN = 0 V

40

10

100

33

VIN = VDD

VIN = 0 V

2.0

IOH = +4 mA

IOL = –4 mA

IOH = +12 mA

IOL = –12 mA

IOH = +2 mA

IOL = –3 mA

0.8VDD

0.2VDD

V

VOH3

VOL3

V

VOH4

VOL4

V

NOTES :

1.Applied to inputs/outputs (IO4MU, IO4MD) and inputs 6.Applied to input (ICD), input/output (IO4MD).

(IC, ICU, ICD, OSCI).

7.Applied to inputs/outputs (IO4MU, IO4MD), output

(OBF4M).

2.Applied to input (ICSU), input/output (IO4MSU).

3.Applied to input (IC, OSCI).

8.Applied to output (OBF12M).

9.Applied to output (OSCO).

4.Applied to inputs (ICU, ICSU), input/output (IO4MSU).

5.Applied to input/output (IO4MU).

18

LR38603

ELECTRICAL CHARACTERISTICS 2

(VDD = 3.3 10ꢀ, TA = –20 to +70˚C)

PARAMETER

SYMBOL

RES

EL

CONDITIONS

MIN.

TYP. MAX. UNIT NOTE

Resolution

9

Bit

LSB

mA

$

Error of linearity

VREF = 1.0 V

RREF = 4.8 k$

ROUT = 75 $

5.0

1.0

Error of differential linearity

Full scaled current

Output impedance

Reference voltage

Reference resistance

ED

1

IFS

13

75

ROUT

VREF

RREF

1.0

4.8

V

2

3

k$

NOTES :

1.Applied to pin (VIDEO).

2.Applied to pin R(VEF).

3.Applied to pin R(EIF).

19

LR38603

speed is held. And then PGA gain is controlled so

that the exposure control data will be less than the

data of CTLD_0 (Address 08h).

AUTOMATIC CAMERA FUNCTION

CONTROL

If the exposure control data are greater than the

data of CTLD_AGC (address 07h), exposure

control starts again.

Automatic Electronic Exposure Control

Electronic shutter speed is controlled so that the

exposure control data approach the data of

REF_IRIS1 (address 06h).

Electronic Shutter Speed Setting

Electronic shutter speeds below can be selected by

either hardware or coefficient data.

Under BLC mode, the data of REF_IRIS2 (address

09h) are available instead of REF_IRIS1.

If the exposure control data are less than the data

of CTLD_AGC (address 07h), an electronic shutter

ELECTRONIC SHUTTER SPEED

EEMDS

EEMD1

EEMD2

EEMD3

NTSC

PAL

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1/60 s

1/50 s

1/100 s

1/120 s

1/250 s

1/500 s

1/1 000 s

1/2 000 s

1/5 000 s

1/10 000 s

1/20 000 s

1/50 000 s

1/100 000 s

1/30 s

1/1 000 s

1/2 000 s

1/5 000 s

1/10 000 s

1/20 000 s

1/50 000 s

1/100 000 s

1/25 s

1/15 s

1/12.5 s

1/6.25 s

AUTO

1/7.5 s

AUTO

1

0

1

1/60 s to MAX_SH (address 05h) 1/50 s to MAX_SH (address 05h)

AUTO

1/60 s to 1/100 000 s

1/50 s to 1/100 000 s

A slower shutter speed of less than 1/60 s (1/50 s

of PAL) can make images whose interval is every

two fields, every four fields, etc.

Electronic exposure control data come from the

following equation using averaged luminance levels

of 64 areas in one image, made by DSP.

VD pulse is also converted to the same frequency

as the output image rate.

20

LR38603

Electronic exposure control data =

e Top level : The highest luminance data in one

image by averaging either 4 pixels

or 8 pixels in horizontal.

[{Weighted data 1 q x (64 – CW_E (address 13h))

+ Weighted data 2 w x CW_E}/64

x (256 – P_HEE (address 17h) – P_LEE (address 18h))

+ Top level e x P_HEE + Bottom level r x

P_LEE]/256

r Bottom level : The lowest luminance data in

one image by averaging either 4

pixels or 8 pixels in horizontal.

Y11

Y21

Y31

Y41

Y51

Y61

Y71

Y81

Y12

Y22

Y32

Y42

Y52

Y62

Y72

Y82

Y13

Y23

Y33

Y43

Y53

Y63

Y73

Y83

Y14

Y24

Y34

Y44

Y54

Y64

Y74

Y84

Y15

Y25

Y35

Y45

Y55

Y65

Y75

Y85

Y16

Y26

Y36

Y46

Y56

Y66

Y76

Y86

Y17

Y27

Y37

Y47

Y57

Y67

Y77

Y87

Y18

Y28

Y38

Y48

Y58

Y68

Y78

Y88

Auto White Balance Control

If white balance control data are less than the data

of AWB_IW_S and AWB_QW_S (address 40h),

then AWB stops.

If white balance control data are less than the data

of AWB_IW_L (address 3Eh) and AWB_QW_L

(address 3Fh) AWB is made active so that white

balance control data are less than the data of

AWB_IW_S and AWB_QW_S.

q Weighted data 1

This comes from the following equation weighting in

horizontal.

When the data are greater than AWB_IW_L and

AWB_QW_L, AWB will be active again.

Weighting factors are the data from UW_E1

(address 0Bh) to UW_E8 (address 12h).

White balance data come from the following

equation using averaged I and Q data of 16 areas

in one image.

Weighted data 1 =

{(Y11 + Y12 + π + Y18)/8 x UW_E1 (address 0Bh)

+ (Y21 + Y22 + π + Y28)/8 x UW_E2 (address 0Ch)

I11

I21

I31

I41

I12

I22

I32

I42

I13

I23

I33

I43

I14

I24

I34

I44

:

+ (Y81 + Y82 + π + Y88)/8 x UW_E8 (address

12h)}/256

The sum from UW_E1 to UW_E8 shall be 256.

Q11

Q21

Q31

Q41

Q12

Q22

Q32

Q42

Q13

Q23

Q33

Q43

Q14

Q24

Q34

Q44

w Weighted data 2

Weighting area can be set by the data of CWP_E

(address 14h), CWA_E (address 15h).

Weighting position can be set by the data of

CWP_E.

White balance data =

{Weighted data 3 q x (64 – CW_IQ (address 33h))

+ weighted data 4 w x CW_IQ}/64

Weighting area size can be set by the data of

CWA_E.

Weighted data come from averaged data in chosen

area.

21

LR38603

Setting target zone :

q Weighted data 3

AWB_IP_S (address 3Ah), AWB_IM_S (address 3Bh)

AWB_QP_S (address 3Ch), AWB_QM_S (address 3Dh)

I (or Q) data come from the following equation.

Weighted data 3 =

Auto Color Matrix and Level

Compensation

Color matrix compensation can be done by

R – Y = R – Y (Data1 x B – Y)

B – Y = B – Y (Data2 x R – Y)

{(I11 + I12 + I13 + I14)/4 + (I21 + I22 + I23 + I24)/4 +

+ (I31 + I32 + I33 + I34)/4 + (I41 + I42 + I43 +

I44)/4}/4

w Weighted data 4

Weighting area can be chosen by CWPA_IQ

Color level compensation can be done by

R – Y = R – Y x Data3

(address 34h).

Weighted data come from averaged data in chosen

area.

B – Y = B – Y x Data4

The above data come from the following equation

along the variation of color temperature.

e White balance area setting

The sum of I and Q can be regulated by the

luminance level and the color level.

MODE1 : Present WBR factor < WBR1

Setting available luminance level range :

High level :

MODE2 : WBR1 ≤ present WBR factor < WBR2

MODE3 : WBR2 ≤ present WBR factor < WBR3

MODE4 : WBR3 ≤ present WBR factor

AWB_HCL (address 2Eh) + [{K_CL (address 31h)

x H peak level + (256 – K_CL) x Exposure control

data}/256

–

REF_WBPK (address 30h)]

x

MODE1 and MODE_MAT (address 25h) = 0

Data1 = REF_MAT_R1M (address 5Ch)

Data2 = REF_MAT_B1M (address 5Dh)

Data3 = REF_GA_R1M (address 48h)

Data4 = REF_GA_B1M (address 49h)

K_WBCL (address 32h)

Low level :

AWB_LCL (address 2Fh) + [{K_CL (address 31h) x

H peak level + (256 – K_CL) x Exposure control

data}/256

–

REF_WBPK (address 30h)]

x

MODE1 and MODE_MAT = 1

K_WBCL (address 32h)

Data1 = REF_MAT_R1M (address 5Ch) : B – Y < 0

REF_MAT_R1P (address 5Eh) : B – Y ≥ 0

Data2 = REF_MAT_B1M (address 5Dh) : R – Y < 0

REF_MAT_B1P (address 5Fh) : R – Y ≥ 0

Data3 = REF_GA_R1M (address 48h) : R – Y < 0

REF_GA_R1P (address 4Ah) : R – Y ≥ 0

Data4 = REF_GA_B1M (address 49h) : B – Y < 0

REF_GA_B1P (address 4Bh) : B – Y ≥ 0

Setting target zone :

AWB_IP_L (address 36h), AWB_IM_L (address 37h)

AWB_QP_L (address 38h), AWB_QM_L (address 39h)

If white balance data are less than the data of

AWB_IW_S and AWB_QW_S (address 40h) the

target zone of auto white balance changes to the

zone by the data below.

22

LR38603

MODE2 and MODE_MAT = 0

MODE3 and MODE_MAT = 1

Data1 = REF_MAT_R1M + K_MAT_R1M (address

68h) x (WBR – WBR1)/32

Data1 = REF_MAT_R2M (address 60h) +

K_MAT_R2M (address 6Ch) x (WBR –

WBR1)/32 : B – Y < 0

Data2 = REF_MAT_B1M + K_MAT_B1M (address

69h) x (WBR – WBR1)/32

REF_MAT_R2P (address 62h) +

K_MAT_R2P (address 6Eh) x (WBR –

WBR1)/32 : B – Y ≥ 0

Data3 = REF_GA_R1M + K_GA_R1M (address

54h) x (WBR – WBR1)/32

Data4 = REF_GA_B1M + K_GA_B1M (address

55h) x (WBR – WBR1)/32

Data2 = REF_MAT_B2M (address 61h) +

K_MAT_B2M (address 6Dh) x (WBR –

WBR1)/32 : R – Y < 0

MODE2 and MODE_MAT = 1

REF_MAT_B2P (address 63h) +

K_MAT_B2P (address 6Fh) x (WBR –

WBR1)/32 : R – Y ≥ 0

Data1 = REF_MAT_R1M + K_MAT_R1M (address

68h) x (WBR – WBR1)/32 : B – Y < 0

REF_MAT_R1P + K_MAT_R1P (address

6Ah) x (WBR – WBR1)/32 : B – Y ≥ 0

Data2 = REF_MAT_B1M + K_MAT_B1M (address

69h) x (WBR – WBR1)/32 : R – Y < 0

REF_MAT_B1P + K_MAT_B1P (address

6Bh) x (WBR – WBR1)/32 : R – Y ≥ 0

Data3 = REF_GA_R1M + K_GA_R1M (address

54h) x (WBR – WBR1)/32 : R – Y < 0

REF_GA_R1P + K_GA_R1P (address

56h) x (WBR – WBR1)/32 : R – Y ≥ 0

Data4 = REF_GA_B1M + K_GA_B1M (address

55h) x (WBR – WBR1)/32 : B – Y < 0

REF_GA_B1P + K_GA_B1P (address

57h) x (WBR – WBR1)/32 : B – Y ≥ 0

Data3 = REF_GA_R2M (address 4Ch) +

K_GA_R2M (address 58h) x (WBR –

WBR1)/32 : R – Y < 0

REF_GA_R2P (address 4Eh) +

K_GA_R2P (address 5Ah) x (WBR –

WBR1)/32 : R – Y ≥ 0

Data4 = REF_GA_B2M (address 4Dh) +

K_GA_B2M (address 59h) x (WBR –

WBR1)/32 : B – Y < 0

REF_GA_B2P (address 4Fh) +

K_GA_B2P (address 5Bh) x (WBR –

WBR1)/32 : B – Y ≥ 0

MODE4 and MODE_MAT = 0

Data1 = REF_MAT_R3M (address 64h)

Data2 = REF_MAT_B3M (address 65h)

Data3 = REF_GA_R3M (address 50h)

Data4 = REF_GA_B3M (address 51h)

MODE3 and MODE_MAT = 0

Data1 = REF_MAT_R2M (address 60h) +

K_MAT_R2M (address 6Ch) x (WBR –

WBR1)/32

Data2 = REF_MAT_B2M (address 61h) +

K_MAT_B2M (address 6Dh) x (WBR –

WBR1)/32

MODE4 and MODE_MAT = 1

Data1 = REF_MAT_R3M (address 64h) : B – Y < 0

REF_MAT_R3P (address 66h) : B – Y ≥ 0

Data2 = REF_MAT_B3M (address 65h) : R – Y < 0

REF_MAT_B3P (address 67h) : R – Y ≥ 0

Data3 = REF_GA_R3M (address 50h) : R – Y < 0

REF_GA_R3P (address 52h) : R – Y ≥ 0

Data4 = REF_GA_B3M (address 51h) : B – Y < 0

REF_GA_B3P (address 53h) : B – Y ≥ 0

Data3 = REF_GA_R2M (address 4Ch) +

K_GA_R2M (address 58h) x (WBR –

WBR1)/32

Data4 = REF_GA_B2M (address 4Dh) +

K_GA_B2M (address 59h) x (WBR –

WBR1)/32

23

LR38603

Color Level Suppression Under Lower

Illumination

Working PGA gain can control both R – Y level

and B – Y level by the following equation.

R – Y (B – Y) level

= {32 – (working PGA gain – COL_S (address 71h))

x COL_H (address 72h)}/32

When (working PGA gain – COL_S (address 71h))

≤ 0, ( ) = 0.

Aperture Level Suppression Under

Lower Illumination

Working PGA gain can control both the horizontal

aperture level and the vertical aperture level by the

following equation.

Horizontal aperture level

= APT_HGA (address 7Ch) x {32 – (working PGA

gain – APT_S (address 80h)) x APT_H (address

81h)}/32

Vertical aperture level

= APT_VGA (address 7Eh) x {32 – (working PGA

gain – APT_S (address 80h)) x APT_H (address

81h)}/32

When (working PGA gain – APT_S (address 80h))

≤ 0 , ( ) = 0.

24

LR38603

Gamma Characteristic Option

• Luminance signal gamma option

Y_GAM (address 7Bh) can choose one output of

below 8 responses.

256

224

192

160

128

96

000

001

010

011

100

101

64

110

111

32

0

64

128 192 256 320 384 448 512 576 640 704 768 832 896 960 1 024

Input Level

• Color signal gamma option

C_GAM (address 24h) can choose one output from

8 responses below.

256

224

192

160

128

96

000

001

010

011

100

101

64

110

111

32

0

64

128 192 256 320 384 448 512 576 640 704 768 832 896 960 1 024

Input Level

25

LR38603

PACKAGE OUTLINES

80 LQFP (P-LQFP080-1212)

0.08

(Unit : mm)

M

0.05

0.125

TYP.

0.08

P-0.5

80-0.2

See Detail A

41

60

61

40

80

21

Detail A

1

20

0.125

0.15

1.0

0.64

MAX.

0.64

0.2

(1.0)

12.0

1.70

0.ꢀ

14.0

0.1

0.2

1.4

Seating plane

0-10˚

0.15

0.55

26


型号：	LR38603
厂家：	SHARP ELECTRIONIC COMPONENTS
描述：	Digital Signal Processor for Color CCD Cameras 数字信号处理器的彩色CCD摄像机数字信号处理器 CD 摄像机
文件：	总26页 (文件大小：160K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LR38603 [SHARP]

相关型号：

LR38616

LR38617

LR38620

LR38627

LR38630

LR38631

LR38637

LR3865

LR38653

LR3865G-15-S08--R

LR3865G-15-S08-X-R

LR3865G-15-SH2-R