S-24C01ADP-11-S [SII]
CMOS 2-WIRE SERIAL EEPROM; CMOS 2线串行EEPROM
| 型号： | S-24C01ADP-11-S |
| 厂家： | 
SEIKO INSTRUMENTS INC |
| 描述： | CMOS 2-WIRE SERIAL EEPROM |
| 文件： | 总23页 (文件大小：275K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Rev. 2.2_30
CMOS 2-WIRE SERIAL EEPROM
S-24C01A/02A/04A
The S-24C0XA is a series of 2-wired, low power 1K/2K/4K-bit EEPROMs
with a wide operating range. They are organized as 128-word × 8-bit,
256-word × 8-bit, and 512-word × 8-bit, respectively. Each is capable of
page write, and sequential read.
The time for byte write and page write is the same, i. e., 1 msec. (max.)
during operation at 5 V 10%.
Features
•Endurance:
•Data retention:
•Write protection:
•S-24C01A:
106 cycles/word
10 years
•Low power consumption
Standby: 1.0 µA Max. (VCC=5.5 V)
Operating: 0.4 mA Max. (VCC=5.5 V)
0.3 mA Max. (VCC=3.3 V)
S-24C02A, S-24C04A
1 kbits
•Wide operating voltage range
•S-24C02A:
2 kbits
Write:
Read:
2.5 to 5.5 V
1.8 to 5.5 V
•S-24C04A:
4 kbits
•Page write
8 bytes (S-24C01A, S-24C02A)
Package
y 8-pin DIP
(PKG drawing code : DP008-A,DP008-C)
(PKG drawing code : FJ008-D,FJ008-E)
y 8-pin SOP
Pin Assignment
8-pin SOP
8-pin DIP
Top view
Top view
8
7
6
5
VCC
TEST/WP
SCL
A0
A1
1
2
3
4
A0
1
2
3
4
8
7
6
5
VCC
TEST/WP
SCL
A1
A2
A2
GND
SDA
S-24C01AFJA-zz-uuw
S-24C02AFJA-zz-uuw
S-24C04AFJA-zz-uuw
GND
SDA
S-24C01ADPx-uu
S-24C02ADPx-uu
S-24C04ADPx-uu
* Lower-case letters x, uu, zz and w differ
depending on the packing form.
See Ordering Information and Dimensions.
Figure 1
Table 1
Pin Functions
Pin Number
Name
Function
DIP
SOP
1
1
2
3
4
5
6
* When in use, connect to
GND or Vcc.
A0
A1
A2
GND
SDA
SCL
Address input (no connection in the S-24C04A*)
Address input
2
3
Address input
4
Ground
5
Serial data input/output
Serial clock input
6
TEST pin (S-24C01A): Connected to GND.
WP (Write Protection) pin (S-24C02A, S-24C04A):
7
8
7
8
TEST/WP
VCC
*
*
Connected to Vcc:
Protection valid
Connected to GND: Protection invalid
Power supply
Seiko Instruments Inc.
1
CMOS 2-WIRE SERIAL EEPROM
S-24C01A/02A/04A
Rev. 2.2_30
Block Diagram
TEST/WP*
VCC
GND
Start/Stop
Detector
SCL
SDA
Serial Clock
Controller
High-Voltage Generator
LOAD
COMP
LOAD
Device Address
Comparator
Data Register
X
INC
A2
A1
A0
Decoder
EEPROM
R / W
Address
Counter
Selector
Y Decoder
Data Output
ACK Output
Controller
DIN
DOUT
*
S-24C02A or S-24C04A
Figure 2
Absolute Maximum Ratings
Table 2
Parameter
Symbol
Ratings
Unit
Power supply voltage
Input voltage
Output voltage
Storage temperature under bias
Storage temperature
VCC
VIN
VOUT
Tbias
Tstg
-0.3 to +7.0
-0.3 to VCC+0.3
-0.3 to VCC
-50 to +95
-65 to +150
V
V
V
°C
°C
2
Seiko Instruments Inc.
CMOS 2-WIRE SERIAL EEPROM
S-24C01A/02A/04A
Rev. 2.2_30
Recommended Operating Conditions
Table 3
Parameter
Symbol
VCC
Conditions
Min.
Typ.
Max.
Unit
Read Operation
Write Operation
VCC=2.5 to 5.5V
VCC=1.8 to 2.5V
VCC=2.5 to 5.5V
VCC=1.8 to 2.5V
1.8
2.5
—
—
—
—
—
—
5.5
5.5
V
V
V
V
V
V
Power supply voltage
0.7×VCC
0.8×VCC
0.0
VCC
High level input voltage
VIH
VCC
0.3×VCC
0.2×VCC
Low level input voltage
Operating temperature
VIL
0.0
—
-40
—
+85
°C
Topr
Pin Capacitance
Table 4
(Ta=25°C, f=1.0 MHz, VCC=5 V)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
Input capacitance
Input/output capacitance
CIN
CI / O
VIN=0 V (SCL, A0, A1, A2, WP)
VI / O=0 V (SDA)
—
—
—
—
10
10
pF
pF
Endurance
Table 5
Parameter
Endurance
Symbol
NW
Min.
106
Typ.
—
Max.
—
Unit
cycles/word
Seiko Instruments Inc.
3
CMOS 2-WIRED SERIAL EEPROM
S-24C01A/02A/04A
Rev. 2.2_30
DC Electrical Characteristics
Table 6
VCC=4.5 V to 5.5 V
VCC=2.5 to 4.5 V
VCC=1.8 to 2.5 V
Typ. Max.
Parameter
Symbol Conditions
Unit
Min.
Typ. Max. Min. Typ. Max. Min.
Current consumption
(READ)
Current consumption
(PROGRAM)
—
—
—
0.4
2.0
—
—
—
—
0.3
1.5
—
—
—
—
0.2
ICC1
ICC2
f=100 kHz
f=100 kHz
mA
mA
—
—
Table 7
VCC=4.5 V to 5.5 V
VCC=2.5 to 4.5 V
VCC=1.8 to 2.5 V
Parameter
Symbol
ISB
Conditions
Unit
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Standby current
consumption
VIN=VCC or GND
—
—
—
—
1.0
1.0
1.0
—
—
—
—
0.6
1.0
1.0
—
—
—
—
0.4
1.0
1.0
µA
µA
µA
Input leakage
current
VIN=GND to VCC
VOUT=GND to VCC
0.1
0.1
0.1
0.1
0.1
0.1
ILI
Output leakage
current
ILO
IOL=3.2 mA
IOL=1.5 mA
IOL=100 µA
—
—
—
—
—
—
0.4
0.3
0.1
—
—
—
—
—
—
0.4
0.3
0.1
—
—
—
—
—
—
—
0.5
0.1
V
V
V
Low level output
voltage
VOL
VAH
Current address
retention voltage
—
1.5
—
5.5
1.5
—
4.5
1.5
—
2.5
V
4
Seiko Instruments Inc.
CMOS 2-WIRE SERIAL EEPROM
S-24C01A/02A/04A
Rev. 2.2_30
AC Electrical Characteristics
VCC
Table 8 Measurement Conditions
R=1.0k
Input pulse voltage
0.1×VCC to 0.9×VCC
SDA
Input pulse rising/falling time
Output judgment voltage
Output load
20 ns
0.5×VCC
C=100pF
100 pF+ Pullup resistance 1.0 kΩ
Figure 3 Output Load Circuit
Table 9
VCC=1.8V to 5.5V
Parameter
Symbol
Unit
Min.
Typ.
Max.
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
100
—
—
3.5
—
—
—
—
—
—
1.0
0.3
—
100
SCL clock frequency
SCL clock time "L"
SCL clock time"H"
fSCL
tLOW
tHIGH
tAA
kHz
µs
µs
µs
µs
µs
µs
ns
ns
µs
µs
µs
µs
ns
4.7
4.0
0.3
0.3
4.7
4.0
50
SDA output delay time
SDA output hold time
Start condition setup time
Start condition hold time
Data input setup time
Data input hold time
Stop condition setup time
SCL · SDA rising time
SCL · SDA falling time
Bus release time
tDH
tSU.STA
tHD.STA
tSU.DAT
tHD.DAT
tSU.STO
tR
tF
tBUF
tI
0
4.7
—
—
4.7
—
Noise suppression time
tHIGH
tLOW
tR
tF
SCL
tHD.DAT
tSU.DAT
tSU.STA
tHD.STA
tSU.STO
SDA IN
tAA
tDH
tBUF
invalid
valid
SDA OUT
Figure 4 Bus Timing
Seiko Instruments Inc.
5
CMOS 2-WIRED SERIAL EEPROM
S-24C01A/02A/04A
Rev. 2.2_30
Table 10
VCC=4.5 to 5.5V
VCC=2.5 to 4.5V
Item
Symbol
tWR
Unit
ms
Min.
—
Typ.
0.8
Max.
1.0
Min.
—
Typ.
4.0
Max.
5.0
Write time
tWR
SCL
SDA
D0
Stop
condition
Start
Write data
condition
Acknowledge
Figure 5 Write Cycle
Pin Functions
1. Address Input Pins (A0, A1, and A2)
Connect pins A0, A1, and A2 to the GND or the VCC, respectively, to assign slave addresses. There are 8
different ways to assign slave addresses in the S-24C01A and S-24C02A through a combination of pins
A0, A1, and A2, and 4 ways to assign them in the S-24C04A through a combination of pins A1 and A2.
When the input slave address coincides with the slave address transmitted from the master device, 1
device can be selected from among multiple devices connected to the bus. Always connect the address
input pin to GND or VCC and leave it unchanged.
2. SDA (Serial Data Input/Output) Pin
The SDA pin is used for bilateral transmission of serial data. It consists of a signal input pin and an Nch
open-drain transistor output pin.
Usually pull up the SDA line via resistance to the VCC, and use it with other open-drain or open-collector
output devices connected in a wired OR configuration.
3. SCL (Serial Clock Input) Pin
The SCL pin is used for serial clock input. It is capable of processing signals at the rising and falling edges
of the SCL clock input signal. Make sure the rising time and falling time conform to the specifications.
4. TEST/WP Pin
The S-24C01A does not have a write protection (WP) function. The pin serves as a TEST pin and shoud
always be connect to the GND.
In the S-24C02A and S-24C04A, this pin is used for write protection. When there is no need for write
protection, connect the pin to the GND; when there is a need for write protection, connect the pin to the
Vcc.
6
Seiko Instruments Inc.
CMOS 2-WIRE SERIAL EEPROM
S-24C01A/02A/04A
Rev. 2.2_30
Operation
1. Start Condition
When the SCL line is "H," the SDA line changes from "H" to "L." This allows the device to go to the start
condition.
All operations begin from the start condition.
2. Stop Condition
When the SCL line is "H," the SDA line changes from "L" to "H." This allows the device to go to the stop
condition.
When the device receives the stop condition signal during a read sequence, the read operation is
interrupted, and the device goes to standby mode.
When the device receives the stop condition signal during write sequence, the retrieval of write data is
halted, and the EEPROM initiates rewrite.
tSU.STA
tHD.STA
tSU.STO
SCL
SDA
Start
Condition
Stop
Condition
Figure 6 Start/Stop Conditions
3. Data Transmission
Changing the SDA line while the SCL line is "L" allows the data to be transmitted. A start or stop condition
is recognized when the SDA line changes while the SCL line is "H."
tSU.DAT
tHD.DAT
SCL
SDA
Figure 7 Data Transmission Timing
Seiko Instruments Inc.
7
CMOS 2-WIRED SERIAL EEPROM
S-24C01A/02A/04A
Rev. 2.2_30
4. Acknowledgment
The unit of data transmission is 8 bits. By turning the SDA line "L," the slave device mounted on the
system bus which receives the data during the 9th clock cycle outputs the acknowledgment signal
verifying the data reception.
When the EEPROM is rewriting, the device does not output the acknowledgment signal.
SCL
(EEPROM Input)
1
8
9
SDA
(Master Output)
Acknow-
ledgment
Output
SDA
(EEPROM Output)
Start
Condition
tAA
tDH
Figure 8 Acknowledgment Output Timing
5. Device Addressing
To perform data communications, the master device mounted on the system outputs the start condition
signal to the slave device. Next, the master device outputs 7-bit length device address and a 1-bit length
read/write instruction code onto the SDA bus.
Upper 4 bits of the device address are called the "Device Code," and set to "1010." Successive 3 bits are called the
"Slave Address." It is used to select a device on the system bus, and compared to the predetermined address value
at the address input pin (A2, A1, or A0).
When the comparison results match, the slave device outputs the acknowledgment signal during the 9th clock
cycle.
Device Code
Slave Address
1
0
0
1
1
0
0
A2
A1
A1
A0
R/W
S-24C01A
S-24C02A
1
A2
A0
R/W
LSB
MSB
Slave
Page
Address
Address
Device Code
1
0
1
0
A2
A1
P0
R/W
LSB
S-24C04A
MSB
Figure 9 Device Address
In the S-24C04A, "A0" does not exist in the slave addresses. So, "A0" becomes "P0." "P0" is a page address bit and
is equivalent to an additional uppermost bit of the word address. Accordingly, when P0="0," the former half area
corresponding to 2 kbits (addresses from 000h to 0FFh) in the entire memory are selected; when P0="1," the latter
half area corresponding to 2 kbits (addresses from 100h to 1FFh) in all areas of the memory are selected.
8
Seiko Instruments Inc.
CMOS 2-WIRE SERIAL EEPROM
S-24C01A/02A/04A
Rev. 2.2_30
6. Write
6.1 Byte Write
When the EEPROM receives a 7-bit length device address and a 1-bit read/write instruction code
"0," following the start condition signal, it outputs the acknowledgment signal. Next, when the
EEPROM receives an 8-bit length word address, it outputs the acknowledgment signal.
After the EEPROM receives 8-bit write data and outputs the acknowledgment signal, it receives the
stop condition signal. Next, the EEPROM at the specified memory address starts to rewrite.
When the EEPROM is rewriting, all operations are prohibited and the acknowledgment signal is not
output.
W
R
I
S
T
A
R
T
S
T
O
P
T
E
DEVICE
WORD ADDRESS
DATA
ADDRES
SDA
1
0 1 0 A2A1 A0 0
W7W6W5W4W3W2W1W0 D7 D6 D5 D4 D3 D2 D1 D0
M
S
B
L
S
B
R
/
W
A
C
K
A
C
K
A
C
K
W7 is optional in the S-24C01A.
A0 is P0 in the S-24C04A.
ADR INC (ADDRESS INCREMENT)
Figure 10 Byte Write
6.2 Page Write
Up to 8 bytes per page can be written in the S-24C01A and S-24C02A.
Up to 16 bytes per page can be written in the S-24C04A.
Basic data transmission procedures are the same as those in the "Byte Write." However, when the
EEPROM receives 8-bit write data which corresponds to the page size, the page can be written.
When the EEPROM receives a 7-bit length device address and a 1-bit read/write instruction code
"0," following the start condition signal, it outputs the acknowledgment signal. When the EEPROM
receives an 8-bit length word address, it outputs the acknowledgment signal.
After the EEPROM receives 8-bit write data and outputs the acknowledgment signal, it receives 8-
bit write data corresponding to the next word address, and outputs the acknowledgment signal. The
EEPROM repeats reception of 8-bit write data and output of the acknowledgment signal in
succession. It is capable of receiving write data corresponding to the maximum page size.
When the EEPROM receives the stop condition signal, it starts to rewrite, corresponding to the size
of the page, on which write data, starting from the specified memory address, is received.
Seiko Instruments Inc.
9
CMOS 2-WIRED SERIAL EEPROM
S-24C01A/02A/04A
Rev. 2.2_30
W
R
I
S
T
A
R
T
S
T
O
T
E
DEVICE
P
DATA (n+1)
DATA (n+x)
WORD ADDRESS (n)
DATA (n)
ADDRES
1
0 1 0 A2 A1A0 0
W7W6W5W4W3W2W1W0 D7 D6 D5 D4 D3 D2 D1 D0
D7
D0
D7
D0
SDA LINE
M
S
B
L R A
A
C
K
A
C
K
A
C
K
A
C
K
S
B
/
C
K
W
W7 is optional in the S-24C01A.
A0 is P0 in the S-24C04A.
ADR INC
ADR INC
ADR INC
Figure 11 Page Write
In the S-24C01A or S-24C02A, the lower 3 bits of the word address are automatically incremented
each when the EEPROM receives 8-bit write data.
Even if the write data exceeds 8 bytes, the upper 5 bits at the word address remain unchanged, the
lower 3 bits are rolled over and overwritten.
In the S-24C04A, the lower 4 bits at the word address are automatically incremented each when the
EEPROM receives 8 bit write data.
Even when the write data exceeds 16 bytes, the upper 4 bits of the word address and page address
P0 remain unchanged, and the lower 4 bits are rolled over and overwritten.
6.3 Acknowledgment Polling
Acknowledgment polling is used to know when the rewriting of the EEPROM is finished.
After the EEPROM receives the stop condition signal and once it starts to rewrite, all operations are
prohibited. Also, the EEPROM cannot respond to the signal transmitted by the master device.
Accordingly, the master device transmits the start condition signal and the device address read/write
instruction code to the EEPROM (namely, the slave device) to detect the response of the slave
device. This allows users to know when the rewriting of the EEPROM is finished.
That is, if the slave device does not output the acknowledgment signal, it means that the EEPROM is
rewriting; when the slave device outputs the acknowledgment signal, you can know that rewriting
has been completed. It is recommended to use read instruction "1" for the read/write instruction
code transmitted by the master device.
6.4 Write Protection
The S-24C02A and the S-24C04A are capable of protecting the memory. When the WP pin is
connected to VCC, writing to 50% of the latter half of all memory area (080h to 0FFh in the S-24C02A;
100h to 1FFh in the S-24C04A) is prohibited. Even when writing is prohibited, since the controller
inside the IC is operating, the response to the signal transmitted by the master device is not available
during the time of writing (tWR).
When the WP pin is connected to GND, the write protection becomes invalid, and writing in all
memory area becomes available. However, when there is no need for using write protection, always
connect the WP pin to GND.
10
Seiko Instruments Inc.
CMOS 2-WIRE SERIAL EEPROM
S-24C01A/02A/04A
Rev. 2.2_30
7. Read
7.1 Current Address Read
The EEPROM is capable of storing the last accessed memory address during both writing and
reading. The memory address is stored as long as the power voltage is more than the retention
voltage VAH.
Accordingly, when the master device recognizes the position of the address pointer inside the
EEPROM, data can be read from the memory address of the current address pointer without
assigning a word address. This is called "Current Address Read."
"Current Address Read" is explained for when the address counter inside the EEPROM is an "n"
address.
When the EEPROM receives a 7-bit length device address and a 1-bit read/write instruction code
"1," following the start condition signal, it outputs the acknowledgment signal. However, in the S-
24C04A, page address P0 becomes invalid, and the memory address of the current address pointer
becomes valid.
Next, 8-bit length data at an "n" address is output from the EEPROM, in synchronization with the
SCL clock.
The address counter is incremented at the falling edge of the SCL clock by which the 8th bit of data
is output, and the address counter goes to address n+1.
The master device does not output the acknowledgment signal and transmits the stop condition
signal to finish reading.
NO ACK from
S
T
A
R
T
R
E
A
D
Master Device
S
T
O
P
DEVICE
ADDRESS
1
0 1 0 A2 A1 A0 1
SDA LINE
D7 D6 D5 D4 D3 D2 D1 D0
DATA
M
S
B
L R
A
C
K
S
B
/
W
ADR INC
(A0 is P0 in the S-24C04A)
Figure 12 Current Address Read
For recognition of the address pointer inside the EEPROM, take into consideration the following:
The memory address counter inside the EEPROM is automatically incremented for every falling
edge of the SCL clock by which the 8th bit of data is output during the time of reading. During the
time of writing, upper bits of the memory address (upper 5 bits of the word address in the S-24C01A
and S-24C02A; upper 4 bits of the word address and page address P0 in the S-24C04A) are left
unchanged and are not incremented.
Seiko Instruments Inc.
11
CMOS 2-WIRED SERIAL EEPROM
S-24C01A/02A/04A
Rev. 2.2_30
7.2 Random Read
Random read is a mode used when the data is read from arbitrary memory addresses.
To load a memory address into the address counter inside the EEPROM, first perform a dummy write
according to the following procedures:
When the EEPROM receives a 7-bit length device address and a 1-bit read/write instruction code "0,"
following the start condition signal, it outputs the acknowledgment signal.
Next, the EEPROM receives an 8-bit length word address and outputs the acknowledgment signal. Last,
the memory address is loaded into the address counter of the EEPROM.
the EEPROM receives the write data during byte or page writing. However, data reception is not
performed during dummy write.
The memory address is loaded into the memory address counter inside the EEPROM during dummy write.
After that, the master device can read the data starting from the arbitrary memory address by transmitting
a new start condition signal and performing the same operation as that in the "Current Read."
That is, when the EEPROM receives a 7-bit length device address and a 1-bit read/write instruction code
"1," following the start condition signal, it outputs the acknowledgment signal.
Next, 8-bit length data is output from the EEPROM, in synchronization with the SCL clock. The master
device does not output an acknowledgment signal and transmits the stop condition signal to finish reading.
NO ACK from
W
R
I
S
T
A
R
T
S
T
A
R
T
Master Device
R
E
A
D
S
T
T
E
DEVICE
DEVICE
O
P
WORD ADDRESS (n)
ADDRESS
ADDRESS
1
0
1
0
A2 A1 A0 0
W7W6W5W4W3W2W1W0
1
0
1
0
A2 A1 A0 1
D7 D6 D5 D4 D3 D2 D1 D0
DATA (n)
SDA LINE
M
S
B
L
S
B
R
/
W
A
C
K
A
C
K
A
C
K
ADR INC
DUMMY WRITE
W7 is optional in the S-24C01A.
A0 is P0 in the S-24C04A.
Figure 13 Random Read
12
Seiko Instruments Inc.
CMOS 2-WIRE SERIAL EEPROM
S-24C01A/02A/04A
Rev. 2.2_30
7.3 Sequential Read
When the EEPROM receives a 7-bit length device address and a 1-bit read/write instruction code "1" in
both current and random read operations, following the start condition signal, it outputs the
acknowledgment signal
When 8-bit length data is output from the EEPROM, in synchronization with the SCL clock, the memory
address counter inside the EEPROM is automatically incremented at the falling edge of the SCL clock, by
which the 8th data is output.
When the master device transmits the acknowledgment signal, the next memory address data is output.
When the master device transmits the acknowledgment signal, the memory address counter inside the
EEPROM is incremented and read data in succession. This is called "Sequential Read."
When the master device does not output an acknowledgement signal and transmits the stop condition
signal, the read operation is finished.
Data can be read in the "Sequential Read" mode in succession. When the memory address counter
reaches the last word address, it rolls over to the first memory address.
NO ACK from
Master Device
S
T
R
E
A
D
A
C
K
A
C
K
A
C
K
O
P
DEVICE
ADDRES
SDA LINE
1
D7
D0
D7
D0
D7
D0
D7
D0
R
/
W
A
C
K
DATA (n)
DATA (n+1)
DATA (n+2)
DATA (n+x)
ADR INC
ADR INC
ADR INC
ADR INC
Figure 14 Sequential Read
Seiko Instruments Inc.
13
CMOS 2-WIRED SERIAL EEPROM
S-24C01A/02A/04A
Rev. 2.2_30
8. Address Increment Timing
The address increment timing is as follows. See Figures 15 and 16. During reading operation, the memory
address counter is automatically incremented at the falling edge of the SCL clock (the 8th read data is
output).
During writing operation, the memory address counter is also automatically incremented at the falling
edge of the SCL clock when the 8th bit write data is fetched.
SCL
SDA
8
9
1
8
9
D7 Output
D0 Output
R / W=1
ACK Output
Address Increment
Figure 15 Address Increment Timing During Reading
SCL
SDA
8
9
1
8
9
R / W=0
ACK Output
D7 Input
D0 Input
ACK Output
Address Increment
Figure 16 Address Increment Timing During Writing
Purchase of I2C components of Seiko Instruments Inc. conveys a license under the Philips I2C
Patent Rights to use these components in an I2C system, provided that the system conforms to the
I2C Standard Specification as defined by Philips.
Please note that any product or system incorporating this IC may infringe upon the Philips I2C Bus
Patent Rights depending upon its configuration.
In the event that such product or system incorporating the I2C Bus infringes upon the Philips Patent
Rights, Seiko Instruments Inc. shall not bear any responsibility for any matters with regard to and
arising from such patent infringement.
14
Seiko Instruments Inc.
CMOS 2-WIRE SERIAL EEPROM
S-24C01A/02A/04A
Rev. 2.2_30
Ordering Information
S-24C0xA yyy - zz - uuw
P code (Distincion for package process)
None
S
1A
Endurance code
11
:
106 cycles
Taping specification
None for DIP and SOP in magazine
TB
Package code
Product name
DP
:
:
:
DIP
DIP
SOP
DPA
FJA
S-24C01A : 1k bits
S-24C02A : 2k bits
S-24C04A : 4k bits
Ordering names for DIP
Package/Tape/Reel
drawings
Endurance
Product name Package code
Taping specification
None
P code
code
DP
None
−1A
DP008-C
S-24C01A
S-24C02A
S-24C04A
DPA
None
−11
None
DP008-A
Note
The endurarance of S-24C0xADP-1A is 106 cycles, though the ordering name does not have the endurance code.
Ordering names for SOP
Package/Tape/Reel
drawings
Endurance
code
Product name Package code
Taping specification
P code
−TB
S-24C01A
S-24C02A
S-24C04A
FJA
FJA
FJA
−11
−11
−11
None
None
FJ008-D
(None for magazine)
FJ008-D
FJ008-D
FJ008-E
−TB
(None for magazine)
S
−TB
None
FJ008-D
(None for magazine)
Note
1) Package dimensions of SOPs whose package code is FJA are the same in the range of deviation.
2) Please contact an SII local office or a local representative for details.
Seiko Instruments Inc.
15
CMOS 2-WIRED SERIAL EEPROM
S-24C01A/02A/04A
Rev. 2.2_30
Characteristics
1. DC Characteristics
1.1 Current consumption (READ) ICC1
Ambient temperature Ta
—
1.2 Current consumption (READ) ICC1
Ambient temperature Ta
—
VCC=5.5 V
fscl=100 KHz
DATA=0101
200
VCC=3.3 V
fscl=100 KHz
DATA=0101
200
ICC1
(µA)
100
ICC1
(µA)
100
0
0
-40
0
85
-40
0
85
Ta (°C)
Ta (°C)
1.4 Current consumption (READ) ICC1
Power supply voltage VCC
—
1.3 Current consumption (READ) ICC1
Ambient temperature Ta
—
VCC=1.8 V
fscl=100 KHz
DATA=0101
40
Ta=25°C
fscl=100 KHz
DATA=0101
100
ICC1
ICC1
(µA)
20
(µA)
50
0
0
-40
0
85
2
3
4
5 6
7
Ta (°C)
VCC (V)
1.6 Current consumption (READ) ICC1
Clock frequency fscl
−
1.5 Current consumption (READ) ICC1
Power supply voltage VCC
—
Ta=25°C
VCC=5.0 V
Ta=25°C
fscl=400 KHz
DATA=0101
100
100
ICC1
(µA)
50
ICC1
(µA)
50
0
0
2
3
4
5 6
7
100K 200K 300K 400K
VCC (V)
fscl(Hz)
1.7 Current consumption (PROGRAM) ICC2
Ambient temperature Ta
−
1.8 Current consumption (PROGRAM) ICC2
Ambient temperature Ta
−
VCC=3.3 V
VCC=5.5 V
1.0
1.0
ICC2
ICC2
0.5
0
0.5
0
-40
0
85
-40
0
85
Ta (°C)
Ta (°C)
16
Seiko Instruments Inc.
CMOS 2-WIRE SERIAL EEPROM
S-24C01A/02A/04A
Rev. 2.2_30
1.9 Current consumption (PROGRAM) ICC2
Ambient temperature Ta
−
1.10 Current consumption (PROGRAM) ICC2
Power supply voltage VCC
−
VCC=2.5 V
Ta=25°C
1.0
1.0
ICC2
ICC2
0.5
0
0.5
0
-40
0
85
2
3
4
5 6
7
Ta (°C)
VCC (V)
1.11 Standby current consumption ISB —
Ambient temperature Ta
1.12 Input leakage current ILI −
Ambient temperature Ta
VCC=5.5 V
10-6
VCC=5.5 V
A0, A1, A2, SDA
10-7
SCL,TEST/WP=0V
1.0
ISB
10-8
ILI
10-9
10-10
10-11
(µA)
0.5
-40
0
85
0
-40
0
85
Ta (°C)
Ta (°C)
1.13 Input leakage current ILI −
1.14 Output leakage current ILO
Ambient temperature Ta
−
Ambient temperature Ta
VCC=5.5 V
VCC=5.5 V
SDA=0V
A0, A1, A2, SDA
SCL, TEST/WP=5.5V
1.0
1.0
ILI
ILO
(µA)
0.5
(µA)
0.5
0
0
-40
0
85
-40
85
0
Ta (°C)
Ta (°C)
1.15 Output leakage current ILO
Ambient temperature Ta
−
VCC=5.5 V
SDA=5.5 V
1.0
ILO
(µA)
0.5
0
-40
0
85
Ta (°C)
Seiko Instruments Inc.
17
CMOS 2-WIRED SERIAL EEPROM
S-24C01A/02A/04A
Rev. 2.2_30
1.16 Low level output voltage VOL −
1.17 Low level output voltage VOL −
Ambient temperature Ta
Ambient temperature Ta
VCC=1.8 V
VCC=4.5 V
IOL=100 µA
IOL=2.3 mA
0.3
0.03
VOL
VOL
0.2
0.02
0.1
0.01
-40
0
85
-40
0
85
Ta (°C)
Ta (°C)
1.18 Low level output current IOL −
1.19 Low level output current IOL −
Ambient temperature Ta
Ambient temperature Ta
VCC=1.8 V
VOL=0.1 V
VCC=4.5 V
VOL=0.45 V
1.0
20
IOL
IOL
0.5
0
10
0
-40
0
85
-40
0
85
Ta (°C)
Ta (°C)
1.20 High input inversion voltage VIH−
1.21 High input inversion voltage VIH−
Power supply voltageVCC
Ambient temperature Ta
Ta=25°C
VCC=5.0 V
A0, A1, A2, SDA
A0, A1, A2, SDA
SCL, TEST/WP
SCL, TEST/WP
3.0
3.0
VIH
2.0
VIH
2.0
(V)
1.0
(V)
1.0
0
0
1 2 3 4 5 6 7
-40
0
85
Ta (°C)
VCC (V)
1.22 Low input inversion voltage VIL −
1.23 Low input inversion voltage VIL −
Power supply voltageVCC
Ambient temperature Ta
Ta=5.0V
Ta=25°C
A0, A1, A2, SDA
A0, A1, A2, SDA
SCL, TEST/WP
3.0
SCL, TEST/WP
3.0
VIL
(V)
2.0
1.0
VIL
(V)
2.0
1.0
0
-40
0
85
Ta (°C)
0
1 2 3 4 5 6 7
VCC (V)
18
Seiko Instruments Inc.
CMOS 2-WIRE SERIAL EEPROM
S-24C01A/02A/04A
Rev. 2.2_30
2. AC Characteristics
2.2 Write time tWR
−
2.1
Maximum operating frequency fmax −
Power supply voltage VCC
Power supply voltage VCC
Ta=25°C
Ta=25°C
4
1M
fmax
tWR
3
2
(Hz)
(ms)
100K
10K
1
1
2
3
4
5 6
7
1
2
3
4
5
VCC (V)
VCC (V)
2.4 Write time tWR
−
2.3 Write time tWR
−
Ambient temperature Ta
Ambient temperature Ta
VCC=2.5 V
4
VCC=4.5 V
1.5
tWR
tWR
3
2
1.0
0.5
-40
0
85
-40
0
85
Ta (°C)
Ta (°C)
2.6 SDA output delay time tPD
Ambient temperature Ta
−
2.5 SDA output delay time tPD
Ambient temperature Ta
−
VCC=2.7 V
VCC=4.5 V
1.5
tPD
1.5
tPD
(µs)
(µs)
1.0
1.0
0.5
0.5
-40
0
85
-40
0
85
Ta (°C)
Ta (°C)
2.7 Data output delay time tPD
Ambient temperature Ta
−
VCC=1.8 V
3.0
tPD
(µs)
2.0
1.0
-40
0
85
Ta (°C)
Seiko Instruments Inc.
19
DP008-A
011129
n 8-Pin DIP
Unit:mm
lDimensions
9.3(9.6max)
8
5
1
4
7.62
1.5
1.0
+0.1
-0.05
0.3
2.54
0.5±0.1
0°~15°
No.:DP008-A-P-SD-1.0
n 8-Pin SOP
FJ008-D Rev.1.0 011129
l Dimensions
5.02±0.2
8
Unit : mm
5
1
4
0.20±0.05
0.4±0.05
1.27
No. : FJ008-A-P-SD-2.0
l Tape Specifications
l Reel Specifications
2000 pcs./reel
4.0±0.1(10-pitches : total 40.0±0.2)
2.0±0.05
0.3±0.05
60°
ø1.55±0.05
ø2.0±0.05
5°max.
2.1±0.1
8.0±0.1
2±0.5
6.7±0.1
Winding core
13.5±0.5
2±0.5
ø21±0.8
ø13±0.2
TB
8
5
1
4
Feed direction
No. : FJ008-D-C-SD-1.0
No. FJ008-D-R-SD-1 0
n 8-Pin SOP
FJ008-E 011204
l Dimensions
Unit : mm
5.02±0.2
5
8
4
1
0.20±0.05
1.27
0.4±0.05
No.: FJ008-A-P-SD-2.0
l Tape Specifications
l Reel Specifications
2000 pcs./reel
4.0±0.1(10 pitches : total 40.0±0.2)
2.0±0.05
+0.1
ø1.5-0.0
0.3±0.05
+1.0
-0.1
ø1.6
2.1±0.1
5°max.
8.0±0.1
Winding core
ø20.2min.
+0.6
-0.4
+0.5
-0.2
12.8
18.2
ø13
+0.6
-0.4
6.4±0.1
2±0.5
TB
8
5
1
4
No.: FJ008-E-R-SD-1.0
Feed direction
No.: FJ008-E-C-SD-1.0
·
·
The information described herein is subject to change without notice.
Seiko Instruments Inc. is not responsible for any problems caused by circuits or diagrams described herein
whose related industrial properties, patents, or other rights belong to third parties. The application circuit
examples explain typical applications of the products, and do not guarantee the success of any specific
mass-production design.
·
·
·
When the products described herein are regulated products subject to the Wassenaar Arrangement or other
agreements, they may not be exported without authorization from the appropriate governmental authority.
Use of the information described herein for other purposes and/or reproduction or copying without the
express permission of Seiko Instruments Inc. is strictly prohibited.
The products described herein cannot be used as part of any device or equipment affecting the human
body, such as exercise equipment, medical equipment, security systems, gas equipment, or any apparatus
installed in airplanes and other vehicles, without prior written permission of Seiko Instruments Inc.
Although Seiko Instruments Inc. exerts the greatest possible effort to ensure high quality and reliability, the
failure or malfunction of semiconductor products may occur. The user of these products should therefore
give thorough consideration to safety design, including redundancy, fire-prevention measures, and
malfunction prevention, to prevent any accidents, fires, or community damage that may ensue.
·
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