S-25A320A [SII]
125°C OPERATION SPI SERIAL E2PROM; 125 ° C SPI串行E2PROM
| 型号： | S-25A320A |
| 厂家： | 
SEIKO INSTRUMENTS INC |
| 描述： | 125°C OPERATION SPI SERIAL E2PROM |
| 文件： | 总31页 (文件大小：361K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Rev.1.0_00
125
°
C OPERATION SPI SERIAL E2PROM
S-25A080A/160A/320A
FOR AUTOMOTIVE ELECTRIC COMPONENT
The S-25A080A/160A/320A is a SPI serial E2PROM which
operates under the high temperature, at high speed, with low
current consumption and the wide range operation. The S-
25A080A/160A/320A respectively has the capacity of 8 Kbit,
16 Kbit, 32 Kbit and the organization of 1024 words × 8-bit,
2048 words × 8-bit, 4096 words × 8-bit, is able to Page Write
and sequential read.
Features
• Wide range operation
Read:
Write:
2.5 V to 5.5 V
2.5 V to 5.5 V
• Operation frequency
6.5 MHz (4.5 V to 5.5 V, at −40°C to +125°C)
• SPI mode (0, 0) and (1, 1)
• Page Write 32 bytes / page
• Sequential read
• Monitors Write to the memory by a status register
• Write protect:
• Protect area:
Software, Hardware
25%, 50%, 100%
• Write protect function during the low power supply
• Function to prevent malfunction by monitoring clock pulse
• CMOS schmitt input ( CS , SCK, SI, WP , HOLD )
• Endurance:
106cycles/word*1 (at +85°C)
8 × 105 cycles/word*1 (at +105°C)
5 × 105 cycles/word*1 (at +125°C)
*1. For each address (Word: 8-bit)
100 years (at +25°C), 50 years (at +125°C)
• Data retention:
• Memory capacitance:
S-25A080A
S-25A160A
S-25A320A
8 Kbit
16 Kbit
32 Kbit
• Data before shipment:
• Lead-free product
Memory array FFh, SRWD = 0, BP1 = 0, BP0 = 0
Package
Drawing code
Package name
Package
FJ008-A
Tape
FJ008-D
Reel
FJ008-D
8-Pin SOP (JEDEC)
Caution Before using the product in medical equipment or automobile equipment including car audio,
keyless entry and engine control unit, contact to SII is indispensable.
Seiko Instruments Inc.
1
125°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE ELECTRIC COMPONENT
Rev.1.0_00
S-25A080A/160A/320A
Pin Configuration
8-Pin SOP (JEDEC)
Top view
Table 1
Pin No.
1
Symbol
Description
CS
SO
1
2
8
7
VCC
CS *1
SO
Chip select input
2
3
4
5
6
7
8
Serial data output
Write protect input
Ground
Serial data input
Serial clock input
Hold input
Power supply
HOLD
WP *1
GND
SI*1
WP
3
4
6
5
SCK
SI
GND
SCK*1
Figure 1
HOLD *1
VCC
S-25A080A0A-J8T2GD
S-25A160A0A-J8T2GD
S-25A320A0A-J8T2GD
*1. All input pins have the CMOS structure. Do not set the input pins in
high impedance during operation.
Remark See Dimensions for details of the package drawings.
2
Seiko Instruments Inc.
125°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE ELECTRIC COMPONENT
Rev.1.0_00
S-25A080A/160A/320A
Block Diagram
Step-up Circuit
Page Latch
Voltage Detector
CS
SCK
SI
Clock Counter
Data Register
Memory
Cell
Array
Mode
Decoder
HOLD
WP
Status
Memory Cell Array
Y Decoder
Address Register
Status Register
Read Circuit
Output
Control
Circuit
SO
VCC
GND
Figure 2
Seiko Instruments Inc.
3
125°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE ELECTRIC COMPONENT
Rev.1.0_00
S-25A080A/160A/320A
Absolute Maximum Ratings
Table 2
Absolute Maximum Rating
Item
Power supply voltage
Input voltage
Symbol
VCC
VIN
Unit
V
V
−0.3 to +7.0
−0.3 to +7.0
Output voltage
Operation ambient temperature
Storage temperature
VOUT
Topr
Tstg
−0.3 to VCC + 0.3
−40 to +125
−65 to +150
V
°C
°C
Caution The absolute maximum ratings are rated values exceeding which the product could suffer
physical damage. These values must therefore not be exceeded under any conditions.
Recommended Operating Conditions
Table 3
Min.
2.5
2.5
Max.
5.5
5.5
CC + 1.0
0.3 × VCC
Item
Symbol
VCC
Condition
Read Operation
Write Operation
CC = 2.5 V to 5.5 V
CC = 2.5 V to 5.5 V
Unit
V
V
V
V
Power supply voltage
VIH
VIL
High level input voltage
Low level input voltage
V
V
0.7 × VCC
−0.3
V
Pin Capacitance
Table 4
(Ta = +25 °C, f = 1.0 MHz, VCC = 5 V)
Item
Symbol
CIN
COUT
Condition
Min.
−
Max.
8
10
Unit
pF
pF
Input capacitance
VIN = 0 V ( CS , SCK, SI, WP , HOLD )
VOUT = 0 V (SO)
Output capacitance
Endurance
Item
−
Table 5
Symbol
NW
Operation Ambient Temperature
Min.
Max.
－
Unit
−40°C to +85°C
−40°C to +105°C
−40°C to +125°C
106
cycles / word*1
cycles / word*1
cycles / word*1
8.0 × 105
5.0 × 105
Endurance
－
－
*1. For each address (Word: 8 bits)
Data Retention
Table 6
Operation Ambient Temperature
+25°C
Item
Symbol
Min.
100
50
Max.
－
Unit
year
year
－
Data retention
－
+125°C
4
Seiko Instruments Inc.
125°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE ELECTRIC COMPONENT
Rev.1.0_00
S-25A080A/160A/320A
DC Electrical Characteristics
Table 7
−40°C to +125°C
VCC = 2.5 V to 3.0 V VCC = 3.0 V to 4.5 V VCC = 4.5 V to 5.5 V
SCK = 3.5 MHz SCK = 5.0 MHz SCK = 6.5 MHz
Item
Symbol Condition
Unit
mA
f
f
f
Min.
Max.
Min.
Max.
Min.
Max.
No load at
SO pin
－
－
－
Current consumption (READ) ICC1
1.5
2.0
2.5
Table 8
−40°C to +125°C
VCC = 2.5 V to 3.0 V
SCK = 3.5 MHz
VCC = 3.0 V to 4.5 V
VCC = 4.5 V to 5.5 V
SCK = 6.5 MHz
Item
Symbol Condition
Unit
f
f
SCK = 5.0 MHz
f
Min.
Max.
Min.
Max.
Min.
Max.
No load at
SO pin
－
－
－
Current consumption (WRITE)
ICC2
2.0
2.5
3.0
mA
Table 9
−40°C to +85°C
+85°C to +125°C
Unit
Item
Condition
Symbol
VCC = 4.5 V to 5.5 V VCC = 2.5 V to 4.5 V VCC = 4.5 V to 5.5 V
VCC = 2.5 V to 4.5 V
Min.
Max.
2.0
Min.
Max.
Min.
Max.
Min.
Max.
CS = Vcc,
Standby
SO = Open
ISB
－
－
－
－
µA
current
3.0
8.0
10.0
Other inputs are
consumption
VCC or GND
Input leakage
current
Output leakage
current
Low level
output voltage VOL2
High level
output voltage VOH2
ILI
－
－
－
－
－
－
－
－
VIN = GND to VCC
µA
µA
1.0
1.0
1.0
1.0
2.0
2.0
2.0
2.0
ILO
VOUT = GND to VCC
VOL1
V
V
V
V
－
－
－
－
0.4
－
－
－
－
－
－
－
0.4
－
－
－
IOL = 2.0 mA
IOL = 1.5 mA
IOH = −2.0 mA
IOH = −0.4 mA
0.4
0.4
－
0.4
0.4
－
VOH1
0.8
0.8
×
×
VCC
VCC
0.8
0.8
×
×
VCC
VCC
－
－
－
－
0.8
×
VCC
0.8 × VCC
AC Electrical Characteristics
Table 10 Measurement Conditions
Input pulse voltage
Output reference voltage
Output load
0.2 × VCC to 0.8 × VCC
0.5 × VCC
100 pF
Seiko Instruments Inc.
5
125°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE ELECTRIC COMPONENT
Rev.1.0_00
S-25A080A/160A/320A
Table 11
−40°C to +125°C
Item
Symbol
Unit
VCC = 2.5 V to 5.5 V
VCC = 3.0 V to 5.5 V
VCC = 4.5 V to 5.5 V
Min.
Max.
Min.
Max.
Min.
Max.
SCK clock frequency
fSCK
−
3.5
−
5.0
−
6.5
MHz
ns
CS setup time during CS
falling
CS setup time during CS
rising
tCSS.CL
90
90
−
−
90
90
−
−
65
65
−
−
tCSS.CH
ns
tCDS
160
90
−
−
−
140
90
−
−
−
110
65
−
−
−
ns
ns
ns
ns
ns
µs
µs
ns
ns
CS deselect time
tCSH.CL
tCSH.CH
tHIGH
tLOW
tRSK
tFSK
tDS
CS hold time during CS falling
90
90
65
CS hold time during CS rising
SCK clock time “H” *1
SCK clock time “L” *1
125
125
−
−
20
30
−
−
1
1
−
−
95
95
−
−
20
30
−
−
1
1
−
−
65
65
−
−
20
30
−
−
1
1
−
−
Rising time of SCK clock *2
Falling time of SCK clock *2
SI data input setup time
SI data input hold time
SCK “L” hold time
tDH
tSKH.HH
tSKH.HL
tSKS.HL
tSKS.HH
70
40
0
−
−
−
−
70
40
0
−
−
−
−
45
30
0
−
−
−
−
ns
ns
ns
ns
during HOLD rising
SCL “L” hold time
during HOLD falling
SCK “L” setup time
during HOLD falling
SCK “L” setup time
during HOLD rising
0
0
0
Disable time of SO output *2
Delay time of SO output
Hold time of SO output
Rising time of SO output *2
Falling time of SO output *2
Disable time of SO output
during HOLD falling *2
Delay time of SO output
during HOLD rising *2
tOZ
tOD
tOH
tRO
tFO
−
−
0
−
−
100
120
−
80
80
−
−
0
−
−
100
90
−
80
80
−
−
0
−
−
75
60
−
50
50
ns
ns
ns
ns
ns
tOZ.HL
−
−
100
−
−
100
−
−
75
ns
tOD.HH
80
80
60
ns
tWS1
tWH1
tWS2
tWH2
0
0
0
−
−
−
−
0
0
0
−
−
−
−
0
0
0
−
−
−
−
ns
ns
ns
ns
WP setup time
WP hold time
WP release / setup time
WP release / hold time
150
150
100
*1. The clock cycle of the SCK clock (frequency fSCK) is 1/fSCK µs. This clock cycle is determined by a combination of
several AC characteristics. Note that the clock cycle cannot be set as (1/fSCK) = tLOW (Min.) + tHIGH (Min.) by minimizing
the SCK clock cycle time.
*2. These are values of sample and not 100% tested.
6
Seiko Instruments Inc.
125°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE ELECTRIC COMPONENT
Rev.1.0_00
S-25A080A/160A/320A
Table 12
−40°C to +105°C
Item
Symbol
Unit
VCC = 2.5 V to 5.5 V
VCC = 3.0 V to 5.5 V
VCC = 4.5 V to 5.5 V
Min.
Max.
Min.
Max.
Min.
Max.
SCK clock frequency
fSCK
−
3.5
−
5.0
−
6.5
MHz
ns
CS setup time during CS
falling
CS setup time during CS
rising
tCSS.CL
90
90
−
−
90
90
−
−
65
65
−
−
tCSS.CH
ns
tCDS
160
90
−
−
−
140
90
−
−
−
110
65
−
−
−
ns
ns
ns
ns
ns
µs
µs
ns
ns
CS deselect time
tCSH.CL
tCSH.CH
tHIGH
tLOW
tRSK
tFSK
tDS
CS hold time during CS falling
90
90
65
CS hold time during CS rising
SCK clock time “H” *1
SCK clock time “L” *1
125
125
−
−
20
30
−
−
1
1
−
−
95
95
−
−
20
30
−
−
1
1
−
−
65
65
−
−
20
30
−
−
1
1
−
−
Rising time of SCK clock *2
Falling time of SCK clock *2
SI data input setup time
SI data input hold time
SCK “L” hold time
tDH
tSKH.HH
tSKH.HL
tSKS.HL
tSKS.HH
70
40
0
−
−
−
−
70
40
0
−
−
−
−
45
30
0
−
−
−
−
ns
ns
ns
ns
during HOLD rising
SCL “L” hold time
during HOLD falling
SCK “L” setup time
during HOLD falling
SCK “L” setup time
during HOLD rising
0
0
0
Disable time of SO output *2
Delay time of SO output
Hold time of SO output
Rising time of SO output *2
Falling time of SO output *2
Disable time of SO output
during HOLD falling *2
Delay time of SO output
during HOLD rising *2
tOZ
tOD
tOH
tRO
tFO
−
−
0
−
−
100
120
−
80
80
−
−
0
−
−
100
90
−
70
70
−
−
0
−
−
75
60
−
50
50
ns
ns
ns
ns
ns
tOZ.HL
−
−
100
−
−
100
−
−
75
ns
tOD.HH
80
80
60
ns
tWS1
tWH1
tWS2
tWH2
0
0
0
−
−
−
−
0
0
0
−
−
−
−
0
0
0
−
−
−
−
ns
ns
ns
ns
WP setup time
WP hold time
WP release / setup time
WP release / hold time
150
150
100
*1. The clock cycle of the SCK clock (frequency fSCK) is 1/fSCK µs. This clock cycle is determined by a combination of
several AC characteristics. Note that the clock cycle cannot be set as (1/fSCK) = tLOW (Min.) + tHIGH (Min.) by minimizing
the SCK clock cycle time.
*2. These are values of sample and not 100% tested.
Seiko Instruments Inc.
7
125°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE ELECTRIC COMPONENT
Rev.1.0_00
S-25A080A/160A/320A
Table 13
−40°C to +85°C
Item
Symbol
Unit
VCC = 2.5 V to 5.5 V
VCC = 3.0 V to 5.5 V
VCC = 4.5 V to 5.5 V
Min.
Max.
Min.
Max.
Min.
Max.
SCK clock frequency
fSCK
−
4.0
−
5.0
−
7.0
MHz
ns
CS setup time during CS
falling
CS setup time during CS
rising
tCSS.CL
90
90
−
−
80
80
−
−
60
60
−
−
tCSS.CH
ns
tCDS
150
90
−
−
−
120
80
−
−
−
100
60
−
−
−
ns
ns
ns
ns
ns
µs
µs
ns
ns
CS deselect time
tCSH.CL
tCSH.CH
tHIGH
tLOW
tRSK
tFSK
tDS
CS hold time during CS falling
90
80
60
CS hold time during CS rising
SCK clock time “H” *1
SCK clock time “L” *1
115
115
−
−
20
30
−
−
1
1
−
−
90
90
−
−
20
30
−
−
1
1
−
−
60
60
−
−
20
30
−
−
1
1
−
−
Rising time of SCK clock *2
Falling time of SCK clock *2
SI data input setup time
SI data input hold time
SCK “L” hold time
tDH
tSKH.HH
tSKH.HL
tSKS.HL
tSKS.HH
70
40
0
−
−
−
−
60
40
0
−
−
−
−
40
30
0
−
−
−
−
ns
ns
ns
ns
during HOLD rising
SCL “L” hold time
during HOLD falling
SCK “L” setup time
during HOLD falling
SCK “L” setup time
during HOLD rising
0
0
0
Disable time of SO output *2
Delay time of SO output
Hold time of SO output
Rising time of SO output *2
Falling time of SO output *2
Disable time of SO output
during HOLD falling *2
Delay time of SO output
during HOLD rising *2
tOZ
tOD
tOH
tRO
tFO
−
−
0
−
−
100
110
−
80
80
−
−
0
−
−
100
85
−
50
50
−
−
0
−
−
70
55
−
40
40
ns
ns
ns
ns
ns
−
−
−
−
tOZ.HL
−
−
100
100
70
ns
tOD.HH
80
75
55
ns
tWS1
tWH1
tWS2
tWH2
0
0
0
−
−
−
−
0
0
0
−
−
−
−
0
0
0
−
−
−
−
ns
ns
ns
ns
WP setup time
WP hold time
WP release / setup time
WP release / hold time
150
150
100
*1. The clock cycle of the SCK clock (frequency fSCK) is 1/fSCK µs. This clock cycle is determined by a combination of
several AC characteristics. Note that the clock cycle cannot be set as (1/fSCK) = tLOW (Min.) + tHIGH (Min.) by minimizing
the SCK clock cycle time.
*2. These are values of sample and not 100% tested.
8
Seiko Instruments Inc.
125°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE ELECTRIC COMPONENT
Rev.1.0_00
S-25A080A/160A/320A
Table 14
Symbol
tPR
−40°C to +125°C
VCC = 2.5 V to 5.5 V
Item
Write time
Unit
ms
Min.
−
Max.
4.0
tCDS
CS
SCK
SI
t
CSH.CL
t
CSS.CH
t
CSS.CL
t
CSH.CH
t
DS
t
DH
t
RSK
t
FSK
MSB IN
LSB IN
High-Z
SO
Figure 3 Serial Input Timing
CS
SCK
SI
t
SKS.HL
t
SKH.HL
t
SKH.HH
t
SKS.HH
tOZ.HL
t
OD.HH
SO
HOLD
Figure 4 Hold Timing
Seiko Instruments Inc.
9
125°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE ELECTRIC COMPONENT
Rev.1.0_00
S-25A080A/160A/320A
tSCK
CS
tOZ
tHIGH
SCK
tLOW
ADDR
LSB IN
SI
t
OD
tOD
t
OH
t
OH
SO
LSB OUT
t
t
RO
FO
Figure 5 Serial Output Timing
t
WS1
tWH1
CS
WP
Figure 6 Valid Timing in Write Protect
t
WS2
tWH2
CS
WP
Figure 7 Invalid Timing in Write Protect
10
Seiko Instruments Inc.
125°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE ELECTRIC COMPONENT
Rev.1.0_00
S-25A080A/160A/320A
Pin Function
1. CS (Chip select input) Pin
This is an input pin to set a chip in the select status. In the “H” input level, the device is in the non-select status and its
output is high impedance. The device is in standby as long as it is not in Write inside. The device goes in active by
setting the chip select to “L”. Input any instruction code after power-on and a falling of chip select.
2. SI (Serial data input) pin
This pin is to input serial data. This pin receives an instruction code, an address and Write data. This pin latches data
at rising edge of serial clock.
3. SO (Serial data output) pin
This pin is to output serial data. The data output changes at falling edge of serial clock.
4. SCK (Serial clock input) pin
This is a clock input pin to set the timing of serial data. An instruction code, an address and Write data are received at
a rising edge of clock. Data is output at falling edge of clock.
5. WP (Write protect input) pin
Write protect is purposed to protect the area size against the Write instruction (BP1, BP0 in the status register). Fix
this pin “H” or “L” not to set it in the floating state.
Refer to “ Protect Operation” for details.
6. HOLD (HOLD input) pin
This pin is used to pause serial communications without setting the device in the non-select status.
In the hold status, the serial output goes in high impedance, the serial input and the serial clock go in “Don’t care”.
During the hold operation, be sure to set the device in active by setting the chip select ( CS pin) to “L”.
Refer to “ Hold Operation” for details.
Seiko Instruments Inc.
11
125°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE ELECTRIC COMPONENT
Rev.1.0_00
S-25A080A/160A/320A
Instruction Setting
Table 15 is the list of instruction for the S-25A080A/160A/320A. The instruction is able to be input by changing the CS
pin “H” to “L”. Input the instruction in the MSB first. Each instruction code is organized with 1-byte as shown below. If the
S-25A080A/160A/320A receives any invalid instruction code, the device goes in the non-select status.
Table 15
Instruction code
Address
SCK input clock
Data
Instruction
Operation
Write enable
SCK input clock
SCK input clock
17 to 24
SCK input clock
1 to 8
9 to 16
−
25 to 32
WREN
WRDI
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
−
−
−
−
−
−
−
−
Write disable
−
RDSR
WRSR
READ
WRITE
Read the status register
Write in the status register
Read memory data
Write memory data
b7 to b0 output *1
b7 to b0 input
A15 to A8 *2
A15 to A8 *2
A7 to A0
A7 to A0
D7 to D0 output *3
D7 to D0 input
*1. Sequential data reading is possible.
*2. In the S-25A080A, the higher addresses A15 to A10 = Don’t care.
In the S-25A160A, the higher addresses A15 to A11 = Don’t care.
In the S-25A320A, the higher addresses A15 to A12 = Don’t care.
*3. After outputting data in the specified address, data in the following address is output.
12
Seiko Instruments Inc.
125°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE ELECTRIC COMPONENT
Rev.1.0_00
S-25A080A/160A/320A
Operation
1. Status register
The status register’s organization is below. The status register can Write and Read by a specific instruction.
b7
b6
0
b5
0
b4
0
b3
b2
b1
b0
SRWD
BP1
BP0
WEL
WIP
Status Register Write Disable
Block Protect Bits
Write Enable Latch
Write In Progress
Figure 8 Organization of Status Register
The status/control bits of the status register are as follows.
1. 1 SRWD (b7) : Status Register Write Disable
Bit SRWD operates in conjunction with the Write protect signal ( WP ). With a combination of bit SRWD and signal
WP (SRWD = “1”, WP = “L”), this device goes in Hardware Protect status. In this case, the bits composed of the
nonvolatile bit in the status register (SRWD, BP1, BP0) go in Read Only, so that the WRSR instruction is not be
performed.
1. 2 BP1, BP0 (b3, b2) : Block Protect
Bit BP1 and BP0 are composed of the nonvolatile bit. The area size of Software Protect against WRITE instruction
is defined by them. Rewriting these bits is possible by the WRSR instruction. To protect the memory area against
the WRITE instruction, set either or both of bit BP1 and BP0 to “1”. Rewriting bit BP1 and BP0 is possible unless
they are in Hardware Protect mode. Refer to “ Protect Operation” for details of “Block Protect”.
1. 3 WEL (b1) : Write Enable Latch
Bit WEL shows the status of internal Write Enable Latch. Bit WEL is set by the WREN instruction only. If bit WEL is
“1”, this is the status that Write Enable Latch is set. If bit WEL is “0”, Write Enable Latch is in reset, so that the S-
25A080A/160A/320A does not receive the WRITE or WRSR instruction. Bit WEL is reset after these operations;
• The power supply voltage is dropping
• Power-on
• After performing WRDI
• After the Write operation by the WRSR instruction
• After the Write operation by the WRITE instruction
Seiko Instruments Inc.
13
125°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE ELECTRIC COMPONENT
Rev.1.0_00
S-25A080A/160A/320A
1. 4 WIP (b0) : Write In Progress
Bit WIP is Read Only and shows whether the internal memory is in the Write operation or not by the WRITE or
WRSR instruction. Bit WIP is “1” during the Write operation but “0” during any other status. Figure 9 shows the
usage example.
CS
WRITE or WRSR instruction
RDSR instruction
RDSR
RDSR instruction
RDSR
RDSR instruction
RDSR
D2 D1 D0
SI
S
S
S
B B
B B
B B
R
R
R
P P
1 0
P P
1 0
P P
1 0
W
D
W
D
W
D
SO
000
WEL, WIP
11
000
WEL, WIP
11
000
WEL, WIP
00
tPR
Figure 9 Usage Example of WEL, WIP Bits during Write
14
Seiko Instruments Inc.
125°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE ELECTRIC COMPONENT
Rev.1.0_00
S-25A080A/160A/320A
2. Write enable (WREN)
Before writing data (WRITE and WRSR), be sure to set bit Write Enable Latch (WEL). This instruction is to set bit
WEL. Its operation is below.
After selecting the device by the chip select ( CS ), input the instruction code from serial data input (SI). To set bit WEL,
set the device in the non-select status by CS at the 8th clock of the serial clock (SCK). To cancel the WREN
instruction, input the clock different from a specified value (n = 8 clock) while CS is in “L”.
CS
WP
SCK
SI
High / Low
1
2
3
4
5
6
7
8
Instruction
High-Z
SO
Figure 10 WREN Operation
Seiko Instruments Inc.
15
125°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE ELECTRIC COMPONENT
Rev.1.0_00
S-25A080A/160A/320A
3. Write disable (WRDI)
The WRDI instruction is one of ways to reset bit Write Enable Latch (WEL). After selecting the device by the chip select
( CS ), input the instruction code from serial data input (SI).
To reset bit WEL, set the device in the non-select status by CS at the 8th clock of the serial clock. To cancel the WRDI
instruction, input the clock different from a specified value (n = 8 clock) while CS is in “L”. Bit WEL is reset after the
operations shown below.
• The power supply voltage is dropping
• Power-on
• After performing WRDI
• After the completion of Write operation by the WRSR instruction
• After the completion of Write operation by the WRITE instruction
CS
WP
SCK
SI
High / Low
1
2
3
4
5
6
7
8
Instruction
High-Z
SO
Figure 11 WRDI Operation
16
Seiko Instruments Inc.
125°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE ELECTRIC COMPONENT
Rev.1.0_00
S-25A080A/160A/320A
4. Read the status register (RDSR)
Reading data in the status register is possible by the RDSR instruction. During the Write operation, it is possible to
confirm the progress by checking bit WIP.
Set the chip select ( CS ) “L” first. After that, input the instruction code from serial data input (SI). The status of bit in the
status register is output from serial data output (SO). Sequential Read is available for the status register. To stop the
Read cycle, set CS to “H”.
It is possible to read the status register always. The bits in it are valid and can be read by RDSR even in the Write
cycle.
However, during the Write cycle in progress, the nonvolatile bits SRWD, BP1, BP0 are fixed in a certain value. These
updated values of bit can be obtained by inputting another new RDSR instruction after the Write cycle has completed.
Contrarily, two of Read Only bits WEL and WIP are being updated while the Write cycle is in progress.
CS
WP
SCK
SI
High / Low
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Instruction
Outputs Data in the Status Register
b6 b5 b4 b3 b2 b1 b0
High-Z
SO
b7
b7
Figure 12 RDSR Operation
Seiko Instruments Inc.
17
125°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE ELECTRIC COMPONENT
Rev.1.0_00
S-25A080A/160A/320A
5. Write in the status register (WRSR)
The values of status register (SRWD, BP1, BP0) can be rewritten by inputting the WRSR instruction. But b6, b5, b4,
b1, b0 of status register cannot be rewritten. b6 to b4 are always “0” when reading the status register.
Before inputting the WRSR instruction, set bit WEL by the WREN instruction. The operation of WRSR is shown below.
Set the chip select ( CS ) “L” first. After that, input the instruction code and data from serial data input (SI). To start
WRSR Write (tPR), set the chip select ( CS ) to “H” after inputting data or before inputting a rising of the next serial
clock. It is possible to confirm the operation status by reading the value of bit WIP during WRSR Write. Bit WIP is “1”
during Write, “0” during any other status. Bit WEL is reset when Write is completed.
With the WRSR instruction, the values of BP1 and BP0; which determine the area size the users can handle as the
Read Only memory; can be changed. Besides bit SRWD can be set or reset by the WRSR instruction depending on
the status of Write protect WP . With a combination of bit SRWD and Write protect WP , the device can be set in
Hardware Protect mode (HPM). In this case, the WRSR instruction is not be performed (Refer to “ Protect
Operation”).
Bit SRWD and BP1, BP0 keep the value which is the one prior to the WRSR instruction during the WRSR instruction.
The newly updated value is changed when the WRSR instruction has completed.
To cancel the WRSR instruction, input the clock different from a specified value (n = 16 clock) while CS is in “L”.
CS
WP
SCK
SI
High / Low
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Instruction
Inputs Data in the Status Register
b6 b5 b4 b3 b2 b1 b0
b7
High-Z
SO
Figure 13 WRSR Operation
18
Seiko Instruments Inc.
125°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE ELECTRIC COMPONENT
Rev.1.0_00
S-25A080A/160A/320A
6. Read memory data (READ)
The Read operation is shown below. Input the instruction code and the address from serial data input (SI) after
inputting “L” to the chip select ( CS ). The input address is loaded to the internal address counter, and data in the
address is output from the serial data output (SO).
Next, by inputting the serial clock (SCK) keeping the chip select ( CS ) in “L”, the address is automatically incremented
so that data in the following address is sequentially output. The address counter rolls over to the first address by
increment in the last address.
To finish the Read cycle, set CS to “H”. It is possible to raise the chip select always during the cycle. During Write, the
Read instruction code is not be accepted or operated.
CS
WP
SCK
SI
High / Low
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Instruction
16-bit Address
A15 A14 A13
A3 A2 A1 A0
Outputs
the Second
Outputs the First Byte
High-Z
SO
D7 D6 D5 D4 D3 D2 D1 D0 D7
Remark In the S-25A080A, the higher addresses A15 to A10 = Don’t care.
In the S-25A160A, the higher addresses A15 to A11 = Don’t care.
In the S-25A320A, the higher addresses A15 to A12 = Don’t care.
Figure 14 Read Operation
Seiko Instruments Inc.
19
125°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE ELECTRIC COMPONENT
Rev.1.0_00
S-25A080A/160A/320A
7. Write memory data (Write)
Figure 15 shows the timing chart when inputting 1-byte data. Input the instruction code, the address and data from
serial data input (SI) after inputting “L” to the chip select ( CS ). To start Write (tPR), set the chip select ( CS ) to “H” after
inputting data or before inputting a rising of the next serial clock. Bit WIP and WEL are reset to “0” when Write has
completed.
The S-25A080A/160A/320A can Page Write of 32 bytes. Its function to transmit data is as same as Byte Write
basically, but it operates Page Write by receiving sequential 8-bit Write data as much data as page size has. Input the
instruction code, the address and data from serial data input (SI) after inputting “L” in CS , as the Write operation
(page) shown in Figure 15. Input the next data while keeping CS in “L”. After that, repeat inputting data of 8-bit
sequentially. At the end, by setting CS to “H”, the Write operation starts (tPR).
5 of the lower bits in the address are automatically incremented every time when receiving Write data of 8-bit. Thus,
even if Write data exceeds 32 bytes, the higher bits in the address do not change. And 5 of lower bits in the address
roll over so that Write data which is previously input is overwritten.
These are cases when the Write instruction is not accepted or operated.
• Bit WEL is not set to “1” (not set to “1” beforehand immediately before the Write instruction)
• During Write
• The address to be written is in the protect area by BP1 and BP0.
To cancel the Write instruction, input the clock different from a specified value (n = 24+m × 8 clock) while CS is in “L”.
CS
WP
SCK
SI
High / Low
1
2
3
4
5
6
7
8
9
10
11
21
22
23
24
25
26
27
28
29
30
31
32
Instruction
16-bit Address
Data Byte 1
A15 A14 A13
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
High-Z
SO
Remark In the S-25A080A, the higher addresses A15 to A10 = Don’t care.
In the S-25A160A, the higher addresses A15 to A11 = Don’t care.
In the S-25A320A, the higher addresses A15 to A12 = Don’t care.
Figure 15 Write Operation (1 byte)
20
Seiko Instruments Inc.
125°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE ELECTRIC COMPONENT
Rev.1.0_00
S-25A080A/160A/320A
CS
WP
High / Low
1
2
3
4
5
6
7
8
9
10 11
22 23 24 25 26 27 28 29 30 31 32
SCK
Instruction
16-bit Address (n)
Data Byte (n)
Data Byte (n + x)
SI
A15 A14 A13
A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
D4 D3 D2 D1 D0
High-Z
SO
Remark In the S-25A080A, the higher addresses A15 to A10 = Don’t care.
In the S-25A160A, the higher addresses A15 to A11 = Don’t care.
In the S-25A320A, the higher addresses A15 to A12 = Don’t care.
Figure 16 Write Operation (Page)
Seiko Instruments Inc.
21
125°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE ELECTRIC COMPONENT
Rev.1.0_00
S-25A080A/160A/320A
Protect Operation
Table 16 shows the block settings of Write protect. Table 17 shows the protect operation for the device. As long as bit
SRWD, the Status Register Write Disable bit, in the status register is reset to “0” (it is in reset before the shipment), the
value of status register can be changed.
These are two statuses when bit SRWD is set to “1”.
• Write in the status register is possible; Write protect ( WP ) is in “H”.
• Write in the status register is impossible; Write protect ( WP ) is in “L”. Therefore the Write protect area which is set by
protect bit (BP1, BP0) in the status register cannot be changed.
These operations are to set Hardware Protect (HPM).
• After setting bit SRWD, set Write protect ( WP ) to “L”.
• Set bit SRWD completed setting Write protect ( WP ) to “L”.
Figure 6 and 7 show the Valid timing in Write protect and Invalid timing in Write protect during the cycle Write to the
status register.
By inputting “H” to Write protect ( WP ), Hardware Protect (HPM) is released. If the Write protect ( WP ) is “H”, Hardware
Protect (HPM) does not function, Software Protect (SPM) which is set by the protect bits in the status register (BP1,
BP0) only works.
Table 16 The Block Settings of Write Protect
Status register
Address of Write protect block
S-25A080A
The area of Write protect
BP1
BP0
0
S-25A160A
None
600h-7FFh
400h-7FFh
000h-7FFh
S-25A320A
0
0
1
1
0 %
25 %
50 %
100 %
None
None
1
0
1
300h-3FFh
200h-3FFh
000h-3FFh
C00h to FFFh
800h to FFFh
000h to FFFh
Table 17 Protect Operation
Mode
Bit SRWD
Bit WEL
Write protect block
General block
Status register
WP pin
1
1
X
X
0
0
X
X
0
0
1
1
0
1
0
1
0
1
Write disable
Write disable
Write disable
Write disable
Write disable
Write disable
Write disable
Write enable
Write disable
Write enable
Write disable
Write enable
Write disable
Write enable
Write disable
Write enable
Write disable
Write disable
Software Protect
(SPM)
Hardware Protect
(HPM)
Remark X = Don’t care
22
Seiko Instruments Inc.
125°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE ELECTRIC COMPONENT
Rev.1.0_00
S-25A080A/160A/320A
Hold Operation
The hold operation is used to pause serial communications without setting the device in the non-select status. In the
hold status, the serial data output goes in high impedance, and both of the serial data input and the serial clock go in
“Don’t care”. Be sure to set the chip select (CS )to “L” to set the device in the select status during the hold status.
Generally, during the hold status, the device holds the select status. But if setting the device in the non-select status, the
users can finish the operation even in progress.
Figure 17 shows the hold operation. Set Hold (HOLD ) to “L” when the serial clock (SCK) is in “L”, Hold (HOLD ) is
switched at the same time the hold status starts. If setting Hold (HOLD ) to “H”, Hold (HOLD ) is switched at the same
time the hold status ends.
Set Hold (HOLD ) to “L” when the serial clock (SCK) is in “H”; the hold status starts when the serial clock goes in “L”
after Hold (HOLD ) is switched. If setting Hold (HOLD ) to “H”, the hold status ends when the serial clock goes in “L”
after Hold (HOLD ) is switched.
Hold status
Hold status
SCK
HOLD
Figure 17 Hold Operation
Seiko Instruments Inc.
23
125°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE ELECTRIC COMPONENT
Rev.1.0_00
S-25A080A/160A/320A
Write Protect Function during the Low Power Supply Voltage
The S-25A080A/160A/320A has a built-in detection circuit which operates with the low power supply voltage. The S-
25A080A/160A/320A cancels the Write operation (WRITE, WRSR) when the power supply voltage drops and power-
on, at the same time, goes in the Write protect status (WRDI) automatically to reset bit WEL. The detection voltage is
1.20 V typ., the release voltage is 1.35 V typ., and its hysteresis is approx. 0.15 V (Refer to Figure 18).
To operate Write, after the power supply voltage dropped once but rose to the voltage level which allows Write again,
be sure to set the Write Enable Latch bit (WEL) before operating Write (WRITE, WRSR).
In the Write operation, data in the address written during the low power supply voltage is not assured.
Hysteresis
approx. 0.15 V
Power supply voltage
Release voltage (+VDET
)
Detection voltage (−VDET
)
1.35 V Typ.
1.20 V Typ.
Cancel the Write instruction
Set in Write protect (WRDI) automatically
Figure 18 Operation during Low Power Supply Voltage
I/O Pin
1. Connection of input pin
All input pins in S-25A080A/160A/320A have the CMOS structure. Do not set these pins in high impedance during
operation when you design. Especially, set the CS input in the non-select status “H” during power-on/off and standby.
The error Write does not occur as long as the CS pin is in the non-select status “H”. Set the CS pin to VCC via a
resistor (the pull-up resistor of 10 kΩ to 100 kΩ). To prevent the error for sure, it is recommended to set other input
pins than the CS pin via a pull-up resistor.
2. Equivalent circuit of I/O pin
Figure 19 and 20 show the equivalent circuits of input pins in S-25A080A/160A/320A. A pull-up and pull-down
elements are not included in each input pin, pay attention not to set it in the floating state when you design.
Figure 21 shows the equivalent circuit of the output pin. This pin has the tri-state output of “H” level/“L” level/high
impedance.
24
Seiko Instruments Inc.
125°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE ELECTRIC COMPONENT
Rev.1.0_00
S-25A080A/160A/320A
2. 1 Input pin
CS, SCK
Figure 19 CS , SCK Pin
SI, WP, HOLD
Figure 20 SI, WP , HOLD Pin
2. 2 Output pin
V
CC
SO
Figure 21 SO Pin
3. Precaution for use
Absolute maximum ratings: Do not operate these ICs in excess of the absolute maximum ratings (as listed on the
data sheet). Exceeding the supply voltage rating can cause latch-up.
Operations with moisture on the E2PROM pins may occur malfunction by short-circuit between pins. Especially, in
occasions like picking the E2PROM up from low temperature tank during the evaluation. Be sure that not remain frost
on the E2PROM pin to prevent malfunction by short-circuit.
Also attention should be paid in using on environment, which is easy to dew for the same reason.
Seiko Instruments Inc.
25
125°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE ELECTRIC COMPONENT
Rev.1.0_00
S-25A080A/160A/320A
Precautions
● Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
● SII claims no responsibility for any and all disputes arising out of or in connection with any infringement of the
products including this IC upon patents owned by a third party.
26
Seiko Instruments Inc.
125°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE ELECTRIC COMPONENT
Rev.1.0_00
S-25A080A/160A/320A
Product Name Structure
S-25AxxxA 0 A
−
J8T2
G
D
Burn-in type
D: Wafer burn-in
Package name (abbreviation) and IC packing specification
J8T2: 8-Pin SOP (JEDEC), Tape
Fixed
Product name
S-25A080A: 8 Kbit
S-25A160A: 16 Kbit
S-25A320A: 32 Kbit
Seiko Instruments Inc.
27
5.02±0.2
8
5
1
4
0.20±0.05
1.27
0.4±0.05
No. FJ008-A-P-SD-2.1
SOP8J-D-PKG Dimensions
FJ008-A-P-SD-2.1
TITLE
No.
SCALE
UNIT
mm
Seiko Instruments Inc.
4.0±0.1(10 pitches:40.0±0.2)
2.0±0.05
ø1.55±0.05
0.3±0.05
8.0±0.1
ø2.0±0.05
2.1±0.1
5°max.
6.7±0.1
8
5
1
4
Feed direction
No. FJ008-D-C-SD-1.1
SOP8J-D-Carrier Tape
FJ008-D-C-SD-1.1
TITLE
No.
SCALE
UNIT
mm
Seiko Instruments Inc.
60°
2±0.5
13.5±0.5
Enlarged drawing in the central part
ø21±0.8
2±0.5
ø13±0.2
No. FJ008-D-R-SD-1.1
SOP8J-D-Reel
TITLE
FJ008-D-R-SD-1.1
No.
SCALE
UNIT
QTY.
2,000
mm
Seiko Instruments Inc.
·
·
The information described herein is subject to change without notice.
Seiko Instruments Inc. is not responsible for any problems caused by circuits or diagrams described herein
whose related industrial properties, patents, or other rights belong to third parties. The application circuit
examples explain typical applications of the products, and do not guarantee the success of any specific
mass-production design.
·
·
·
When the products described herein are regulated products subject to the Wassenaar Arrangement or other
agreements, they may not be exported without authorization from the appropriate governmental authority.
Use of the information described herein for other purposes and/or reproduction or copying without the
express permission of Seiko Instruments Inc. is strictly prohibited.
The products described herein cannot be used as part of any device or equipment affecting the human
body, such as exercise equipment, medical equipment, security systems, gas equipment, or any apparatus
installed in airplanes and other vehicles, without prior written permission of Seiko Instruments Inc.
Although Seiko Instruments Inc. exerts the greatest possible effort to ensure high quality and reliability, the
failure or malfunction of semiconductor products may occur. The user of these products should therefore
give thorough consideration to safety design, including redundancy, fire-prevention measures, and
malfunction prevention, to prevent any accidents, fires, or community damage that may ensue.
·
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