SI50122-A3-GMR [SILICON]
Processor Specific Clock Generator, 100MHz, CMOS, PDSO10, 2 X 2.50 MM, ROHS COMPLIANT, TDFN-10;
| 型号： | SI50122-A3-GMR |
| 厂家： | 
SILICON |
| 描述： | Processor Specific Clock Generator, 100MHz, CMOS, PDSO10, 2 X 2.50 MM, ROHS COMPLIANT, TDFN-10 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总14页 (文件大小：293K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si50122-A3/A4
CRYSTAL-LESS PCI-EXPRESS GEN 1 & GEN 2
DUAL OUTPUT CLOCK GENERATOR
Features
Crystal-less clock generator with Triangular spread spectrum
integrated CMEMS
profile for maximum EMI
reduction (Si50122-A4)
PCI-Express Gen 1/2 compliant
Industrial Temperature –40 to
Two PCIe 100 MHz differential
85 °C
HCSL outputs
2.5 V, 3.3 V Power supply
One 25 MHz single-ended
LVCMOS output
Small package 10-pin TDFN
(2.0x2.5 mm)
Supports Serial (ATA) at
100 MHz
Si50122-A3 does not support
Ordering Information:
spread spectrum outputs
Low power differential output
See page 10
buffers
Si50122-A4 supports 0.5% down
spread outputs
No termination resistors required
for differential output clocks
Pin Assignments
Applications
VSS
REFOUT
NC
1
2
3
4
5
10
9
Digital TV
Network Attached Storage
Multi-function Printer
Wireless Access Point
Digital Video Cameras
VDD
VDD
Set top box
Solid State Drives (SSD)
Wireless Access Point
Home Gateway
8
DIFF2
DIFF2
7
DIFF1
DIFF1
6
VSS
Description
Si50122-A3/A4 is a high performance, crystal-less PCIe clock generator
that can generate two 100 MHz PCIe clock and one 25 MHz LVCMOS
clock outputs. The differential clock outputs are compliant to PCIe Gen1
and Gen 2 specifications. The ultra-small footprint (2.0x2.5 mm) and
industry leading low power consumption make Si50122-A3/A4 the ideal
clock solution for consumer and embedded applications where board
space is limited and low power is needed.
Patents pending
Functional Block Diagram
VDD
REFOUT
DIFF1
PLL
(SSC)
Divider
CMEMS
DIFF2
VSS
Rev 0.7 9/14
Copyright © 2014 by Silicon Laboratories
Si50122-A3/A4
Si50122-A3/A4
2
Rev 0.7
Si50122-A3/A4
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
5. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
6. Recommended Design Guideline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Rev 0.7
3
Si50122-A3/A4
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Supply Voltage (3.3 V Supply)
V
V
3.3 V ± 10%
2.97
3.3
3.63
V
DD
DD
Supply Voltage (2.5 V Supply)
2.5 V ± 10%
2.25
2.5
2.75
V
Table 2. DC Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Operating Voltage
Operating Voltage
V
V
3.3 V ± 10%
2.97
3.30
3.63
V
VDD=3.3 V
VDD=2.5 V
DD
DD
DD
2.5 V ± 10%
2.25
—
2.5
20
18
3
2.75
23
21
5
V
Operating Supply Current
I
Full active; 3.3 V ± 10%
Full active; 2.5 V ± 10%
Input Pin Capacitance
Output Pin Capacitance
mA
mA
pF
—
Input Pin Capacitance
Output Pin Capacitance
C
—
IN
C
—
—
5
pF
OUT
4
Rev 0.7
Si50122-A3/A4
Table 3. AC Electrical Specifications
Parameter
DIFF Clocks
Symbol
Condition
Min
Typ
Max
Unit
Duty Cycle
Measured at 0 V differential
Measured at 0 V differential
VDD = 3.3 V
45
—
—
—
55
100
—
%
ps
T
DC
Skew
T
SKEW
—
100
—
MHz
ppm
V/ns
Output Frequency
Frequency Accuracy
Slew Rate
F
OUT
—
100
5.0
F
All output clocks
ACC
—
t
Measured differentially from
±150 mV
0.6
r/f2
300
550
mV
Crossing Point Voltage at 0.7 V
Swing
V
—
OX
—
1.15
—
V
V
—
—
Voltage High
V
HIGH
–0.3
Voltage Low
V
S
LOW
RNG
MOD
—
30
—
–0.5
33
%
Spread Range
Modulation Frequency
Down Spread, –A4 only
–A4 only
31.5
kHz
F
DIFF Clocks Jitter Parameters, VDD = 3.3 V ± 10%
—
—
—
20.7
0.8
35
2.1
2.2
ps
ps
ps
PCIe Gen1 Pk-Pk
Pk-Pk
PCIe Gen 1
GEN1
PCIe Gen2 Phase Jitter
RMS
10 kHZ < F < 1.5 MHz
1.5 MHZ < F < Nyquist
GEN2
1.4
DIFF Clocks Jitter Parameters, VDD = 2.5V ± 10%
PCIe Gen1 Pk-Pk
Pk-Pk
PCIe Gen 1
—
—
—
25
0.9
1.7
40
2.9
3.0
ps
ps
ps
GEN1
PCIe Gen2 Phase Jitter
RMS
10 kHZ < F < 1.5 MHz
1.5 MHZ < F < Nyquist
GEN2
25 MHz at 3.3 V
Duty Cycle
45
—
55
%
ns
T
Measurement at 1.5 V
DC
1.2
1.2
—
3.0
3.0
Output Rise Time
t
C = 10 pF, 20% to 80%
L
r
ns
Output Fall Time
t
C = 10 pF, 20% to 80%
f
L
Cycle to Cycle Jitter
—
—
250
100
ps
T
Measurement at 1.5 V
Measured at 1.5 V
CCJ
ACC
Long Term Accuracy
—
ppm
ms
L
Powerup Time
Clock Stabilization from Powerup
T
First powerup to first output
—
—
10
STABLE
Note: Visit www.pcisig.com for complete PCIe specifications.
Rev 0.7
5
Si50122-A3/A4
Table 4. Thermal Conditions
Parameter
Symbol
Test Condition
Min
Typ
Max Unit
Temperature, Storage
T
Non-functional
–65
150
85
°C
°C
°C
S
Temperature, Operating Ambient
Temperature, Junction
T
Functional
Functional
–40
—
A
T
150
J
Dissipation, Junction to Case
Dissipation, Junction to Ambient
Ø
JEDEC (JESD 51)
JEDEC (JESD 51)
—
38.3 °C/W
90.4 °C/W
JC
JA
Ø
—
Table 5. Absolute Maximum Conditions
Parameter
Main Supply Voltage
Symbol
Test Condition
Min
Typ
Max Unit
V
—
4.6
4.6
—
V
DD_3.3V
Input Voltage
V
Relative to V
–0.5
V
DC
IN
SS
ESD Protection (Human Body Model)
Flammability Rating
ESD
JEDEC (JESD 22 - A114) 2000
UL (Class)
V
HBM
UL-94
V–0
Note: While using multiple power supplies, the voltage on any input or I/O pin cannot exceed the power pin during powerup.
Power supply sequencing is NOT required.
6
Rev 0.7
Si50122-A3/A4
2. Test and Measurement Setup
Figures 1–3 show the test load configuration for the differential clock signals.
M easurem ent
P oint
2 pF
L1
O U T+
50
L1 = 5"
M easurem ent
P oint
2 pF
L1
O U T-
50
Figure 1. 0.7 V Differential Load Configuration
Figure 2. Differential Measurement for Differential Output Signals
(for AC Parameters Measurement)
Rev 0.7
7
Si50122-A3/A4
Figure 3. Single-ended Measurement for Differential Output Signals
(for AC Parameters Measurement)
L1 = 0.5", L2 = 5"
Measurement
Point
50
REF
L2
L1
10 pF
33
Figure 4. Single-ended Clocks with Single Load Configuration
80%
1.5V
20%
Figure 5. Single-ended Output Signal (for AC Parameter Measurement)
8
Rev 0.7
Si50122-A3/A4
3. Pin Descriptions
VSS
REFOUT
NC
1
2
3
4
5
10
9
VDD
VDD
8
DIFF2
DIFF2
7
DIFF1
DIFF1
6
VSS
Figure 6. 10-Pin TDFN
Table 6. Si50122-Ax-GM 10-Pin TDFN Descriptions
Pin #
Name
Type
Description
Connect to Ground
1
VSS
GND
25 MHz LVCMOS clock output
2
3
REFOUT
NC
O, SE
NC
No Connect. Do not connect this pin to anything.
0.7 V, 100 MHz differential clock output
0.7 V, 100 MHz differential clock output
Connect to Ground
4
DIFF1
DIFF1
VSS
O, DIF
O, DIF
GND
5
6
0.7 V, 100 MHz differential clock output
0.7 V, 100 MHz differential clock output
Power supply
7
DIFF2
DIFF2
VDD
O, DIF
O, DIF
PWR
PWR
8
9
Power supply
10
VDD
Rev 0.7
9
Si50122-A3/A4
4. Ordering Guide
Part Number
Spread Option
Package Type
Temperature
Si50122-A3-GM
No Spread
No Spread
10-pin TDFN
Industrial, –40 to 85 C
Si50122-A3-GMR
Si50122-A4-GM
Si50122-A4-GMR
10-pin TDFN—Tape and Reel
10-pin TDFN
Industrial, –40 to 85 C
Industrial, –40 to 85 C
Industrial, –40 to 85 C
–0.5% Spread
–0.5% Spread
10-pin TDFN—Tape and Reel
GMR
Si50122
Ax
Operating Temp Range:
G: -40 to +85 °C
Base part number
M:10-TDFNPackage,ROHS6,Pb-free
R: Tape & Reel
(blank) = Tubes
A: Product Revision A
x=3: non-spread outputs
x=4: -0.5% spread outputs
Figure 7. Ordering Information
10
Rev 0.7
Si50122-A3/A4
5. Package Outlines
Figure 8. 10-Pin TDFN Package Drawing
Rev 0.7
11
Si50122-A3/A4
Table 7. Package Diagram Dimensions
Symbol
Min
Nom
Max
A
0.80
0.85
0.90
A1
0.00
0.20
—
0.05
0.30
A3
0.203 REF
0.25
b
D
2.00 BSC
0.50 BSC
2.50 BSC
e
E
L
0.35
0.4
0.45
aaa
0.10
bbb
0.10
0.10
0.05
0.08
ccc
ddd
eee
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
12
Rev 0.7
Si50122-A3/A4
6. Recommended Design Guideline
3.3V / 2.5V
FB
VDD
4.7uF 0.1uF
Si50122
Note: FB Specifications:
DC resistance 0.1–0.3
Impedance at 100 MHz > 1000
Figure 9. Recommended Application Schematic
Rev 0.7
13
Si50122-A3/A4
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
Patent Notice
Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analog-
intensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
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plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brand names mentioned herein are trademarks or registered trademarks of their respective holders.
14
Rev 0.7
相关型号：
SI50122-A4-GM
Processor Specific Clock Generator, 100MHz, CMOS, PDSO10, 2 X 2.50 MM, ROHS COMPLIANT, TDFN-10
SILICON
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