SI5013 [SILICON]
OC-12/3, STM-4/1 SONET/SDH CDR IC WITH LIMITING AMPLIFIER; OC - 12/3 ， STM - 4/1 SONET /限幅放大器的SDH CDR IC
| 型号： | SI5013 |
| 厂家： | 
SILICON |
| 描述： | OC-12/3, STM-4/1 SONET/SDH CDR IC WITH LIMITING AMPLIFIER |
| 文件： | 总26页 (文件大小：402K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si5013
OC-12/3, STM-4/1 SONET/SDH CDR IC WITH LIMITING AMPLIFIER
Features
High-speed clock and data recovery device with integrated limiting amplifier:
ꢀ Supports OC-12/3, STM-4/1
ꢀ DSPLL® technology
ꢀ Loss-of-signal level alarm
ꢀ Data slicing level control
ꢀ 10 mV differential sensitivity
(typ)
ꢀ Jitter generation 2.3 mUI
PP
rms
ꢀ 3.3 V supply
ꢀ Small footprint: 5 x 5 mm
ꢀ Reference and reference-less
Ordering Information:
operation supported
See page 22.
Applications
ꢀ SONET/SDH/ATM routers
ꢀ Add/drop multiplexers
ꢀ Digital cross connects
ꢀ Board level serial links
ꢀ SONET/SDH test equipment
ꢀ Optical transceiver modules
ꢀ SONET/SDH regenerators
Pin Assignments
Si5013
Description
28 27 26 25 24 23 22
RATESEL
GND
VDD
21
1
2
3
4
5
6
7
The Si5013 is a fully-integrated, high-performance limiting amplifier (LA)
and clock and data recovery (CDR) IC for high-speed serial
communication systems. It derives timing information and data from a
serial input at OC-12/3 and STM-4/1 rates. Use of an external reference
clock is optional. Silicon Laboratories DSPLL technology eliminates
sensitive noise entry points, thus making the PLL less susceptible to
board-level interaction and helping to ensure optimal jitter performance.
20 REXT
LOS_LVL
SLICE_LVL
REFCLK+
REFCLK–
LOL
19 RESET/CAL
GND
Pad
18
17
16
15
VDD
DOUT+
DOUT–
TDI
®
8
9
10 11 12 13 14
The Si5013 represents a new standard in low jitter, low power, small size,
and integration for high-speed LA/CDRs. It operates from a 3.3 V supply
over the industrial temperature range (–40 to 85 °C).
Functional Block Diagram
LOS_LVL
Signal
Detect
DSQLCH
LOS
2
DOUT+
DOUT–
Retimer
BUF
BUF
2
DIN+
DIN–
Limiting
Amp
DSPLL
BER
Monitor
2
CLKOUT+
CLKOUT–
CLK_DSBL
REFCLK+
REFCLK–
(Optional)
2
Lock
Detection
Reset/
Calibration
Bias Gen.
REXT
BER_ALM
RESET/CAL
RATESEL
BER_LVL
SLICE_LVL
LOL
LTR
Rev. 1.5 10/05
Copyright © 2005 by Silicon Laboratories
Si5013
Si5013
2
Rev. 1.5
Si5013
TABLE OF CONTENTS
Section
Page
1. Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
4.1. Limiting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
®
4.2. DSPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
4.3. Multi-Rate Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
4.4. Operation Without an External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
4.5. Operation With an External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
4.6. Lock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
4.7. Lock-to-Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
4.8. Loss-of-Signal (LOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
4.9. Bit Error Rate (BER) Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4.10. Data Slicing Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4.11. PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4.12. RESET/DSPLL Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4.13. Clock Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4.14. Data Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4.15. Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4.16. Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4.17. Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4.18. Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4.19. Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5. Pin Descriptions: Si5013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Rev. 1.5
3
Si5013
1. Detailed Block Diagram
LTR
LOS
BER_LVL
BER_ALM
RATESEL
DSQLCH
BER
Monitor
Signal
Detect
LOS_LVL
DOUT+
DOUT–
Retime
DIN+
DIN–
CLKOUT+
CLKOUT–
Limiting
Amp
Phase
Detector
CLK
Dividers
A/D
DSP
VCO
n
CLKDSBL
Slicing
Control
SLICE_LVL
Lock
Detection
REFCLK±
(optional)
LOL
Bias
Generation
REXT
Calibration
RESET/CAL
4
Rev. 1.5
Si5013
2. Electrical Specifications
Table 1. Recommended Operating Conditions
1
1
Symbol
Test Condition
Typ
Unit
Parameter
Min
Max
Ambient Temperature
Si5013 Supply Voltage
Notes:
T
–40
25
85
°C
V
A
2
V
3.135
3.3
3.465
DD
1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.
2. The Si5013 specifications are guaranteed when using the recommended application circuit (including component
tolerance) of "3.Typical Application Schematic" on page 11.
V
SIGNAL+
SIGNAL–
VIS
t
A. Operation with Single-Ended Inputs
V
SIGNAL+
SIGNAL–
0.5 VID
(SIGNAL+) – (SIGNAL–)
VID
t
B. Operation with Differential Inputs and Outputs
Figure 1. Differential Voltage Measurement (DIN, REFCLK, DOUT, CLKOUT)
tCf-D
tCr-D
DOUT
CLKOUT
Figure 2. Clock to Data Timing
Rev. 1.5
5
Si5013
80%
20%
DOUT,
CLKOUT
tF
tR
Figure 3. DOUT and CLKOUT Rise/Fall Times
taq
RESET/Cal
LOL
DATAIN
LOL
taq
Figure 4. PLL Acquisition Time
DATAIN
LOS Threshold
Level
LOS
tLOS
Figure 5. LOS Response
6
Rev. 1.5
Si5013
Table 2. DC Characteristics
(VDD = 3.3 V ±5%, TA = –40 to 85 °C)
Parameter
Symbol Test Condition
Min
Typ
Max
Unit
1
Supply Current
I
DD
OC-12
OC-3
—
—
180
190
190
197
mA
Power Dissipation
OC-12
OC-3
P
D
—
—
594
627
657
682
mW
2
Common Mode Input Voltage (DIN)
V
V
See Figure 11
See Figure 10
See Figure 1A
See Figure 1B
See Figure 1A
See Figure 1B
Line-to-Line
1.30
1.90
10
1.50
2.10
—
1.62
2.30
500
V
V
ICM
ICM
2
Common Mode Input Voltage (REFCLK)
2
DIN Single-ended Input Voltage Swing
V
mV
mV
mV
mV
Ω
IS
ID
IS
ID
IN
2
DIN Differential Input Voltage Swing
V
10
—
1000
750
2
REFCLK Single-ended Input Voltage Swing
V
V
R
200
200
84
—
2
REFCLK Differential Input Voltage Swing
—
1500
116
Input Impedance (DIN)
100
800
Differential Output Voltage Swing
(DOUT)
V
100 Ω Load
Line-to-Line
700
1000
mV
OD
PP
Differential Output Voltage Swing
(CLKOUT)
V
100 Ω Load
Line-to-Line
700
1.6
800
1100
2.35
mV
PP
OD
Output Common Mode Voltage
(DOUT, CLKOUT)
V
100 Ω Load
Line-to-Line
1.95
V
OCM
Output Impedance (DOUT,CLKOUT)
Input Voltage Low (LVTTL Inputs)
Input Voltage High (LVTTL Inputs)
Input Low Current (LVTTL Inputs)
Input High Current (LVTTL Inputs)
Input Impedance (LVTTL Inputs)
R
Single-ended
84
—
100
—
116
.8
Ω
V
OUT
V
IL
IH
IL
V
2.0
—
—
—
V
I
—
10
10
—
µA
µA
kΩ
kΩ
I
—
—
IH
R
R
10
50
—
IN
IN
LOS_LVL, BER_LVL, SLICE_LVL Input
Impedance
100
125
Output Voltage Low (LVTTL Outputs)
Output Voltage High (LVTTL Outputs)
V
I = 2 mA
—
—
—
0.4
—
V
V
OL
O
V
I = 2 mA
2.0
OH
O
Notes:
1. No Load on LVTTL outputs.
2. These inputs may be driven differentially or single-endedly. When driven single-endedly, the unused input must be ac
coupled to ground.
Rev. 1.5
7
Si5013
Table 3. AC Characteristics (Clock and Data)
(VDD = 3.3 V ±5%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output Clock Rate
f
Rate Sel = 1
Rate Sel = 0
616
154
—
—
675
158
MHz
CLK
Output Rise Time—OC-12
Output Fall Time—OC-12
t
Figure 3
Figure 3
—
—
47
125
125
50
155
155
53
ps
ps
R
t
F
Output Clock Duty Cycle—
OC-12/3
% of
UI
Clock to Data Delay
OC-12
OC-3
t
Figure 2
Figure 2
Cr-D
800
4000
860
4100
940
4200
ps
Clock to Data Delay
OC-12
t
Cf-D
0
35
70
ps
OC-3
800
850
1000
Input Return Loss
100 kHz–622 MHz
–15
—
—
dB
Slicing Level Offset
V
SLICE_LVL = 750 mV to 2.25 V
See Figure 8 on page 14.
SLICE
(relative to the internally set
input common mode voltage)
*
Loss-of-Signal Range
V
LOS_LVL = 1.50 to 2.50 V
Figure 5 on page 6
0
8
—
40
25
mV
µs
LOS
(peak-to-peak differential)
Loss-of-Signal Response Time
t
20
LOS
*Note: Adjustment voltage is calculated as follows: V
= (LOS_LVL – 1.50)/25.
LOS
8
Rev. 1.5
Si5013
Table 4. AC Characteristics (PLL Characteristics)
(VDD = 3.3 V ±5%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Jitter Tolerance
(OC-12 Mode)
J
f = 30 Hz
f = 300 Hz
60
6
—
—
—
—
UI
UI
UI
UI
UI
UI
UI
UI
TOL(PP)
PP
PP
PP
PP
PP
PP
PP
PP
*
f = 25 kHz
4
—
—
f = 250 kHz
0.4
60
6
—
—
Jitter Tolerance
J
f = 30 Hz
—
—
TOL(PP)
*
(OC-3 Mode)
f = 300 Hz
—
—
f = 6.5 kHz
4
—
—
f = 65 kHz
0.4
—
—
—
—
—
—
—
—
*
RMS Jitter Generation
J
with no jitter on serial data
with no jitter on serial data
OC-12 Mode
OC-3 Mode
2.3
20
—
4.0
45
500
130
0.1
2
mUI
mUI
kHz
kHz
dB
GEN(rms)
*
Peak-to-Peak Jitter Generation
J
GEN(PP)
*
Jitter Transfer Bandwidth
J
BW
—
*
Jitter Transfer Peaking
J
0.03
1.5
P
Acquisition Time—OC-12
(Reference clock applied)
T
After falling edge of
PWRDN/CAL
ms
AQ
From the return of valid
data
—
—
—
60
4.0
13
—
12
—
µs
ms
Acquisition Time—OC-12
(Reference-less operation)
T
After falling edge of
PWRDN/CAL
AQ
From the return of valid
data
ms
Reference Clock Range
See "4.4.Operation With-
out an External Refer-
ence" on page 12.
155.5
77.76
19.44
MHz
Input Reference Clock Frequency
Tolerance
C
–500
—
—
500
—
ppm
ppm
TOL
Frequency Difference at which
Receive PLL goes out of Lock
(REFCLK compared to the divided
down VCO clock)
±650
*Note: As defined in Bellcore specifications: GR-253-CORE, Issue 3, September 2000. Using PRBS 223 – 1 data pattern.
Rev. 1.5
9
Si5013
Table 5. Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
DC Supply Voltage
V
–0.5 to 3.5
–0.3 to 3.6
V
V
DD
LVTTL Input Voltage
V
DIG
Differential Input Voltages
Maximum Current any output PIN
Operating Junction Temperature
Storage Temperature Range
ESD HBM Tolerance (100 pf, 1.5 kΩ)
V
–0.3 to (V + 0.3)
V
DIF
DD
±50
–55 to 150
–55 to 150
1
mA
°C
°C
kV
T
JCT
T
STG
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Table 6. Thermal Characteristics
Parameter
Symbol
Test Condition
Value
Unit
Thermal Resistance Junction to Ambient
ϕ
Still Air
38
°C/W
JA
10
Rev. 1.5
Si5013
3. Typical Application Schematic
BER Alarm
Indicator
LVTTL
Control Inputs
Loss-of-Signal
Indicator
Loss-of-Lock
Indicator
DIN+
DOUT+
DOUT–
High-Speed
Serial Input
Recovered
Data
DIN–
System
Reference
Clock
Si5013
REFCLK+
REFCLK–
CLKOUT+
CLKOUT–
Recovered
Clock
(Optional)
100 pF x 4
VDD
10 kΩ
(1%)
0.1
F
µ
Loss-of-Signal Data Slice
Level Set
Level Set
Bit Error Rate
Level Set
Rev. 1.5
11
Si5013
traditional methods, and it eliminates performance
degradation caused by external component aging. In
4. Functional Description
The Si5013 integrates a high-speed limiting amplifier addition, because external loop filter components are
with a multi-rate CDR unit. No external reference clock not required, sensitive noise entry points are eliminated,
is required for clock and data recovery. The limiting thus making the DSPLL less susceptible to board-level
amplifier magnifies very low-level input data signals so noise sources and making SONET/SDH jitter
that accurate clock and data recovery can be compliance easier to attain in the application.
performed. The CDR uses Silicon Laboratories DSPLL®
4.3. Multi-Rate Operation
technology to recover a clock synchronous to the input
data stream. The recovered clock retimes the incoming The Si5013 supports clock and data recovery for OC-
data, and both are output synchronously via current- 12/3 and STM-4/1 data streams.
mode logic (CML) drivers. Silicon Laboratories’ DSPLL
Multi-rate operation is achieved by configuring the
technology ensures superior jitter performance while
device to divide down the output of the VCO to the
eliminating the need for external loop filter components
desired data rate. The divide factor is configured by the
found in traditional phase-locked loop (PLL)
RATESEL pin. The RATESEL configuration and
associated data rates are given in Table 7.
implementations.
The limiting amplifier includes a control input for
Table 7. Multi-Rate Configuration
RATESEL SONET/SDH
adjusting the data slicing level and provides a loss-of-
signal level alarm output. The CDR includes a bit error
rate performance monitor which signals a high bit error
rate condition (associated with excessive incoming
jitter) relative to an externally adjustable bit error rate
threshold.
1
0
622.08 Mbps
155.52 Mbps
The optional reference clock minimizes the CDR
acquisition time and provides a stable reference for
maintaining the output clock when locking to a reference
is desired.
4.4. Operation Without an External Refer-
ence
The Si5013 can perform clock and data recovery
without an external reference clock. Tying the
REFCLK+ input to VDD and the REFCLK– input to
GND configures the device to operate without an
external reference clock. Clock recovery is achieved by
monitoring the timing quality of the incoming data
relative to the VCO frequency. Lock is maintained by
continuously monitoring the incoming data timing quality
and adjusting the VCO accordingly. Details of the lock
detection and the lock-to-reference functions while in
this mode are described in their respective sections
below.
4.1. Limiting Amplifier
The limiting amplifier accepts the low-level signal output
from a transimpedance amplifier (TIA). The low-level
signal is amplified to a usable level for the CDR unit. The
minimum input swing requirement is specified in Table 2
on page 7. Larger input amplitudes (up to the maximum
input swing specified in Table 2) are accommodated
without degradation of performance. The limiting
amplifier ensures optimal data slicing by using a digital
dc offset cancellation technique to remove any dc bias
introduced by the amplification stage.
Note: Without an external reference the acquisition of data is
dependent solely on the data itself and typically
requires more time to acquire lock than when a refer-
ence is applied.
®
4.2. DSPLL
The Si5013 PLL structure (shown in the "1.Detailed
Block Diagram" on page 4) utilizes Silicon Laboratories'
DSPLL technology to maintain superior jitter
performance while eliminating the need for external loop
4.5. Operation With an External Reference
The Si5013 can also perform clock and data recovery
with an external reference. The device’s optional
external reference clock centers the DSPLL, minimizes
the acquisition time, and maintains a stable output clock
(CLKOUT) when lock-to-reference (LTR) is asserted.
filter
components
found
in
traditional
PLL
implementations. This is achieved using a digital signal
processing (DSP) algorithm to replace the loop filter
commonly found in analog PLL designs. This algorithm
processes the phase detector error term and generates
a digital control value to adjust the frequency of the
voltage-controlled oscillator (VCO). This technology
enables CDR with far less jitter than is generated using
When the reference clock is present, the Si5013 uses
the reference clock to center the VCO output frequency
so that clock and data is recovered from the input data
stream. The device self configures for operation with
one of three reference clock frequencies. This
12
Rev. 1.5
Si5013
eliminates the need to externally configure the device to
operate with a particular reference clock. The REFCLK
frequency should be 19.44, 77.76, or 155.52 MHz with a
frequency accuracy of ±100 ppm.
4.8. Loss-of-Signal (LOS)
The Si5013 indicates a loss-of-signal condition on the
LOS output pin when the input peak-to-peak signal level
on DIN falls below an externally controlled threshold.
The LOS threshold range is specified in Table 3 on
page 8 and is set by applying a voltage on the LOS_LVL
pin. The graph in Figure 6 illustrates the LOS_LVL
mapping to the LOS threshold. The LOS output is
asserted when the input signal drops below the
programmed peak-to-peak value. If desired, the LOS
function may be disabled by grounding LOS_LVL or by
adjusting LOS_LVL to be less than 1 V.
4.6. Lock Detect
The Si5013 provides lock-detect circuitry that indicates
whether the PLL has achieved frequency lock with the
incoming data. The operation of the lock-detector
depends on the reference clock option used.
When an external reference clock is provided, the circuit
compares the frequency of a divided-down version of
the recovered clock with the frequency of the applied
reference clock (REFCLK). If the recovered clock
frequency deviates from that of the reference clock by
the amount specified in Table 4 on page 9, the PLL is
declared out of lock, and the loss-of-lock (LOL) pin is
asserted. In this state, the PLL will periodically try to
reacquire lock with the incoming data stream. During
reacquisition, the recovered clock frequency (CLKOUT)
drifts over a ±600 ppm range relative to the applied
reference clock and the LOL output alarm may toggle
until the PLL has reacquired frequency lock. Due to the
low noise and stability of the DSPLL, there is the
possibility that the PLL will not drift enough to render an
out-of-lock condition, even if the data is removed from
inputs.
Note: The LOS circuit is designed to only work with pseudo-
random, dc-balanced data.
40 mV
30 mV
15 mV
40mV/V
LOS Limited by Device Noise
0 mV
0 V
1.00 V
1.50 V
1.875 V
2.25 V
2.50 V
LOS_LVL (V)
In applications requiring a more stable output clock
during out-of-lock conditions, the lock-to-reference
(LTR) input can be used to force the PLL to lock to the
externally supplied reference.
Figure 6. LOS_LVL Mapping
R1
In the absence of an external reference, the lock detect
circuitry uses a data quality measure to determine when
frequency lock has been lost with the incoming data
stream. During reacquisition, CLKOUT may vary by
approximately ±10% from the nominal data rate.
3
LOS_LVL
Set LOS
Level
Si5013
CDR
R2
10k
4.7. Lock-to-Reference
The LTR input can be used to force a stable output
clock when an alarm condition, like LOS, exists. In
typical applications, the LOS output is tied to the LTR
input to force a stable output clock when the input data
signal is lost. When LTR is asserted, the DSPLL is
prevented from acquiring the data signal present on
DIN. The operation of the LTR control input depends on
which reference clocking mode is used.
9
LOS
LOS Alarm
Figure 7. LOS Signal Hysteresis
In many applications it is desirable to produce a fixed
amount of signal hysteresis for an alarm indicator such
as LOS, since a marginal data input signal could cause
intermittent toggling, leading to false alarm status.
When it is anticipated that very low-level DIN signals will
be encountered, the introduction of an adequate
amount of LOS hysteresis is recommended to minimize
any undesirable LOS signal toggling. Figure 7 illustrates
a simple circuit that may be used to set a fixed level of
When an external reference clock is present, assertion
of LTR forces the DSPLL to lock CLKOUT to the
provided reference. If no external reference clock is
used, LTR forces the DSPLL to hold the digital
frequency control input to the VCO at the last value.
This produces a stable output clock as long as supply
and temperature are constant.
Rev. 1.5
13
Si5013
LOS signal hysteresis for the Si5013 CDR. The value of
R1 may be chosen to provide a range of hysteresis from
3 to 8 dB where a nominal value of 800 Ω adjusts the
hysteresis level to approximately 6 dB. Use a value of
500 Ω or 1000 Ω for R1 to provide 3 dB or 8 dB of
hysteresis, respectively.
4.10. Data Slicing Level
The Si5013 provides the ability to externally adjust the
slicing level for applications that require bit error rate
(BER) optimization. Adjustments in slicing level of
±15 mV (typical, relative to the internally set input
common mode voltage) are supported. The slicing level
is set by applying a voltage between 0.75 and 2.25 V to
the SLICE_LVL input. See Figure 8 for the operation
levels of the slice circuit.
Hysteresis is defined as the ratio of the LOS deassert
level (LOSD) and the LOS assert level (LOSA). The
hysteresis in decibels is calculated as 20log(LOSD/
LOSA).
When SLICE_LVL is driven below 500 mV, the slicing
level adjustment is disabled, and the slicing level is set
to the cross-point of the differential input signal.
4.9. Bit Error Rate (BER) Detection
The Si5013 uses a proprietary Silicon Laboratories
algorithm to generate a bit-error-rate (BER) alarm on
the BER_ALM pin if the observed BER is greater than a
user programmable threshold. Bit error detection relies
on the input data edge timing; edges occurring outside
of the expected event window are counted as bit errors.
The BER threshold is programmed by applying a
voltage to the BER_LVL pin between 500 mV and
2.25 V corresponding to a BER of approximately 10–10
and 10–6, respectively. The voltage present on
BER_LVL maps to the BER as follows: log10(BER) = (4
x BER_LVL) – 13. (BER_LVL is in volts; BER is in bits
per second.).
Note: The slice circuit is designed to only work with pseudo-
random, dc-balanced data.
4.11. PLL Performance
The PLL implementation used in the Si5013 is fully
compliant with the jitter specifications proposed for
SONET/SDH equipment by Bellcore GR-253-CORE,
Issue 3, September 2000 and ITU-T G.958.
4.11.1. Jitter Tolerance
The Si5013’s tolerance to input jitter exceeds that of the
Bellcore/ITU mask shown in Figure 8. This mask
defines the level of peak-to-peak sinusoid jitter that
must be tolerated when applied to the differential data
input of the device.
25
20
15
10
5
10 mV
Upper Limit
0
-5
Typical
-10
10 mV
-15
-20
Note: SLICE is a continuous curve. This chart shows
the range of results from part-to-part.
Lower Limit
-25
0.00
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
Figure 8. OC-12 and OC-3 Slice Specification
14
Rev. 1.5
Si5013
4.11.2. Jitter Transfer
positive and negative terminals of CLKOUT are tied to
VDD through 100 Ω on-chip resistors.
The Si5013 exceeds all relevant Bellcore/ITU
specifications related to SONET/SDH jitter transfer.
Jitter transfer is defined as the ratio of output signal jitter
to input signal jitter as a function of jitter frequency.
These measurements are made with an input test signal
that is degraded with sinusoidal jitter whose magnitude
is defined by the mask in Figure 9.
4.14. Data Squelch
The Si5013 provides a data squelching pin (DSQLCH)
that is used to set the recovered data output (DOUT) to
binary zero. When the DSQLCH pin is asserted, the
DOUT+ signal is held low and the DOUT– signal is held
high. This pin can be is used to squelch corrupt data
during LOS and LOL situations. Care must be taken
when ac coupling these outputs; a long string of zeros
or ones will not be held through ac coupling capacitors.
Jitter
Transfer
4.15. Device Grounding
0.1 dB
20 dB/Decade
Slope
The Si5013 uses the GND pad on the bottom of the 28-
pin micro leaded package (QFN) for device ground. This
pad should be connected directly to the analog supply
ground. See Figure 15 on page 19 and Figure 16 on
page 23 for the ground (GND) pad location.
Acceptable
Range
Fc
4.16. Bias Generation Circuitry
Frequency
The Si5013 makes use of an external resistor to set
internal bias currents. The external resistor allows
precise generation of bias currents which significantly
reduces power consumption versus traditional
implementations that use an internal resistor. The bias
generation circuitry requires a 10 kΩ (1%) resistor
connected between REXT and GND.
SONET
Data Rate
OC-12
OC-3
Fc
(kHz)
500
130
Figure 9. Jitter Transfer Specification
4.11.3. Jitter Generation
The Si5013 exceeds all relevant specifications for jitter
generation proposed for SONET/SDH equipment. The
jitter generation specification defines the amount of jitter
that may be present on the recovered clock and data
outputs when a jitter free input signal is provided. The
4.17. Voltage Regulator
The Si5013 operates from a 3.3 V external supply
voltage. Internally the device operates from a 2.5 V
supply. The Si5013 regulates 2.5 V internally down from
the external 3.3 V supply.
Si5013 typically generates less than 3.0 mUI
when presented with jitter-free input data.
of jitter
rms
In addition to supporting 3.3 V systems, the on-chip
linear regulator offers better power supply noise
rejection versus a direct 2.5 V supply.
4.12. RESET/DSPLL Calibration
The Si5013 achieves optimal jitter performance by
automatically calibrating the loop gain parameters within
the DSPLL on powerup. Calibration may also be
initiated by a high-to-low transition on the RESET/CAL
pin. The RESET/CAL pin must be held high for at least
1 µs. When RESET/CAL is released (set to low) the
digital logic resets to a known initial condition,
recalibrates the DSPLL, and begins to lock to the
incoming data stream. For a valid reset to occur when
using Reference mode, a proper, external reference
clock frequency must be applied.
4.18. Differential Input Circuitry
The Si5013 provides differential inputs for both the high-
speed data (DIN) and the reference clock (REFCLK)
inputs. An example termination for these inputs is
shown in Figures 10 and 11, respectively. In
applications where direct dc coupling is possible, the
0.1 µF capacitors may be omitted. (LOS operation is
only guaranteed when ac coupled.) The data input
limiting amplifier requires an input signal with a
differential peak-to-peak voltage as specified in Table 2
–12
on page 7 to ensure a BER of at least 10 . The
REFCLK input differential peak-to-peak voltage
requirement is also specified in Table 2.
4.13. Clock Disable
The Si5013 provides a clock disable pin (CLK_DSBL)
that is used to disable the recovered clock output
(CLKOUT). When the CLK_DSBL pin is asserted, the
Rev. 1.5
15
Si5013
Si5013
2.5 V (±5%)
Clock source
2.5 kΩ
0.1 µF
0.1 µF
Zo = 50 Ω
RFCLK+
RFCLK–
100 Ω
Zo = 50 Ω
10 kΩ
2.5 kΩ
10 kΩ
GND
Figure 10. Input Termination for REFCLK (ac coupled)
Si5013
TIA
2.5 V (±5%)
0.1 µF
Zo = 50 Ω
DIN+
50 Ω
50 Ω
5 kΩ
7.5 kΩ
0.1 µF
Zo = 50 Ω
DIN–
GND
Figure 11. Input Termination for DIN (ac coupled)
16
Rev. 1.5
Si5013
Si5013
2.5 V (±5%)
Clock
source
2.5 kΩ
0.1 µF
Zo = 50 Ω
RFCLK +
RFCLK –
10 kΩ
2.5 kΩ
50 Ω
10 kΩ
0.1 µF
GND
Figure 12. Single-Ended Input Termination for REFCLK (ac coupled)
2.5 V
Si5013
Signal
source
(±5%)
0.1 µF
Zo = 50 Ω
DIN+
50 Ω
5 kΩ
100Ω
50 Ω
7.5 kΩ
DIN–
0.1 µF
GND
Figure 13. Single-Ended Input Termination for DIN (ac coupled)
Rev. 1.5
17
Si5013
4.19. Differential Output Circuitry
The Si5013 utilizes a current-mode logic (CML) architecture to output both the recovered clock (CLKOUT) and
data (DOUT). An example of output termination with ac coupling is shown in Figure 14. In applications in which
direct dc coupling is possible, the 0.1 µF capacitors may be omitted. The differential peak-to-peak voltage swing of
the CML architecture is specified in Table 2 on page 7.
Si5013
VDD
50 Ω
2.5 V (±5%)
100 Ω
DOUT+,
CLKOUT+
0.1 µF
0.1 µF
Zo = 50 Ω
Zo = 50 Ω
DOUT–,
CLKOUT–
100 Ω
2.5 V (±5%)
50 Ω
VDD
Figure 14. Output Termination for DOUT and CLKOUT (ac coupled)
18
Rev. 1.5
Si5013
5. Pin Descriptions: Si5013
28 27 26 25 24 23 22
RATESEL
VDD
21
1
2
3
4
5
6
7
GND
LOS_LVL
SLICE_LVL
REFCLK+
REFCLK–
LOL
20 REXT
19 RESET/CAL
GND
Pad
18
17
16
15
VDD
DOUT+
DOUT–
TDI
8
9
10 11 12 13 14
Figure 15. Si5013 Pin Configuration
Table 8. Si5013 Pin Descriptions
Pin #
Pin Name
I/O
Signal Level
Description
1
RATESEL
I
LVTTL
Data Rate Select.
This pin configures the onboard PLL for clock and
data recovery at one of two user selectable data
rates. See Table 7 for configuration settings.
Notes:
1. This input has a weak internal pullup.
2. After any change in RATESEL, the device must be
reset.
3
4
LOS_LVL
I
I
LOS Level Control.
The LOS threshold is set by the input voltage level
applied to this pin. Figure 6 on page 13 shows the
input setting to output threshold mapping.
LOS is disabled when the voltage applied is less
than 1 V.
SLICE_LVL
Slicing Level Control.
The slicing threshold level is set by applying a volt-
age to this pin as described in the Slicing Level sec-
tion of the data sheet. If this pin is tied to GND,
slicing level adjustment is disabled, and the slicing
level is set to the midpoint of the differential input
signal on DIN. Slicing level becomes active when
the voltage applied to the pin is greater than
500 mV.
Rev. 1.5
19
Si5013
Table 8. Si5013 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
5
6
REFCLK+
REFCLK–
I
See Table 2 Differential Reference Clock (Optional).
When present, the reference clock sets the center
operating frequency of the DSPLL for clock and
data recovery. Tie REFCLK+ to VDD and REFCLK–
to GND to operate without an external reference
clock.
See Table 7 on page 12 for typical reference clock
frequencies.
7
8
O
LVTTL
LVTTL
Loss-of-Lock.
LOL
LTR
This output is driven low when the recovered clock
frequency deviates from the reference clock by the
amount specified in Table 4 on page 9. If no exter-
nal reference is supplied, this signal will be active
when the internal PLL is no longer locked to the
incoming data.
I
Lock-to-Reference.
When this pin is low, the DSPLL disregards the data
inputs. If an external reference is supplied, the out-
put clock locks to the supplied reference. If no
external reference is used, the DSPLL locks the
control loop until LTR is released.
Note: This input has a weak internal pullup.
9
O
LVTTL
LVTTL
Loss-of-Signal.
LOS
This output pin is driven low when the input signal is
below the threshold set via LOS_LVL. (LOS opera-
tion is guaranteed only when ac coupling is used on
the DIN inputs.)
10
DSQLCH
Data Squelch.
When driven high, this pin forces the data present
on DOUT+ to zero and DOUT– to one. For normal
operation, this pin should be low. DSQLCH may be
used during LOS/LOL conditions to prevent random
data from being presented to the system.
Note: This input has a weak internal pulldown.
11,14,18,21,
25
VDD
3.3 V
Supply Voltage.
Nominally 3.3 V.
12
13
DIN+
DIN–
I
See Table 2 Differential Data Input.
Clock and data are recovered from the differential
signal present on these pins. AC coupling is recom-
mended.
15
GND
GND
Production Test Input.
This pin is used during production testing and must
be tied to GND for normal operation.
20
Rev. 1.5
Si5013
Table 8. Si5013 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
Differential Data Output.
16
17
DOUT–
DOUT+
O
CML
The data output signal is a retimed version of the
data recovered from the signal present on DIN.
19
RESET/CAL
I
LVTTL
Reset/Calibrate.
Driving this input high for at least 1 µs will reset
internal device circuitry. A high to low transition on
this pin will force a DSPLL calibration. For normal
operation, drive this pin low.
Note: This input has a weak internal pulldown.
20
REXT
External Bias Resistor.
This resistor is used to establish internal bias cur-
rents within the device. This pin must be connected
to GND through a 10 kΩ (1%) resistor.
22
23
CLKOUT–
CLKOUT+
O
I
CML
Differential Clock Output.
The output clock is recovered from the data signal
present on DIN except when LTR is asserted or the
LOL state has been entered.
24
26
CLKDSBL
BER_LVL
LVTTL
Clock Disable.
When this input is high, the CLKOUT output drivers
are disabled. For normal operation, this pin should
be low.
Note: This input has a weak internal pulldown.
I
Bit Error Rate Level Control.
The BER threshold level is set by applying a volt-
age to this pin. When the BER exceeds the pro-
grammed threshold, BER_ALM is driven low. If this
pin is tied to GND, BER_ALM is disabled. There is
no hysteresis.
27
O
LVTTL
Bit Error Rate Alarm.
BER_ALM
This pin will be driven low to indicate that the BER
threshold set by BER_LVL has been exceeded. The
alarm will clear after the BER rate has improved by
approximately a factor of 2.
28
NC
No Connect.
Leave this pin disconnected.
Supply Ground.
GND Pad, 2
GND
GND
Nominally 0.0 V. The GND pad found on the bottom
of the 28-lead QFN (see Figure 16 on page 23)
must be connected directly to supply ground. Min-
imize the ground path inductance for optimal perfor-
mance.
Rev. 1.5
21
Si5013
6. Ordering Guide
Part Number
Si5013-X-GM
Notes:
Package
Voltage
Lead-Free
Temperature
28-lead QFN
3.3
Yes
–40 to 85 °C
1. “X” denotes product revision.
2. Add an “R” at the end of the device to denote tape and reel option; 2500 quantity per reel.
22
Rev. 1.5
Si5013
7. Package Outline
Figure 16 illustrates the package details for the Si5013. Table 9 lists the values for the dimensions shown in the
illustration.
2X
0.10 C
A
A
D
D/2
0.05 C
A
b
M
D1
0.10
N
C
A
B
A1
D1/2
D2
2X
N
C
B
0.10
1
2
3
1
2
3
E1/2
E1
E/2
E
B
(Ne–1) Xe
REF.
E2
L
θ
C
SEATING
PLANE
e
TOP VIEW
(Nd–1) Xe
REF.
C
C
C
L
b
A1
BOTTOM VIEW
SECTION "C–C"
e
SCALE: NONE
Approximate device weight is 62.2 mg.
Figure 16. 28-Lead Quad Flat No-Lead (QFN)
Table 9. Package Diagram Dimensions
Controlling Dimension: mm
Symbol
Millimeters
Nom
Min
—
Max
0.90
0.05
0.30
A
A1
b
0.85
0.00
0.18
0.01
0.23
D
5.00 BSC
4.75 BSC
3.10
D1
D2
E
2.95
2.95
3.25
3.25
5.00 BSC
4.75 BSC
3.10
E1
E2
N
28
Nd
Ne
e
7
7
0.50 BSC
0.60
L
0.50
0.75
12°
θ
Rev. 1.5
23
Si5013
values.
DOCUMENT CHANGE LIST
Revision 0.2 to Revision 1.0
ꢀ Updated Table 8 on page 19.
ꢁ Changed “clock input” to “DIN inputs” for Loss Of Signal
ꢀ Updated Figure 16, “28-Lead Quad Flat No-Lead
(QFN),” on page 23.
ꢀ Added Figure 4, “PLL Acquisition Time,” on page 6.
ꢀ Table 2 on page 7
ꢀ Updated Table 9, “Package Diagram Dimensions,”
on page 23.
ꢁ Updated values: Supply Current
ꢁ Updated values: Power Dissipation
ꢁ Updated values: Common Mode Input Voltage
(REFCLK)
ꢁ Changed dimension A.
ꢁ Changed dimension E2.
ꢁ Updated values: Output Common Mode Voltage
Revision 1.2 to Revision 1.3
ꢀ Table 3 on page 8
ꢀ Updated Figure 16, “28-Lead Quad Flat No-Lead
ꢁ Updated values: Output Clock Rise Time
ꢁ Updated values: Output Clock Fall Time
(QFN),” on page 23.
ꢀ Updated Table 9, “Package Diagram Dimensions,”
ꢁ Updated values: Clock to Data Delay t
Cf-D
on page 23.
ꢀ Table 4 on page 9
ꢁ Updated values: Jitter Tolerance (OC-12)
ꢁ Updated values: RMS Jitter Generation
ꢁ Updated values: Peak-to-Peak Jitter Generation
ꢁ Updated values: Acquisition Time (reference clock
applied)
ꢁ Updated values: Acquisition Time
(reference-less operation)
ꢁ Updated values: Freq Difference at which Receive PLL
goes out of Lock
Revision 1.3 to Revision 1.4
ꢀ Updated "Features" on page 1.
ꢀ Table 2 on page 7.
ꢁ Updated supply current values.
ꢁ Updated power dissipation values.
ꢁ Updated differential output voltage swing
(DOUT and CLKOUT).
ꢀ Table 3 on page 8.
ꢁ Updated values: Freq Difference at which Receive PLL
goes into Lock
ꢁ Added output clock rate values.
ꢁ Updated duty cycle values.
ꢁ Updated slice accuracy values.
ꢀ Table 4 on page 9.
ꢁ Updated jitter tolerance values (OC-12 mode).
ꢁ Updated acquisition time values.
ꢁ Updated reference clocks range.
ꢁ Updated reference clocks tolerance.
ꢀ "3.Typical Application Schematic" on page 11.
ꢁ Added 1% to Rext.
ꢀ Removed “Hysteresis Dependency” Figure.
ꢀ Added Figure 7, “LOS Signal Hysteresis,” on page
13.
ꢀ Corrected error: Table 8 on page 19—changed
description for LOS_LVL from “LOS is disabled when
the voltage applied is less than 500 mV” to “LOS is
disabled when the voltage applied is less than
1.0 V.”
ꢀ "4.11.PLL Performance" on page 14.
ꢁ Removed OC-24 note.
Revision 1.0 to Revision 1.1
ꢀ Corrected “Revision 0.2 to Revision 1.0” Change
ꢀ Table 8 on page 19.
List.
ꢁ Added no-hysteresis text to BER_LVL.
ꢀ Updated "6.Ordering Guide" on page 22.
ꢁ Added “X” to part number.
ꢀ Table 4 on page 9
ꢁ Updated values: Jitter Tolerance (OC-3)
Revision 1.1 to Revision 1.2
Revision 1.4 to Revision 1.5
ꢀ Added Figure 5, “LOS Response,” on page 6.
ꢀ Updated Table 2 on page 7.
ꢀ Updated Table 2 on page 7.
ꢁ Added limits for V
.
ICM
ꢁ Added “Output Common Mode Voltage (DOUT)” with
updated values.
ꢁ Added “Output Common Mode Voltage (CLKOUT)” with
updated values.
ꢁ Updated V
.
OD
ꢀ Updated Table 3 on page 8.
ꢁ Updated T
ꢁ Updated T
.
Cr-D
.
Cf-D
ꢀ Updated Table 3 on page 8.
ꢁ Revised SLICE specification.
ꢁ Added “Output Clock Duty Cycle—OC-12/3.”
ꢁ Added “Loss-of-Signal Response Time” with updated
ꢀ Updated "4.8.Loss-of-Signal (LOS)" on page 13.
24
Rev. 1.5
Si5013
ꢁ Added note describing valid signal.
ꢁ Revised Figure 6, “LOS_LVL Mapping,” on page 13.
ꢀ Updated "4.10.Data Slicing Level" on page 14.
ꢁ Added Figure 8 on page 14.
ꢁ Revised text.
Rev. 1.5
25
Si5013
CONTACT INFORMATION
Silicon Laboratories Inc.
4635 Boston Lane
Austin, TX 78735
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: HighSpeed@silabs.com
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-
plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
26
Rev. 1.5
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