SI50122-A5-GM [SILICON]
Processor Specific Clock Generator, 100MHz, CMOS, PDSO10, TDFN-10;
| 型号： | SI50122-A5-GM |
| 厂家： | 
SILICON |
| 描述： | Processor Specific Clock Generator, 100MHz, CMOS, PDSO10, TDFN-10 时钟 光电二极管 外围集成电路 |
| 文件： | 总14页 (文件大小：1196K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si50122-A5/A6
CRYSTAL-LESS PCI-EXPRESS GEN 1, GEN 2, & GEN 3
DUAL OUTPUT CLOCK GENERATOR
Features
Crystal-less clock generator with Triangular spread spectrum
integrated CMEMS
profile for maximum EMI
reduction (Si50122-A6)
PCI-Express Gen 1/2/3 compliant
Two PCIe 100 MHz differential
Industrial Temperature –40 to
HCSL outputs
85 °C
One 25 MHz single-ended
2.5 V, 3.3 V Power supply
LVCMOS output
Small package 10-pin TDFN
Supports Serial (ATA) at
(2.0x2.5 mm)
100 MHz
Si50122-A5 does not support
Ordering Information:
Low power differential output
spread spectrum outputs
See page 10
buffers
Si50122-A6 supports 0.5% down
No termination resistors required
spread outputs
for differential output clocks
Pin Assignments
Applications
VSS
REFOUT
NC
1
2
3
4
5
10
9
VDD
VDD
Network Attached Storage
Multi-function Printer
Digital TV
Solid State Drives (SSD)
Wireless Access Point
Home Gateway
8
Si50122
DIFF2
DIFF2
Set top box
Digital Video Cameras
7
DIFF1
Description
6
DIFF1
VSS
Si50122-A5/A6 is a high performance, crystal-less PCIe clock generator
that can generate two 100 MHz PCIe clock and one 25 MHz LVCMOS
clock outputs. The clock outputs are compliant to PCIe Gen 1, Gen 2, and
Gen 3 specifications. The ultra-small footprint (2.0x2.5 mm) and industry-
leading low power consumption make Si50122-A5/A6 the ideal clock
solution for consumer and embedded applications where board space is
limited and low power is needed.
Patents pending
Functional Block Diagram
VDD
REFOUT
DIFF1
PLL
(SSC)
Divider
CMEMS
DIFF2
VSS
Rev 0.7 9/14
Copyright © 2014 by Silicon Laboratories
Si50122-A5/A6
Si50122-A5/A6
2
Rev 0.7
Si50122-A5/A6
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
5. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
6. Recommended Design Guideline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Rev 0.7
3
Si50122-A5/A6
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Supply Voltage (3.3 V Supply)
V
V
3.3 V ± 10%
2.97
3.3
3.63
V
DD
DD
Supply Voltage (2.5 V Supply)
2.5 V ± 10%
2.25
2.5
2.75
V
Table 2. DC Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Operating Voltage
Operating Voltage
V
V
3.3 V ± 10%
2.97
3.30
3.63
V
VDD=3.3 V
VDD=2.5 V
DD
DD
DD
2.5 V ± 10%
2.25
—
2.5
20
18
3
2.75
23
21
5
V
Operating Supply Current
I
Full active; 3.3 V ± 10%
Full active; 2.5 V ± 10%
Input Pin Capacitance
Output Pin Capacitance
mA
mA
pF
—
Input Pin Capacitance
Output Pin Capacitance
C
—
IN
C
—
—
5
pF
OUT
4
Rev 0.7
Si50122-A5/A6
Table 3. AC Electrical Specifications
Parameter
DIFF Clocks
Symbol
Test Condition
Min
Typ
Max
Unit
Duty Cycle
Measured at 0 V differential
Measured at 0 V differential
VDD = 3.3 V
T
45
—
—
—
55
100
—
%
DC
Skew
T
ps
SKEW
Output Frequency
Frequency Accuracy
Slew Rate
F
—
100
—
MHz
ppm
V/ns
OUT
All output clocks
F
—
100
5.0
ACC
t
Measured differentially from
±150 mV
0.6
—
r/f2
Crossing Point Voltage at 0.7 V
Swing
V
300
—
550
mV
OX
Voltage High
V
—
–0.3
—
—
—
1.15
—
V
V
HIGH
Voltage Low
V
S
LOW
RNG
MOD
Spread Range
Modulation Frequency
Down Spread, -A6 only
-A6 only
—
–0.5
33
%
F
30
31.5
kHz
DIFF Clocks Jitter Parameters, V = 3.3 V ±10%
DD
PCIe Gen1 Pk-Pk
Pk-Pk
PCIe Gen 1
—
—
—
—
20.7
0.8
1.4
35
2.1
2.2
0.7
ps
ps
ps
ps
GEN1
PCIe Gen2 Phase Jitter
RMS
10 kHz < F < 1.5 MHz
1.5 MHz < F < Nyquist
GEN2
PCIe Gen3 Phase Jitter
RMS
Includes PLL BW 2-4 MHz,
CDR = 10 MHz
0.4
GEN3
DIFF Clocks Jitter Parameters, V = 2.5 V ±10%
DD
PCIe Gen1 Pk-Pk
Pk-Pk
PCIe Gen 1
—
—
—
—
25
0.9
1.7
0.4
40
2.9
3.0
0.7
ps
ps
ps
ps
GEN1
PCIe Gen2 Phase Jitter
RMS
10 kHz < F < 1.5 MHz
1.5 MHz < F < Nyquist
GEN2
PCIe Gen3 Phase Jitter
RMS
Includes PLL BW 2-4 MHz,
CDR = 10 MHz
GEN3
25 MHz at 3.3 V
Duty Cycle
T
Measurement at 1.5 V
45
—
1.2
1.2
—
55
3.0
3.0
250
50
%
ns
DC
Output Rise Time
t
C = 10 pF, 20% to 80%
L
r
Output Fall Time
t
C = 10 pF, 20% to 80%
ns
f
L
Cycle to Cycle Jitter
Long Term Accuracy
Powerup Time
T
Measurement at 1.5 V
Measured at 1.5 V
—
—
ps
CCJ
ACC
L
—
ppm
Clock Stabilization from Powerup
T
First power up to first output
—
—
10
ms
STABLE
Note: Visit www.pcisig.com for complete PCIe specifications.
Rev 0.7
5
Si50122-A5/A6
Table 4. Thermal Conditions
Parameter
Symbol
Test Condition
Min
Typ
Max Unit
Temperature, Storage
T
Non-functional
–65
150
85
°C
°C
°C
S
Temperature, Operating Ambient
Temperature, Junction
T
Functional
Functional
–40
—
A
T
150
J
Dissipation, Junction to Case
Dissipation, Junction to Ambient
Ø
JEDEC (JESD 51)
JEDEC (JESD 51)
—
38.3 °C/W
90.4 °C/W
JC
JA
Ø
—
Table 5. Absolute Maximum Conditions
Parameter
Main Supply Voltage
Symbol
Test Condition
Min
Typ
Max Unit
V
—
4.6
4.6
—
V
DD_3.3V
Input Voltage
V
Relative to V
–0.5
V
DC
IN
SS
ESD Protection (Human Body Model)
Flammability Rating
ESD
JEDEC (JESD 22 - A114) 2000
UL (Class)
V
HBM
UL-94
V–0
Note: While using multiple power supplies, the voltage on any input or I/O pin cannot exceed the power pin during powerup.
Power supply sequencing is NOT required.
6
Rev 0.7
Si50122-A5/A6
2. Test and Measurement Setup
This diagram shows the test load configuration for the differential clock signals.
M easurem ent
P oint
2 pF
L1
O U T+
50
L1 = 5"
M easurem ent
P oint
2 pF
L1
O U T-
50
Figure 1. 0.7 V Differential Load Configuration
Figure 2. Differential Measurement for Differential Output Signals
(for AC Parameters Measurement)
Rev 0.7
7
Si50122-A5/A6
Figure 3. Single-ended Measurement for Differential Output Signals
(for AC Parameters Measurement)
L1 = 0.5", L2 = 5"
Measurement
Point
50
REF
L2
L1
10 pF
33
Figure 4. Single-ended Clocks with Single Load Configuration
80%
1.5V
20%
Figure 5. Single-ended Output Signal (for AC Parameter Measurement)
8
Rev 0.7
Si50122-A5/A6
3. Pin Descriptions
VSS
1
2
3
4
5
10
9
VDD
VDD
REFOUT
NC
8
Si50122
DIFF2
DIFF2
7
DIFF1
DIFF1
6
VSS
Figure 6. 10-Pin TDFN
Table 6. Si50122-Ax-GM 10-Pin TDFN Descriptions
Pin #
Name
Type
Description
GND Ground
1
VSS
O, SE 25 MHz LVCMOS clock
NC No Connect
2
3
REFOUT
NC
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
GND Ground
4
DIFF1
DIFF1
VSS
5
6
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
PWR Power supply
7
DIFF2
DIFF2
VDD
8
9
PWR Power supply
10
VDD
Rev 0.7
9
Si50122-A5/A6
4. Ordering Guide
Part Number
Spread Option
Package Type
Temperature
Si50122-A5-GM
No Spread
No Spread
10-pin TDFN
Industrial, –40 to 85 C
Si50122-A5-GMR
Si50122-A6-GM
Si50122-A6-GMR
10-pin TDFN—Tape and Reel
10-pin TDFN
Industrial, –40 to 85 C
Industrial, –40 to 85 C
Industrial, –40 to 85 C
–0.5% Spread
–0.5% Spread
10-pin TDFN—Tape and Reel
GMR
Ax
Si50122
Operating Temp Rang:e
G:- 40 to+ 85° C
Base part number
M: 10-TDFNPackage,ROHS6, Pb-free
R : Tape & Reel
A: Product Revision A
x=5: non- spread outputs
x=6:-0.5 % spread outputs
( blank) = Tubes
Figure 7. Ordering Information
10
Rev 0.7
Si50122-A5/A6
5. Package Outlines
Figure 8. 10-Pin TDFN Package Drawing
Rev 0.7
11
Si50122-A5/A6
Table 7. Package Diagram Dimensions
Symbol
Min
Nom
Max
A
0.80
0.85
0.90
A1
0.00
0.20
—
0.05
0.30
A3
0.203 REF
0.25
b
D
2.00 BSC
0.50 BSC
2.50 BSC
e
E
L
0.35
0.4
0.45
aaa
0.10
bbb
0.10
0.10
0.05
0.08
ccc
ddd
eee
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
12
Rev 0.7
Si50122-A5/A6
6. Recommended Design Guideline
3.3 V /2.5V
FB
VDD
4.7uF 0.1uF
Si 50122
Note: FB Specifications:
DC resistance 0.1–0.3
Impedance at 100 MHz > 1000
Figure 9. Recommended Application Schematic
Rev 0.7
13
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