SI8230BD-B-ISR [SILICON]
Peripheral Driver, PDSO16;
| 型号： | SI8230BD-B-ISR |
| 厂家： | 
SILICON |
| 描述： | Peripheral Driver, PDSO16 驱动 |
| 文件： | 总52页 (文件大小：424K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si823x
0.5 AND 4.0 AMP ISODRIVERS (2.5 AND 5 KVRMS
)
Features
Pin Assignments
Two completely isolated drivers 60 ns maximum propagation
in one package
delay
Up to 5 kVRMS input-to-output
isolation
Up to 1500 VDC peak driver-to-
driver differential voltage
HS/LS and dual driver versions
Independent HS and LS inputs or
SOIC-16 (Wide)
PWM input versions
1
16
15
14
13
12
11
10
9
VIA
VIB
VDDA
VOA
GNDA
NC
2
Transient immunity >30 kV/µs
3
4
5
6
7
8
VDDI
GNDI
DISABLE
DT
Overlap protection and
programmable dead time
Si8230
Si8233
Up to 8 MHz switching frequency
0.5 A peak output (Si8230/1/2)
4.0 A peak output (Si8233/4/5/6)
NC
Operating temperature range
VDDB
VOB
GNDB
–40 to +125 °C
NC
UL/VDE/CSA approval
RoHS-compliant
VDDI
SOIC-16 (Narrow)
Applications
1
16
15
14
VIA
VIB
VDDA
Power delivery systems
Motor control systems
Lighting control systems
Plasma displays
2
VOA
GNDA
NC
VDDI
GNDI
3
4
5
6
7
8
Si823013
Si8233 12
Isolated dc-dc power supplies
Solar and industrial inverters
DISABLE
DT
NC
11
10
9
VDDB
VOB
GNDB
Description
NC
The Si823x isolated driver family combines two independent, isolated
drivers into a single package. The Si8230/1/3/4 are high-side/low-side
drivers, and the Si8232/5/6 are dual drivers. Versions with peak output
currents of 0.5 A (Si8230/1/2) and 4.0 A (Si8233/4/5/6) are available. All
drivers operate with a maximum supply voltage of 24 V.
VDDI
LGA-14 (5 x 5 mm)
1
14
13
12
11
10
GNDI
VIA
VDDA
VOA
2
3
4
5
6
7
The Si823x drivers utilize Silicon Labs' proprietary silicon isolation
technology, which provides up to 5 kV
GNDA
NC
VIB
withstand voltage per UL1577,
RMS
Si8230
Si8233
VDDI
and fast 60 ns propagation times. Driver outputs can be grounded to the
same or separate grounds or connected to a positive or negative voltage.
The TTL level compatible inputs with >400 mV hysteresis are available in
individual control input (Si8230/2/3/5/6) or PWM input (Si8231/4)
configurations. High integration, low propagation delay, small installed
size, flexibility, and cost-effectiveness make the Si823x family ideal for a
wide range of isolated MOSFET/IGBT gate drive applications.
DISABLE
VDDB
7
8
DT
VOB
VDDI
GNDB
Patents Pending
Safety Approval
UL 1577 recognized
Up to 5000 Vrms for 1 minute
CSA component notice 5A
approval
VDE certification conformity
IEC 60747-5-2 (VDE 0884 Part 2)
EN 60950 (reinforced insulation)
(Pending)
IEC 60950, 61010, 60601
(reinforced insulation)
Rev. 0.3 4/10
Copyright © 2010 by Silicon Laboratories
Si823x
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si823x
Block Diagrams
PWM
VIA
VIA
DT
VDDA
VDDA
VDDA
VOA
VOA
VOA
DT
GNDA
GNDA
GNDA
Overlap Protection,
Programmable Dead
Time, Control Gating
Programmable Dead
Time, Control Gating
VDDI
VDDI
VDDI
Control Gating
UVLO
UVLO
UVLO
VDDB
VDDB
VDDB
DISABLE
DISABLE
DISABLE
GNDI
VOB
VOB
VOB
VIB
VIB
GNDB
GNDB
GNDB
GNDI
GNDI
Si8230/3
Si8231/4
Si8232/5/6
2
Rev. 0.3
Si823x
TABLE OF CONTENTS
Section
Page
1. Top-Level Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2.1. Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2.2. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3. Typical Operating Characteristics (0.5 Amp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4. Typical Operating Characteristics (4.0 Amp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5. Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
5.1. Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
5.2. Device Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
5.3. Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
5.4. Power Dissipation Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
5.5. Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
5.6. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
5.7. Programmable Dead Time and Overlap Protection . . . . . . . . . . . . . . . . . . . . . . . . .26
6. RF Radiated Emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
6.1. RF, Magnetic, and Common Mode Transient Immunity . . . . . . . . . . . . . . . . . . . . . .28
7. Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
7.1. High-Side / Low-Side Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
7.2. Dual Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
7.3. Dual Driver with Thermally Enhanced Package (Si8236) . . . . . . . . . . . . . . . . . . . . .30
8. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
9. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
10. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
11. Land Pattern: Wide-Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
12. Package Outline: Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
13. Land Pattern: Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
14. Package Outline: 14 LD LGA (5 x 5 mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
15. Land Pattern: 14 LD LGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
16. Package Outline: 14 LD LGA with Thermal Pad (5 x 5 mm) . . . . . . . . . . . . . . . . . . . . .48
17. Land Pattern: 14 LD LGA with Thermal Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Rev. 0.3
3
Si823x
1. Top-Level Block Diagrams
VDDI
VDDA
VIA
VOA
UVLO
GNDA
DT CONTROL
&
OVERLAP
PROTECTION
DT
VDDI
VDDI
VDDI
VDDB
UVLO
VOB
UVLO
DISABLE
GNDB
VIB
GNDI
Si8230/3
Figure 1. Si8230/3 Two-Input High-Side / Low-Side Isolated Drivers
VDDI
VDDA
PWM
LPWM
VOA
UVLO
GNDA
DT CONTROL
&
OVERLAP
DT
PROTECTION
VDDI
VDDI
VDDB
VDDI
UVLO
VOB
UVLO
DISABLE
GNDB
LPWM
GNDI
Si8231/4
Figure 2. Si8231/4 Single-Input High-Side / Low-Side Isolated Drivers
4
Rev. 0.3
Si823x
VDDI
VDDA
VIA
VOA
UVLO
GNDA
VDDI
VDDI
UVLO
VDDI
VDDB
DISABLE
VOB
UVLO
GNDB
VIB
GNDI
Si8232/5/6
Figure 3. Si8232/5/6 Dual Isolated Drivers
Rev. 0.3
5
Si823x
2. Electrical Specifications
Table 1. Electrical Characteristics1
4.5 V < VDDI < 5.5 V, VDDA = VDDB = 12 V or 15 V. TA = –40 to +125 °C. Typical specs at 25 °C
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
DC Specifications
Input-side Power Supply
Voltage
VDDI
4.5
6.5
—
—
5.5
24
V
V
Voltage between VDDA and
VDDA, VDDB GNDA, and VDDB and GNDB
(See “9. Ordering Guide” )
Driver Supply Voltage
Si8230/32/33/35/36
—
—
2
2
3
3
mA
mA
Input Supply Quiescent
Current
IDDI(Q)
Si8231/34
IDDA(Q),
Output Supply Quiescent
Current
Current per channel
IDDB(Q)
—
—
3.0
mA
IDDI
PWM freq = 500 kHz
PWM freq = 500 kHz
—
—
2.5
3.6
—
—
mA
mA
Input Supply Active Current
Output Supply Active Current
IDDO
IVIA, IVIB,
IPWM
–10
—
+10
µA dc
Input Pin Leakage Current
IDISABLE
VIH
–10
2.0
—
—
—
+10
—
µA dc
V
Input Pin Leakage Current
Logic High Input Threshold
Logic Low Input Threshold
Input Hysteresis
VIL
—
0.8
—
V
VIHYST
400
450
mV
(VDDA
/VDDB)
— 0.04
VOAH,
VOBH
IOA, IOB = –1 mA
—
—
V
V
Logic High Output Voltage
Logic Low Output Voltage
VOAL, VOBL
IOA, IOB = 1 mA
Si8230/1/2, Figure 4
Si8233/4/5/6, Figure 4
Si8230/1/2, Figure 5
Si8233/4/5/6, Figure 5
Si8230/1/2
—
—
—
—
—
—
—
—
—
—
0.5
4.0
0.25
2.0
5.0
1.0
15
0.04
—
IOA(SCL),
IOB(SCL)
Output Short-circuit Pulsed
Sink Current
—
A
—
IOA(SCH),
IOB(SCH)
Output Short-circuit Pulsed
Source Current
—
—
RON(SINK)
Output Sink Resistance
Si8233/4/5/6
—
Si8230/1/2
—
RON(SOURCE)
Output Source Resistance
Si8233/4/5/6
2.7
—
Notes:
1. VDDA = VDDB = 12 V for 5, 8, and 10 V UVLO devices; VDDA = VDDB = 15 V for 12.5 V UVLO devices.
2. TDD is the minimum overlap time without triggering overlap protection (Si8230/1/3/4 only).
3. The largest RDT resistor that can be used is 220 k.
6
Rev. 0.3
Si823x
Table 1. Electrical Characteristics1 (Continued)
4.5 V < VDDI < 5.5 V, VDDA = VDDB = 12 V or 15 V. TA = –40 to +125 °C. Typical specs at 25 °C
Parameter
Symbol
VDDIUV+
VDDIUV–
VDDIHYS
VDDAUV+
Test Conditions
VDDI rising
Min
3.60
3.30
—
Typ
4.0
Max
4.45
4.15
—
Units
V
VDDI Undervoltage Threshold
VDDI Undervoltage Threshold
VDDI Lockout Hysteresis
VDDI falling
3.70
250
V
mV
,
VDDA, VDDB Undervoltage
Threshold
VDDA, VDDB rising
VDDBUV+
See Figure 36 on page 25.
See Figure 37 on page 25.
See Figure 38 on page 25.
See Figure 39 on page 25.
5.20
7.50
9.60
12.4
5.80
8.60
11.1
13.8
6.30
9.40
12.2
14.8
V
V
V
V
5 V threshold
8 V threshold
10 V threshold
12.5 V threshold
VDDAUV–
,
VDDA, VDDB Undervoltage
Threshold
VDDA, VDDB falling
VDDBUV–
See Figure 36 on page 25.
See Figure 37 on page 25.
See Figure 38 on page 25.
See Figure 39 on page 25.
4.90
7.20
9.40
11.6
5.52
8.10
10.1
12.8
6.0
V
V
V
V
5 V threshold
8 V threshold
10 V threshold
12.5 V threshold
8.70
10.9
13.8
VDDAHYS
,
VDDA, VDDB
Lockout hysteresis
UVLO voltage = 5 V
UVLO voltage = 8 V
—
—
—
280
600
—
—
—
mV
mV
mV
VDDBHYS
VDDAHYS
,
VDDA, VDDB
Lockout hysteresis
VDDBHYS
VDDAHYS
,
VDDA, VDDB
Lockout hysteresis
UVLO voltage = 10 V or 12.5 V
1000
VDDBHYS
AC Specifications
Minimum Pulse Width
—
—
—
10
30
—
—
60
ns
ns
ns
tPHL, tPLH
PWD
CL = 200 pF
Propagation Delay
Pulse Width Distortion
5.60
|t
- t
|
PLH PHL
Minimum Overlap Time2
TDD
DT
DT = VDDI, No-Connect
Figure 41, RDT = 100 k
Figure 41, RDT = 6 k
—
—
—
—
—
0.4
900
70
—
—
—
12
20
ns
ns
Programmed Dead Time3
ns
ns
ns
CL = 200 pF (Si8230/1/2)
CL = 200 pF (Si8233/4/5/6)
—
tR,tF
Output Rise and Fall Time
—
Notes:
1. VDDA = VDDB = 12 V for 5, 8, and 10 V UVLO devices; VDDA = VDDB = 15 V for 12.5 V UVLO devices.
2. TDD is the minimum overlap time without triggering overlap protection (Si8230/1/3/4 only).
3. The largest RDT resistor that can be used is 220 k.
Rev. 0.3
7
Si823x
Table 1. Electrical Characteristics1 (Continued)
4.5 V < VDDI < 5.5 V, VDDA = VDDB = 12 V or 15 V. TA = –40 to +125 °C. Typical specs at 25 °C
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
Shutdown Time from
Disable True
tSD
—
—
60
ns
Restart Time from
Disable False
tRESTART
tSTART
CMTI
—
—
30
—
5
60
7
ns
µs
Time from VDD_ = VDD_UV+
to VOA, VOB = VIA, VIB
Device Start-up Time
Common Mode
Transient Immunity
VIA, VIB, PWM = VDDI or 0 V
50
—
kV/µs
Notes:
1. VDDA = VDDB = 12 V for 5, 8, and 10 V UVLO devices; VDDA = VDDB = 15 V for 12.5 V UVLO devices.
2. TDD is the minimum overlap time without triggering overlap protection (Si8230/1/3/4 only).
3. The largest RDT resistor that can be used is 220 k.
8
Rev. 0.3
Si823x
2.1. Test Circuits
Figures 4 and 5 depict sink current and source current test circuits.
VDDA = VDDB = 15 V
VDDI
(5 V)
VDD
OUT_
10
IN_
Si823x
INPUT
SCHOTTKY
+
5 V
VSS
100 µF
_
1 µF
1 µF
CER
10 µF
EL
Measure
50 ns
RSNS
0.1
VDDI
GND
200 ns
INPUT WAVEFORM
Figure 4. Sink Current Test Circuit
VDDA = VDDB = 15 V
VDDI
(5 V)
VDD
OUT_
10
IN_
Si823x
INPUT
SCHOTTKY
1 µF
+
VSS
100 µF
5 V
_
1 µF
CER
10 µF
EL
Measure
RSNS
0.1
50 ns
VDDI
GND
200 ns
INPUT WAVEFORM
Figure 5. Source Current Test Circuit
Rev. 0.3
9
Si823x
Table 2. Absolute Maximum Ratings1
Parameter
Symbol
Min
–65
–40
–0.6
–0.6
–0.5
—
Typ
—
—
—
—
—
—
—
Max
+150
+125
6.0
Units
°C
°C
V
2
Storage Temperature
T
STG
Ambient Temperature under Bias
Input-side Supply Voltage
T
A
VDDI
VDDA, VDDB
VIN
Driver-side Supply Voltage
30
V
Voltage on any pin with respect to ground
Output Drive Current per channel
Lead Solder Temperature (10 sec.)
VDD + 0.5
10
V
I
mA
°C
O
—
260
Maximum Isolation (Input to Output) (1 sec)
WB SOIC-16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
6500
2500
4250
2500
3850
650
V
V
V
V
V
V
V
V
RMS
RMS
RMS
RMS
RMS
RMS
RMS
RMS
Maximum Isolation (Output to Output) (1 sec)
WB SOIC-16
Maximum Isolation (Input to Output) (1 sec)
NB SOIC-16
Maximum Isolation (Output to Output) (1 sec)
NB SOIC-16
Maximum Isolation (Input to Output) (1 sec)
14 LD LGA without thermal pad
Maximum Isolation (Output to Output) (1 sec)
14 LD LGA without thermal pad
Maximum Isolation (Input to Output) (1 sec)
14 LD LGA with thermal pad
1850
0
Maximum Isolation (Output to Output) (1 sec)
14 LD LGA with thermal pad
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
2. VDE certifies storage temperature from –40 to 150 °C.
Table 3. Regulatory Information*
CSA
The Si823x is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.
VDE
The Si823x is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001.
UL
The Si823x is certified under UL1577 component recognition program. For more details, see File E257455.
*Note: Regulatory Certifications apply to 1.5 kV
rated devices which are production tested to 1.8 kV
for 1 sec.
for 1 sec.
RMS
RMS
rated devices which are production tested to 3.0 kV
RMS
Regulatory Certifications apply to 2.5 kV
RMS
Regulatory Certifications apply to 3.75 kV
rated devices which are production tested to 4.5 kV
for 1 sec.
RMS
RMS
Regulatory Certifications apply to 5.0 kV
rated devices which are production tested to 6.0 kV
for 1 sec.
RMS
RMS
For more information, see "9.Ordering Guide" on page 37.
10
Rev. 0.3
Si823x
Table 4. Insulation and Safety-Related Specifications
Test
Value
NBSOIC-16
14 LD
LGA w/
Pad
14 LD
LGA
Parameter
Symbol
Unit
WBSOIC-16
Condition
WBSOIC-16
5 kV
RMS
2.5 kV
2.5 kV
RMS
RMS
1.5 kV
RMS
Nominal Air Gap
(Clearance)
L(1O1)
L(1O2)
8.0
4.01
4.01
3.5
3.5
1.75
1.75
mm
mm
mm
1
Nominal External Tracking
8.0
1
(Creepage)
Minimum Internal Gap
(Internal Clearance)
0.014
0.014
0.014
0.014
DIN IEC
60112/VDE
0303 Part 1
Tracking Resistance
(Comparative Tracking
Index)
CTI
>175
>175
>175
>175
V
Resistance
(Input-Output)
12
12
12
12
R
10
10
10
10
IO
2
Capacitance
(Input-Output)
C
f = 1 MHz
1.4
4.0
1.4
4.0
1.4
4.0
1.4
4.0
pF
pF
IO
2
3
C
Input Capacitance
I
Notes:
1. The values in this table correspond to the nominal creepage and clearance values as detailed in “10. Package Outline:
16-Pin Wide Body SOIC” , “12. Package Outline: Narrow Body SOIC” , “14. Package Outline: 14 LD LGA (5 x 5 mm)” ,
and “16. Package Outline: 14 LD LGA with Thermal Pad (5 x 5 mm)” . VDE certifies the clearance and creepage limits
as 4.7 mm minimum for the NB SOIC-16 and 8.5 mm minimum for the WB SOIC-16 package. UL does not impose a
clearance and creepage minimum for component level certifications. CSA certifies the clearance and creepage limits
as 3.9 mm minimum for the NB SOIC 16 and 7.6 mm minimum for the WB SOIC-16 package.
2. To determine resistance and capacitance, the Si823x is converted into a 2-terminal device. Pins 1–8 (1-7, 14 LD LGA)
are shorted together to form the first terminal and pins 9–16 (8-14, 14 LD LGA) are shorted together to form the second
terminal. The parameters are then measured between these two terminals.
3. Measured from input pin to ground.
Table 5. IEC 60664-1 (VDE 0884 Part 2) Ratings
Specification
14 LD
Parameter
Test Conditions
WB
NB
14 LD
LGA
LGA
SOIC-16 SOIC-16
w/ Pad
Basic Isolation Group
Material Group
IIIa
I-IV
I-IV
I-III
I-III
IIIa
I-IV
I-III
I-II
IIIa
I-IV
I-III
I-II
IIIa
I-IV
I-III
I-II
Rated Mains Voltages < 150 V
Rated Mains Voltages < 300 V
Rated Mains Voltages < 400 V
Rated Mains Voltages < 600 V
RMS
RMS
RMS
RMS
Installation Classification
I-II
I-II
I-I
Rev. 0.3
11
Si823x
Table 6. IEC 60747-5-2 Insulation Characteristics*
Characteristic
Parameter
Symbol
Test Condition
Unit
WB
NB SOIC-16 14 LD LGA
SOIC-16
14 LD LGA
w/ Pad
Maximum Working Insulation
Voltage
V
891
560
373
V peak
IORM
Method a
After Environmen-
tal Tests
Subgroup 1
1590
896
597
(V
x 1.6 = V
,
IORM
PR
t = 60 sec, Partial
m
Discharge < 5 pC)
Method b1
(V
x 1.875 = V
, 100%
IORM
PR
V
V peak
Input to Output Test Voltage
PR
Production Test,
1375
1018
1050
672
700
448
t = 1 sec,
m
Partial Discharge <
5 pC)
After Input and/or
Safety Test
Subgroup 2/3
(V
x 1.2 = V
,
IORM
PR
t = 60 sec, Partial
m
Discharge < 5 pC)
Highest Allowable Overvolt-
age (Transient Overvoltage,
V
6000
2
4000
2
2650
2
V peak
TR
t
= 10 sec)
TR
Pollution Degree (DIN VDE
0110, Table 1)
Insulation Resistance at T ,
9
9
9
S
R
>10
>10
>10
S
V
= 500 V
IO
*Note: The Si823x is suitable for basic electrical isolation within the safety limit data. Maintenance of the safety data is
ensured by protective circuits. The Si823x provides a climate classification of 40/125/21.
12
Rev. 0.3
Si823x
Table 7. IEC Safety Limiting Values1
14 LD
LGA w/
Pad
WB
NB
14
Parameter
Symbol
Test Condition
Unit
SOIC-16 SOIC-16 LD LGA
T
150
50
150
50
150
50
150
100
°C
Case Temperature
S
= 100 °C/W (WB SOIC-16),
JA
105 °C/W (NB SOIC-16, 14 LD LGA),
50 °C/W (14 LD LGA w/ Pad)
I
mA
W
Safety Input Current
Device Power
S
V
= 5.5 V,
DDI
V
= V
= 24 V,
DDA
DDB
T = 150 °C, T = 25 °C
J
A
P
1.2
1.2
1.2
1.2
D
2
Dissipation
Notes:
1. Maximum value allowed in the event of a failure. Refer to the thermal derating curve in Figure 6.
2. The Si823x is tested with V
= 5.5 V, V
= V
= 24 V, T = 150 ºC, C = 100 pF, input 2 MHz 50% duty cycle
DDI
DDA
DDB J L
square wave.
Rev. 0.3
13
Si823x
Table 8. Thermal Characteristics
Parameter
14 LD
LGA w/
Pad
WB
SOIC-16
NB
SOIC-16
14 LD
LGA
Symbol
Unit
IC Junction-to-Air Thermal Resis-
tance
100
105
105
50
°C/W
JA
60
50
40
30
20
10
VDDI = 5.5 V
VDDA, VDDB = 24 V
0
0
50
100
150
200
Case Temperature (ºC)
Figure 6. WB SOIC-16, NB SOIC-16, 14 LD LGA Thermal Derating Curve, Dependence of Safety
Limiting Values with Case Temperature per DIN EN 60747-5-2
120
VDDI = 5.5 V
VDDA, VDDB = 24 V
100
80
60
40
20
0
0
50
100
150
200
Case Temperature (ºC)
Figure 7. 14 LD LGA with Pad Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
14
Rev. 0.3
Si823x
2.2. Theory of Operation
The operation of an Si823x channel is analogous to that of an opto coupler and gate driver, except an RF carrier is
modulated instead of light. This simple architecture provides a robust isolated data path and requires no special
considerations or initialization at start-up. A simplified block diagram for a single Si823x channel is shown in
Figure 8.
Transmitter
Receiver
Driver
VDD
RF
OSCILLATOR
Semiconductor-
Based Isolation
Barrier
Dead
time
control
B
MODULATOR
DEMODULATOR
A
0.5 to 4 A
peak
Gnd
Figure 8. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier.
Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The
Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the
result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it
provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See
Figure 9 for more details.
Input Signal
Modulation Signal
Output Signal
Figure 9. Modulation Scheme
Rev. 0.3
15
Si823x
3. Typical Operating Characteristics (0.5 Amp)
The typical performance characteristics depicted in Figures 10 through 21 are for information purposes only. Refer
to Table 1 on page 6 for actual specification limits.
10
7
Duty Cycle = 50%
CL = 100 pF
1 Channel Switching
8
6
4
2
0
1MHz
6
5
4
3
2
1
0
Tfall
500kHz
100kHz
Trise
50 kHz
VDD=12V, 25°C
CL = 100 pF
9
14
19
24
VDDA Supply Voltage (V)
9
12
15
18
21
24
VDDA Supply (V)
Figure 13. Supply Current vs. Supply Voltage
Figure 10. Rise/Fall Time vs. Supply Voltage
30
5
4
25
H-L
3
20
VDDA = 15V,
f = 250kHz, CL = 0 pF
Duty Cycle = 50%
2 Channels Switching
2
1
L-H
15
VDD=12V, 25°C
CL = 100 pF
-50
0
50
Temperature (°C)
100
10
9
12
15
18
21
24
VDDA Supply (V)
Figure 14. Supply Current vs. Temperature
Figure 11. Propagation Delay vs. Supply
Voltage
40
35
Trise
30
4
Duty Cycle = 50%
25
CL = 0 pF
1 Channel Switching
3.5
3
1MHz
20
15
10
5
Tfall
500kHz
100kHz
2.5
2
VDD=12V, 25°C
1.5
1
0
50 kHz
0.0
0.5
1.0
Load (nF)
1.5
2.0
9
14
19
24
VDDA Supply Voltage (V)
Figure 15. Rise/Fall Time vs. Load
Figure 12. Supply Current vs. Supply Voltage
16
Rev. 0.3
Si823x
4
3.75
3.5
3.25
3
50
45
40
35
30
25
20
15
10
L-H
H-L
2.75
2.5
2.25
2
VDD=12V, Vout=VDD-5V
VDD=12V, 25°C
10
15
20
25
0.0
0.5
1.0
Load (nF)
1.5
2.0
Supply Voltage (V)
Figure 16. Propagation Delay vs. Load
Figure 19. Output Source Current vs. Supply
Voltage
30
7
6.75
6.5
25
L-H
6.25
6
20
5.75
5.5
H-L
5.25
5
15
4.75
4.5
VDD=12V, Load = 200pF
10
4.25
4
VDD=12V, Vout=5V
-10 20
-40
-20
0
20
40
60
80
100
120
-40
50
80
110
Temperature (°C)
Temperature (°C)
Figure 17. Propagation Delay vs. Temperature
Figure 20. Output Sink Current vs. Temperature
9
8
7
6
5
3.5
3.25
3
2.75
2.5
VDD=12V, Vout=5V
2.25
4
VDD=12V, Vout=VDD-5V
10
12
14
16
18
20
22
24
2
-40
-10
20
50
80
110
Supply Voltage (V)
Temperature (°C)
Figure 18. Output Sink Current vs. Supply
Voltage
Figure 21. Output Source Current vs.
Temperature
Rev. 0.3
17
Si823x
4. Typical Operating Characteristics (4.0 Amp)
The typical performance characteristics depicted in Figures 22 through 33 are for information purposes only. Refer
to Table 1 on page 6 for actual specification limits.
10
14
12
10
8
Duty Cycle = 50%
CL = 100 pF
1MHz
1 Channel Switching
8
6
4
2
0
Tfall
500kHz
6
Trise
100kHz
50 kHz
4
2
0
9
14
19
24
VDD=12V, 25°C
CL = 100 pF
VDDA Supply Voltage (V)
Figure 25. Supply Current vs. Supply Voltage
9
12
15
18
21
24
VDDA Supply (V)
10
8
Figure 22. Rise/Fall Time vs. Supply Voltage
30
6
VDDA = 15V,
f = 250kHz, CL = 0 pF
4
25
Duty Cycle = 50%
2 Channels Switching
2
L-H
0
20
-50
0
50
100
H-L
Temperature (°C)
15
Figure 26. Supply Current vs. Temperature
VDD=12V, 25°C
CL = 100 pF
10
40
35
9
12
15
18
21
24
VDDA Supply (V)
Trise
30
Figure 23. Propagation Delay vs. Supply
Voltage
25
20
15
10
5
Tfall
14
Duty Cycle = 50%
CL = 0 pF
1 Channel Switching
12
10
8
1MHz
VDD=12V, 25°C
0
500kHz
0
1
2
3
4
5
6
7
8
9
10
6
Load (nF)
4
100kHz
50 kHz
2
Figure 27. Rise/Fall Time vs. Load
0
9
14
19
24
VDDA Supply Voltage (V)
Figure 24. Supply Current vs. Supply Voltage
18
Rev. 0.3
Si823x
4
3.75
3.5
3.25
3
50
45
40
35
30
25
20
15
10
H-L
L-H
2.75
2.5
2.25
2
VDD=12V, Vout=VDD-5V
VDD=12V, 25°C
10
15
20
25
0
1
2
3
4
5
6
7
8
9
10
Supply Voltage (V)
Load (nF)
Figure 31. Output Source Current vs. Supply
Voltage
Figure 28. Propagation Delay vs. Load
30
7
6.75
6.5
H-L
25
20
15
10
6.25
6
L-H
5.75
5.5
5.25
5
4.75
4.5
4.25
4
VDD=12V, Vout=5V
-10 20
VDD=12V, Load = 200pF
-40
50
80
110
-40
-20
0
20
40
60
80
100
120
Temperature (°C)
Temperature (°C)
Figure 32. Output Sink Current vs. Temperature
Figure 29. Propagation Delay vs. Temperature
3.5
3.25
3
9
8
7
6
5
2.75
2.5
2.25
VDD=12V, Vout=5V
VDD=12V, Vout=VDD-5V
4
2
10
12
14
16
18
20
22
24
-40
-10
20
50
80
110
Supply Voltage (V)
Temperature (°C)
Figure 30. Output Sink Current vs. Supply
Voltage
Figure 33. Output Source Current vs.
Temperature
Rev. 0.3
19
Si823x
5. Application Information
The Si823x family of isolated drivers consists of high-side, low-side, and dual driver configurations.
5.1. Products
Table 9 shows the configuration and functional overview for each product in this family.
Table 9. Si823x Family Overview
Part Number
Configuration
Overlap
Protection
Programmable
Dead Time
Inputs
Peak Output
Current (A)
Si8230
Si8231
Si8232
Si8233
Si8234
Si8235/6
High-Side/Low-Side
High-Side/Low-Side
Dual Driver
VIA, VIB
PWM
0.5
0.5
0.5
4.0
4.0
4.0
—
—
VIA, VIB
VIA, VIB
PWM
High-Side/Low-Side
High-Side/Low-Side
Dual Driver
—
—
VIA, VIB
5.2. Device Behavior
Table 10 contains truth tables for the Si8230/3, Si8231/4, and Si8232/5/6 families.
Table 10. Si823x Family Truth Table*
Si8230/3 (High-Side/Low-Side) Truth Table
Inputs
Output
VDDI State Disable
Notes
VIA
VIB
VOA
VOB
Output transition occurs after internal dead time
expires.
L
L
L
Powered
Powered
Powered
Powered
L
L
L
L
L
L
L
Output transition occurs after internal dead time
expires.
H
L
H
L
L
Output transition occurs after internal dead time
expires.
H
H
H
L
Invalid state. Output transition occurs after internal
dead time expires.
H
Output returns to input state within 7 µs of VDDI
power restoration.
X
X
X
X
Unpowered
Powered
X
H
L
L
L
L
Device is disabled.
Si8231/4 (PWM Input High-Side/Low-Side) Truth Table
Output
PWM Input
VDDI State Disable
Notes
VOA
VOB
Output transition occurs after internal dead time
expires.
H
L
Powered
Powered
L
L
H
L
Output transition occurs after internal dead time
expires.
L
H
Output returns to input state within 7 µs of VDDI
power restoration.
X
X
Unpowered
Powered
X
H
L
L
L
L
Device is disabled.
*Note: This truth table assumes VDDA and VDDB are powered. If VDDA or VDDB power is lost, the respective output state
(VOA or VOB) is undetermined.
20
Rev. 0.3
Si823x
Table 10. Si823x Family Truth Table* (Continued)
Si8232/5/6 (Dual Driver) Truth Table
Output
Inputs
VDDI State Disable
Notes
VIA
VIB
VOA
VOB
Output transition occurs immediately
(no internal dead time).
L
L
L
Powered
Powered
Powered
Powered
L
L
L
L
L
L
Output transition occurs immediately
(no internal dead time).
H
L
L
H
H
H
L
Output transition occurs immediately
(no internal dead time).
H
H
Output transition occurs immediately
(no internal dead time).
H
H
Output returns to input state within 7 µs of VDDI
power restoration.
X
X
X
X
Unpowered
Powered
X
H
L
L
L
L
Device is disabled.
*Note: This truth table assumes VDDA and VDDB are powered. If VDDA or VDDB power is lost, the respective output state
(VOA or VOB) is undetermined.
Rev. 0.3
21
Si823x
5.3. Power Supply Connections
Isolation requirements mandate individual supplies for VDDI, VDDA, and VDDB. The decoupling caps for these
supplies must be placed as close to the VDD and GND pins of the Si823x as possible. The optimum values for
these capacitors depend on load current and the distance between the chip and the regulator that powers it. Low
effective series resistance (ESR) capacitors, such as Tantalum, are recommended.
5.4. Power Dissipation Considerations
Proper system design must assure that the Si823x operates within safe thermal limits across the entire load range.
The Si823x total power dissipation is the sum of the power dissipated by bias supply current, internal switching
losses, and power delivered to the load. Equation 1 shows total Si823x power dissipation. In a non-overlapping
system, such as a high-side/low-side driver, n = 1. For a dual driver with each driver having an independent load, n
can have a maximum value of 2, corresponding to a 100% overlap between the two outputs.
PD = V
I
DDI DDI + 2V I
DDO QOUT + CintVDDO2F + 2nCLVDDO2F
where:
PD is the total Si823x device power dissipation (W)
IDDI is the input-side maximum bias current (3 mA)
IQOUT is the driver die maximum bias current (2.5 mA)
Cint is the internal parasitic capacitance (75 pF for the 0.5 A driver and 370 pF for the 4.0 A driver)
VDDI is the input-side VDD supply voltage (4.5 to 5.5 V)
VDDO is the driver-side supply voltage (10 to 24 V)
F is the switching frequency (Hz)
n is the overlap constant (max value = 2)
Equation 1.
The maximum power dissipation allowable for the Si823x is a function of the package thermal resistance, ambient
temperature, and maximum allowable junction temperature, as shown in Equation 2:
T
jmax – TA
---------------------------
PDmax
where:
ja
PDmax = Maximum Si823x power dissipation (W)
Tjmax = Si823x maximum junction temperature (145 °C)
TA = Ambient temperature (°C)
ja = Si823x junction-to-air thermal resistance (105 °C/W)
F = Si823x switching frequency (Hz)
Equation 2.
Substituting values for PDMAX TjMAX, TA, and into Equation 2 results in a maximum allowable total power
ja
dissipation of 1.1 W. Maximum allowable load is found by substituting this limit and the appropriate datasheet
values from Table 1 on page 6 into Equation 1 and simplifying. The result is Equation 3 (0.5 A driver) and
Equation 4 (4.0 A driver), both of which assume VDDI = 5 V and VDDA = VDDB = 18 V.
1.4 10–3
–11
–10
--------------------------
CL(MAX)
=
– 7.5 10
F
Equation 3.
1.4 10–3
--------------------------
CL(MAX)
=
– 3.7 10
F
Equation 4.
22
Rev. 0.3
Si823x
Equation 1 and Equation 2 are graphed in Figure 34 where the points along the load line represent the package
dissipation-limited value of CL for the corresponding switching frequency.
1 6 ,0 0 0
0 .5 A D rive r (p F )
1 4 ,0 0 0
4 A D rive r (p F )
1 2 ,0 0 0
1 0 ,0 0 0
8 ,0 0 0
6 ,0 0 0
4 ,0 0 0
2 ,0 0 0
0
F re q u e n c y (K h z)
Figure 34. Max Load vs. Switching Frequency
Rev. 0.3
23
Si823x
5.5. Layout Considerations
It is most important to minimize ringing in the drive path and noise on the Si823x VDD lines. Care must be taken to
minimize parasitic inductance in these paths by locating the Si823x as close to the device it is driving as possible.
In addition, the VDD supply and ground trace paths must be kept short. For this reason, the use of power and
ground planes is highly recommended. A split ground plane system having separate ground and VDD planes for
power devices and small signal components provides the best overall noise performance.
5.6. Device Operation
Device behavior during start-up, normal operation and shutdown is shown in Figure 35, where UVLO+ and UVLO-
are the positive-going and negative-going thresholds respectively. Note that outputs VOA and VOB default low
when input side power supply (VDDI) is not present.
5.6.1. Device Startup
Outputs VOA and VOB are held low during power-up until VDD is above the UVLO threshold for time period
tSTART. Following this, the outputs follow the states of inputs VIA and VIB.
5.6.2. Under Voltage Lockout
Under Voltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or
when VDD is below its specified operating circuits range. The input (control) side, Driver A and Driver B, each have
their own under voltage lockout monitors.
The Si823x input side enters UVLO when VDDI < VDDI
, and exits UVLO when VDDI > VDDI
. The driver
UV+
UV–
outputs, VOA and VOB, remain low when the input side of the Si823x is in UVLO and their respective VDD supply
(VDDA, VDDB) is within tolerance. Each driver output can enter or exit UVLO independently. For example, VOA
unconditionally enters UVLO when VDDA falls below VDDA
and exits UVLO when VDDA rises above
UV–
VDDA
.
UV+
UVLO+
VDDHYS
UVLO-
VDDI
UVLO+
UVLO-
VDDHYS
VDDA
VIA
DISABLE
tSD
tRESTART
tPHL
tPLH
tSD
tSTART
tSTART
tSTART
VOA
Figure 35. Device Behavior during Normal Operation and Shutdown
24
Rev. 0.3
Si823x
5.6.3. Under Voltage Lockout (UVLO)
The UVLO circuit unconditionally drives VO low when VDD is below the lockout threshold. Referring to Figures 36
through 39, upon power up, the Si823x is maintained in UVLO until VDD rises above VDD . During power down,
UV+
the Si823x enters UVLO when VDD falls below the UVLO threshold plus hysteresis (i.e., VDD < VDD
–
UV+
VDD
).
HYS
VDDUV+ (Typ)
VDDUV+ (Typ)
3.5
4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5
8.5
9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5
Supply Voltage (VDD - VSS) (V)
Supply Voltage (VDD - VSS) (V)
Figure 36. Si823x UVLO Response (5 V)
Figure 38. Si823x UVLO Response (10 V)
VDDUV+ (Typ)
VDDUV+ (Typ)
11.3 11.8 12.3 12.8 13.3 13.8 14.3 14.8 15.3
6.0
6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
Supply Voltage (VDD - VSS) (V)
Supply Voltage (VDD - VSS) (V)
Figure 39. Si823x UVLO Response (12.5 V)
Figure 37. Si823x UVLO Response (8 V)
Rev. 0.3
25
Si823x
5.6.4. Control Inputs
VIA, VIB, and PWM inputs are high-true, TTL level-compatible logic inputs. A logic high signal on VIA or VIB
causes the corresponding output to go high. For PWM input versions (Si8231/4), VOA is high and VOB is low when
the PWM input is high, and VOA is low and VOB is high when the PWM input is low.
5.6.5. Disable Input
When brought high, the DISABLE input unconditionally drives VOA and VOB low regardless of the states of VIA
and VIB. Device operation terminates within tSD after DISABLE = V and resumes within tRESTART after
IH
DISABLE = V . The DISABLE input has no effect if VDDI is below its UVLO level (i.e. VOA, VOB remain low).
IL
5.7. Programmable Dead Time and Overlap Protection
All high-side/low-side drivers (Si8230/1/3/4) include programmable overlap protection to prevent outputs VOA and
VOB from being high at the same time. These devices also include programmable dead time, which adds a user-
programmable delay between transitions of VOA and VOB (Figure 26.A). When enabled, dead time is present on
all transitions, even after overlap recovery (Figure 26.B). The amount of dead time delay (DT) is programmed by a
single resistor (RDT) connected from the DT input to ground per Equation 5. Note that the dead time pin can be
tied to VDDI or left floating to provide a nominal dead time at approximately 400 ps.
DT 10 RDT
where:
DT= dead time (ns)
and
RDT= dead time programming resistor (k
Equation 5.
The device driving VIA and VIB should provide a minimum dead time of TDD to avoid activating overlap protection.
Input/output timing waveforms for the two-input drivers are shown in Figure 40, and dead time waveforms are
shown in Figure 41.
Ref
A
B
C
D
E
Description
VIA
Normal operation: VIA high, VIB low.
Normal operation: VIB high, VIA low.
Contention: VIA = VIB = high.
`
VIB
Recovery from contention: VIA transitions low.
Normal operation: VIA = VIB = low.
Normal operation: VIA high, VIB low.
Contention: VIA = VIB = high.
VOA
VOB
F
G
H
I
Recovery from contention: VIB transitions low.
Normal operation: VIB transitions high.
A
B
C
D
E
F
G
H
I
Figure 40. Input / Output Waveforms for High-Side / Low-Side Two-Input Drivers
26
Rev. 0.3
Si823x
OVERLAP
OVERLAP
VOB
VIA
VIB
VIA
VIB
50%
DT
DT
DT
DT
90%
VOA
VOA
VOB
10%
DT
DT
90%
VOB
10%
B. Dead Time Operation During Overlap
A. Typical Dead Time Operation
Figure 41. Dead Time Waveforms for High-Side/Low-Side Two-Input Drivers
Rev. 0.3
27
Si823x
6. RF Radiated Emissions
The Si823x family uses a RF carrier frequency of approximately 700 MHz. This results in a small amount of
radiated emissions at this frequency and its harmonics. The radiation is not from the IC but, rather, is due to a small
amount of RF energy driving the isolated ground planes which can act as a dipole antenna.
The unshielded Si8230 evaluation board passes FCC Class B (Part 15) requirements. Table 11 shows measured
emissions compared to FCC requirements. Note that the data reflects worst-case conditions where all inputs are
tied to logic 1 and the RF transmitters are fully active.
Radiated emissions can be reduced if the circuit board is enclosed in a shielded enclosure or if the PCB is a less
efficient antenna.
Table 11. Radiated Emissions
Frequency Measured FCC Spec Compared to
(MHz)
(dBµV/m) (dBµV/m)
Spec (dB)
712
29
39
42
43
44
44
44
37
54
54
54
54
54
54
–8
1424
2136
2848
4272
4984
5696
–15
–12
–11
–10
–10
–10
6.1. RF, Magnetic, and Common Mode Transient Immunity
The Si823x families have very high common mode transient immunity while transmitting data. This is typically
measured by applying a square pulse with very fast rise/fall times between the isolated grounds. Measurements
show no failures at 30 kV/µs (minimum). During a high surge event, the output may glitch low for up to 20–30 ns,
but the output corrects immediately after the surge event.
The Si823x families pass the industrial requirements of CISPR24 for RF immunity of 10 V/m using an unshielded
evaluation board. As shown in Figure 20, the isolated ground planes form a parasitic dipole antenna. The PCB
should be laid-out to not act as an efficient antenna for the RF frequency of interest. RF susceptibility is also
significantly reduced when the end system is housed in a metal enclosure, or otherwise shielded.
The Si823x digital isolator can be used in close proximity to large motors and various other magnetic-field
producing equipment. In theory, data transmission errors can occur if the magnetic field is too large and the field is
too close to the isolator. However, in actual use, the Si823x devices provide extremely high immunity to external
magnetic fields and have been independently evaluated to withstand magnetic fields of at least 1000 A/m
according to the IEC 61000-4-8 and IEC 61000-4-9 specifications.
GND1
GND2
Isolator
Dipole
Antenna
Figure 42. Dipole Antenna
28
Rev. 0.3
Si823x
7. Applications
The following examples illustrate typical circuit configurations using the Si823x.
7.1. High-Side / Low-Side Driver
Figure 43A shows the Si8230/3 controlled using the VIA and VIB input signals, and Figure 43B shows the Si8231/4
controlled by a single PWM signal.
VDD2
VDD2
D1
D1
VDDI
VDDI
C2
1 µF
C2
1 µF
VDDI
GNDI
VDDI
C1
1uF
C1
1uF
1500 V max
1500 V max
VDDA
VDDA
GNDI
PWM
CB
CB
Q1
Q1
OUT1
OUT2
VIA
VIB
PWMOUT
CONTROLLER
I/O
VOA
VOA
GNDA
GNDA
DT
DT
RDT
RDT
CONTROLLER
Si8230/3
Si8231/4
VDDB
VDDB
VDDB
VDDB
C3
10uF
C3
10uF
I/O
DISABLE
DISABLE
GNDB
VOB
GNDB
VOB
Q2
Q2
A
B
Figure 43. Si823x in Half-Bridge Application
For both cases, D1 and CB form a conventional bootstrap circuit that allows VOA to operate as a high-side driver
for Q1, which has a maximum drain voltage of 1500 V. VOB is connected as a conventional low-side driver. Note
that the input side of the Si823x requires VDD in the range of 4.5 to 5.5 V, while the VDDA and VDDB output side
supplies must be between 6.5 and 24 V with respect to their respective grounds. The boot-strap start up time will
depend on the CB cap chosen. VDD2 is usually the same as VDDB. Also note that the bypass capacitors on the
Si823x should be located as close to the chip as possible. Moreover, it is recommended that 0.1 and 10 µF bypass
capacitors be used to reduce high frequency noise and maximize performance.
Rev. 0.3
29
Si823x
7.2. Dual Driver
Figure 44 shows the Si823x configured as a dual driver. Note that the drain voltages of Q1 and Q2 can be
referenced to a common ground or to different grounds with as much as 1500 V dc between them.
VDDI
VDDI
Q1
C1
10 µF
VOA
GNDI
VDDA
VDDA
GNDA
VIA
VIB
PH1
PH2
C2
10 µF
CONTROLLER
Si8235/6
VDDB
VDDB
GNDB
C3
I/O
DISABLE
10 µF
Q2
VOB
Figure 44. Si8235 in a Dual Driver Application
7.3. Dual Driver with Thermally Enhanced Package (Si8236)
The thermal pad of the Si8236 must be connected to a heat spreader to lower thermal resistance. Generally, the
larger the thermal shield’s area, the lower the thermal resistance. It is recommended that a thermal vias also be
used to add mass to the shield. Vias generally have much more mass than the shield alone and consume less
space, thus reducing thermal resistance more effectively. While the heat spreader is not generally a circuit ground,
it is a good reference plane for the Si8236 and is also useful as a shield layer for EMI reduction.
2
With a 10mm thermal plane on the outer layers (including 20 thermal vias), the thermal impedance of the Si8236
was measured at 50 °C/W. This is a significant improvement over the Si835 which does not include a thermal pad.
The Si8235’s thermal resistance was measured at 105 °C /W.
30
Rev. 0.3
Si823x
8. Pin Descriptions
SOIC-16 (Narrow)
SOIC-16 (Wide)
1
16
15
14
13
12
11
10
9
1
16
15
14
VIA
VIB
VIA
VIB
VDDA
VOA
GNDA
NC
VDDA
VOA
GNDA
NC
2
2
3
4
5
6
7
8
3
4
5
6
7
8
VDDI
GNDI
DISABLE
DT
VDDI
GNDI
DISABLE
DT
Si8230
Si8233
Si823013
Si8233 12
NC
NC
11
10
9
VDDB
VOB
GNDB
VDDB
VOB
GNDB
NC
NC
VDDI
VDDI
Table 12. Si8230/3 Two-Input HS/LS Isolated Driver (SOIC-16)
Pin
1
Name
VIA
Description
Non-inverting logic input terminal for Driver A.
Non-inverting logic input terminal for Driver B.
2
VIB
3
VDDI Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
GNDI Input-side ground terminal.
4
5
DISABLE Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW. It is
strongly recommended that this input be connected to external logic level to avoid erroneous
operation due to capacitive noise coupling.
6
DT
Dead time programming input. The value of the resistor connected from DT to ground sets the
dead time between output transitions of VOA and VOB. Defaults to 1 ns dead time when con-
nected to VDDI or left open (see "5.7.Programmable Dead Time and Overlap Protection" on
page 26).
7
NC
No connection.
8
VDDI Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
GNDB Ground terminal for Driver B.
9
10
11
12
13
14
15
16
VOB Driver B output (low-side driver).
VDDB Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V.
NC
NC
No connection.
No connection.
GNDA Ground terminal for Driver A.
VOA Driver A output (high-side driver).
VDDA Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V.
Rev. 0.3
31
Si823x
SOIC-16 (Narrow)
SOIC-16 (Wide)
1
16
15
14
13
12
11
10
9
1
16
15
14
PWM
NC
PWM
NC
VDDA
VOA
GNDA
NC
VDDA
VOA
GNDA
NC
2
2
3
4
5
6
7
8
3
4
5
6
7
8
VDDI
GNDI
VDDI
GNDI
DISABLE
DT
Si8231
Si8234
Si823113
Si8234 12
DISABLE
DT
NC
NC
11
10
9
VDDB
VOB
GNDB
VDDB
VOB
GNDB
NC
NC
VDDI
VDDI
Table 13. Si8231/4 PWM Input HS/LS Isolated Driver (SOIC-16)
Description
Pin
1
Name
PWM PWM input.
NC No connection.
2
3
VDDI Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
GNDI Input-side ground terminal.
4
5
DISABLE Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW. It is
strongly recommended that this input be connected to external logic level to avoid erroneous
operation due to capacitive noise coupling.
6
DT
Dead time programming input. The value of the resistor connected from DT to ground sets the
dead time between output transitions of VOA and VOB. Defaults to 1 ns dead time when con-
nected to VDDI or left open (see "5.7.Programmable Dead Time and Overlap Protection" on
page 26).
7
NC
No connection.
8
VDDI Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
GNDB Ground terminal for VOB driver output.
9
10
11
12
13
14
15
16
VOB Driver B output (low-side driver).
VDDB Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V.
NC
NC
No connection.
No connection.
GNDA Ground terminal for Driver A.
VOA Driver A output (high-side driver).
VDDA Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V.
32
Rev. 0.3
Si823x
SOIC-16 (Narrow)
SOIC-16 (Wide)
1
16
15
14
13
12
11
10
9
1
16
15
14
VIA
VIB
VIA
VIB
VDDA
VOA
GNDA
NC
VDDA
VOA
GNDA
NC
2
2
3
4
5
6
7
8
3
4
5
6
7
8
VDDI
GNDI
VDDI
GNDI
Si8232
Si8235
Si823213
Si8235 12
DISABLE
DISABLE
NC
NC
11
10
9
VDDB
VOB
GNDB
VDDB
VOB
GNDB
NC
NC
NC
NC
VDDI
VDDI
Table 14. Si8232/5 Dual Isolated Driver (SOIC-16)
Description
Pin
1
Name
VIA
Non-inverting logic input terminal for Driver A.
Non-inverting logic input terminal for Driver B.
2
VIB
3
VDDI Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
GNDI Input-side ground terminal.
4
5
DISABLE Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW. It is
strongly recommended that this input be connected to external logic level to avoid erroneous
operation due to capacitive noise coupling.
6
NC
NC
No connection.
No connection.
7
8
VDDI Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
GNDB Ground terminal for VOB driver output.
9
10
11
12
13
14
15
16
VOB
Driver B output.
VDDB Driver output VOB power supply voltage terminal; connect to a source of 6.5 to 24 V.
NC
NC
No connection.
No connection.
GNDA Ground terminal for Driver A.
VOA Driver B output.
VDDA Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V.
Rev. 0.3
33
Si823x
LGA-14 (5 x 5 mm)
1
14
13
12
11
10
GNDI
VIA
VDDA
VOA
2
3
4
5
GNDA
NC
VIB
VDDI
Si8233
DISABLE
VDDB
6
7
7
8
DT
VOB
VDDI
GNDB
Table 15. Si8233 Two-Input HS/LS Isolated Driver (14 LD LGA)
Pin
GNDI
VIA
Name
Description
1
2
3
4
5
Input-side ground terminal.
Non-inverting logic input terminal for Driver A.
VIB
Non-inverting logic input terminal for Driver B.
VDDI
DISABLE
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW.
It is strongly recommended that this input be connected to external logic level to avoid
erroneous operation due to capacitive noise coupling.
DT
6
Dead time programming input. The value of the resistor connected from DT to ground
sets the dead time between output transitions of VOA and VOB. Defaults to 1 ns dead
time when connected to VDDI or left open (see"5.7.Programmable Dead Time and
Overlap Protection" on page 26).
VDDI
GNDB
VOB
7
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
Ground terminal for Driver B.
8
9
Driver B output (low-side driver).
VDDB
NC
10
11
12
13
14
Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V.
No connection.
GNDA
VOA
Ground terminal for Driver A.
Driver A output (high-side driver).
VDDA
Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V.
34
Rev. 0.3
Si823x
LGA-14 (5 x 5 mm)
1
14
13
12
11
10
GNDI
PWM
VDDA
VOA
2
3
4
5
GNDA
NC
NC
VDDI
Si8234
DISABLE
VDDB
6
7
7
8
DT
VOB
VDDI
GNDB
Table 16. Si8234 PWM Input HS/LS Isolated Driver (14 LD LGA)
Pin
GNDI
PWM
NC
Name
Description
1
2
3
4
5
Input-side ground terminal.
PWM input.
No connection.
VDDI
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
DISABLE
Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW.
It is strongly recommended that this input be connected to external logic level to avoid
erroneous operation due to capacitive noise coupling.
DT
6
Dead time programming input. The value of the resistor connected from DT to ground
sets the dead time between output transitions of VOA and VOB. Defaults to 1 ns dead
time when connected to VDDI or left open (see "5.7.Programmable Dead Time and
Overlap Protection" on page 26).
VDDI
GNDB
VOB
7
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
Ground terminal for Driver B.
8
9
Driver B output (low-side driver).
VDDB
NC
10
11
12
13
14
Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V.
No connection.
GNDA
VOA
Ground terminal for Driver A.
Driver A output (high-side driver).
VDDA
Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V.
Rev. 0.3
35
Si823x
LGA-14 (5 x 5 mm)
1
14
13
12
11
10
GNDI
VIA
VDDA
VOA
2
3
4
5
GNDA
NC
VIB
Si8235
Si8236
VDDI
DISABLE
VDDB
6
7
7
8
NC
VOB
VDDI
GNDB
Table 17. Si8235/6 Dual Isolated Driver (14 LD LGA)
Pin
GNDI
VIA
Name
Description
Input-side ground terminal.
1
2
3
4
5
Non-inverting logic input terminal for Driver A.
Non-inverting logic input terminal for Driver B.
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
VIB
VDDI
DISABLE
Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW.
It is strongly recommended that this input be connected to external logic level to avoid
erroneous operation due to capacitive noise coupling.
NC
6
7
No connection.
VDDI
GNDB
VOB
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
Ground terminal for Driver B.
8
9
Driver B output (low-side driver).
VDDB
NC
10
11
12
13
14
Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V.
No connection.
GNDA
VOA
Ground terminal for Driver A.
Driver A output (high-side driver).
VDDA
Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V.
36
Rev. 0.3
Si823x
9. Ordering Guide
The ordering part number (OPN) naming convention is described in Figure 45. The currently available OPNs are
listed in Table 18. The part number convention is not intended to imply that all possible device configuration options
and their corresponding ordering part numbers (OPN) will be available or are included in the ordering guide table.
However, if there is a specific device configuration of interest that is currently not listed in the ordering guide table,
contact your local Silicon Labs sales representative, or go to the Silicon Labs Technical Support web page at
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a request for your
specific device configuration and OPN. Ordering part number options for 10 V and 12.5 V UVLO will be made
available only by request.
Si823YUV-R-TPn
ISOdriver Product
Peak Output Current (0,1,2=0.5A, 3,4,5=4A)
UVLO* level (A=5V, B=8V, C=10V, D=12.5V)
Insulation Rating (A=1.5kV,B=2.5kV,C=3.75kV,D=5kV)
Product Revision
Temp Range (I=-40 to +125C)
Package Type (S=SOIC, M=LGA)
Package Extension (1=Narrow Body)
Note: UVLO = Under Voltage Lock Out for VDDA, VDDB.
Figure 45. ISODriver OPN Naming Convention
Rev. 0.3
37
Si823x
Table 18. Ordering Part Numbers
Legacy
Ordering Part
Number (OPN)
Peak
Current Voltage
UVLO
Isolation
Rating
Temperature
Range
Package Ordering Part
Inputs Configuration
Type
Number (OPN)
2.5 kV Only
Wide Body (WB) Package Options
High Side/
Si8230BB-B-IS VIA, VIB
Si8230-A-IS
Low Side
High Side/
Low Side
0.5 A
4.0 A
8 V
Si8231BB-B-IS
PWM
Si8231-A-IS
Si8232-A-IS
Si8233-B-IS
Si8232BB-B-IS VIA,VIB
Si8233BB-C-IS VIA,VIB
Dual Driver
SOIC-16
Wide Body
2.5 kVrms –40 to +125 °C
High Side/
Low Side
High Side/
Low Side
8 V
Si8234BB-C-IS
PWM
Si8234-B-IS
Si8235-B-IS
Si8235BB-C-IS VIA,VIB
Dual Driver
Narrow Body (NB) Package Options
High Side/
Si8230BB-B-IS1 VIA,VIB
Low Side
High Side/
Low Side
0.5 A
4.0 A
8 V
Si8231BB-B-IS1
PWM
SOIC-16
Narrow
Body
Si8232BB-B-IS1 VIA,VIB
Si8233BB-C-IS1 VIA,VIB
Dual Driver
2.5 kVrms –40 to +125 °C
N/A
High Side/
Low Side
High Side/
Low Side
8 V
Si8234BB-C-IS1
PWM
Si8235BB-C-IS1 VIA,VIB
Dual Driver
Note: All packages are RoHS-compliant.
Moisture sensitivity level is MSL3 for wide-body SOIC-16 and 14-LD LGA packages and MSL2A for narrow-body
SOIC-16 packages with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifications
and peak solder temperatures.
38
Rev. 0.3
Si823x
Table 18. Ordering Part Numbers (Continued)
Legacy
Ordering Part
Number (OPN)
Peak
Current Voltage
UVLO
Isolation
Rating
Temperature
Range
Package Ordering Part
Inputs Configuration
Type
Number (OPN)
2.5 kV Only
LGA Package Options
High Side/
Low Side
Si8233BB-C-IM VIA,VIB
Si8233-B-IM
Si8234-B-IM
High Side/
Low Side
8 V
LGA-14
5x5 mm
Si8234BB-C-IM
PWM
2.5 kVrms
1.5 kVrms
Si8235BB-C-IM VIA,VIB
Si8235AB-C-IM VIA,VIB
Si8236BA-C-IM VIA, VIB
Dual Driver
Dual Driver
Dual Driver
Si8235-B-IM
N/A
4.0 A
5 V
–40 to +125 °C
8 V
5 V
LGA-14
5x5 mm
with Ther-
mal Pad
Si8236-B-IM
Si8236AA-C-IM VIA,VIB
Dual Driver
5 kV Ordering Options
High Side/
Low Side
Si8230BD-B-IS VIA, VIB
High Side/
Low Side
0.5 A
Si8231BD-B-IS
PWM
Si8232BD-B-IS VIA, VIB
Si8233BD-C-IS VIA, VIB
Dual Driver
SOIC-16
Wide Body
8 V
5.0 kVrms –40 to +125 °C
N/A
High Side/
Low Side
High Side/
Low Side
4.0 A
Si8234BD-C-IS
PWM
Si8235BD-C-IS VIA, VIB
Dual Driver
Note: All packages are RoHS-compliant.
Moisture sensitivity level is MSL3 for wide-body SOIC-16 and 14-LD LGA packages and MSL2A for narrow-body
SOIC-16 packages with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifications
and peak solder temperatures.
Rev. 0.3
39
Si823x
10. Package Outline: 16-Pin Wide Body SOIC
Figure 46 illustrates the package details for the Si823x in a 16-Pin Wide Body SOIC. Table 19 lists the values for
the dimensions shown in the illustration.
Figure 46. 16-Pin Wide Body SOIC
Table 19. Package Diagram Dimensions
Millimeters
Symbol
Min
—
Max
2.65
0.3
A
A1
D
E
E1
b
0.1
10.3 BSC
10.3 BSC
7.5 BSC
0.31
0.51
0.33
c
0.20
e
1.27 BSC
h
0.25
0.4
0°
0.75
1.27
7°
L
40
Rev. 0.3
Si823x
11. Land Pattern: Wide-Body SOIC
Figure 47 illustrates the recommended land pattern details for the Si823x in a 16-pin wide-body SOIC. Table 20
lists the values for the dimensions shown in the illustration.
Figure 47. 16-Pin SOIC Land Pattern
Table 20. 16-Pin Wide Body SOIC Land Pattern Dimensions
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
9.40
1.27
0.60
1.90
C1
E
X1
Y1
Pad Length
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN
for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
Rev. 0.3
41
Si823x
12. Package Outline: Narrow Body SOIC
Figure 48 illustrates the package details for the Si823x in a 16-pin narrow-body SOIC (SO-16). Table 21 lists the
values for the dimensions shown in the illustration.
Figure 48. 16-pin Small Outline Integrated Circuit (SOIC) Package
Table 21. Package Diagram Dimensions
Dimension
Min
—
Max
1.75
0.25
—
A
A1
A2
b
0.10
1.25
0.31
0.17
0.51
0.25
c
D
9.90 BSC
6.00 BSC
3.90 BSC
1.27 BSC
E
E1
e
L
0.40
1.27
L2
0.25 BSC
42
Rev. 0.3
Si823x
Table 21. Package Diagram Dimensions (Continued)
h
0.25
0°
0.50
8°
θ
aaa
bbb
ccc
ddd
0.10
0.20
0.10
0.25
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise
noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MS-
012, Variation AC.
4. Recommended card reflow profile is per the JEDEC/IPC J-
STD-020C specification for Small Body Components.
Rev. 0.3
43
Si823x
13. Land Pattern: Narrow Body SOIC
Figure 49 illustrates the recommended land pattern details for the Si823x in a 16-pin narrow-body SOIC. Table 22
lists the values for the dimensions shown in the illustration.
Figure 49. 16-Pin Narrow Body SOIC PCB Land Pattern
Table 22. 16-Pin Narrow Body SOIC Land Pattern Dimensions
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
5.40
1.27
0.60
1.55
C1
E
X1
Y1
Pad Length
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N
for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
44
Rev. 0.3
Si823x
14. Package Outline: 14 LD LGA (5 x 5 mm)
Figure 50 illustrates the package details for the Si823x in an LGA outline. Table 23 lists the values for the
dimensions shown in the illustration.
Figure 50. Si823x LGA Outline
Table 23. Package Diagram Dimensions
Dimension
MIN
0.74
0.25
NOM
0.84
MAX
0.94
0.35
A
b
0.30
D
5.00 BSC
4.15 BSC
0.65 BSC
5.00 BSC
3.90 BSC
0.75
D1
e
E
E1
L
0.70
0.05
—
0.80
0.15
0.10
0.10
0.08
0.15
0.08
L1
aaa
bbb
ccc
ddd
eee
0.10
—
—
—
—
—
—
—
—
—
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
Rev. 0.3
45
Si823x
15. Land Pattern: 14 LD LGA
Figure 51 illustrates the recommended land pattern details for the Si823x in a 14-pin LGA. Table 24 lists the values
for the dimensions shown in the illustration.
Figure 51. 14-Pin LGA Land Pattern
46
Rev. 0.3
Si823x
Table 24. 14-Pin LGA Land Pattern Dimensions
Dimension
(mm)
4.20
0.65
0.80
0.40
C1
E
X1
Y1
Notes:
General:
1. All dimensions shown are in millimeters (mm).
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All dimensions shown are at Maximum Material Condition (MMC). Least
Material Condition (LMC) is calculated based on a Fabrication
Allowance of 0.05 mm.
Solder Mask Design:
4. All metal pads are to be non-solder mask defined (NSMD). Clearance
between the solder mask and the metal pad is to be 60 µm minimum, all
the way around the pad.
Stencil Design:
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal
walls should be used to assure good solder paste release.
6. The stencil thickness should be 0.125 mm (5 mils).
7. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly:
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-
020D specification for Small Body Components.
Rev. 0.3
47
Si823x
16. Package Outline: 14 LD LGA with Thermal Pad (5 x 5 mm)
Figure 52 illustrates the package details for the Si8236 ISOdriver in an LGA outline. Table 25 lists the values for the
dimensions shown in the illustration.
Figure 52. Si823x LGA Outline with Thermal Pad
Table 25. Package Diagram Dimensions
Dimension
MIN
0.74
0.25
NOM
0.84
MAX
0.94
0.35
A
b
0.30
D
5.00 BSC
4.15 BSC
0.65 BSC
5.00 BSC
3.90 BSC
0.75
D1
e
E
E1
L
0.70
0.05
1.40
4.15
—
0.80
0.15
1.50
4.25
0.10
0.10
0.08
0.15
0.08
L1
P1
P2
aaa
bbb
ccc
ddd
eee
0.10
1.45
4.20
—
—
—
—
—
—
—
—
—
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
48
Rev. 0.3
Si823x
17. Land Pattern: 14 LD LGA with Thermal Pad
Figure 53 illustrates the recommended land pattern details for the Si8236 in a 14-pin LGA with thermal pad.
Table 26 lists the values for the dimensions shown in the illustration.
Figure 53. 14-Pin LGA with Thermal Pad Land Pattern
Rev. 0.3
49
Si823x
Table 26. 14-Pin LGA with Thermal Pad Land Pattern Dimensions
Dimension
(mm)
4.20
1.50
4.25
0.65
0.80
0.40
C1
C2
D2
E
X1
Y1
Notes:
General:
1. All dimensions shown are in millimeters (mm).
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All dimensions shown are at Maximum Material Condition (MMC). Least
Material Condition (LMC) is calculated based on a Fabrication
Allowance of 0.05 mm.
Solder Mask Design:
4. All metal pads are to be non-solder mask defined (NSMD). Clearance
between the solder mask and the metal pad is to be 60 µm minimum, all
the way around the pad.
Stencil Design:
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal
walls should be used to assure good solder paste release.
6. The stencil thickness should be 0.125 mm (5 mils).
7. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly:
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-
020D specification for Small Body Components.
50
Rev. 0.3
Si823x
DOCUMENT CHANGE LIST
Revision 0.11 to Revision 0.2
Updated all specs to reflect latest silicon revision.
Updated Table 1 on page 6 to include new UVLO
options.
Updated Table 2 on page 10 to reflect new maximum
package isolation ratings
Added Figures 34, 35, and 36.
Updated Ordering Guide to reflect new package
offerings.
Added "5.6.3.Under Voltage Lockout (UVLO)" on
page 25 to describe UVLO operation.
Revision 0.2 to Revision 0.3
Moved Sections 2, 3, and 4 to after Section 5.
Updated Tables 15, 16, and 17.
Removed Si8230, Si8231, and Si8232 from pinout and
from title.
Updated and added Ordering Guide footnotes.
Updated UVLO specifications in Table 1 on page 6.
Added PWD and Output Supply Active Current
specifications in Table 1.
Updated and added typical operating condition
graphs in "3.Typical Operating Characteristics
(0.5 Amp)" on page 16 and "4.Typical Operating
Characteristics (4.0 Amp)" on page 18.
Rev. 0.3
51
Si823x
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-
plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
The sale of this product contains no licenses to Power-One’s intellectual property. Contact Power-One, Inc. for appropriate licenses.
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
52
Rev. 0.3
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