SI8421AD-D-ISR [SILICON]
Analog Circuit, 1 Func, CMOS, PDSO16, SOIC-16;
| 型号： | SI8421AD-D-ISR |
| 厂家： | 
SILICON |
| 描述： | Analog Circuit, 1 Func, CMOS, PDSO16, SOIC-16 光电二极管 接口集成电路 |
| 文件： | 总37页 (文件大小：815K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV)
Data Sheet
Low-Power, Single and Dual-Channel Digital Isolators
KEY FEATURES
Silicon Lab's family of ultra-low-power digital isolators are CMOS devices offering sub-
stantial data rate, propagation delay, power, size, reliability, and external BOM advan-
tages when compared to legacy isolation technologies. The operating parameters of
these products remain stable across wide temperature ranges and throughout device
• High-speed operation
• DC to 150 Mbps
• No start-up initialization required
• Wide Operating Supply Voltage:
• 2.6 – 5.5 V
service life for ease of design and highly uniform performance. All device versions have
Schmitt trigger inputs for high noise immunity and only require VDD bypass capacitors.
• Up to 5000 V
isolation
RMS
Data rates up to 150 Mbps are supported, and all devices achieve worst-case propaga-
tion delays of less than 10 ns. Ordering options include a choice of isolation ratings (up
to 5 kV) and a selectable fail-safe operating mode to control the default output state dur-
ing power loss. All products are safety certified by UL, CSA, and VDE, and products in
• High electromagnetic immunity
• Ultra low power (typical)
• 5 V Operation:
• < 2.6 mA/channel at 1 Mbps
wide-body packages support reinforced insulation withstanding up to 5 kVRMS
.
• < 6.8 mA/channel at 100 Mbps
• 2.70 V Operation:
• < 2.3 mA/channel at 1 Mbps
Applications
• < 4.6 mA/channel at 100 Mbps
• Schmitt trigger inputs
• Industrial automation systems
• Medical electronics
• Isolated ADC, DAC
• Motor control
• Selectable fail-safe mode
• Default high or low output
• Hybrid electric vehicles
• Isolated switch mode supplies
• Power inverters
• Communication systems
• Precise timing (typical)
• 11 ns propagation delay max
• 1.5 ns pulse width distortion
• 0.5 ns channel-channel skew
• 2 ns propagation delay skew
• 5 ns minimum pulse width
• Transient immunity 45 kV/µs
• AEC-Q100 qualification
Safety Regulatory Approvals
• UL 1577 recognized
• VDE certification conformity
• Up to 5000 VRMS for 1 minute
• CSA component notice 5A approval
• IEC 60747-5-5 (VDE0884 Part 5)
• EN60950-1 (reinforced insulation)
• IEC 60950-1, 61010-1, 60601-1
(reinforced insulation)
• Wide temperature range
• –40 to 125 °C at 150 Mbps
• RoHS compliant packages
• SOIC-16 wide body
• SOIC-8 narrow body
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Features List
1. Features List
• High-speed operation
• Schmitt trigger inputs
• DC to 150 Mbps
• Selectable fail-safe mode
• Default high or low output
• Precise timing (typical)
• No start-up initialization required
• Wide Operating Supply Voltage:
• 2.6 – 5.5 V
• 11 ns propagation delay max
• 1.5 ns pulse width distortion
• 0.5 ns channel-channel skew
• 2 ns propagation delay skew
• 5 ns minimum pulse width
• Transient immunity 45 kV/µs
• AEC-Q100 qualification
• Wide temperature range
• –40 to 125 °C at 150 Mbps
• RoHS compliant packages
• SOIC-16 wide body
• Up to 5000 VRMS isolation
• High electromagnetic immunity
• Ultra low power (typical)
• 5 V Operation:
• < 2.6 mA/channel at 1 Mbps
• < 6.8 mA/channel at 100 Mbps
• 2.70 V Operation:
• < 2.3 mA/channel at 1 Mbps
• < 4.6 mA/channel at 100 Mbps
• SOIC-8 narrow body
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Ordering Guide
2. Ordering Guide
Table 2.1. Ordering Guide1,2,3
Ordering Part
Number (OPN)
Number of Number of Maximum
Default
Output
State
Isolation
Rating
Temp
Range
Package
Type
Inputs
Inputs
Data Rate
(Mbps)
VDD1 Side VDD2 Side
Si8422AB-D-IS
Si8422BB-D-IS
Si8423AB-D-IS
Si8423BB-D-IS
1
1
2
2
1
1
1
0
0
0
1
150
1
High
High
High
High
Low
2.5 kVrms
–40 to 125 °C
NB SOIC-8
150
1
Si8410AD-D-IS4
Si8410BD-D-IS4
Si8420AD-D-IS4
Si8420BD-D-IS4
Si8421AD-D-IS4
5.0 kVrms
–40 to 125 °C
WB SOIC-16
1
2
2
1
1
0
0
0
1
1
150
1
Low
Low
Low
Low
Low
150
1
Si8421BD-D-IS4
Si8422AD-D-IS
Si8422BD-D-IS
Si8423AD-D-IS
Si8423BD-D-IS
150
1
1
2
2
1
1
0
0
1
High
High
High
High
150
1
150
1. All devices >1 kVRMS are AEC-Q100 qualified.
2. “Si” and “SI” are used interchangeably.
3. All packages are RoHS-compliant with peak solder reflow temperatures of 260 °C according to the JEDEC industry standard clas-
sifications.
4. Refer to Si8410/20/21 data sheet for information regarding 2.5 kV rated versions of these products.
5. An "R" at the end of the part number denotes tape and reel packaging option.
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Functional Description
3. Functional Description
3.1 Theory of Operation
The operation of an Si84xx channel is analogous to that of an opto coupler, except an RF carrier is modulated instead of light. This
simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. A simplified
block diagram for a single Si84xx channel is shown in the figure below.
Transmitter
Receiver
RF
OSCILLATOR
Semiconductor-
Based Isolation
Barrier
MODULATOR
DEMODULATOR
A
B
Figure 3.1. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier. Referring to the
Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The Receiver contains a demodulator that
decodes the input state according to its RF energy content and applies the result to output B via the output driver. This RF on/off keying
scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and better immunity to
magnetic fields. See the figure below for more details.
Input Signal
Modulation Signal
Output Signal
Figure 3.2. Modulation Scheme
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Functional Description
3.2 Eye Diagram
The figure below illustrates an eye-diagram taken on an Si8422. For the data source, the test used an Anritsu (MP1763C) Pulse Pattern
Generator set to 1000 ns/div. The output of the generator's clock and data from an Si8422 were captured on an oscilloscope. The re-
sults illustrate that data integrity was maintained even at the high data rate of 150 Mbps. The results also show that 2 ns pulse width
distortion and 350 ps peak jitter were exhibited.
Figure 3.3. Eye Diagram
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Device Operation
4. Device Operation
Device behavior during start-up, normal operation, and shutdown is shown in Figure 4.1 Device Behavior during Normal Operation on
page 6, where UVLO+ and UVLO- are the positive-going and negative-going thresholds respectively. Refer to the table below to
determine outputs when power supply (VDD) is not present.
Table 4.1. Si84xx Logic Operation Table
VI Input1,4
VDDI State1,2,3 VDDO State1,2,3
VO Output1,4
Comments
H
L
P
P
P
P
P
H
L
Normal operation.
X5
H6 (Si8422/23)
UP
Upon transition of VDDI from unpowered to powered,
O returns to the same state as VI in less than 1 μs.
V
L6 (Si8410/20/21)
X5
P
UP
Undetermined Upon transition of VDDO from unpowered to powered,
VO returns to the same state as VI within 1 μs.
Notes:
1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals.
2. Powered (P) state is defined as 2.72.60 V < VDD < 5.5 V.
3. Unpowered (UP) state is defined as VDD = 0 V.
4. X = not applicable; H = Logic High; L = Logic Low.
5. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current.
6. See Section 2. Ordering Guide for details. This is the selectable fail-safe operating mode (ordering option). Some devices have
default output state = H, and some have default output state = L, depending on the ordering part number (OPN).
4.1 Device Startup
Outputs are held low during powerup until VDD is above the UVLO threshold for time period tSTART. Following this, the outputs follow
the states of inputs.
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Device Operation
4.2 Under Voltage Lockout
Under Voltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or when VDD is below
its specified operating circuits range. Both Side A and Side B each have their own undervoltage lockout monitors. Each side can enter
or exit UVLO independently. For example, Side A unconditionally enters UVLO when VDD1 falls below VDD1(UVLO–) and exits UVLO
when VDD1 rises above VDD1(UVLO+). Side B operates the same as Side A with respect to its VDD2 supply.
UVLO+
UVLO-
VDD1
UVLO+
UVLO-
VDD2
INPUT
tPHL
tPLH
tSD
tSTART
tSTART
tSTART
OUTPUT
Figure 4.1. Device Behavior during Normal Operation
4.3 Layout Recommendations
To ensure safety in the end user application, high voltage circuits (i.e., circuits with >30 VAC) must be physically separated from the
safety extra-low voltage circuits (SELV is a circuit with <30 VAC) by a certain distance (creepage/clearance). If a component, such as a
digital isolator, straddles this isolation barrier, it must meet those creepage/clearance requirements and also provide a sufficiently large
high-voltage breakdown protection rating (commonly referred to as working voltage protection). Table 5.5 Regulatory Information1 on
page 20 and Table 5.6 Insulation and Safety-Related Specifications on page 21 detail the working voltage and creepage/clearance
capabilities of the Si84xx. These tables also detail the component standards (UL1577, IEC60747, CSA 5A), which are readily accepted
by certification bodies to provide proof for end-system specifications requirements. Refer to the end-system specification (61010-1,
60950-1, 60601-1, etc.) requirements before starting any design that uses a digital isolator.
4.3.1 Supply Bypass
The Si841x/2x family requires a 0.1 μF bypass capacitor between VDD1 and GND1 and VDD2 and GND2. The capacitor should be
placed as close as possible to the package. To enhance the robustness of a design, it is further recommended that the user also add 1
μF bypass capacitors and include 100 Ω resistors in series with the inputs and outputs if the system is excessively noisy.
4.3.2 Pin Connections
No connect pins are not internally connected. They can be left floating, tied to VDD, or tied to GND.
4.3.3 Output Pin Termination
The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of the on-
chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will
be a factor, output pins should be appropriately terminated with controlled impedance PCB traces.
4.4 Fail-Safe Operating Mode
Si84xx devices feature a selectable (by ordering option) mode whereby the default output state (when the input supply is unpowered)
can either be a logic high or logic low when the output supply is powered. See Table 4.1 Si84xx Logic Operation Table on page 5 and
Section 2. Ordering Guide for more information.
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Device Operation
4.5 Typical Performance Characteristics
The typical performance characteristics depicted in the following diagrams are for information purposes only. Refer to Table 5.2 Electri-
cal Characteristics on page 9 through Table 5.4 Electrical Characteristics1 on page 17 for actual specification limits.
Figure 4.2. Si8410 Typical VDD1 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
Figure 4.3. Si8420 Typical VDD1 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
Figure 4.4. Si8421 Typical VDD1 or VDD2 Supply Current vs.
Data Rate 5, 3.3, and 2.70 V Operation (15 pF Load)
Figure 4.5. Si8410 Typical VDD2 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
(15 pF Load)
Figure 4.6. Si8420 Typical VDD2 Supply Current vs. Data Rate
5, 3.3, and 2.70 V Operation
Figure 4.7. Si8422 Typical VDD1 or VDD2 Supply Current vs.
Data Rate 5, 3.3, and 2.70 V Operation (15 pF Load)
(15 pF Load)
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Device Operation
Figure 4.8. Si8423 Typical VDD1 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
Figure 4.9. Si8423 Typical VDD2 Supply Current vs. Data Rate
5, 3.3, and 2.70 V Operation
(15 pF Load)
Figure 4.10. Propagation Delay
vs. Temperature
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Electrical Specifications
5. Electrical Specifications
Table 5.1. Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Ambient Operating Temperature1
Supply Voltage
TA
–40
25
125
C°
VDD1
VDD2
2.70
2.70
—
—
5.5
5.5
V
V
Note:
1. The maximum ambient temperature is dependent upon data frequency, output loading, the number of operating channels, and
supply voltage.
Table 5.2. Electrical Characteristics
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 °C)
Parameter
Symbol
VDDUV+
VDDHYS
Test Condition
Min
2.15
45
Typ
2.3
75
Max
2.5
95
Unit
V
VDD Undervoltage Threshold
VDD1, VDD2 rising
VDD Negative-Going Lockout
Hysteresis
mV
Positive-Going Input Threshold
Negative-Going Input Threshold
Input Hysteresis
VT+
VT–
VHYS
VIH
All inputs rising
All inputs falling
1.6
1.1
0.40
2.0
—
—
—
1.9
1.4
0.50
—
V
V
V
V
V
V
0.45
—
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
VIL
—
0.8
—
VOH
loh = –4 mA
lol = 4 mA
VDD1,VDD2
– 0.4
4.8
Low Level Output Voltage
Input Leakage Current
VOL
IL
—
—
—
0.2
—
0.4
±10
—
V
μA
Ω
Output Impedance1
ZO
50
DC Supply Current (All inputs 0 V or at Supply)
Si8410Ax, Bx
VDD1
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.0
3.0
3.0
1.0
1.5
1.5
4.5
1.5
mA
VDD2
VDD1
VDD2
Si8420Ax, Bx
VDD1
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.3
1.7
5.8
1.7
2.0
2.6
8.7
2.6
mA
VDD2
VDD1
VDD2
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Electrical Specifications
Parameter
Si8421Ax, Bx
VDD1
Symbol
Test Condition
Min
Typ
Max
Unit
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.7
1.7
3.7
3.7
2.6
2.6
5.6
5.6
mA
VDD2
VDD1
VDD2
Si8422Ax, Bx
VDD1
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
3.7
3.7
1.7
1.7
5.6
5.6
2.6
2.6
mA
VDD2
VDD1
VDD2
Si8423Ax, Bx
VDD1
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
5.4
1.7
1.3
1.7
8.1
2.6
2.0
2.6
mA
VDD2
VDD1
VDD2
1 Mbps Supply Current (All inputs = 500 kHz square wave, CL = 15 pF on all outputs)
Si8410Ax, Bx
VDD1
—
—
2.0
1.1
3.0
1.7
mA
mA
mA
mA
mA
VDD2
Si8420Ax, Bx
VDD1
—
—
3.5
1.9
5.3
2.9
VDD2
Si8421Ax, Bx
VDD1
—
—
2.8
2.8
4.2
4.2
VDD2
Si8422Ax, Bx
VDD1
—
—
2.8
2.8
4.2
4.2
VDD2
Si8423Ax, Bx
VDD1
—
—
3.4
1.9
5.1
2.9
VDD2
10 Mbps Supply Current (All inputs = 5 MHz square wave, CL = 15 pF on all outputs)
Si8410Bx
VDD1
—
—
2.1
1.5
3.1
2.1
mA
VDD2
Si8420Bx
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
—
Typ
3.6
2.6
Max
5.4
Unit
VDD1
mA
—
3.6
VDD2
Si8421Bx
VDD1
—
—
3.2
3.2
4.5
4.5
mA
mA
mA
VDD2
Si8422Bx
VDD1
—
—
3.2
3.2
4.5
4.5
VDD2
Si8423Bx
VDD1
—
—
3.4
2.5
5.1
3.5
VDD2
100 Mbps Supply Current (All inputs = 50 MHz square wave, CL = 15 pF on all outputs)
Si8410Bx
VDD1
—
—
2.1
5.0
3.1
6.3
mA
mA
mA
mA
mA
VDD2
Si8420Bx
VDD1
—
—
3.7
9.8
5.4
12.3
VDD2
Si8421Bx
VDD1
—
—
6.8
6.8
8.5
8.5
VDD2
Si8422Bx
VDD1
—
—
6.8
6.8
8.5
8.5
VDD2
Si8423Bx
VDD1
—
—
3.4
9.2
5.1
11.5
VDD2
Timing Characteristics
Si841xAx, Si842xAx
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
0
—
—
—
1.0
250
35
Mbps
ns
—
—
tPHL, tPLH
See Figure 5.1 Propagation
Delay Timing on page 12
ns
Pulse Width Distortion
PWD
See Figure 5.1 Propagation
Delay Timing on page 12
—
—
—
—
25
40
ns
ns
|tPLH - tPHL
|
Propagation Delay Skew2
tPSK(P-P)
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Channel-Channel Skew
Si841xBx, Si842xBx
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
tPSK
—
—
35
ns
0
—
—
150
6.0
11
Mbps
ns
—
tPHL, tPLH
See Figure 5.1 Propagation
Delay Timing on page 12
4.0
8.0
ns
Pulse Width Distortion
PWD
See Figure 5.1 Propagation
Delay Timing on page 12
—
1.5
3.0
ns
|tPLH - tPHL
|
Propagation Delay Skew2
Channel-Channel Skew
All Models
tPSK(P-P)
tPSK
—
—
2.0
0.5
3.0
1.5
ns
ns
Output Rise Time
tr
tf
CL = 15 pF
CL = 15 pF
—
—
—
2.0
2.0
350
4.0
4.0
—
ns
ns
ps
Output Fall Time
Peak Eye Diagram Jitter
tJIT(PK)
See Figure 3.3 Eye Diagram
on page 4
Common Mode Transient
Immunity
CMTI
tSU
VI = VDD or 0 V
20
—
45
15
—
kV/μs
μs
Start-up Time3
40
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of
the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission
line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same
supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
1.4 V
Typical
Input
tPLH
tPHL
90%
10%
90%
10%
1.4 V
Typical
Output
tr
tf
Figure 5.1. Propagation Delay Timing
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Electrical Specifications
Table 5.3. Electrical Characteristics
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = –40 to 125 °C)
Parameter
Symbol
VDDUV+
VDDHYS
Test Condition
Min
2.15
45
Typ
2.3
75
Max
2.5
95
Unit
V
VDD Undervoltage Threshold
VDD1, VDD2 rising
VDD Negative-Going Lockout
Hysteresis
mV
Positive-Going Input Threshold
Negative-Going Input Threshold
Input Hysteresis
VT+
VT–
VHYS
VIH
All inputs rising
All inputs falling
1.6
1.1
0.40
2.0
—
—
—
1.9
1.4
0.50
—
V
V
V
V
V
V
0.45
—
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
VIL
—
0.8
—
VOH
loh = –4 mA
lol = 4 mA
VDD1,VDD2
3.1
– 0.4
Low Level Output Voltage
Input Leakage Current
VOL
IL
—
—
—
0.2
—
0.4
±10
—
V
μA
Ω
Output Impedance (Si8410/20)1
ZO
50
DC Supply Current (All inputs 0 V or at supply)
Si8410Ax, Bx
VDD1
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.0
1.0
3.0
1.0
1.5
1.5
4.5
1.5
mA
mA
mA
VDD2
VDD1
VDD2
Si8420Ax, Bx
VDD1
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.3
1.7
5.8
1.7
2.0
2.6
8.7
2.6
VDD2
VDD1
VDD2
Si8421Ax, Bx
VDD1
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.7
1.7
3.7
3.7
2.6
2.6
5.6
5.6
VDD2
VDD1
VDD2
Si8422Ax, Bx
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
Min
—
Typ
3.7
3.7
1.7
1.7
Max
5.6
5.6
2.6
2.6
Unit
VDD1
mA
—
VDD2
VDD1
VDD2
—
—
Si8423Ax, Bx
VDD1
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
5.4
1.7
1.3
1.7
8.1
2.6
2.0
2.6
mA
VDD2
VDD1
VDD2
1 Mbps Supply Current (All inputs = 500 kHz square wave, CL = 15 pF on all outputs)
Si8410Ax, Bx
VDD1
—
—
2.0
1.1
3.0
1.7
mA
mA
mA
mA
mA
VDD2
Si8420Ax, Bx
VDD1
—
—
3.5
1.9
5.3
2.9
VDD2
Si8421Ax, Bx
VDD1
—
—
2.8
2.8
4.2
4.2
VDD2
Si8422Ax, Bx
VDD1
—
—
2.8
2.8
4.2
4.2
VDD2
Si8423Ax, Bx
VDD1
—
—
3.4
1.9
5.1
2.9
VDD2
10 Mbps Supply Current (All inputs = 5 MHz square wave, CL = 15 pF on all outputs)
Si8410Bx
VDD1
—
—
2.0
1.3
3.0
1.8
mA
mA
mA
VDD2
Si8420Bx
VDD1
—
—
3.5
2.3
5.3
3.2
VDD2
Si8421Bx
VDD1
—
—
3.0
3.0
4.4
4.4
VDD2
Si8422Bx
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
—
Typ
3.0
3.0
Max
4.4
Unit
VDD1
mA
—
4.4
VDD2
Si8423Bx
VDD1
—
—
3.4
2.2
5.1
3.1
mA
VDD2
100 Mbps Supply Current (All inputs = 50 MHz square wave, CL = 15 pF on all outputs)
Si8410Bx
VDD1
—
—
2.0
3.6
3.0
4.5
mA
mA
mA
mA
mA
VDD2
Si8420Bx
VDD1
—
—
4.5
7.0
5.3
8.8
VDD2
Si8421Bx
VDD1
—
—
5.3
5.3
6.6
6.6
VDD2
Si8422Bx
VDD1
—
—
5.3
5.3
6.6
6.6
VDD2
Si8423Bx
VDD1
—
—
3.4
6.6
5.1
8.3
VDD2
Timing Characteristics
Si841xAx, Si842xAx
Maximum Data Rate
Minimum Pulse Width
0
—
—
—
1.0
250
35
Mbps
ns
—
—
Propagation Delay
tPHL, tPLH
See Figure 5.1 Propagation
Delay Timing on page 12
ns
Pulse Width Distortion
PWD
See Figure 5.1 Propagation
Delay Timing on page 12
—
—
25
ns
|tPLH – tPHL
|
Propagation Delay Skew2
Channel-Channel Skew
Si841xBx, Si842xBx
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
tPSK(P-P)
tPSK
—
—
—
—
40
35
ns
ns
0
—
—
150
6.0
11
Mbps
ns
—
tPHL, tPLH
See Figure 5.1 Propagation
Delay Timing on page 12
4.0
8.0
ns
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Pulse Width Distortion
PWD
See Figure 5.1 Propagation
Delay Timing on page 12
—
1.5
3.0
ns
|tPLH – tPHL
|
Propagation Delay Skew2
Channel-Channel Skew
All Models
tPSK(P-P)
tPSK
—
—
2.0
0.5
3.0
1.5
ns
ns
Output Rise Time
tr
tf
CL = 15 pF
CL = 15 pF
—
—
—
2.0
2.0
350
4.0
4.0
—
ns
ns
ps
Output Fall Time
Peak Eye Diagram Jitter
tJIT(PK)
See Figure 3.3 Eye Diagram
on page 4
Common Mode Transient
Immunity
CMTI
tSU
VI = VDD or 0 V
20
—
45
15
—
kV/μs
μs
Start-up Time3
40
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of
the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission
line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same
supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Electrical Specifications
Table 5.4. Electrical Characteristics1
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA = –40 to 125 °C)
Parameter
Symbol
VDDUV+
VDDHYS
Test Condition
Min
2.15
45
Typ
2.3
75
Max
2.5
95
Unit
V
VDD Undervoltage Threshold
VDD1, VDD2 rising
VDD Negative-Going Lockout
Hysteresis
mV
Positive-Going Input Threshold
Negative-Going Input Threshold
Input Hysteresis
VT+
VT–
VHYS
VIH
All inputs rising
All inputs falling
1.6
1.1
0.40
2.0
—
—
—
1.9
1.4
0.50
—
V
V
V
V
V
V
0.45
—
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
VIL
—
0.8
—
VOH
loh = –4 mA
lol = 4 mA
VDD1,VDD2
2.3
– 0.4
Low Level Output Voltage
Input Leakage Current
VOL
IL
—
—
—
0.2
—
0.4
±10
—
V
μA
Ω
Output Impedance2
ZO
50
DC Supply Current (All inputs 0 V or at supply)
Si8410Ax, Bx
VDD1
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.0
1.0
3.0
1.0
1.5
1.5
4.5
1.5
mA
mA
mA
VDD2
VDD1
VDD2
Si8420Ax, Bx
VDD1
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.3
1.7
5.8
1.7
2.0
2.6
8.7
2.6
VDD2
VDD1
VDD2
Si8421Ax, Bx
VDD1
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.7
1.7
3.7
3.7
2.6
2.6
5.6
5.6
VDD2
VDD1
VDD2
Si8422Ax, Bx
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
Min
—
Typ
3.7
3.7
1.7
1.7
Max
5.6
5.6
2.6
2.6
Unit
VDD1
mA
—
VDD2
VDD1
VDD2
—
—
Si8423Ax, Bx
VDD1
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
5.4
1.7
1.3
1.7
8.1
2.6
2.0
2.6
mA
VDD2
VDD1
VDD2
1 Mbps Supply Current (All inputs = 500 kHz square wave, CL = 15 pF on all outputs)
Si8410Ax, Bx
VDD1
—
—
2.0
1.1
3.0
1.7
mA
mA
mA
mA
mA
VDD2
Si8420Ax, Bx
VDD1
—
—
3.5
1.9
5.3
2.9
VDD2
Si8421Ax, Bx
VDD1
—
—
2.8
2.8
4.2
4.2
VDD2
Si8422Ax, Bx
VDD1
—
—
2.8
2.8
4.2
4.2
VDD2
Si8423Ax, Bx
VDD1
—
—
3.3
1.8
5.0
2.8
VDD2
10 Mbps Supply Current (All inputs = 5 MHz square wave, CL = 15 pF on all outputs)
Si8410Bx
VDD1
—
—
2.0
1.1
3.0
1.7
mA
mA
mA
VDD2
Si8420Bx
VDD1
—
—
3.5
2.1
5.3
3.0
VDD2
Si8421Bx
VDD1
—
—
2.9
2.9
4.3
4.3
VDD2
Si8422Bx
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
—
Typ
2.9
2.9
Max
4.3
Unit
VDD1
mA
—
4.3
VDD2
Si8423Bx
VDD1
—
—
3.4
2.0
5.1
2.9
mA
VDD2
100 Mbps Supply Current (All inputs = 50 MHz square wave, CL = 15 pF on all outputs)
Si8410Bx
VDD1
—
—
2.0
2.0
3.0
3.0
mA
mA
mA
mA
mA
VDD2
Si8420Bx
VDD1
—
—
3.5
5.5
5.3
6.9
VDD2
Si8421Bx
VDD1
—
—
4.6
4.6
5.8
5.8
VDD2
Si8422Bx
VDD1
—
—
4.6
4.6
5.8
5.8
VDD2
Si8423Bx
VDD1
—
—
3.4
5.2
5.1
6.5
VDD2
Timing Characteristics
Si841xAx, Si842xAx
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
0
—
—
—
1.0
250
35
Mbps
ns
—
—
tPHL, tPLH
See Figure 5.1 Propagation
Delay Timing on page 12
ns
Pulse Width Distortion
PWD
See Figure 5.1 Propagation
Delay Timing on page 12
—
—
25
ns
|tPLH - tPHL
|
Propagation Delay Skew3
Channel-Channel Skew
Si841xBx, Si842xBx
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
tPSK(P-P)
tPSK
—
—
—
—
40
35
ns
ns
0
—
—
150
6.0
11
Mbps
ns
—
tPHL, tPLH
See Figure 5.1 Propagation
Delay Timing on page 12
4.0
8.0
ns
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Pulse Width Distortion
PWD
See Figure 5.1 Propagation
Delay Timing on page 12
—
1.5
3.0
ns
|tPLH - tPHL
|
Propagation Delay Skew3
Channel-Channel Skew
All Models
tPSK(P-P)
tPSK
—
—
2.0
0.5
3.0
1.5
ns
ns
Output Rise Time
tr
tf
CL = 15 pF
CL = 15 pF
—
—
—
2.0
2.0
350
4.0
4.0
—
ns
ns
ps
Output Fall Time
Peak Eye Diagram Jitter
tJIT(PK)
See Figure 3.3 Eye Diagram
on page 4
Common Mode Transient
Immunity
CMTI
tSU
VI = VDD or 0 V
20
—
45
15
—
kV/μs
μs
Start-up Time4
40
Notes:
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is constrained
to TA = 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of
the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission
line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same
supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to valid data at the output.
Table 5.5. Regulatory Information1
CSA
The Si84xx is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.
61010-1: Up to 600 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage.
60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
60601-1: Up to 125 VRMS reinforced insulation working voltage; up to 380 VRMS basic insulation working voltage.
VDE
The Si84xx is certified according to IEC 60747-5-5. For more details, see File 5006301-4880-0001.
60747-5-5: Up to 891 Vpeak for basic insulation working voltage.
60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
UL
The Si84xx is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 5000 VRMS isolation voltage for basic insulation.
Note:
1. Regulatory Certifications apply to 2.5 kVRMS rated devices which are production tested to 3.0 kVRMS for 1 sec. Regulatory Certifi-
cations apply to 5.0 kVRMS rated devices which are production tested to 6.0 kVRMS for 1 sec.
For more information, see Section 2. Ordering Guide.
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Electrical Specifications
Table 5.6. Insulation and Safety-Related Specifications
Parameter
Symbol
Test Condi-
tion
Value
Unit
WB SOIC-16
NB SOIC-8
Nominal Air Gap (Clearance)1
L(IO1)
L(IO2)
8.0 min
8.0 min
4.9 min
mm
mm
Nominal External Tracking (Creepage)1
Minimum Internal Gap (Internal Clearance)
4.01 min
0.014
600
0.008
600
mm
Tracking Resistance
(Proof Tracking Index)
PTI
VRMS
IEC60112
Erosion Depth
ED
0.019
0.040
mm
Ω
Resistance (Input-Output)2
Capacitance (Input-Output)2
101,2
2.0
101,2
1.0
RIO
CIO
CI
f = 1 MHz
pF
pF
Input Capacitance3
4.0
4.0
Notes:
1. The values in this table correspond to the nominal creepage and clearance values as detailed in Section 7.1 Package Outline
(16-Pin Wide Body SOIC) and Section 7.2 Package Outline (8-Pin Narrow Body SOIC). VDE certifies the clearance and creepage
limits as 8.5 mm minimum for the WB SOIC-16 package and 4.7 mm minimum for the NB SOIC-8 package. UL does not impose
a clearance and creepage minimum for component level certifications. CSA certifies the clearance and creepage limits as 3.9 mm
minimum for the NB SOIC-8 and 7.6 mm minimum for the WB SOIC-16 package.
2. To determine resistance and capacitance, the Si84xx is converted into a 2-terminal device. Pins 1–8 (1–4, NB SOIC-8) are shor-
ted together to form the first terminal and pins 9–16 (5–8, NB SOIC-8) are shorted together to form the second terminal. The
parameters are then measured between these two terminals.
3. Measured from input pin to ground.
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Electrical Specifications
Table 5.7. IEC 60747-5-5 Insulation Characteristics for Si84xxxx1
Parameter
Symbol
Test Condi-
tion
Characteristic
Unit
WB
NB SOIC-8
SOIC-16
Maximum Working Insulation Voltage
Input to Output Test Voltage
VIORM
891
560
Vpeak
Method b1
1671
1050
(VIORM
x
1.875 = VPR
,
100%
Production
Test, tm = 1
sec,
Partial Dis-
charge < 5
pC)
Transient Overvoltage
VIOTM
t = 60 sec
6000
2
4000
2
Vpeak
Ω
Pollution Degree
(DIN VDE 0110, Table 1)
>109
>109
Insulation Resistance at TS, VIO = 500 V
RS
Note:
1. Maintenance of the safety data is ensured by protective circuits. The Si84xx provides a climate classification of 40/125/21.
Table 5.8. IEC Safety Limiting Values1
Parameter
Symbol
Test Condi-
tion
Max
WB SOIC-16
Unit
NB SOIC-8
150
Case Temperature
TS
IS
150
220
°C
Safety Input, Output, or Supply Current
θJA = 140
°C/W (NB
160
mA
SOIC-8), 100
°C (WB SO-
IC-16),
VI = 5.5 V, TJ
= 150 °C, TA
= 25 °C
Device Power Dissipation2
PD
150
150
mW
Notes:
1. Maximum value allowed in the event of a failure; also see the thermal derating curve in Figure 5.2 (WB SOIC-16) Thermal Derat-
ing Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-5 on page 23 and Figure 5.3 (NB SOIC-8) Thermal Derating Curve, Dependence
of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-5 on page 23.
2. The Si84xx is tested with VDD1 = VDD2 = 5.5 V, TJ = 150 °C, CL = 15 pF, input a 150 Mbps 50% duty cycle square wave.
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Electrical Specifications
Table 5.9. Thermal Characteristics
Parameter
Symbol
WB SOIC-16
NB SOIC-8
Unit
IC Junction-to-Air Thermal Resistance
θJA
100
140
°C/W
500
460
VDD1, VDD2 = 2.70 V
375
250
125
0
360
VDD1, VDD2 = 3.3 V
VDD1, VDD2 = 5.5 V
220
0
50
100
150
200
Case Temperature (ºC)
Figure 5.2. (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-5
400
320
VDD1, VDD2 = 2.70 V
300
270
VDD1, VDD2 = 3.3 V
200
160
VDD1, VDD2 = 5.5 V
100
0
0
50
100
150
200
Case Temperature (ºC)
Figure 5.3. (NB SOIC-8) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-5
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Electrical Specifications
Table 5.10. Absolute Maximum Ratings1
Parameter
Symbol
Min
Typ
Max
Unit
Storage Temperature2
Operating Temperature
Junction Temperature
TSTG
–65
—
150
C°
TA
–40
—
—
—
—
—
—
—
—
—
—
125
150
C°
°C
TJ
Supply Voltage
VDD1, VDD2
–0.5
–0.5
–0.5
—
6.0
V
Input Voltage
VI
VO
IO
VDD + 0.5
VDD + 0.5
10
V
Output Voltage
V
Output Current Drive Channel
Lead Solder Temperature (10 s)
Maximum Isolation Voltage (1 s) NB SOIC-8
mA
C°
—
260
—
4500
6500
VRMS
VRMS
Maximum Isolation Voltage (1 s) WB SO-
IC-16
—
Notes:
1. Permanent device damage may occur if the above absolute maximum ratings are exceeded. Functional operation should be re-
stricted to conditions as specified in the operational sections of this data sheet.
2. VDE certifies storage temperature from –40 to 150 °C.
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Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Pin Descriptions
6. Pin Descriptions
6.1 Pin Descriptions (Wide-Body SOIC)
GND2
NC
GND2
NC
GND2
NC
GND2
NC
GND1
NC
GND1
NC
GND1
NC
GND1
NC
I
s
o
l
I
s
o
l
I
s
o
l
I
s
o
l
VDD1
A1
VDD1
A1
VDD1
A1
VDD1
A1
VDD2
B1
VDD2
B1
VDD2
B1
VDD2
B1
RF
RCVR
RF
XMITR
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
a
t
i
o
n
a
t
i
o
n
a
t
i
o
n
a
t
i
o
n
RF
XMITR
RF
RCVR
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
NC
NC
A2
NC
B2
A2
NC
B2
A2
NC
B2
NC
GND1
NC
NC
NC
NC
NC
NC
GND1
NC
NC
GND1
NC
NC
GND1
NC
NC
GND2
GND2
GND2
GND2
Si8420/23 WB SOIC-16
Si8410 WB SOIC-16
Si8421 WB SOIC-16
Si8422 WB SOIC-16
Figure 6.1. Wide-Body SOIC
Table 6.1. Pin Descriptions
Name
SOIC-16 Pin#
SOIC-16 Pin#
Type
Description
Si8410
Si842x
GND1
NC1
1
1
Ground
Side 1 ground.
NC
2, 5, 6, 8,10,
11, 12, 15
2, 6, 8,10,
11, 15
No Connect
VDD1
A1
3
4
3
4
Supply
Digital I/O
Digital I/O
Ground
Side 1 power supply.
Side 1 digital input or output.
Side 1 digital input or output.
Side 1 ground.
A2
NC
7
5
GND1
GND2
B2
7
9
9
Ground
Side 2 ground.
NC
13
14
16
12
13
14
16
Digital I/O
Digital I/O
Supply
Side 2 digital input or output.
Side 2 digital input or output.
Side 2 power supply.
Side 2 ground.
B1
VDD2
GND2
Ground
Note:
1. No Connect. These pins are not internally connected. They can be left floating, tied to VDD or tied to GND.
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Rev. 1.4 | 25
Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Pin Descriptions
6.2 Pin Descriptions (Narrow-Body SOIC)
VDD1
VDD1
VDD2
B1
VDD2
I
s
o
l
a
t
i
I
s
o
l
a
t
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
B1
A1
A1
A2
RF
XMITR
RF
XMITR
RF
RCVR
RF
RCVR
A2
B2
B2
i
o
n
o
n
GND2
GND2
GND1
GND1
Si8423 NB SOIC-8
Si8422 NB SOIC-8
Figure 6.2. Narrow-Body SOIC
Type
Name
SOIC-8 Pin#
Description
Si842x
VDD1
GND1
A1
1
4
2
3
7
6
8
5
Supply
Ground
Side 1 power supply.
Side 1 ground.
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Supply
Side 1 digital input or output.
Side 1 digital input or output.
Side 2 digital input or output.
Side 2 digital input or output.
Side 2 power supply.
A2
B1
B2
VDD2
GND2
Ground
Side 2 ground.
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Rev. 1.4 | 26
Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Package Outlines
7. Package Outlines
7.1 Package Outline (16-Pin Wide Body SOIC)
The figure below illustrates the package details for the Si84xx Digital Isolator. The table below lists the values for the dimensions shown
in the illustration.
Figure 7.1. 16-Pin Wide Body SOIC
Table 7.1. Package Diagram Dimensions
Symbol
Millimeters
Min
—
Max
2.65
0.3
A
A1
D
E
E1
b
0.1
10.3 BSC
10.3 BSC
7.5 BSC
0.31
0.20
0.51
0.33
c
e
1.27 BSC
h
0.25
0.4
0°
0.75
1.27
7°
L
θ
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Rev. 1.4 | 27
Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Package Outlines
7.2 Package Outline (8-Pin Narrow Body SOIC)
The figure below illustrates the package details for the Si84xx. The table below lists the values for the dimensions shown in the illustra-
tion.
Figure 7.2. 8-pin Small Outline Integrated Circuit (SOIC) Package
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Rev. 1.4 | 28
Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Package Outlines
Table 7.2. Package Diagram Dimensions
Symbol
Millimeters
Min
1.35
Max
1.75
A
A1
A2
B
0.10
0.25
1.40 REF
0.33
1.55 REF
0.51
C
D
E
0.19
0.25
4.80
5.00
3.80
4.00
e
1.27 BSC
H
h
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
L
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Rev. 1.4 | 29
Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Land Patterns
8. Land Patterns
8.1 Land Pattern (16-Pin Wide-Body SOIC)
The figure below illustrates the recommended land pattern details for the Si84xx in a 16-pin wide-body SOIC. The table below lists the
values for the dimensions shown in the illustration.
Figure 8.1. 16-Pin SOIC Land Pattern
Table 8.1. 16-Pin Wide Body SOIC Land Pattern Dimensions
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
9.40
1.27
0.60
1.90
C1
E
X1
Y1
Pad Length
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN for Density Level B (Median Land Protru-
sion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
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Rev. 1.4 | 30
Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Land Patterns
8.2 Land Pattern (8-Pin Narrow Body SOIC)
The figure below illustrates the recommended land pattern details for the Si84xx in an 8-pin narrow-body SOIC. The table below lists
the values for the dimensions shown in the illustration.
Figure 8.2. PCB Land Pattern: 8-Pin Narrow Body SOIC
Table 8.2. PCM Land Pattern Dimensions (8-Pin Narrow Body SOIC)
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
5.40
1.27
0.60
1.55
C1
E
X1
Y1
Pad Length
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X173-8N for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
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Rev. 1.4 | 31
Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Top Markings
9. Top Markings
9.1 Top Marking (16-Pin Wide Body SOIC)
Si84XYSV
YYWWTTTTTT
e4
TW
Figure 9.1. Isolator Top Marking
Table 9.1. Top Marking Explanation
Line 1 Marking: Base Part Number
Si84 = Isolator product series
Ordering Options
XY = Channel Configuration
X = # of data channels (2, 1)
(See 2. Ordering Guide for more information).
Y = # of reverse channels (1, 0)1,2
S = Speed Grade
A = 1 Mbps
B = 150 Mbps
V = Insulation rating
A = 1 kV; B = 2.5 kV; C = 3.75 kV; D = 5 kV
Line 2 Marking: YY = Year
WW = Workweek
Assigned by assembly subcontractor. Corresponds to the year
and workweek of the mold date.
TTTTTT = Mfg Code
Line 3 Marking: Circle = 1.7 mm Diameter
(Center-Justified)
Manufacturing code from assembly house.
“e4” Pb-Free Symbol.
Country of Origin ISO Code Abbreviation
TW = Taiwan.
Notes:
1. The Si8422 has one reverse channel.
2. The Si8423 has zero reverse channels.
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Rev. 1.4 | 32
Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Top Markings
9.2 Top Marking (8-Pin Narrow-Body SOIC)
Si84XYSV
YYWWRF
e3
AIXX
Figure 9.2. Isolator Top Marking
Table 9.2. Top Marking Explanation
Line 1 Marking: Base Part Number
Si84 = Isolator product series
Ordering Options
XY = Channel Configuration
X = # of data channels (2, 1)
(See 2. Ordering Guide for more information).
Y = # of reverse channels (1, 0)1,2
S = Speed Grade
A = 1 Mbps
B = 150 Mbps
V = Insulation rating
A = 1 kV; B = 2.5 kV; C = 3.75 kV; D = 5 kV
Line 2 Marking: YY = Year
WW = Workweek
Assigned by assembly subcontractor. Corresponds to the year
and workweek of the mold date.
R = Product (OPN) Revision
F = Wafer Fab
Line 3 Marking: Circle = 1.1 mm Diameter
Left-Justified
“e3” Pb-Free Symbol.
First two characters of the manufacturing code.
Last four characters of the manufacturing code.
A = Assembly Site
I = Internal Code
XX = Serial Lot Number
Notes:
1. The Si8422 has one reverse channel.
2. The Si8423 has zero reverse channels.
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Rev. 1.4 | 33
Si8410/20/21 (5 kV) Si8422/23 (2.5 & 5 kV) Data Sheet
Document Change List
10. Document Change List
10.1 Revision 0.1
• Initial release.
10.2 Revision 0.1 to Revision 1.0
• Updated features list.
• Updated transient immunity.
• Removed block diagram from front page.
• Added chip graphics on front page.
Added Peak Eye Diagram jitter in Table 5.2 Electrical Characteristics on page 9 through Table 5.4 Electrical Characteristics1 on
page 17.
•
• Updated transient immunity
• Moved Table 4.1 Si84xx Logic Operation Table on page 5 to Section 4. Device Operation.
• Added Section 4. Device Operation.
• Added Section 4.4 Fail-Safe Operating Mode.
• Moved Section 4.5 Typical Performance Characteristics.
• Deleted RF Radiated Emissions section.
• Deleted RF Magnetic and Common-Mode Transient Immunity section.
• Updated MSL rating to MSL2A.
10.3 Revision 1.0 to Revision 1.1
• Numerous text edits.
• Added table notes to Table 9.1 Top Marking Explanation on page 32 and Table 9.2 Top Marking Explanation on page 33.
10.4 Revision 1.1 to Revision 1.2
Updated Timing Characteristics in Table 5.2 Electrical Characteristics on page 9 through Table 5.4 Electrical Characteristics1 on
page 17.
•
10.5 Revision 1.2 to Revision 1.3
• Added references to AEC-Q100 qualified throughout.
• Changed all 60747-5-2 references to 60747-5-5.
Updated Table 2.1 Ordering Guide1,2,3 on page 2.
• Added table notes 1 and 2.
•
• Removed references to moisture sensitivity levels.
• Added Revision D ordering information.
• Removed older revisions.
• Updated Section 9.1 Top Marking (16-Pin Wide Body SOIC).
10.6 Revision 1.3 to Revision 1.4
September 16, 2016
• Updated data sheet format.
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Rev. 1.4 | 34
Table of Contents
1. Features List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1 Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.2 Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.1 Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.2 Under Voltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.3 Layout Recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.3.1 Supply Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.3.2 Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.3.3 Output Pin Termination . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.4 Fail-Safe Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.5 Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . 7
5. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1 Pin Descriptions (Wide-Body SOIC) . . . . . . . . . . . . . . . . . . . . . .25
6.2 Pin Descriptions (Narrow-Body SOIC). . . . . . . . . . . . . . . . . . . . . .26
7. Package Outlines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.1 Package Outline (16-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . . . .27
7.2 Package Outline (8-Pin Narrow Body SOIC). . . . . . . . . . . . . . . . . . . .28
8. Land Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.1 Land Pattern (16-Pin Wide-Body SOIC) . . . . . . . . . . . . . . . . . . . . .30
8.2 Land Pattern (8-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . .31
9. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.1 Top Marking (16-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . . . . .32
9.2 Top Marking (8-Pin Narrow-Body SOIC) . . . . . . . . . . . . . . . . . . . . .33
10. Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.1 Revision 0.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
10.2 Revision 0.1 to Revision 1.0. . . . . . . . . . . . . . . . . . . . . . . . .34
10.3 Revision 1.0 to Revision 1.1. . . . . . . . . . . . . . . . . . . . . . . . .34
10.4 Revision 1.1 to Revision 1.2. . . . . . . . . . . . . . . . . . . . . . . . .34
10.5 Revision 1.2 to Revision 1.3. . . . . . . . . . . . . . . . . . . . . . . . .34
10.6 Revision 1.3 to Revision 1.4. . . . . . . . . . . . . . . . . . . . . . . . .34
Table of Contents 35
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Disclaimer
Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or
intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"
parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes
without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included
information. Silicon Labs shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted
hereunder to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any Life Support System without the specific written consent of
Silicon Labs. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant
personal injury or death. Silicon Labs products are not designed or authorized for military applications. Silicon Labs products shall under no circumstances be used in weapons of mass
destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.
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EFM32®, EFR, Ember®, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZRadio®, EZRadioPRO®,
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