SI8622EB-B-ISR [SILICON]
Analog Circuit, 1 Func, CMOS, PDSO8, SOIC-8;
| 型号： | SI8622EB-B-ISR |
| 厂家： | 
SILICON |
| 描述： | Analog Circuit, 1 Func, CMOS, PDSO8, SOIC-8 光电二极管 |
| 文件： | 总40页 (文件大小：1012K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si861x/2x Data Sheet
Low-Power Single and Dual-Channel Digital Isolators
KEY FEATURES
Silicon Lab's family of ultra-low-power digital isolators are CMOS devices offering sub-
stantial data rate, propagation delay, power, size, reliability, and external BOM advan-
tages over legacy isolation technologies. The operating parameters of these products
remain stable across wide temperature ranges and throughout device service life for
ease of design and highly uniform performance. All device versions have Schmitt trigger
inputs for high noise immunity and only require VDD bypass capacitors.
• High-speed operation
• DC to 150 Mbps
• No start-up initialization required
• Wide Operating Supply Voltage
• 2.5–5.5 V
• Up to 5000 V
isolation
RMS
Data rates up to 150 Mbps are supported, and all devices achieve propagation delays of
less than 10 ns. Ordering options include a choice of isolation ratings (2.5, 3.75 and 5
kV) and a selectable fail-safe operating mode to control the default output state during
power loss. All products are safety certified by UL, CSA, VDE, and CQC, and products
• Reinforced VDE 0884-10, 10 kV surge-
capable (Si862xxT)
• 60-year life at rated working voltage
• High electromagnetic immunity
• Ultra low power (typical)
in wide-body packages support reinforced insulation withstanding up to 5 kVRMS
.
Automotive Grade is available for certain part numbers. These products are built using
automotive-specific flows at all steps in the manufacturing process to ensure the robust-
ness and low defectivity required for automotive applications.
5 V Operation
• 1.6 mA per channel at 1 Mbps
• 5.5 mA per channel at 100 Mbps
Automotive Applications
Industrial Applications
• On-board chargers
• Industrial automation systems
2.5 V Operation
• Battery management systems
• 1.5 mA per channel at 1 Mbps
• Medical electronics
• 3.5 mA per channel at 100 Mbps
• Schmitt trigger inputs
• Charging stations
• Isolated switch mode supplies
• Traction inverters
• Isolated ADC, DAC
• Selectable fail-safe mode
• Default high or low output (ordering
option)
• Hybrid Electric Vehicles
• Motor control
• Battery Electric Vehicles
• Power inverters
• Communications systems
• Precise timing (typical)
• 10 ns propagation delay
Safety Regulatory Approvals
• UL 1577 recognized
• 1.5 ns pulse width distortion
• 0.5 ns channel-channel skew
• 2 ns propagation delay skew
• 5 ns minimum pulse width
• Transient Immunity 50 kV/µs
• AEC-Q100 qualification
• Up to 5000 VRMS for 1 minute
• CSA component notice 5A approval
• IEC 60950-1, 61010-1, 60601-1 (re-
inforced insulation)
• VDE certification conformity
• Wide temperature range
• –40 to 125 °C
• Si862xxT options certified to rein-
forced VDE 0884-10
• RoHS-compliant packages
• SOIC-16 wide body
• All other options certified to IEC
60747-5-5 and reinforced 60950-1
• SOIC-8 narrow body
• Automotive-grade OPNs available
• AIAG compliant PPAP documentation
support
• CQC certification approval
• GB4943.1
• IMDS and CAMDS listing support
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Rev. 1.71
Si861x/2x Data Sheet
Ordering Guide
1. Ordering Guide
Table 1.1. Ordering Guide for Valid OPNs1, 2
Ordering Part
Number (OPN)
Number of
Inputs
VDD1 Side VDD2 Side
Number of
Inputs
Max Data Rate
(Mbps)
Default
Output
State
Isolation
Rating (kV)
Temp (C)
Package
Si8610BB-B-IS
Si8610BC-B-IS
Si8610EC-B-IS
Si8610BD-B-IS
Si8610ED-B-IS
Si8620BB-B-IS
Si8620EB-B-IS
Si8620BC-B-IS
Si8620EC-B-IS
Si8620BD-B-IS
Si8620ED-B-IS
Si8621BB-B-IS
Si8621BC-B-IS
Si8621EC-B-IS
Si8621BD-B-IS
Si8621ED-B-IS
Si8622BB-B-IS
Si8622EB-B-IS
Si8622BC-B-IS
Si8622EC-B-IS
Si8622BD-B-IS
Si8622ED-B-IS
1
1
1
1
1
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
Low
Low
High
Low
High
Low
High
Low
High
Low
High
Low
Low
High
Low
High
Low
High
Low
High
Low
High
2.5
3.75
3.75
5.0
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
SOIC-8
SOIC-8
SOIC-8
WB SOIC-16
WB SOIC-16
SOIC-8
5.0
2.5
2.5
SOIC-8
3.75
3.75
5.0
SOIC-8
SOIC-8
WB SOIC-16
WB SOIC-16
SOIC-8
5.0
2.5
3.75
3.75
5.0
SOIC-8
SOIC-8
WB SOIC-16
WB SOIC-16
SOIC-8
5.0
2.5
2.5
SOIC-8
3.75
3.75
5.0
SOIC-8
SOIC-8
WB SOIC-16
WB SOIC-16
5.0
Product Options with Reinforced VDE 0884-10 Rating with 10 kV Surge Capability
Si8620BT-IS
Si8620ET-IS
Si8621BT-IS
Si8621ET-IS
Si8622BT-IS
Si8622ET-IS
2
2
1
1
1
1
0
0
1
1
1
1
150
150
150
150
150
150
Low
High
Low
High
Low
High
5.0
5.0
5.0
5.0
5.0
5.0
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
WB SOIC-16
WB SOIC-16
WB SOIC-16
WB SOIC-16
WB SOIC-16
WB SOIC-16
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Rev. 1.71 | 2
Si861x/2x Data Sheet
Ordering Guide
Ordering Part
Number (OPN)
Number of
Inputs
VDD1 Side VDD2 Side
Number of
Inputs
Max Data Rate
(Mbps)
Default
Output
State
Isolation
Rating (kV)
Temp (C)
Package
Note:
1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifica-
tions and peak solder temperatures.
2. “Si” and “SI” are used interchangeably.
3. An "R" at the end of the part number denotes tape and reel packaging option.
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Rev. 1.71 | 3
Si861x/2x Data Sheet
Ordering Guide
Automotive Grade OPNs
Automotive-grade devices are built using automotive-specific flows at all steps in the manufacturing process to ensure robustness and
low defectivity. These devices are supported with AIAG-compliant Production Part Approval Process (PPAP) documentation, and fea-
ture International Material Data System (IMDS) and China Automotive Material Data System (CAMDS) listing. Qualifications are compli-
ant with AEC-Q100, and a zero-defect methodology is maintained throughout definition, design, evaluation, qualification, and mass pro-
duction steps.
Table 1.2. Ordering Guide for Automotive Grade OPNs1, 2, 4, 5
Ordering Part
Number (OPN)
Number of
Inputs
VDD1 Side VDD2 Side
Number of
Inputs
Max Data Rate
(Mbps)
Default
Output
State
Isolation
Rating (kV)
Temp (C)
Package
Si8620BB-AS
Si8620EB-AS
Si8621BB-AS
Si8621EC-AS
Si8621BD-AS
Si8621ED-AS
Si8622EC-AS
Si8622ED-AS
2
2
1
1
1
1
1
1
0
0
1
1
1
1
1
1
150
150
150
150
150
150
150
150
Low
High
Low
High
Low
High
High
High
2.5
2.5
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
–40 to 125 °C
SOIC-8
SOIC-8
2.5
SOIC-8
3.75
5.0
SOIC-8
WB SOIC-16
WB SOIC-16
SOIC-8
5.0
3.75
5.0
WB SOIC-16
Product Options with Reinforced VDE 0884-10 Rating with 10 kV Surge Capability
Si8622ET-AS 150 High 5.0
Note:
1
1
–40 to 125 °C
WB SOIC-16
1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifica-
tions.
2. “Si” and “SI” are used interchangeably.
3. An "R" at the end of the part number denotes tape and reel packaging option.
4. Automotive-Grade devices (with an "–A" suffix) are identical in construction materials, topside marking, and electrical parameters
to their Industrial-Grade (with a "–I" suffix) version counterparts. Automotive-Grade products are produced utilizing full automotive
process flows and additional statistical process controls throughout the manufacturing flow. The Automotive-Grade part number is
included on shipping labels.
5. Additional Ordering Part Numbers may be available in Automotive-Grade. Please contact your local Silicon Labs sales represen-
tative for further information.
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Rev. 1.71 | 4
Table of Contents
1. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 Layout Recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3.1 Supply Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3.2 Output Pin Termination. . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4 Fail-Safe Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.5 Typical Performance Characteristis. . . . . . . . . . . . . . . . . . . . . . .10
4. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5. Pin Descriptions (Wide-Body SOIC) . . . . . . . . . . . . . . . . . . . . . . 29
6. Pin Descriptions (Narrow-Body SOIC) . . . . . . . . . . . . . . . . . . . . . 30
7. Package Outline: 16-Pin Wide Body SOIC. . . . . . . . . . . . . . . . . . . . 31
8. Land Pattern: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . 33
9. Package Outline: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . 34
10. Land Pattern: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . 35
11. Top Marking: 16-Pin Wide Body SOIC. . . . . . . . . . . . . . . . . . . . . 36
12. Top Marking: 8-Pin Narrow Body SOIC
. . . . . . . . . . . . . . . . . . . . 37
13. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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Rev. 1.71 | 5
Si861x/2x Data Sheet
System Overview
2. System Overview
2.1 Theory of Operation
The operation of an Si861x/2x channel is analogous to that of an opto coupler, except an RF carrier is modulated instead of light. This
simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. A simplified
block diagram for a single Si861x/2x channel is shown in the figure below.
Figure 2.1. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier. Referring to the trans-
mitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The Receiver contains a demodulator that de-
codes the input state according to its RF energy content and applies the result to output B via the output driver. This RF on/off keying
scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and improved immunity
to magnetic fields. See the following figure for more details.
Figure 2.2. Modulation Scheme
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Si861x/2x Data Sheet
System Overview
2.2 Eye Diagram
The figure below illustrates an eye diagram taken on an Si8610. For the data source, the test used an Anritsu (MP1763C) Pulse Pattern
Generator set to 1000 ns/div. The output of the generator's clock and data from an Si8610 were captured on an oscilloscope. The re-
sults illustrate that data integrity was maintained even at the high data rate of 150 Mbps. The results also show that 2 ns pulse width
distortion and 350 ps peak jitter were exhibited.
Figure 2.3. Eye Diagram
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Rev. 1.71 | 7
Si861x/2x Data Sheet
Device Operation
3. Device Operation
Device behavior during start-up, normal operation, and shutdown is shown in Figure 3.1 Device Behavior during Normal Operation on
page 9, where UVLO+ and UVLO– are the respective positive-going and negative-going thresholds. Refer to the following table to
determine outputs when power supply (VDD) is not present.
Table 3.1. Si86xx Logic Operation
VI Input1, 2 VDDI State1, 3, 4 VDDO State1, 3, 4 VO Output1, 2
Comments
H
L
P
P
P
P
P
H
L
Normal operation.
X5
L6
UP
Upon transition of VDDI from unpowered to powered, VO re-
turns to the same state as VI in less than 1 µs.
H6
X5
P
UP
Undetermined Upon transition of VDDO from unpowered to powered, VO re-
turns to the same state as VI within 1 µs.
Note:
1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals.
2. X = not applicable; H = Logic High; L = Logic Low; Hi-Z = High Impedance.
3. “Powered” state (P) is defined as 2.5 V < VDD < 5.5 V.
4. “Unpowered” state (UP) is defined as VDD = 0 V.
5. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current.
6. See Ordering Guide for details. This is the selectable fail-safe operating mode (ordering option). Some devices have default out-
put state = H, and some have default output state = L, depending on the ordering part number (OPN). For default high devices,
the data channels have pull-ups on inputs/outputs. For default low devices, the data channels have pull-downs on inputs/outputs.
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Rev. 1.71 | 8
Si861x/2x Data Sheet
Device Operation
3.1 Device Startup
Outputs are held low during powerup until VDD is above the UVLO threshold for time period tSTART. Following this, the outputs follow
the states of inputs.
3.2 Undervoltage Lockout
Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or when VDD is below its
specified operating circuits range. Both Side A and Side B each have their own undervoltage lockout monitors. Each side can enter or
exit UVLO independently. For example, Side A unconditionally enters UVLO when VDD1 falls below VDD1(UVLO–) and exits UVLO when
VDD1 rises above VDD1(UVLO+). Side B operates the same as Side A with respect to its VDD2 supply.
Figure 3.1. Device Behavior during Normal Operation
3.3 Layout Recommendations
To ensure safety in the end-user application, high-voltage circuits (i.e., circuits with >30 VAC) must be physically separated from the
safety extra-low-voltage circuits (SELV is a circuit with <30 VAC) by a certain distance (creepage/clearance). If a component, such as a
digital isolator, straddles this isolation barrier, it must meet those creepage/clearance requirements and also provide a sufficiently large
high-voltage breakdown protection rating (commonly referred to as working voltage protection). Table 4.6 Insulation and Safety-Related
Specifications on page 25 and Table 4.8 IEC 60747-5-5 Insulation Characteristics for Si86xxxx1 on page 26 detail the working volt-
age and creepage/clearance capabilities of the Si86xx. These tables also detail the component standards (UL1577, IEC60747, CSA
5A), which are readily accepted by certification bodies to provide proof for end-system specifications requirements. Refer to the end-
system specification (61010-1, 60950-1, 60601-1, etc.) requirements before starting any design that uses a digital isolator.
3.3.1 Supply Bypass
The Si861x/2x family requires a 0.1 µF bypass capacitor between VDD1 and GND1 and VDD2 and GND2. The capacitor should be
placed as close as possible to the package. To enhance the robustness of a design, the user may also include resistors (50–300 Ω ) in
series with the inputs and outputs if the system is excessively noisy.
3.3.2 Output Pin Termination
The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of the on-
chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will
be a factor, output pins should be appropriately terminated with controlled impedance PCB traces.
3.4 Fail-Safe Operating Mode
Si86xx devices feature a selectable (by ordering option) mode whereby the default output state (when the input supply is unpowered)
can either be a logic high or logic low when the output supply is powered. See Table 3.1 Si86xx Logic Operation on page 8 and
1. Ordering Guide for more information.
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Rev. 1.71 | 9
Si861x/2x Data Sheet
Device Operation
3.5 Typical Performance Characteristis
The typical performance characteristics depicted in the following diagrams are for information purposes only. Refer to 4. Electrical
Specifications for actual specification limits.
Figure 3.2. Si8610 Typical VDD1 Supply Current vs. Data Rate
Figure 3.3. Si8610 Typical VDD2 Supply Current vs. Data Rate
5, 3.3, and 2.50 V Operation
5, 3.3, and 2.50 V Operation (15 pF Load)
Figure 3.4. Si8620 Typical VDD1 Supply Current vs. Data Rate
5, 3.3, and 2.50 V Operation
Figure 3.5. Si8620 Typical VDD2 Supply Current vs. Data Rate
5, 3.3, and 2.50 V Operation (15 pF Load)
Figure 3.6. Si8621 Typical VDD1 or VDD2 Supply Current vs.
Data Rate 5, 3.3, and 2.50 V Operation (15 pF Load)
Figure 3.7. Si8622 Typical VDD1 or VDD2 Supply Current vs.
Data Rate 5, 3.3, and 2.50 V Operation (15 pF Load)
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Rev. 1.71 | 10
Si861x/2x Data Sheet
Device Operation
Figure 3.8. Propagation Delay vs. Temperature (5.0 V Data)
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Rev. 1.71 | 11
Si861x/2x Data Sheet
Electrical Specifications
4. Electrical Specifications
Table 4.1. Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Ambient Operating Temperature1
Supply Voltage
1251
5.5
TA
–40
25
°C
VDD1
VDD2
2.5
2.5
—
—
V
V
5.5
Note:
1. The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels, and supply
voltage.
Table 4.2. Electrical Characteristics1
Parameter
VDD Undervoltage Threshold
VDD Undervoltage Threshold
VDD Undervoltage Hysteresis
Positive-Going Input Threshold
Negative-Going Input Threshold
Input Hysteresis
Symbol
VDDUV+
VDDUV–
VDDHYS
VT+
Test Condition
VDD1, VDD2 rising
VDD1, VDD2 falling
Min
Typ
2.24
2.16
70
Max
2.375
2.325
95
Unit
V
1.95
1.88
V
50
mV
V
All inputs rising
All inputs falling
1.4
1.67
1.23
0.44
—
1.9
VT–
1.0
1.4
V
VHYS
VIH
0.38
0.50
—
V
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Si86xxxB/C/D
2.0
V
VIL
—
VDD1, VDD2 – 0.4
—
—
0.8
V
VOH
loh = –4 mA
lol = 4 mA
4.8
—
V
VOL
0.2
0.4
V
IL
—
—
—
—
—
50
±10
±15
—
µA
Ω
Si86xxxT
Output Impedance2
ZO
DC Supply Current (All Inputs 0 V or at Supply)
Si8610Bx, Ex
VDD1
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
0.6
0.8
1.8
0.8
1.2
1.5
2.9
1.5
VDD2
VDD1
VDD2
mA
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Rev. 1.71 | 12
Si861x/2x Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Si8620Bx, Ex
VDD1
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
0.8
1.4
3.3
1.4
1.4
2.2
5.3
2.2
VDD2
mA
VDD1
VDD2
Si8621Bx, Ex
VDD1
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
1.2
1.2
2.4
2.4
1.9
1.9
3.8
3.8
VDD2
mA
VDD1
VDD2
Si8622Bx, Ex
VDD1
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
2.6
3.3
4.0
4.8
4.2
5.3
6.4
7.7
VDD2
mA
VDD1
VDD2
1 Mbps Supply Current (All Inputs = 500 kHz Square Wave, CI = 15 pF on All Outputs)
Si8610Bx, Ex
VDD1
mA
mA
—
—
1.2
0.9
2.0
1.5
VDD2
Si8620Bx, Ex
VDD1
—
—
2.1
1.6
3.1
2.4
VDD2
Si8621Bx, Ex
VDD1
mA
mA
—
—
1.9
1.9
2.9
2.9
VDD2
Si8622Bx, Ex
VDD1
—
—
3.4
4.2
5.1
6.2
VDD2
10 Mbps Supply Current (All Inputs = 5 MHz Square Wave, CI = 15 pF on All Outputs)
Si8610Bx, Ex
VDD1
mA
—
—
1.2
1.2
2.0
2.0
VDD2
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Rev. 1.71 | 13
Si861x/2x Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Si8620Bx, Ex
VDD1
mA
—
—
2.1
2.2
3.1
3.3
VDD2
Si8621Bx, Ex
VDD1
mA
mA
—
—
2.2
2.2
3.3
3.3
VDD2
Si8622Bx, Ex
VDD1
—
—
3.7
4.4
5.5
6.7
VDD2
100 Mbps Supply Current (All Inputs = 50 MHz Square Wave, CI = 15 pF on All Outputs)
Si8610Bx, Ex
VDD1
mA
mA
—
1.2
4.8
2.0
6.7
VDD2
—
Si8620Bx, Ex
VDD1
—
—
2.1
8.9
3.1
VDD2
12.5
Si8621Bx, Ex
VDD1
mA
mA
—
—
5.8
5.8
8.1
8.1
VDD2
Si8622Bx, Ex
VDD1
—
—
7.6
8.2
10.6
11.4
VDD2
Timing Characteristics
Si861x/2x Bx, Ex
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
0
—
—
150
5.0
13
Mbps
ns
—
tPHL, tPLH
See Figure 4.1 Propa-
gation Delay Timing on
page 16
5.0
8.0
ns
Pulse Width Distortion
|tPLH – tPHL|
See Figure 4.1 Propa-
gation Delay Timing on
page 16
PWD
—
0.2
4.5
ns
Propagation Delay Skew3
Channel-Channel Skew
All Models
tPSK(P-P)
tPSK
—
—
2.0
0.4
4.5
2.5
ns
ns
silabs.com | Building a more connected world.
Rev. 1.71 | 14
Si861x/2x Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
CL = 15 pF
See Figure 4.1 Propa-
gation Delay Timing on
page 16
tr
Output Rise Time
—
2.5
4.0
ns
CL = 15 pF
See Figure 4.1 Propa-
gation Delay Timing on
page 16
tf
Output Fall Time
—
—
2.5
4.0
—
ns
ps
Peak Eye Diagram Jitter
tJIT(PK)
See Figure 2.3 Eye Di-
agram on page 7
350
VI = VDD or 0 V
VCM = 1500 V
Common Mode Transient Immunity
Si86xxxB/C/D
CMTI
kV/µs
µs
See Figure 4.2 Com-
mon-Mode Transient
Immunity Test Circuit
on page 16
35
60
—
50
100
15
—
—
40
Si86xxxT
Start-up Time4
tSU
Note:
1. VDD1 = 5 V ±10%; VDD2 = 5 V ±10%, TA = –40 to 125 °C
2. The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of
the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission
line effects will be a factor, output pins should be appropriately terminated with controlled-impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same
supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to the appearance of valid data at the output.
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Rev. 1.71 | 15
Si861x/2x Data Sheet
Electrical Specifications
Figure 4.1. Propagation Delay Timing
Figure 4.2. Common-Mode Transient Immunity Test Circuit
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Rev. 1.71 | 16
Si861x/2x Data Sheet
Electrical Specifications
Table 4.3. Electrical Characteristics1
Parameter
VDD Undervoltage Threshold
VDD Undervoltage Threshold
VDD Undervoltage Hysteresis
Positive-Going Input Threshold
Negative-Going Input Threshold
Input Hysteresis
Symbol
VDDUV+
VDDUV–
VDDHYS
VT+
Test Condition
VDD1, VDD2 rising
VDD1, VDD2 falling
Min
Typ
2.24
2.16
70
Max
2.375
2.325
95
Unit
V
1.95
1.88
V
50
mV
V
All inputs rising
All inputs falling
1.4
1.67
1.23
0.44
—
1.9
VT–
1.0
1.4
V
VHYS
VIH
0.38
0.50
—
V
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Si86xxxB/C/D
2.0
V
VIL
—
VDD1, VDD2 – 0.4
—
—
0.8
V
VOH
loh = –4 mA
lol = 4 mA
3.1
—
V
VOL
0.2
0.4
V
IL
—
—
—
—
—
50
±10
±15
—
µA
Ω
Si86xxxT
Output Impedance2
ZO
DC Supply Current (All Inputs 0 V or at Supply)
Si8610Bx, Ex
VDD1
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
0.6
0.8
1.8
0.8
1.2
1.5
2.9
1.5
VDD2
mA
mA
mA
VDD1
VDD2
Si8620Bx, Ex
VDD1
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
0.8
1.4
3.3
1.4
1.4
2.2
5.3
2.2
VDD2
VDD1
VDD2
Si8621Bx, Ex
VDD1
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
1.2
1.2
2.4
2.4
1.9
1.9
3.8
3.8
VDD2
VDD1
VDD2
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Rev. 1.71 | 17
Si861x/2x Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Si8622Bx, Ex
VDD1
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
2.6
3.3
4.0
4.8
4.2
5.3
6.4
7.7
VDD2
mA
VDD1
VDD2
1 Mbps Supply Current (All Inputs = 500 kHz Square Wave, CI = 15 pF on All Outputs)
Si8610Bx, Ex
VDD1
mA
mA
mA
mA
—
—
1.2
0.9
2.0
1.5
VDD2
Si8620Bx, Ex
VDD1
—
—
2.1
1.6
3.1
2.4
VDD2
Si8621Bx, Ex
VDD1
—
—
1.9
1.9
2.9
2.9
VDD2
Si8622Bx, Ex
VDD1
—
—
3.4
4.2
5.1
6.2
VDD2
10 Mbps Supply Current (All Inputs = 5 MHz Square Wave, CI = 15 pF on All Outputs)
Si8610Bx, Ex
VDD1
mA
mA
mA
mA
—
—
1.2
1.0
2.0
1.8
VDD2
Si8620Bx, Ex
VDD1
—
—
2.1
1.9
3.1
2.8
VDD2
Si8621Bx, Ex
VDD1
—
—
2.0
2.0
3.0
3.0
VDD2
Si8622Bx, Ex
VDD1
—
—
3.5
4.3
5.3
6.4
VDD2
100 Mbps Supply Current (All Inputs = 50 MHz Square Wave, CI = 15 pF on All Outputs)
Si8610Bx, Ex
VDD1
mA
—
1.2
3.4
2.0
5.1
VDD2
—
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Rev. 1.71 | 18
Si861x/2x Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Si8620Bx, Ex
VDD1
mA
—
—
2.1
6.3
3.1
8.8
VDD2
Si8621Bx, Ex
VDD1
mA
mA
—
—
4.4
4.4
6.1
6.1
VDD2
Si8622Bx, Ex
VDD1
—
—
5.9
6.6
8.2
9.3
VDD2
Timing Characteristics
Si861x/2x Bx, Ex
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
0
—
—
150
5.0
13
Mbps
ns
—
tPHL, tPLH
See Figure 4.1 Propa-
gation Delay Timing on
page 16
5.0
8.0
ns
Pulse Width Distortion
|tPLH – tPHL|
See Figure 4.1 Propa-
gation Delay Timing on
page 16
PWD
—
0.2
4.5
ns
Propagation Delay Skew3
Channel-Channel Skew
All Models
tPSK(P-P)
tPSK
—
—
2.0
0.4
4.5
2.5
ns
ns
CL = 15 pF
See Figure 4.1 Propa-
gation Delay Timing on
page 16
tr
Output Rise Time
—
2.5
4.0
ns
CL = 15 pF
See Figure 4.1 Propa-
gation Delay Timing on
page 16
tf
Output Fall Time
—
—
2.5
4.0
—
ns
ps
Peak Eye Diagram Jitter
tJIT(PK)
See Figure 2.3 Eye Di-
agram on page 7
350
VI = VDD or 0 V
VCM = 1500 V
Common Mode Transient Immunity
Si86xxxB/C/D
CMTI
kV/µs
µs
See Figure 4.2 Com-
mon-Mode Transient
Immunity Test Circuit
on page 16
35
60
—
50
100
15
—
—
40
Si86xxxT
Start-up Time4
tSU
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Rev. 1.71 | 19
Si861x/2x Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Note:
1. VDD1 = 3.3 V ±10%; VDD2 = 3.3 V ±10%, TA = –40 to 125 °C
2. The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of
the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission
line effects will be a factor, output pins should be appropriately terminated with controlled-impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same
supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to the appearance of valid data at the output.
Table 4.4. Electrical Characteristics1
Parameter
VDD Undervoltage Threshold
VDD Undervoltage Threshold
VDD Undervoltage Hysteresis
Positive-Going Input Threshold
Negative-Going Input Threshold
Input Hysteresis
Symbol
VDDUV+
VDDUV–
VDDHYS
VT+
Test Condition
VDD1, VDD2 rising
VDD1, VDD2 falling
Min
Typ
2.24
2.16
70
Max
2.375
2.325
95
Unit
V
1.95
1.88
V
50
mV
V
All inputs rising
All inputs falling
1.6
—
1.9
VT–
1.1
—
1.4
V
VHYS
VIH
0.40
0.45
—
0.50
—
V
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Si86xxxB/C/D
2.0
V
VIL
—
VDD1, VDD2 – 0.4
—
—
0.8
V
VOH
loh = –4 mA
lol = 4 mA
2.3
0.2
—
V
VOL
0.4
V
IL
—
—
—
—
—
50
±10
±15
—
µA
Ω
Si86xxxT
Output Impedance2
ZO
DC Supply Current (All Inputs 0 V or at Supply)
Si8610Bx, Ex
VDD1
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
0.6
0.8
1.8
0.8
1.2
1.5
2.9
1.5
VDD2
mA
VDD1
VDD2
Si8620Bx, Ex
VDD1
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
0.8
1.4
3.3
1.4
1.4
2.2
5.3
2.2
VDD2
mA
VDD1
VDD2
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Rev. 1.71 | 20
Si861x/2x Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Si8621Bx, Ex
VDD1
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
1.2
1.2
2.4
2.4
1.9
1.9
3.8
3.8
VDD2
mA
VDD1
VDD2
Si8622Bx, Ex
VDD1
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
2.6
3.3
4.0
4.8
4.2
5.3
6.4
7.7
VDD2
mA
VDD1
VDD2
1 Mbps Supply Current (All Inputs = 500 kHz Square Wave, CI = 15 pF on All Outputs)
Si8610Bx, Ex
VDD1
mA
mA
mA
mA
—
—
1.2
0.9
2.0
1.5
VDD2
Si8620Bx, Ex
VDD1
—
—
2.1
1.6
3.1
2.4
VDD2
Si8621Bx, Ex
VDD1
—
—
1.9
1.9
2.9
2.9
VDD2
Si8622Bx, Ex
VDD1
—
—
3.4
4.2
5.1
6.2
VDD2
10 Mbps Supply Current (All Inputs = 5 MHz Square Wave, CI = 15 pF on All Outputs)
Si8610Bx, Ex
VDD1
mA
mA
mA
—
—
1.2
1.0
2.0
1.6
VDD2
Si8620Bx, Ex
VDD1
—
—
2.1
1.7
3.1
2.6
VDD2
Si8621Bx, Ex
VDD1
—
—
2.0
2.0
2.9
2.9
VDD2
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Rev. 1.71 | 21
Si861x/2x Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Si8622Bx, Ex
VDD1
mA
—
—
3.5
4.2
5.2
6.3
VDD2
100 Mbps Supply Current (All Inputs = 50 MHz Square Wave, CI = 15 pF on All Outputs)
Si8610Bx, Ex
VDD1
mA
mA
mA
mA
—
1.2
2.7
2.0
4.4
VDD2
—
Si8620Bx, Ex
VDD1
—
—
2.1
5.1
3.1
7.1
VDD2
Si8621Bx, Ex
VDD1
—
—
3.7
3.7
5.2
5.2
VDD2
Si8622Bx, Ex
VDD1
—
—
5.2
6.0
7.3
8.4
VDD2
Timing Characteristics
Si861x/2x Bx, Ex
Maximum Data Rate
Minimum Pulse Width
Propagation Delay
0
—
—
150
5.0
14
Mbps
ns
—
tPHL, tPLH
See Figure 4.1 Propa-
gation Delay Timing on
page 16
5.0
8.0
ns
Pulse Width Distortion
|tPLH – tPHL|
See Figure 4.1 Propa-
gation Delay Timing on
page 16
PWD
—
0.2
5.0
ns
Propagation Delay Skew3
Channel-Channel Skew
All Models
tPSK(P-P)
tPSK
—
—
2.0
0.4
5.0
2.5
ns
ns
CL = 15 pF
See Figure 4.1 Propa-
gation Delay Timing on
page 16
tr
Output Rise Time
—
2.5
4.0
ns
CL = 15 pF
See Figure 4.1 Propa-
gation Delay Timing on
page 16
tf
Output Fall Time
—
—
2.5
4.0
—
ns
ps
Peak Eye Diagram Jitter
tJIT(PK)
See Figure 2.3 Eye Di-
agram on page 7
350
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Rev. 1.71 | 22
Si861x/2x Data Sheet
Electrical Specifications
Parameter
Symbol
CMTI
tSU
Test Condition
Min
Typ
Max
Unit
kV/µs
µs
VI = VDD or 0 V
VCM = 1500 V
Common Mode Transient Immunity
Si86xxxB/C/D
See Figure 4.2 Com-
mon-Mode Transient
Immunity Test Circuit
on page 16
35
60
—
50
100
15
—
—
40
Si86xxxT
Start-up Time4
Note:
1. VDD1 = 2.5 V ±5%; VDD2 = 2.5 V ±5%, TA = –40 to 125 °C
2. The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of
the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission
line effects will be a factor, output pins should be appropriately terminated with controlled-impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same
supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to the appearance of valid data at the output.
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Rev. 1.71 | 23
Si861x/2x Data Sheet
Electrical Specifications
Table 4.5. Regulatory Information1, 2, 3, 4
For All Product Options Except Si86xxxT
CSA
The Si861x/2x is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.
61010-1: Up to 600 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage.
60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
60601-1: Up to 125 VRMS reinforced insulation working voltage; up to 380 VRMS basic insulation working voltage.
VDE
The Si861x/2x is certified according to IEC 60747-5-5. For more details, see File 5006301-4880-0001.
60747-5-5: Up to 1200 Vpeak for basic insulation working voltage.
60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
UL
The Si861x/2x is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 5000 VRMS isolation voltage for basic protection.
CQC
The Si861x/2x is certified under GB4943.1-2011. For more details, see certificates CQC13001096110 and CQC13001096239.
Rated up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
For All Si86xxxT Product Options
CSA
Certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.
60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
VDE
Certified according to VDE 0884-10.
UL
Certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 5000 VRMS isolation voltage for basic protection.
CQC
Certified under GB4943.1-2011.
Rated up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
Note:
1. Regulatory Certifications apply to 2.5 kVRMS rated devices, which are production tested to 3.0 kVRMS for 1 s.
2. Regulatory Certifications apply to 3.75 kVRMS rated devices, which are production tested to 4.5 kVRMS for 1 s.
3. Regulatory Certifications apply to 5.0 kVRMS rated devices, which are production tested to 6.0 kVRMS for 1 s.
4. For more information, see 1. Ordering Guide.
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Rev. 1.71 | 24
Si861x/2x Data Sheet
Electrical Specifications
Table 4.6. Insulation and Safety-Related Specifications
Parameter
Symbol
Test Condition
Value
Unit
WB SOIC-16
NB SOIC-8
Nominal Air Gap (Clearance)1
L(IO1)
L(IO2)
8.0
4.9
4.01
0.014
mm
mm
mm
Nominal External Tracking1
Minimum Internal Gap
(Internal Clearance)
Tracking Resistance
(Proof Tracking Index)
Erosion Depth
8.0
0.014
PTI
IEC60112
f = 1 MHz
600
600
VRMS
ED
0.019
0.019
mm
W
Resistance (Input-Output)2
Capacitance (Input-Output)2
1012
2.0
1012
2.0
RIO
CIO
CI
pF
pF
Input Capacitance3
4.0
4.0
Note:
1. The values in this table correspond to the nominal creepage and clearance values. VDE certifies the clearance and creepage
limits as 4.7 mm minimum for the NB SOIC-16 package and 8.5 mm minimum for the WB SOIC-16 package. UL does not impose
a clearance and creepage minimum for component-level certifications. CSA certifies the clearance and creepage limits as 3.9 mm
minimum for the NB SOIC-16 and 7.6 mm minimum for the WB SOIC-16 package.
2. To determine resistance and capacitance, the Si86xx is converted into a 2-terminal device. Pins 1–8 (1–4 on NB SOIC-8) are
shorted together to form the first terminal, and pins 9–16 (5–8 on NB SOIC-8) are shorted together to form the second terminal.
The parameters are then measured between these two terminals.
3. Measured from input pin to ground.
Table 4.7. IEC 60664-1 Ratings
Parameter
Test Conditions
Specification
WB SOIC-16
NB SOIC-8
Basic Isolation Group
Material Group
I
I
Installation Classification
Rated Mains Voltages < 150 VRMS
Rated Mains Voltages < 300 VRMS
Rated Mains Voltages < 400 VRMS
Rated Mains Voltages < 600 VRMS
I-IV
I-IV
I-III
I-III
I-IV
I-III
I-II
I-II
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Rev. 1.71 | 25
Si861x/2x Data Sheet
Electrical Specifications
Table 4.8. IEC 60747-5-5 Insulation Characteristics for Si86xxxx1
Test Condition
Parameter
Symbol
Characteristic
WB SOIC-16 NB SOIC-8
Unit
Maximum Working
Insulation Voltage
VIORM
1200
630
Vpeak
Vpeak
Input to Output Test
Voltage
VPR
Method b1
2250
6000
1182
(VIORM x 1.875 = VPR, 100%
Production Test, tm = 1 sec,
Partial Discharge < 5 pC)
t = 60 sec
Transient Overvolt-
age
VIOTM
6000
Vpeak
Vpeak
Tested per IEC 60065 with surge voltage of 1.2 µs/50 µs
Si86xxxT tested with magnitude 6250 V x 1.6 = 10 kV
Si86xxxB/C/D tested with 4000 V
VIOSM
Surge Voltage
6250
4000
2
—
4000
2
Pollution Degree
(DIN VDE 0110, Ta-
ble 1)
>109
>109
Insulation Resist-
RS
Ω
ance at TS, VIO
=
500 V
Note:
1. Maintenance of the safety data is ensured by protective circuits. The Si86xxxx provides a climate classification of 40/125/21.
Table 4.9. IEC Safety Limiting Values1
Parameter
Symbol
Test Condition
Max
WB SOIC-16
Unit
NB SOIC-8
150
Case Temperature
TS
IS
150
220
°C
Safety Input, Output, or Supply Current
θJA = 140 °C/W (NB SOIC-8)
100 °C/W (WB SOIC-16)
160
mA
VI = 5.5 V, TJ = 150 °C, TA = 25 °C
Device Power Dissipation2
PD
150
150
mW
Note:
1. Maximum value allowed in the event of a failure; also see the thermal derating curve in Figure 4.3 (WB SOIC-16) Thermal Derat-
ing Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-5/VDE 0884-10, as Applies on
page 27 and Figure 4.4 (NB SOIC-8) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature
per DIN EN 60747-5-5/VDE 0884-10, as Applies on page 27.
2. The Si86xx is tested with VDD1 = VDD2 = 5.5 V; TJ = 150 ºC; CL = 15 pF, input a 150 Mbps 50% duty cycle square wave.
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Rev. 1.71 | 26
Si861x/2x Data Sheet
Electrical Specifications
Table 4.10. Thermal Characteristics
Parameter
Symbol
WB SOIC-16
NB SOIC-8
140
Unit
IC Junction-to-Air Thermal Resistance
θJA
100
°C/W
Figure 4.3. (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN
60747-5-5/VDE 0884-10, as Applies
Figure 4.4. (NB SOIC-8) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN
60747-5-5/VDE 0884-10, as Applies
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Rev. 1.71 | 27
Si861x/2x Data Sheet
Electrical Specifications
Table 4.11. Absolute Maximum Ratings1
Parameter
Storage Temperature2
Symbol
Min
Max
Unit
TSTG
–65
150
°C
Operating Temperature
Junction Temperature
Supply Voltage
TA
–40
—
125
150
°C
°C
TJ
VDD1, VDD2
–0.5
–0.5
–0.5
—
7.0
V
Input Voltage
VI
VO
IO
VDD + 0.5
VDD + 0.5
10
V
Output Voltage
V
Output Current Drive Channel
Lead Solder Temperature (10 s)
Maximum Isolation (Input to Output) (1 sec)
NB SOIC-16
mA
°C
—
260
—
4500
VRMS
Maximum Isolation (Input to Output) (1 sec)
WB SOIC-16
—
6500
VRMS
Note:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to
conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum ratings for exteneded peri-
ods may degrade performance.
2. VDE certifies storage temperature from –40 to 150 °C.
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Rev. 1.71 | 28
Si861x/2x Data Sheet
Pin Descriptions (Wide-Body SOIC)
5. Pin Descriptions (Wide-Body SOIC)
GND2
NC
GND2
NC
GND2
NC
GND2
NC
GND1
NC
GND1
NC
GND1
NC
GND1
NC
I
s
o
l
I
s
o
l
I
s
o
l
I
s
o
l
VDD1
A1
VDD1
A1
VDD1
A1
VDD1
A1
VDD2
B1
VDD2
B1
VDD2
B1
VDD2
B1
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
RF
RCVR
RF
XMITR
a
t
i
o
n
a
t
i
o
n
a
t
i
o
n
a
t
i
o
n
RF
RCVR
RF
RCVR
RF
XMITR
RF
XMITR
RF
RCVR
RF
XMITR
NC
NC
NC
A2
NC
B2
A2
NC
B2
A2
NC
B2
NC
NC
NC
NC
GND1
NC
NC
GND1
NC
NC
GND1
NC
NC
GND1
NC
NC
GND2
GND2
GND2
GND2
Si8610 WB SOIC-16
Si8620 WB SOIC-16
Si8621 WB SOIC-16
Si8622 WB SOIC-16
Name
SOIC-16 Pin#
SOIC-16 Pin#
Type
Description
Si8610
Si862x
GND1
NC1
1
1
Ground
Side 1 ground.
NC
2, 5, 6, 8,10,
2, 6, 8,10,
No Connect
11, 12, 15
11, 15
3
VDD1
A1
3
4
Supply
Digital I/O
Digital I/O
Ground
Side 1 power supply.
Side 1 digital input or output.
Side 1 digital input or output.
Side 1 ground.
4
A2
NC
7
5
GND1
GND2
B2
7
9
9
Ground
Side 2 ground.
NC
13
14
16
12
13
14
16
Digital I/O
Digital I/O
Supply
Side 2 digital input or output.
Side 2 digital input or output.
Side 2 power supply.
Side 2 ground.
B1
VDD2
GND2
Ground
Note:
1. No Connect. These pins are not internally connected. They can be left floating, tied to VDD, or tied to GND.
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Rev. 1.71 | 29
Si861x/2x Data Sheet
Pin Descriptions (Narrow-Body SOIC)
6. Pin Descriptions (Narrow-Body SOIC)
VDD1
VDD2
VDD1
VDD1
VDD1
VDD2
B1
VDD2
B1
VDD2
B1
I
s
o
l
a
t
i
o
n
I
s
o
l
a
t
i
o
n
I
s
o
l
a
t
i
o
n
I
s
o
l
a
t
i
o
n
RF
XMITR
RF
XMITR
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
RF
RCVR
GND2/NC
A1
A1
A2
A1
A2
A1
A2
RF
RCVR
VDD1/NC
B1
RF
XMITR
RF
RCVR
RF
RCVR
RF
XMITR
RF
XMITR
RF
RCVR
B2
B2
B2
GND1
GND2
GND1
GND2
GND1
GND2
GND1
GND2
Si8610 NB SOIC-8
Si8620 NB SOIC-8
Si8621 NB SOIC-8
Si8622 NB SOIC-8
Name
SOIC-8 Pin#
Si861x
SOIC-8 Pin#
Type
Description
Si862x
VDD1/NC1
GND1
A1
1, 3
1
Supply
Side 1 power supply.
4
2
4
2
3
7
6
8
5
Ground
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Supply
Side 1 ground.
Side 1 digital input or output.
Side 1 digital input or output.
Side 2 digital input or output.
Side 2 digital input or output.
Side 2 power supply.
A2
NA
6
B1
B2
NA
8
VDD2
GND2/NC1
5.7
Ground
Side 2 ground.
Note:
1. No connect. These pins are not internally connected. They can be left floating, tied to VDD, or tied to GND.
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Rev. 1.71 | 30
Si861x/2x Data Sheet
Package Outline: 16-Pin Wide Body SOIC
7. Package Outline: 16-Pin Wide Body SOIC
The figure below illustrates the package details for the Triple-Channel Digital Isolator. The table lists the values for the dimensions
shown in the illustration.
Figure 7.1. 16-Pin Wide Body SOIC
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Rev. 1.71 | 31
Si861x/2x Data Sheet
Package Outline: 16-Pin Wide Body SOIC
Table 7.1. 16-Pin Wide Body SOIC Package Diagram Dimensions1, 2, 3, 4
Dimension
Min
—
Max
2.65
0.30
—
A
A1
A2
b
0.10
2.05
0.31
0.20
0.51
0.33
c
D
10.30 BSC
10.30 BSC
7.50 BSC
1.27 BSC
E
E1
e
L
0.40
0.25
0°
1.27
0.75
8°
h
θ
aaa
bbb
ccc
ddd
eee
fff
—
0.10
0.33
0.10
0.25
0.10
0.20
—
—
—
—
—
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Outline MS-013, Variation AA.
4. Recommended reflow profile per JEDEC J-STD-020 specification for small body, lead-free components.
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Rev. 1.71 | 32
Si861x/2x Data Sheet
Land Pattern: 16-Pin Wide Body SOIC
8. Land Pattern: 16-Pin Wide Body SOIC
The figure below illustrates the recommended land pattern details for the Si861x/2x in a 16-pin wide-body SOIC package. The table
lists the values for the dimensions shown in the illustration.
Figure 8.1. PCB Land Pattern: 16-Pin Wide Body SOIC
Table 8.1. 16-Pin Wide Body SOIC Land Pattern Dimensions1, 2
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
9.40
1.27
0.60
1.90
C1
E
X1
Y1
Pad Length
Note:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN for Density Level B (Median Land Protru-
sion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
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Rev. 1.71 | 33
Si861x/2x Data Sheet
Package Outline: 8-Pin Narrow Body SOIC
9. Package Outline: 8-Pin Narrow Body SOIC
The figure below illustrates the package details for the Si86xx. The table lists the values for the dimensions shown in the illustration.
Figure 9.1. 8-Pin Small Outline Integrated Circuit (SOIC) Package
Table 9.1. 8-Pin Small Outline Integrated Circuit (SOIC) Package Diagram Dimensions
Symbol
Millimeters
Min
1.35
Max
1.75
A
A1
A2
B
0.10
0.25
1.40 REF
0.33
1.55 REF
0.51
C
D
E
0.19
0.25
4.80
5.00
3.80
4.00
e
1.27 BSC
H
h
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
L
m
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Rev. 1.71 | 34
Si861x/2x Data Sheet
Land Pattern: 8-Pin Narrow Body SOIC
10. Land Pattern: 8-Pin Narrow Body SOIC
The figure below illustrates the recommended land pattern details for the Si86xx in an 8-pin narrow-body SOIC. The table lists the val-
ues for the dimensions shown in the illustration.
Figure 10.1. PCB Land Pattern: 8-Pin Narrow Body SOIC
Table 10.1. 8-Pin Narrow Body SOIC Land Pattern Dimensions1, 2
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
5.40
1.27
0.60
1.55
C1
E
X1
Y1
Pad Length
Note:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X173-8N for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
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Rev. 1.71 | 35
Si861x/2x Data Sheet
Top Marking: 16-Pin Wide Body SOIC
11. Top Marking: 16-Pin Wide Body SOIC
Si86XYSV
YYWWRTTTTT
e4
CC
Figure 11.1. 16-Pin Wide Body SOIC Top Marking
Table 11.1. 16-Pin Wide Body SOIC Top Marking Explanation
Line 1 Marking:
Base Part Number
Ordering Options
Si86 = Isolator product series
X = # of data channels (2, 1)
Y = # of reverse channels (2, 1, 0)1
(See Ordering Guide for more
information.)
S = Speed Grade (max data rate) and operating mode:
B = 150 Mbps (default output = low)
E = 150 Mbps (default output = high)
V = Insulation rating
B = 2.5 kV; C = 3.75 kV; D = 5.0 kV; T = 5.0 kV with 10 kV surge
capability.
Line 2 Marking:
Line 3 Marking:
YY = Year
Assigned by assembly subcontractor. Corresponds to the year
and workweek of the mold date.
WW = Workweek
RTTTTT = Mfg Code
Manufacturing code from assembly house
“R” indicates revision
Circle = 1.7 mm Diameter
(Center-Justified)
“e4” Pb-Free Symbol
Country of Origin ISO Code Ab- CC = Country of Origin ISO Code Abbreviation
breviation
• TW = Taiwan
• TH = Thailand
Note:
1. The Si8622 has 1 forward and 1 reverse channel, but directionality is reversed compared to the Si8621, as shown in 5. Pin De-
scriptions (Wide-Body SOIC) and 6. Pin Descriptions (Narrow-Body SOIC)
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Rev. 1.71 | 36
Si861x/2x Data Sheet
Top Marking: 8-Pin Narrow Body SOIC
12. Top Marking: 8-Pin Narrow Body SOIC
Si86XYSV
YYWWRT
e3
TTTT
Figure 12.1. 8-Pin Narrow Body SOIC Top Marking
Table 12.1. 8-Pin Narrow Body SOIC Top Marking Explanation
Line 1 Marking:
Line 2 Marking:
Base Part Number
Ordering Options
Si86 = Isolator Product Series
XY = Channel Configuration
S = Speed Grade (max data rate)
V = Insulation rating
(See Ordering Guide for more information).
YY = Year
Assigned by assembly subcontractor. Corresponds to
the year and workweek of the mold date.
WW = Workweek
R = Product (OPN) Revision
T = First character of the manufacturing code
Circle = 1.1 mm Diameter
First two characters of the manufacturing code from As-
sembly.
Line 3 Marking:
Note:
“e3” Pb-Free Symbol.
TTTT = Last four characters of the manufac- Last four characters of the manufacturing code.
turing code
1. The Si8622 has 1 forward and 1 reverse channel, but directionality is reversed compared to the Si8621, as shown in 5. Pin De-
scriptions (Wide-Body SOIC) and 6. Pin Descriptions (Narrow-Body SOIC)
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Rev. 1.71 | 37
Si861x/2x Data Sheet
Revision History
13. Revision History
Revision 1.71
• Added new table to Ordering Guide for Automotive-Grade OPN options.
Revision 1.7
• Added following note to 1. Ordering Guide: "An 'R' at the end of the part number denotes tape and reel packaging option."
Revision 1.6
• Added product options Si862xxT in 1. Ordering Guide.
• Added spec line items for Input Leakage Current pertaining to Si862xxT in 4. Electrical Specifications.
• Updated IEC 60747-5-2 to IEC 60747-5-5 in all instances in document.
Revision 1.5
• Updated Table 5 on page 17.
• Added CQC certificate numbers.
• Updated "5. Ordering Guide" on page 11.
• Removed references to moisture sensitivity levels.
• Removed Note 2.
Revision 1.4
• Added Figure 2, “Common Mode Transient Immunity Test Circuit,” on page 8.
• Added references to CQC throughout.
• Added references to 2.5 kVRMS devices throughout.
• Updated "5. Ordering Guide" on page 11.
• Updated "10.1. 16-Pin Wide Body SOIC Top Marking" on page 18.
Revision 1.3
• Updated Table 11 on page 21.
• Added junction temperature spec.
• Updated "2.3.1. Supply Bypass" on page 6.
• Removed “3.3.2. Pin Connections” on page 22.
• Updated "5. Ordering Guide" on page 11.
• Removed Rev A devices.
• Updated "6. Package Outline: 16-Pin Wide Body SOIC" on page 13.
• Updated Top Marks.
• Added revision description.
Revision 1.2
• Updated Table 1 on page 4.
• Deleted reference to EN.
• Updated "5. Ordering Guide" on page 11 to include MSL2A.
Revision 1.1
• Updated High Level Output Voltage VOH to 3.1 V in Table 3, “Electrical Characteristics,” on page 9.
• Updated High Level Output Voltage VOH to 2.3 V in Table 4, “Electrical Characteristics,” on page 13.
Revision 1.0
• Updated “Table 3. Electrical Characteristics”.
• Reordered spec tables to conform to new convention.
• Removed “pending” throughout document.
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Rev. 1.71 | 38
Si861x/2x Data Sheet
Revision History
Revision 0.3
• Added chip graphics on page 1.
• Updated Table 6, “Insulation and Safety-Related Specifications,” on page 18.
• Updated Table 8, “IEC 60747-5-5 Insulation Characteristics for Si86xxxx*,” on page 19.
• Updated "3. Pin Descriptions (Wide-Body SOIC)" on page 9.
• Updated "4. Pin Descriptions (Narrow-Body SOIC)" on page 10.
• Updated "5. Ordering Guide" on page 11.
Revision 0.2
• Added chip graphics on page 1.
• Moved Tables 1 and 11 to page 21.
• Updated Table 6, “Insulation and Safety-Related Specifications,” on page 18.
• Updated Table 8, “IEC 60747-5-5 Insulation Characteristics for Si86xxxx*,” on page 19.
• Moved Table 1 to page 4.
• Moved “Typical Performance Characteristics” to page 7.
• Updated "3. Pin Descriptions (Wide-Body SOIC)" on page 9.
• Updated "4. Pin Descriptions (Narrow-Body SOIC)" on page 10.
• Updated "5. Ordering Guide" on page 11.
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Rev. 1.71 | 39
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Disclaimer
Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or
intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"
parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes
without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included
information. Silicon Labs shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted
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