SI8630EC-B-IS1 [SILICON]
Analog Circuit, 1 Func, CMOS, PDSO16, SOIC-16;
| 型号： | SI8630EC-B-IS1 |
| 厂家： | 
SILICON |
| 描述： | Analog Circuit, 1 Func, CMOS, PDSO16, SOIC-16 光电二极管 |
| 文件： | 总37页 (文件大小：973K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si8630/31/35 Data Sheet
Low-Power Single and Dual-Channel Digital Isolators
KEY FEATURES
Silicon Lab's family of ultra-low-power digital isolators are CMOS devices offering sub-
stantial data rate, propagation delay, power, size, reliability, and external BOM advan-
tages over legacy isolation technologies. The operating parameters of these products
remain stable across wide temperature ranges and throughout device service life for
ease of design and highly uniform performance. All device versions have Schmitt trigger
inputs for high noise immunity and only require VDD bypass capacitors.
• High-speed operation
• DC to 150 Mbps
• No start-up initialization required
• Wide Operating Supply Voltage
• 2.5–5.5 V
• Up to 5000 V
isolation
RMS
Data rates up to 150 Mbps are supported, and all devices achieve propagation delays of
less than 10 ns. Ordering options include a choice of isolation ratings (2.5, 3.75 and 5
kV) and a selectable fail-safe operating mode to control the default output state during
power loss. All products are safety certified by UL, CSA, VDE, and CQC, and products
• Reinforced VDE 0884-10, 10 kV surge-
capable (Si862xxT)
• 60-year life at rated working voltage
• High electromagnetic immunity
• Ultra low power (typical)
in wide-body packages support reinforced insulation withstanding up to 5 kVRMS
.
Automotive Grade is available for certain part numbers. These products are built using
automotive-specific flows at all steps in the manufacturing process to ensure the robust-
ness and low defectivity required for automotive applications.
5 V Operation
• 1.6 mA per channel at 1 Mbps
• 5.5 mA per channel at 100 Mbps
Automotive Applications
Industrial Applications
• On-board chargers
• Industrial automation systems
2.5 V Operation
• Battery management systems
• 1.5 mA per channel at 1 Mbps
• Medical electronics
• 3.5 mA per channel at 100 Mbps
• Schmitt trigger inputs
• Charging stations
• Isolated switch mode supplies
• Traction inverters
• Isolated ADC, DAC
• Selectable fail-safe mode
• Default high or low output (ordering
option)
• Hybrid Electric Vehicles
• Motor control
• Battery Electric Vehicles
• Power inverters
• Communications systems
• Precise timing (typical)
• 10 ns propagation delay
Safety Regulatory Approvals
• UL 1577 recognized
• 1.5 ns pulse width distortion
• 0.5 ns channel-channel skew
• 2 ns propagation delay skew
• 5 ns minimum pulse width
• Transient Immunity 50 kV/µs
• AEC-Q100 qualification
• Up to 5000 VRMS for 1 minute
• CSA component notice 5A approval
• IEC 60950-1, 61010-1, 60601-1 (re-
inforced insulation)
• VDE certification conformity
• Wide temperature range
• –40 to 125 °C
• Si862xxT options certified to rein-
forced VDE 0884-10
• RoHS-compliant packages
• SOIC-16 wide body
• All other options certified to IEC
60747-5-5 and reinforced 60950-1
• SOIC-16 narrow body
• Automotive-grade OPNs available
• AIAG compliant PPAP documentation
support
• CQC certification approval
• GB4943.1
• IMDS and CAMDS listing support
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Rev. 1.81
Si8630/31/35 Data Sheet
Ordering Guide
1. Ordering Guide
Table 1.1. Ordering Guide for Valid OPNs1, 2
Ordering Part Number (OPN) Number of Number of Max Data
Default
Output
State
Isolation
Rating
(kVrms)
Temp Range (°C)
Package
Inputs
Inputs
Rate
VDD1 Side VDD2 Side
(Mbps)
Si8630BB-B-IS
Si8630BB-B-IS1
Si8630BC-B-IS1
Si8630EC-B-IS1
Si8630BD-B-IS
Si8630ED-B-IS
Si8631BB-B-IS
Si8631BB-B-IS1
Si8631BC-B-IS1
Si8631EC-B-IS1
Si8631BD-B-IS
Si8631ED-B-IS
Si8635BB-B-IS
Si8635BC-B-IS1
Si8635BD-B-IS
3
3
3
3
3
3
2
2
2
2
2
2
3
3
3
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
Low
Low
Low
High
Low
High
Low
Low
Low
High
Low
High
Low
Low
Low
2.5
2.5
–40 to +125 °C WB SOIC-16
–40 to +125 °C NB SOIC-16
–40 to +125 °C NB SOIC-16
–40 to +125 °C NB SOIC-16
–40 to +125 °C WB SOIC-16
–40 to +125 °C WB SOIC-16
–40 to +125 °C WB SOIC-16
–40 to +125 °C NB SOIC-16
–40 to +125 °C NB SOIC-16
–40 to +125 °C NB SOIC-16
–40 to +125 °C WB SOIC-16
–40 to +125 °C WB SOIC-16
–40 to +125 °C WB SOIC-16
–40 to +125 °C NB SOIC-16
–40 to +125 °C WB SOIC-16
3.75
3.75
5.0
5.0
2.5
2.5
3.75
3.75
5.0
5.0
2.5
3.75
5.0
Product Options with Reinforced VDE 0884-10 Rating with 10 kV Surge Capability
Si8630BT-IS
Si8630ET-IS
Si8631BT-IS
Si8631ET-IS
Si8635BT-IS
Si8635ET-IS
3
3
2
2
3
3
0
0
1
1
0
0
150
150
150
150
150
150
Low
High
Low
High
Low
High
5.0
5.0
5.0
5.0
5.0
5.0
–40 to +125 °C WB SOIC-16
–40 to +125 °C WB SOIC-16
–40 to +125 °C WB SOIC-16
–40 to +125 °C WB SOIC-16
–40 to +125 °C WB SOIC-16
–40 to +125 °C WB SOIC-16
Note:
1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifica-
tions and peak solder temperatures.
2. “Si” and “SI” are used interchangeably.
3. An "R" at the end of the part number denotes tape and reel packaging option.
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Rev. 1.81 | 2
Si8630/31/35 Data Sheet
Ordering Guide
Automotive Grade OPNs
Automotive-grade devices are built using automotive-specific flows at all steps in the manufacturing process to ensure robustness and
low defectivity. These devices are supported with AIAG-compliant Production Part Approval Process (PPAP) documentation, and fea-
ture International Material Data System (IMDS) and China Automotive Material Data System (CAMDS) listing. Qualifications are compli-
ant with AEC-Q100, and a zero-defect methodology is maintained throughout definition, design, evaluation, qualification, and mass pro-
duction steps.
Table 1.2. Ordering Guide for Automotive Grade OPNs1, 2, 4, 5
Ordering Part Number (OPN)
Number Number Max Da- Default Isolation
Temp
Range
(°C)
Pack-
age
of In-
puts
of In-
puts
ta Rate Output
Rating
(kVrms)
(Mbps)
State
VDD1
Side
VDD2
Side
Si8631BB-AS1
Si8631BC-AS1
Si8631BD-AS
2
2
2
1
1
1
150
150
150
Low
Low
Low
2.5
3.75
5.0
–40 to
+125 °C
NB SO-
IC-16
–40 to
+125 °C
NB SO-
IC-16
–40 to
+125 °C
WB SO-
IC-16
Note:
1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifica-
tions.
2. “Si” and “SI” are used interchangeably.
3. An "R" at the end of the part number denotes tape and reel packaging option.
4. Automotive-Grade devices (with an "–A" suffix) are identical in construction materials, topside marking, and electrical parameters
to their Industrial-Grade (with a "–I" suffix) version counterparts. Automotive-Grade products are produced utilizing full automotive
process flows and additional statistical process controls throughout the manufacturing flow. The Automotive-Grade part number is
included on shipping labels.
5. Additional Ordering Part Numbers may be available in Automotive-Grade. Please contact your local Silicon Labs sales represen-
tative for further information.
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Rev. 1.81 | 3
Table of Contents
1. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 Layout Recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3.1 Supply Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3.2 Output Pin Termination. . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4 Fail-Safe Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.5 Typical Performance Characteristis. . . . . . . . . . . . . . . . . . . . . . .10
4. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6. Package Outline: 16-Pin Wide Body SOIC. . . . . . . . . . . . . . . . . . . . 27
7. Land Pattern: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . 29
8. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . 30
9. Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . 32
10. Top Marking: 16-Pin Wide Body SOIC. . . . . . . . . . . . . . . . . . . . . 33
11. Top Marking: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . 34
12. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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Rev. 1.81 | 4
Si8630/31/35 Data Sheet
System Overview
2. System Overview
2.1 Theory of Operation
The operation of an Si863x channel is analogous to that of an opto coupler, except an RF carrier is modulated instead of light. This
simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. A simplified
block diagram for a single Si863x channel is shown in the figure below.
Figure 2.1. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier. Referring to the trans-
mitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The Receiver contains a demodulator that de-
codes the input state according to its RF energy content and applies the result to output B via the output driver. This RF on/off keying
scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and improved immunity
to magnetic fields. See the following figure for more details.
Figure 2.2. Modulation Scheme
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Si8630/31/35 Data Sheet
System Overview
2.2 Eye Diagram
The figure below illustrates an eye diagram taken on an Si8630. For the data source, the test used an Anritsu (MP1763C) Pulse Pattern
Generator set to 1000 ns/div. The output of the generator's clock and data from an Si8630 were captured on an oscilloscope. The re-
sults illustrate that data integrity was maintained even at the high data rate of 150 Mbps. The results also show that 2 ns pulse width
distortion and 350 ps peak jitter were exhibited.
Figure 2.3. Eye Diagram
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Rev. 1.81 | 6
Si8630/31/35 Data Sheet
Device Operation
3. Device Operation
Device behavior during start-up, normal operation, and shutdown is shown in Figure 3.1 Device Behavior during Normal Operation on
page 9, where UVLO+ and UVLO– are the respective positive-going and negative-going thresholds. Refer to the following tables to
determine outputs when power supply (VDD) is not present and for logic conditions when enable pins are used.
Table 3.1. Si86xx Logic Operation
VI Input1, 2
EN Input1, 2, 3, 4 VDDI State1, 5, 6 VDDO State1, 5, 6 VO Output1, 2
Comments
H
L
H or NC
H or NC
L
P
P
P
P
P
P
H
L
Enabled, normal operation.
X7
X7
Hi-Z8
L9
Disabled.
H or NC
UP
P
Upon transition of VDDI from unpowered to
powered, VO returns to the same state as
VI in less than 1 µs.
H9
X7
X7
Hi-Z8
L
UP
P
P
Disabled.
X7
UP
Undetermined Upon transition of VDDO from unpowered
to powered, VO returns to the same state
as VI within 1 µs, if EN is in either the H or
NC state. Upon transition of VDDO from
unpowered to powered, VO returns to Hi-Z
within 1 µs if EN is L.
Note:
1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals. EN is the
enable control input located on the same output side.
2. X = not applicable; H = Logic High; L = Logic Low; Hi-Z = High Impedance.
3. It is recommended that the enable inputs be connected to an external logic high or low level when the Si86xx is operating in noisy
environments.
4. No Connect (NC) replaces EN1 on Si8630/35. No Connect replaces EN2 on the Si8635. No Connects are not internally connec-
ted and can be left floating, tied to VDD, or tied to GND.
5. “Powered” state (P) is defined as 2.5 V < VDD < 5.5 V.
6. “Unpowered” state (UP) is defined as VDD = 0 V.
7. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current.
8. When using the enable pin (EN) function, the output pin state is driven into a high-impedance state when the EN pin is disabled
(EN = 0).
9. See Ordering Guide for details. This is the selectable fail-safe operating mode (ordering option). Some devices have default out-
put state = H, and some have default output state = L, depending on the ordering part number (OPN). For default high devices,
the data channels have pull-ups on inputs/outputs. For default low devices, the data channels have pull-downs on inputs/outputs.
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Rev. 1.81 | 7
Si8630/31/35 Data Sheet
Device Operation
Table 3.2. Enable Input Truth
EN11, 2
—
EN21, 2
Part Number
Operation
Si8630
H
L
Outputs B1, B2, B3 are enabled and follow input state.
Outputs B1, B2, B3 are disabled and in high impedance state.3
Output A3 enabled and follows the input state.
—
Si8631
H
L
X
X
Output A3 disabled and in high impedance state.3
Outputs B1, B2 are enabled and follow the input state.
X
X
H
L
Outputs B1, B2 are disabled and in high impedance state.3
Outputs B1, B2, B3 are enabled and follow the input state.
Si8635
—
—
Note:
1. Enable inputs EN1 and EN2 can be used for multiplexing, for clock sync, or other output control. These inputs are internally
pulled-up to local VDD allowing them to be connected to an external logic level (high or low) or left floating. To minimize noise
coupling, do not connect circuit traces to EN1 or EN2 if they are left floating. If EN1, EN2 are unused, it is recommended they be
connected to an external logic level, especially if the Si86xx is operating in a noisy environment.
2. X = not applicable; H = Logic High; L = Logic Low.
3. When using the enable pin (EN) function, the output pin state is driven into a high-impedance state when the EN pin is disabled
(EN = 0).
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Si8630/31/35 Data Sheet
Device Operation
3.1 Device Startup
Outputs are held low during powerup until VDD is above the UVLO threshold for time period tSTART. Following this, the outputs follow
the states of inputs.
3.2 Undervoltage Lockout
Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or when VDD is below its
specified operating circuits range. Both Side A and Side B each have their own undervoltage lockout monitors. Each side can enter or
exit UVLO independently. For example, Side A unconditionally enters UVLO when VDD1 falls below VDD1(UVLO–) and exits UVLO when
VDD1 rises above VDD1(UVLO+). Side B operates the same as Side A with respect to its VDD2 supply.
Figure 3.1. Device Behavior during Normal Operation
3.3 Layout Recommendations
To ensure safety in the end-user application, high-voltage circuits (i.e., circuits with >30 VAC) must be physically separated from the
safety extra-low-voltage circuits (SELV is a circuit with <30 VAC) by a certain distance (creepage/clearance). If a component, such as a
digital isolator, straddles this isolation barrier, it must meet those creepage/clearance requirements and also provide a sufficiently large
high-voltage breakdown protection rating (commonly referred to as working voltage protection). Table 4.6 Insulation and Safety-Related
Specifications on page 22 and Table 4.8 IEC 60747-5-5 Insulation Characteristics for Si86xxxx 1 on page 23 detail the working volt-
age and creepage/clearance capabilities of the Si86xx. These tables also detail the component standards (UL1577, IEC60747, CSA
5A), which are readily accepted by certification bodies to provide proof for end-system specifications requirements. Refer to the end-
system specification (61010-1, 60950-1, 60601-1, etc.) requirements before starting any design that uses a digital isolator.
3.3.1 Supply Bypass
The Si863x family requires a 0.1 µF bypass capacitor between VDD1 and GND1 and VDD2 and GND2. The capacitor should be placed
as close as possible to the package. To enhance the robustness of a design, the user may also include resistors (50–300 Ω ) in series
with the inputs and outputs if the system is excessively noisy.
3.3.2 Output Pin Termination
The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of the on-
chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will
be a factor, output pins should be appropriately terminated with controlled impedance PCB traces.
3.4 Fail-Safe Operating Mode
Si86xx devices feature a selectable (by ordering option) mode whereby the default output state (when the input supply is unpowered)
can either be a logic high or logic low when the output supply is powered. See Table 3.1 Si86xx Logic Operation on page 7 and
1. Ordering Guide for more information.
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Rev. 1.81 | 9
Si8630/31/35 Data Sheet
Device Operation
3.5 Typical Performance Characteristis
The typical performance characteristics depicted in the following diagrams are for information purposes only. Refer to 4. Electrical
Specifications for actual specification limits.
Figure 3.2. Si8630/35 Typical VDD1 Supply Current vs. Data
Figure 3.3. Si8630/35 Typical VDD2 Supply Current vs. Data
Rate 5, 3.3, and 2.5 V Operation
Rate 5, 3.3, and 2.5 V Operation (15 pF Load)
Figure 3.4. Si8631 Typical VDD1 Supply Current vs. Data Rate
Figure 3.5. Si8631 Typical VDD2 Supply Current vs. Data Rate
5, 3.3, and 2.5 V Operation
5, 3.3, and 2.5 V Operation (15 pF Load)
Figure 3.6. Propagation Delay vs. Temperature (5.0 V Data)
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Rev. 1.81 | 10
Si8630/31/35 Data Sheet
Electrical Specifications
4. Electrical Specifications
Table 4.1. Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Ambient Operating Temperature 1
Supply Voltage
125 1
5.5
TA
–40
25
°C
VDD1
VDD2
2.5
2.5
—
—
V
V
5.5
Note:
1. The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels, and supply
voltage.
Table 4.2. Electrical Characteristics 1
Parameter
VDD Undervoltage Threshold
VDD Undervoltage Threshold
VDD Undervoltage Hysteresis
Positive-Going Input Threshold
Negative-Going Input Threshold
Input Hysteresis
Symbol
VDDUV+
VDDUV–
VDDHYS
VT+
Test Condition
VDD1, VDD2 rising
VDD1, VDD2 falling
Min
Typ
2.24
2.16
70
Max
2.375
2.325
95
Unit
V
1.95
1.88
V
50
mV
V
All inputs rising
All inputs falling
1.4
1.67
1.23
0.44
—
1.9
VT–
1.0
1.4
V
VHYS
VIH
0.38
0.50
—
V
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Si863xxA/B/C/D
2.0
V
VIL
—
VDD1, VDD2 – 0.4
—
—
0.8
V
VOH
loh = –4 mA
lol = 4 mA
4.8
—
V
VOL
0.2
0.4
V
IL
—
—
—
—
—
50
±10
±15
—
µA
Ω
Si863xxT
Output Impedance 2
Enable Input Current
Si863xxA/B/C/D
Si863xxT
ZO
IENH, IENL
VENx = VIH or VIL
—
—
2.0
—
—
µA
10.0
DC Supply Current (All Inputs 0 V or at Supply)
Si8630Bx, Ex, Si8635Bx
VDD1
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
0.9
1.9
4.6
1.9
1.6
3.0
7.4
3.0
VDD2
VDD1
VDD2
mA
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Rev. 1.81 | 11
Si8630/31/35 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Si8631Bx, Ex
VDD1
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
1.3
1.7
3.9
3.0
2.1
2.7
5.9
4.5
VDD2
mA
VDD1
VDD2
1 Mbps Supply Current (All Inputs = 500 kHz Square Wave, CI = 15 pF on All Outputs)
Si8630Bx, Ex, Si8635Bx
VDD1
mA
mA
—
—
2.8
2.2
3.9
3.1
VDD2
Si8631Bx, Ex
VDD1
—
—
2.7
2.6
3.8
3.6
VDD2
10 Mbps Supply Current (All Inputs = 5 MHz Square Wave, CI = 15 pF on All Outputs)
Si8630Bx, Ex, Si8635Bx
VDD1
mA
mA
—
—
2.8
3.1
3.9
4.3
VDD2
Si8631Bx, Ex
VDD1
—
—
3.0
3.1
4.2
4.4
VDD2
100 Mbps Supply Current (All Inputs = 50 MHz Square Wave, CI = 15 pF on All Outputs)
Si8630Bx, Ex, Si8635Bx
VDD1
mA
mA
—
—
2.8
3.9
VDD2
13.2
17.8
Si8631Bx, Ex
VDD1
—
—
6.6
9.9
8.8
VDD2
13.4
Timing Characteristics
Si863xBx, Ex
Maximum Data Rate
Minimum Pulse Width
0
—
—
150
5.0
13
Mbps
ns
—
Propagation Delay
tPHL, tPLH
See Figure 4.2 Propagation
Delay Timing on page 14
5.0
8.0
ns
Pulse Width Distortion
|tPLH – tPHL|
See Figure 4.2 Propagation
Delay Timing on page 14
PWD
tPSK(P-P)
tPSK
—
0.2
4.5
ns
Propagation Delay Skew 3
Channel-Channel Skew
—
—
2.0
0.4
4.5
2.5
ns
ns
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Rev. 1.81 | 12
Si8630/31/35 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
All Models
CL = 15 pF
tr
Output Rise Time
—
2.5
4.0
ns
See Figure 4.2 Propagation
Delay Timing on page 14
CL = 15 pF
tf
Output Fall Time
—
—
2.5
4.0
—
ns
ps
See Figure 4.2 Propagation
Delay Timing on page 14
Peak Eye Diagram Jitter
tJIT(PK)
See Figure 2.3 Eye Diagram
on page 6
350
VI = VDD or 0 V
VCM = 1500 V
Common Mode Transient Immunity
Si86xxxB/C/D
CMTI
kV/µs
See Figure 4.3 Common-
Mode Transient Immunity Test
Circuit on page 14
35
60
—
50
100
6.0
—
—
11
Si86xxxT
Enable to Data Valid
ten1
ten2
tSD
See Figure 4.1 ENABLE Tim-
ing Diagram on page 14
ns
ns
ns
Enable to Data Tri-State
See Figure 4.1 ENABLE Tim-
ing Diagram on page 14
—
—
8.0
8.0
12
12
Input power loss to valid default output
See Figure 3.1 Device Behav-
ior during Normal Operation
on page 9
Start-up Time 4
tSU
—
15
40
µs
Note:
1. VDD1 = 5 V ±10%; VDD2 = 5 V ±10%, TA = –40 to 125 °C
2. The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of
the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission
line effects will be a factor, output pins should be appropriately terminated with controlled-impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same
supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to the appearance of valid data at the output.
silabs.com | Building a more connected world.
Rev. 1.81 | 13
Si8630/31/35 Data Sheet
Electrical Specifications
Figure 4.1. ENABLE Timing Diagram
Figure 4.2. Propagation Delay Timing
Figure 4.3. Common-Mode Transient Immunity Test Circuit
silabs.com | Building a more connected world.
Rev. 1.81 | 14
Si8630/31/35 Data Sheet
Electrical Specifications
Table 4.3. Electrical Characteristics 1
Parameter
VDD Undervoltage Threshold
VDD Undervoltage Threshold
VDD Undervoltage Hysteresis
Positive-Going Input Threshold
Negative-Going Input Threshold
Input Hysteresis
Symbol
Test Condition
VDD1, VDD2 rising
VDD1, VDD2 falling
Min
Typ
2.24
2.16
70
Max
2.375
2.325
95
Unit
V
VDDUV+
VDDUV–
VDDHYS
VT+
1.95
1.88
V
50
mV
V
All inputs rising
All inputs falling
1.4
1.67
1.23
0.44
—
1.9
VT–
1.0
1.4
V
VHYS
VIH
0.38
0.50
—
V
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Si863xxA/B/C/D
2.0
V
VIL
—
VDD1, VDD2 – 0.4
—
—
0.8
V
VOH
loh = –4 mA
lol = 4 mA
3.1
—
V
VOL
0.2
0.4
V
IL
—
—
—
—
—
50
±10
±15
—
µA
Ω
Si863xxT
Output Impedance 2
Enable Input Current
Si863xxA/B/C/D
Si863xxT
ZO
IENH, IENL
VENx = VIH or VIL
—
—
2.0
—
—
µA
10.0
DC Supply Current (All Inputs 0 V or at Supply)
Si8630Bx, Ex, Si8635Bx
VDD1
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
0.9
1.9
4.6
1.9
1.6
3.0
7.4
3.0
VDD2
mA
VDD1
VDD2
Si8631Bx, Ex
VDD1
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
1.3
1.7
3.9
3.0
2.1
2.7
5.9
4.5
VDD2
mA
VDD1
VDD2
1 Mbps Supply Current (All Inputs = 500 kHz Square Wave, CI = 15 pF on All Outputs)
Si8630Bx, Ex, Si8635Bx
VDD1
mA
—
—
2.8
2.2
3.9
3.1
VDD2
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Rev. 1.81 | 15
Si8630/31/35 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Si8631Bx, Ex
VDD1
mA
—
—
2.7
2.6
3.8
3.6
VDD2
10 Mbps Supply Current (All Inputs = 5 MHz Square Wave, CI = 15 pF on All Outputs)
Si8630Bx, Ex, Si8635Bx
VDD1
mA
mA
—
—
2.8
2.6
3.9
3.6
VDD2
Si8631Bx, Ex
VDD1
—
—
2.8
2.6
4.0
3.9
VDD2
100 Mbps Supply Current (All Inputs = 50 MHz Square Wave, CI = 15 pF on All Outputs)
Si8630Bx, Ex, Si8635Bx
VDD1
mA
mA
—
—
2.8
9.3
3.9
VDD2
12.5
Si8631Bx, Ex
VDD1
—
—
5.2
7.3
7.0
9.8
VDD2
Timing Characteristics
Si863xBx, Ex
Maximum Data Rate
Minimum Pulse Width
0
—
—
150
5.0
13
Mbps
ns
—
Propagation Delay
tPHL, tPLH
See Figure 4.2 Propagation
Delay Timing on page 14
5.0
8.0
ns
Pulse Width Distortion
|tPLH – tPHL|
See Figure 4.2 Propagation
Delay Timing on page 14
PWD
tPSK(P-P)
tPSK
—
0.2
4.5
ns
Propagation Delay Skew 3
Channel-Channel Skew
All Models
—
—
2.0
0.4
4.5
2.5
ns
ns
CL = 15 pF
tr
Output Rise Time
—
2.5
4.0
ns
See Figure 4.2 Propagation
Delay Timing on page 14
CL = 15 pF
tf
Output Fall Time
—
—
2.5
4.0
—
ns
ps
See Figure 4.2 Propagation
Delay Timing on page 14
Peak Eye Diagram Jitter
tJIT(PK)
See Figure 2.3 Eye Diagram
on page 6
350
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Rev. 1.81 | 16
Si8630/31/35 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
VI = VDD or 0 V
VCM = 1500 V
Common Mode Transient Immunity
Si86xxxB/C/D
CMTI
kV/µs
See Figure 4.3 Common-
Mode Transient Immunity Test
Circuit on page 14
35
60
—
50
100
6.0
—
—
11
Si86xxxT
Enable to Data Valid
ten1
ten2
tSD
See Figure 4.1 ENABLE Tim-
ing Diagram on page 14
ns
ns
ns
Enable to Data Tri-State
See Figure 4.1 ENABLE Tim-
ing Diagram on page 14
—
—
8.0
8.0
12
12
Input power loss to valid default output
See Figure 3.1 Device Behav-
ior during Normal Operation
on page 9
Start-up Time 4
tSU
—
15
40
µs
Note:
1. VDD1 = 3.3 V ±10%; VDD2 = 3.3 V ±10%, TA = –40 to 125 °C
2. The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of
the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission
line effects will be a factor, output pins should be appropriately terminated with controlled-impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same
supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to the appearance of valid data at the output.
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Rev. 1.81 | 17
Si8630/31/35 Data Sheet
Electrical Specifications
Table 4.4. Electrical Characteristics 1
Parameter
VDD Undervoltage Threshold
VDD Undervoltage Threshold
VDD Undervoltage Hysteresis
Positive-Going Input Threshold
Negative-Going Input Threshold
Input Hysteresis
Symbol
Test Condition
VDD1, VDD2 rising
VDD1, VDD2 falling
Min
Typ
2.24
2.16
70
Max
2.375
2.325
95
Unit
V
VDDUV+
VDDUV–
VDDHYS
VT+
1.95
1.88
V
50
mV
V
All inputs rising
All inputs falling
1.4
1.67
1.23
0.44
—
1.9
VT–
1.0
1.4
V
VHYS
VIH
0.38
0.50
—
V
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Si863xxA/B/C/D
2.0
V
VIL
—
VDD1, VDD2 – 0.4
—
—
0.8
V
VOH
loh = –4 mA
lol = 4 mA
2.3
—
V
VOL
0.2
0.4
V
IL
—
—
—
—
—
50
±10
±15
—
µA
Ω
Si863xxT
Output Impedance 2
Enable Input Current
Si863xxA/B/C/D
Si863xxT
ZO
IENH, IENL
VENx = VIH or VIL
—
—
2.0
—
—
µA
10.0
DC Supply Current (All Inputs 0 V or at Supply)
Si8630Bx, Ex, Si8635Bx
VDD1
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
0.9
1.9
4.6
1.9
1.6
3.0
7.4
3.0
VDD2
mA
VDD1
VDD2
Si8631Bx, Ex
VDD1
VI = 0(Bx), 1(Ex)
VI = 0(Bx), 1(Ex)
VI = 1(Bx), 0(Ex)
VI = 1(Bx), 0(Ex)
—
—
—
—
1.3
1.7
3.9
3.0
2.1
2.7
5.9
4.5
VDD2
mA
VDD1
VDD2
1 Mbps Supply Current (All Inputs = 500 kHz Square Wave, CI = 15 pF on All Outputs)
Si8630Bx, Ex, Si8635Bx
VDD1
mA
—
—
2.8
2.2
3.9
3.1
VDD2
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Rev. 1.81 | 18
Si8630/31/35 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Si8631Bx, Ex
VDD1
mA
—
—
2.7
2.6
3.8
3.6
VDD2
10 Mbps Supply Current (All Inputs = 5 MHz Square Wave, CI = 15 pF on All Outputs)
Si8630Bx, Ex, Si8635Bx
VDD1
mA
mA
—
—
2.8
2.4
3.9
3.3
VDD2
Si8631Bx, Ex
VDD1
—
—
2.8
2.7
3.9
3.7
VDD2
100 Mbps Supply Current (All Inputs = 50 MHz Square Wave, CI = 15 pF on All Outputs)
Si8630Bx, Ex, Si8635Bx
VDD1
mA
mA
—
—
2.8
7.5
3.9
VDD2
10.1
Si8631Bx, Ex
VDD1
—
—
4.5
6.1
6.1
8.2
VDD2
Timing Characteristics
Si863xBx, Ex
Maximum Data Rate
Minimum Pulse Width
0
—
—
150
5.0
14
Mbps
ns
—
Propagation Delay
tPHL, tPLH
See Figure 4.2 Propagation
Delay Timing on page 14
5.0
8.0
ns
Pulse Width Distortion
|tPLH -tPHL|
See Figure 4.2 Propagation
Delay Timing on page 14
PWD
tPSK(P-P)
tPSK
—
0.2
5.0
ns
Propagation Delay Skew 3
Channel-Channel Skew
All Models
—
—
2.0
0.4
5.0
2.5
ns
ns
CL = 15 pF
tr
Output Rise Time
—
2.5
4.0
ns
See Figure 4.2 Propagation
Delay Timing on page 14
CL = 15 pF
tf
Output Fall Time
—
—
2.5
4.0
—
ns
ps
See Figure 4.2 Propagation
Delay Timing on page 14
Peak Eye Diagram Jitter
tJIT(PK)
See Figure 2.3 Eye Diagram
on page 6
350
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Rev. 1.81 | 19
Si8630/31/35 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
VI = VDD or 0 V
VCM = 1500 V
Common Mode Transient Immunity
Si86xxxB/C/D
CMTI
kV/µs
See Figure 4.3 Common-
Mode Transient Immunity Test
Circuit on page 14
35
60
—
50
100
6.0
—
—
11
Si86xxxT
Enable to Data Valid
ten1
ten2
tSD
See Figure 4.1 ENABLE Tim-
ing Diagram on page 14
ns
ns
ns
Enable to Data Tri-State
See Figure 4.1 ENABLE Tim-
ing Diagram on page 14
—
—
8.0
8.0
12
12
Input power loss to valid default output
See Figure 3.1 Device Behav-
ior during Normal Operation
on page 9
Start-up Time 4
tSU
—
15
40
µs
Note:
1. VDD1 = 2.5 V ±5%; VDD2 = 2.5 V ±5%, TA = –40 to 125 °C
2. The nominal output impedance of an isolator driver channel is approximately 50 Ω, ±40%, which is a combination of the value of
the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission
line effects will be a factor, output pins should be appropriately terminated with controlled-impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same
supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to the appearance of valid data at the output.
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Rev. 1.81 | 20
Si8630/31/35 Data Sheet
Electrical Specifications
Table 4.5. Regulatory Information 1, 2, 3, 4
For All Product Options Except Si863xxT
CSA
The Si863x is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.
61010-1: Up to 600 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage.
60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
60601-1: Up to 125 VRMS reinforced insulation working voltage; up to 380 VRMS basic insulation working voltage.
VDE
The Si863x is certified according to IEC 60747-5-5. For more details, see File 5006301-4880-0001.
60747-5-5: Up to 1200 Vpeak for basic insulation working voltage.
60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
UL
The Si863x is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 5000 VRMS isolation voltage for basic protection.
CQC
The Si863x is certified under GB4943.1-2011. For more details, see certificates CQC13001096110 and CQC13001096239.
Rated up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
For All Si863xxT Product Options
CSA
Certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.
60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
VDE
Certified according to VDE 0884-10.
UL
Certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 5000 VRMS isolation voltage for basic protection.
CQC
Certified under GB4943.1-2011
Rated up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
Note:
1. Regulatory Certifications apply to 2.5 kVRMS rated devices, which are production tested to 3.0 kVRMS for 1 s.
2. Regulatory Certifications apply to 3.75 kVRMS rated devices, which are production tested to 4.5 kVRMS for 1 s.
3. Regulatory Certifications apply to 5.0 kVRMS rated devices, which are production tested to 6.0 kVRMS for 1 s.
4. For more information, see 1. Ordering Guide.
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Rev. 1.81 | 21
Si8630/31/35 Data Sheet
Electrical Specifications
Table 4.6. Insulation and Safety-Related Specifications
Parameter
Symbol
Test Condition
Value
Unit
WB SOIC-16
NB SOIC-16
Nominal Air Gap (Clearance) 1
L(IO1)
L(IO2)
8.0
4.9
4.01
0.014
mm
mm
mm
Nominal External Tracking 1
Minimum Internal Gap
(Internal Clearance)
Tracking Resistance
(Proof Tracking Index)
Erosion Depth
8.0
0.014
PTI
IEC60112
f = 1 MHz
600
600
VRMS
ED
0.019
0.019
mm
Ω
Resistance (Input-Output) 2
Capacitance (Input-Output) 2
1012
2.0
1012
2.0
RIO
CIO
CI
pF
pF
Input Capacitance 3
4.0
4.0
Note:
1. The values in this table correspond to the nominal creepage and clearance values. VDE certifies the clearance and creepage
limits as 4.7 mm minimum for the NB SOIC-16 package and 8.5 mm minimum for the WB SOIC-16 package. UL does not impose
a clearance and creepage minimum for component-level certifications. CSA certifies the clearance and creepage limits as 3.9 mm
minimum for the NB SOIC-16 and 7.6 mm minimum for the WB SOIC-16 package.
2. To determine resistance and capacitance, the Si86xx is converted into a 2-terminal device. Pins 1–8 are shorted together to form
the first terminal and pins 9–16 are shorted together to form the second terminal. The parameters are then measured between
these two terminals.
3. Measured from input pin to ground.
Table 4.7. IEC 60664-1 Ratings
Parameter
Test Conditions
Specification
WB SOIC-16
NB SOIC-16
Basic Isolation Group
Material Group
I
I
Installation Classification
Rated Mains Voltages < 150 VRMS
Rated Mains Voltages < 300 VRMS
Rated Mains Voltages < 400 VRMS
Rated Mains Voltages < 600 VRMS
I-IV
I-IV
I-III
I-III
I-IV
I-III
I-II
I-II
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Si8630/31/35 Data Sheet
Electrical Specifications
Table 4.8. IEC 60747-5-5 Insulation Characteristics for Si86xxxx 1
Test Condition
Parameter
Symbol
Characteristic
WB SOIC-16 NB SOIC-16
Unit
Maximum Working
Insulation Voltage
VIORM
1200
630
Vpeak
Vpeak
Input to Output Test
Voltage
VPR
Method b1
2250
6000
1182
(VIORM x 1.875 = VPR, 100%
Production Test, tm = 1 sec,
Partial Discharge < 5 pC)
t = 60 sec
Transient Overvolt-
age
VIOTM
6000
Vpeak
Vpeak
Tested per IEC 60065 with surge voltage of 1.2 µs/50 µs
Si863xxT tested with magnitude 6250 V x 1.6 = 10 kV
Si863xxB/C/D tested with 4000 V
VIOSM
Surge Voltage
6250
4000
2
—
4000
2
Pollution Degree
(DIN VDE 0110, Ta-
ble 1)
>109
>109
Insulation Resist-
RS
Ω
ance at TS, VIO
=
500 V
Note:
1. Maintenance of the safety data is ensured by protective circuits. The Si86xxxx provides a climate classification of 40/125/21.
Table 4.9. IEC Safety Limiting Values 1
Parameter
Symbol
Test Condition
Max
WB SOIC-16
Unit
NB SOIC-16
150
Case Temperature
TS
IS
150
220
°C
Safety Input, Output, or Supply Current
θJA = 100 °C/W (WB SOIC-16)
105 °C/W (NB SOIC-16)
210
mA
VI = 5.5 V, TJ = 150 °C, TA = 25 °C
Device Power Dissipation 2
PD
275
275
mW
Note:
1. Maximum value allowed in the event of a failure; also see the thermal derating curve in Figure 4.4 (WB SOIC-16) Thermal Derat-
ing Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-5/VDE 0884-10, as Applies on
page 24 and Figure 4.5 (NB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature
per DIN EN 60747-5-5/VDE 0884-10, as Applies on page 24.
2. The Si86xx is tested with VDD1 = VDD2 = 5.5 V; TJ = 150 ºC; CL = 15 pF, input a 150 Mbps 50% duty cycle square wave.
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Rev. 1.81 | 23
Si8630/31/35 Data Sheet
Electrical Specifications
Table 4.10. Thermal Characteristics
Parameter
Symbol
WB SOIC-16
NB SOIC-16
105
Unit
IC Junction-to-Air Thermal Resistance
θJA
100
°C/W
Figure 4.4. (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN
60747-5-5/VDE 0884-10, as Applies
Figure 4.5. (NB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN
60747-5-5/VDE 0884-10, as Applies
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Rev. 1.81 | 24
Si8630/31/35 Data Sheet
Electrical Specifications
Table 4.11. Absolute Maximum Ratings 1
Parameter
Storage Temperature 2
Symbol
Min
Max
Unit
TSTG
–65
150
°C
Operating Temperature
Junction Temperature
Supply Voltage
TA
–40
—
125
150
°C
°C
TJ
VDD1, VDD2
–0.5
–0.5
–0.5
—
7.0
V
Input Voltage
VI
VO
IO
VDD + 0.5
VDD + 0.5
10
V
Output Voltage
V
Output Current Drive Channel
Lead Solder Temperature (10 s)
Maximum Isolation (Input to Output) (1 sec)
NB SOIC-16
mA
°C
—
260
—
4500
VRMS
Maximum Isolation (Input to Output) (1 sec)
WB SOIC-16
—
6500
VRMS
Note:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to
conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum ratings for exteneded peri-
ods may degrade performance.
2. VDE certifies storage temperature from –40 to 150 °C.
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Rev. 1.81 | 25
Si8630/31/35 Data Sheet
Pin Descriptions
5. Pin Descriptions
VDD1
GND1
A1
VDD1
VDD2
GND2
B1
VDD2
GND2
B1
GND1
I
s
o
l
a
t
i
o
n
I
s
o
l
a
t
i
o
n
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
A1
A2
RF
XMITR
RF
RCVR
RF
XMITR
RF
RCVR
A2
A3
B2
B2
RF
XMITR
RF
RCVR
RF
RCVR
RF
XMITR
B3
A3
NC
B3
NC
NC
NC
EN2/NC
GND2
EN2
GND2
NC
EN1
GND1
GND1
Si8630/35
Si8631
Name
SOIC-16 Pin#
Type
Supply
Ground
Description
VDD1
1
Side 1 power supply.
Side 1 ground.
21
3
GND1
A1
A2
A3
NC
Digital Input
Digital Input
Digital I/O
NA
Side 1 digital input.
Side 1 digital input.
4
5
Side 1 digital input or output.
No Connect.
6
EN1/NC2
GND1
7
Digital Input
Side 1 active high enable. NC on Si8630/35
Side 1 ground.
81
Ground
Ground
91
GND2
Side 2 ground.
EN2/NC2
NC
10
Digital Input
Side 2 active high enable. NC on Si8635.
11
12
13
14
NA
No Connect.
B3
Digital I/O
Digital Output
Digital Output
Ground
Side 2 digital input or output.
Side 2 digital output.
Side 2 digital output.
Side 2 ground.
B2
B1
151
16
GND2
VDD2
Supply
Side 2 power supply.
Note:
1. For narrow-body devices, Pin 2 and Pin 8 GND must be externally connected to respective ground. Pin 9 and Pin 15 must also be
connected to external ground.
2. No Connect. These pins are not internally connected. They can be left floating, tied to VDD or tied to GND.
silabs.com | Building a more connected world.
Rev. 1.81 | 26
Si8630/31/35 Data Sheet
Package Outline: 16-Pin Wide Body SOIC
6. Package Outline: 16-Pin Wide Body SOIC
The figure below illustrates the package details for the Triple-Channel Digital Isolator. The table lists the values for the dimensions
shown in the illustration.
Figure 6.1. 16-Pin Wide Body SOIC
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Rev. 1.81 | 27
Si8630/31/35 Data Sheet
Package Outline: 16-Pin Wide Body SOIC
Table 6.1. 16-Pin Wide Body SOIC Package Diagram Dimensions1, 2, 3, 4
Dimension
Min
—
Max
2.65
0.30
—
A
A1
A2
b
0.10
2.05
0.31
0.20
0.51
0.33
c
D
10.30 BSC
10.30 BSC
7.50 BSC
1.27 BSC
E
E1
e
L
0.40
0.25
0°
1.27
0.75
8°
h
θ
aaa
bbb
ccc
ddd
eee
fff
—
0.10
0.33
0.10
0.25
0.10
0.20
—
—
—
—
—
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Outline MS-013, Variation AA.
4. Recommended reflow profile per JEDEC J-STD-020 specification for small body, lead-free components.
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Rev. 1.81 | 28
Si8630/31/35 Data Sheet
Land Pattern: 16-Pin Wide Body SOIC
7. Land Pattern: 16-Pin Wide Body SOIC
The figure below illustrates the recommended land pattern details for the Si863x in a 16-pin wide-body SOIC package. The table lists
the values for the dimensions shown in the illustration.
Figure 7.1. PCB Land Pattern: 16-Pin Wide Body SOIC
Table 7.1. 16-Pin Wide Body SOIC Land Pattern Dimensions1, 2
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
9.40
1.27
0.60
1.90
C1
E
X1
Y1
Pad Length
Note:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN for Density Level B (Median Land Protru-
sion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
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Rev. 1.81 | 29
Si8630/31/35 Data Sheet
Package Outline: 16-Pin Narrow Body SOIC
8. Package Outline: 16-Pin Narrow Body SOIC
The figure below illustrates the package details for the Si863x in a 16-pin narrow-body SOIC (SO-16). The table lists the values for the
dimensions shown in the illustration.
Figure 8.1. 16-Pin Narrow Body SOIC
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Rev. 1.81 | 30
Si8630/31/35 Data Sheet
Package Outline: 16-Pin Narrow Body SOIC
Table 8.1. 16-Pin Narrow Body SOIC Package Diagram Dimensions1, 2, 3, 4
Dimension
Min
—
Max
1.75
0.25
—
A
A1
A2
b
0.10
1.25
0.31
0.17
0.51
0.25
c
D
9.90 BSC
6.00 BSC
3.90 BSC
1.27 BSC
E
E1
e
L
0.40
1.27
L2
h
0.25 BSC
0.25
0°
0.50
8°
θ
aaa
bbb
ccc
ddd
0.10
0.20
0.10
0.25
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MS-012, Variation AC.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Rev. 1.81 | 31
Si8630/31/35 Data Sheet
Land Pattern: 16-Pin Narrow Body SOIC
9. Land Pattern: 16-Pin Narrow Body SOIC
The figure below illustrates the recommended land pattern details for the Si863x in a 16-pin narrow-body SOIC package. The table lists
the values for the dimensions shown in the illustration.
Figure 9.1. PCB Land Pattern: 16-Pin Narrow Body SOIC
Table 9.1. 16-Pin Narrow Body SOIC Land Pattern Dimensions1, 2
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
5.40
1.27
0.60
1.55
C1
E
X1
Y1
Pad Length
Note:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
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Rev. 1.81 | 32
Si8630/31/35 Data Sheet
Top Marking: 16-Pin Wide Body SOIC
10. Top Marking: 16-Pin Wide Body SOIC
Si86XYSV
YYWWRTTTTT
e4
CC
Figure 10.1. 16-Pin Wide Body SOIC Top Marking
Table 10.1. 16-Pin Wide Body SOIC Top Marking Explanation
Line 1 Marking:
Base Part Number
Ordering Options
Si86 = Isolator product series
X = # of data channels (3)
Y = # of reverse channels (5, 1, 0)1
(See 1. Ordering Guide for more
information.)
S = Speed Grade (max data rate) and operating mode:
B = 150 Mbps (default output = low)
E = 150 Mbps (default output = high)
V = Insulation rating
B = 2.5 kV; C = 3.75 kV; D = 5.0 kV; T = 5.0 kV with 10 kV surge
capability.
Line 2 Marking:
Line 3 Marking:
YY = Year
Assigned by assembly subcontractor. Corresponds to the year
and workweek of the mold date.
WW = Workweek
RTTTTT = Mfg Code
Manufacturing code from assembly house
“R” indicates revision
Circle = 1.7 mm Diameter
(Center-Justified)
“e4” Pb-Free Symbol
Country of Origin ISO Code Ab- CC = Country of Origin ISO Code Abbreviation
breviation
• TW = Taiwan
• TH = Thailand
Note:
1. Si8635 has 0 reverse channels.
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Rev. 1.81 | 33
Si8630/31/35 Data Sheet
Top Marking: 16-Pin Narrow Body SOIC
11. Top Marking: 16-Pin Narrow Body SOIC
Si86XYSV
YYWWRTTTTT
e3
Figure 11.1. 16-Pin Narrow Body SOIC Top Marking
Table 11.1. 16-Pin Narrow Body SOIC Top Marking Explanation
Line 1 Marking:
Base Part Number
Ordering Options
Si86 = Isolator product series
XY = Channel Configuration
X = # of data channels (3)
(See 1. Ordering Guide for more
information.)
Y = # of reverse channels (5, 1, 0)1
S = Speed Grade (max data rate) and operating mode:
B = 150 Mbps (default output = low)
E = 150 Mbps (default output = high)
V = Insulation rating
B = 2.5 kV; C = 3.75 kV
“e3” Pb-Free Symbol
Line 2 Marking:
Circle = 1.2 mm Diameter
YY = Year
Assigned by the Assembly House. Corresponds to the year and
work week of the mold date.
WW = Work Week
RTTTTT = Mfg Code
Manufacturing code from assembly house
“R” indicates revision
Note:
1. Si8635 has 0 reverse channels.
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Rev. 1.81 | 34
Si8630/31/35 Data Sheet
Revision History
12. Revision History
Revision 1.81
January 2018
• Added new table to Ordering Guide for Automotive-Grade OPN options.
Revision 1.8
November 30th, 2016
• Added note to Ordering Guide table for denoting tape and reel marking.
Revision 1.7
July 19, 2016
• Added "R" part to the Ordering Guide.
Revision 1.6
October 29, 2015
• Added product options Si863xxT in 1. Ordering Guide.
• Added spec line items for Input and Enable Leakage Currents pertaining to Si863xxT in 4. Electrical Specifications.
• Added new spec for tSD in Electrical Specifications
• Updated IEC 60747-5-2 to IEC 60747-5-5 in all instances in document
Revision 1.5
June 6, 2015
• Updated Table 5 on page 14.
• Added CQC certificate numbers.
• Updated "4. Ordering Guide" on page 10.
• Removed references to moisture sensitivity levels.
• Removed Note 2.
Revision 1.4
September 25, 2013
• Added Figure 3, “Common-Mode Transient Immunity Test Circuit,” on page 8.
• Added references to CQC throughout.
• Added references to 2.5 kVRMS devices throughout.
• Updated "4. Ordering Guide" on page 10.
• Updated "9.1. Si863x Top Marking (16-Pin Wide Body SOIC)" on page 17.
Revision 1.3
June 26, 2012
• Updated Table 11 on page 20.
• Added junction temperature spec.
• Updated "2.3.1. Supply Bypass" on page 7.
• Removed “3.3.2. Pin Connections” on page 23.
• Updated "3. Pin Descriptions" on page 9.
• Updated table notes.
• Updated "4. Ordering Guide" on page 10.
• Removed Rev A devices.
• Updated "6. Land Pattern: 16-Pin Wide-Body SOIC" on page 13.
• Updated Top Marks.
• Added revision description.
silabs.com | Building a more connected world.
Rev. 1.81 | 35
Si8630/31/35 Data Sheet
Revision History
Revision 1.2
March 21, 2012
• Updated "4. Ordering Guide" on page 10 to include MSL2A.
Revision 1.1
September 14, 2011
• Updated High Level Output Voltage VOH to 3.1 V in Table 3, “Electrical Characteristics,” on page 9.
• Updated High Level Output Voltage VOH to 2.3 V in Table 4, “Electrical Characteristics,” on page 12.
Revision 1.0
July 14, 2011
• Reordered spec tables to conform to new convention.
• Removed “pending” throughout document.
Revision 0.2
March 31, 2011
• Added chip graphics on page 1.
• Moved Tables 1 and 11 to page 20.
• Updated Table 6, “Insulation and Safety-Related Specifications,” on page 17.
• Updated Table 8, “IEC 60747-5-5 Insulation Characteristics for Si86xxxx*,” on page 18.
• Moved Table 1 to page 4.
• Moved Table 2 to page 5.
• Moved “Typical Performance Characteristics” to page 8.
• Updated "3. Pin Descriptions" on page 9.
• Updated "4. Ordering Guide" on page 10.
• Removed references to QSOP-16 package.
Revision 0.1
September 15, 2010
• Initial release.
silabs.com | Building a more connected world.
Rev. 1.81 | 36
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Disclaimer
Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or
intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"
parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes
without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included
information. Silicon Labs shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted
hereunder to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any Life Support System without the specific written consent of
Silicon Labs. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant
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