500DHAF200M000ACFR [SILICON]
XO, Clock, 0.9MHz Min, 200MHz Max, 200MHz Nom;
| 型号： | 500DHAF200M000ACFR |
| 厂家： | 
SILICON |
| 描述： | XO, Clock, 0.9MHz Min, 200MHz Max, 200MHz Nom 石英晶振 |
| 文件： | 总6页 (文件大小：71K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si500D
DIFFERENTIAL OUTPUT SILICON OSCILLATOR
Features
Quartz-free, MEMS-free, and PLL-free all-silicon
oscillator
Any-rate output frequencies from 0.9 to 200 MHz
Short lead times
Excellent temperature stability (±20 ppm)
Highly reliable startup and operation
High immunity to shock and vibration
Low jitter: <1.5 ps
0 to 85 °C operation includes 10-year aging in hot
environments
Footprint compatible with industry-
standard 3.2 x 5.0 mm XOs
CMOS and SSTL versions available
Driver stopped, tri-state, or powerdown
operation
RoHS compliant
1.8, 2.5, or 3.3 V options
Low power
More than 10x better fit rate than
competing crystal solutions
Specifications
Parameters
Condition
Min
Typ
Max
Units
Frequency Range
0.9
—
200
MHz
Temperature stability,
0 to +70 °C
—
—
—
—
±10
—
—
ppm
ppm
ppm
ppm
Temperature stability,
0 to +85 °C
±20
—
Frequency Stability
Total stability,
±150
±250
0 to +70 °C operation1
Total stability,
—
0 to +85 °C operation2
Operating Temperature
Storage Temperature
0
—
—
+85
+125
1.98
2.75
3.63
36.0
22.2
16.5
29.3
C°
C°
V
–55
1.71
2.25
2.97
—
1.8 V option
2.5 V option
3.3 V option
LVPECL
—
Supply Voltage
—
V
—
V
34.0
19.3
14.9
25.3
mA
mA
mA
mA
Low Power LVPECL
LVDS
—
—
HCSL
—
Differential CMOS(3.3 V
option,10 pF,200 MHz)
—
29.0
31.8
mA
Supply Current
Differential SSTL-3
Differential SSTL-2
Differential SSTL-18
Tri-State
—
24.5
24.3
22.2
9.7
27.7
mA
mA
mA
mA
mA
%
—
26.7
—
25
10.7
—
—
Powerdown
1.0
1.9
Output Symmetry
VDIFF = 0
46 – 13 ns/TCLK
—
54 + 13 ns/TCLK
Notes:
1. Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,
first-year aging at 25 °C, shock, vibration, and one solder reflow.
2. Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,
ten-year aging at 85 °C, shock, vibration, and one solder reflow.
3. See “AN409: Output Termination Options for the Si500S and Si500D Silicon Oscillators” for further details regarding
output clock termination recommendations.
4. Min column entries are minima of VOH. Max column entries are maxima of VOL.
Rev. 0.3 5/09
Copyright © 2009 by Silicon Laboratories
Si500D
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si500D
Parameters
Condition
LVPECL/LVDS
Min
Typ
—
Max
460
Units
ps
—
—
Rise and Fall Times (20/80%)3
HCSL/Differential SSTL
Differential CMOS, 15 pF, >80 MHz
Mid-level
—
800
ps
—
1.1
—
1.6
ns
LVPECL Output Option
VDD – 1.5
VDD – 1.34
V
(DC coupling, 50 to VDD
–
Diff swing
Mid-level
.720
—
—
.880
—
VPK
V
2.0 V)3
Low Power LVPECL Output
Option
N/A
(AC coupling, 100 Differential
Diff swing
.68
—
.95
VPK
Load)3
Mid-level
Diff swing
1.15
0.25
—
—
—
—
—
—
—
—
—
1.26
0.45
0.96
0.45
0.425
0.82
55
V
VPK
V
LVDS Output Option (2.5/3.3 V)
(RTERM = 100 diff)3
Mid-level
0.85
LVDS Output Option (1.8 V)
(RTERM = 100 diff)3
Diff swing
0.25
VPK
V
Mid-level
0.35
HCSL Output Option3
CMOS Output Voltage3
Diff swing
0.65
VPK
V
DC termination per pad
VOH, sourcing 9 mA
VOL, sinking 9 mA
45
VDD – 0.6
—
—
0.6
V
.5 x VDD
0.375
–
SSTL-18
.5 x VDD + 0.375
—
V
SSTL Output Voltage4
SSTL-2
SSTL-3
.5 x VDD + 0.48
.45 x VDD + 0.48
—
—
.5 x VDD – 0.48
.45 VDD – 0.48
V
V
From time VDD crosses min spec
supply
Powerup Time
—
—
—
—
—
—
2
ms
ns
ns
OE Deassertion to Clk Stop
250 + 3 x TCLK
250 + 3 x TCLK
Return from Output Driver
Stopped Mode
Return From Tri-State Time
—
—
—
—
12 + 3 x TCLK
2
µs
Return From Powerdown Time
ms
ps
RMS
Non-CMOS
—
—
—
—
1
2
3
Period Jitter (1-sigma)
ps
RMS
CMOS, CL = 7 pF
1
1.0 MHz – min(20 MHz,
0.4 x FOUT),non-CMOS
1.0 MHz – min(20 MHz,
0.4 x FOUT),CMOS format
ps
RMS
0.6
0.7
1
Integrated Phase Jitter
ps
RMS
1.5
Notes:
1. Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,
first-year aging at 25 °C, shock, vibration, and one solder reflow.
2. Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,
ten-year aging at 85 °C, shock, vibration, and one solder reflow.
3. See “AN409: Output Termination Options for the Si500S and Si500D Silicon Oscillators” for further details regarding
output clock termination recommendations.
4. Min column entries are minima of VOH. Max column entries are maxima of VOL.
2
Rev. 0.3
Si500D
Package Specifications
Table 1. Package Diagram Dimensions (mm)
Dimension
Min
0.80
Nom
0.85
0.03
0.64
Max
0.90
0.05
0.69
Dimension
Min
0.00
—
Nom
0.05
—
Max
0.10
0.10
0.10
0.08
A
A1
b
L1
0.00
aaa
bbb
ccc
0.59
—
—
D
3.20 BSC.
—
—
e
E
L
1.27 BSC.
4.00 BSC.
0.95
ddd
eee
—
—
—
—
0.10
0.05
1.00
1.05
Table 2. Pad Connections
Table 3. Tri-State/Powerdown/Driver Stopped
Function on OE (3rd Option Code)
1
2
OE
A
B
C
D
E
F
NC—Make no external
connection to this pin
Open Active Active Active Active Active
Active
3
4
5
6
GND
Output
1
Tri-
State
Power-
down
Driver
Stopped
Active
Active
Active
Level
0
Tri-
State
Power-
down
Driver
Stopped
Complementary Output
VDD
Active
Active
Active
Level
0 C CC CC
T T T T T T
Y YWW
Dimension
(mm)
C1
E
X1
Y1
2.70
1.27
0.75
1.55
0 = Si500
CCCCC = mark code
TTTTTT = assembly manufacturing code
YY = year
WW = work week
Figure 2. Top Mark
Figure 1. Recommended Land Pattern
Rev. 0.3
3
Si500D
Environmental Compliance
Parameter
Conditions/Test Method
MIL-STD-883, Method 2002.4
MIL-STD-883, Method 2007.3 A
MIL-STD-202, 260 C° for 8 seconds
MIL-STD-883, Method 2003.8
IEC 68-2-3
Mechanical Shock
Mechanical Vibration
Resistance to Soldering Heat
Solderability
Damp Heat
Moisture Sensitivity Level
J-STD-020, MSL 3
Ordering Information
The Si500D supports a variety of options including frequency, output format, supply voltage, and tri-
state/powerdown. Specific device configurations are programmed into the Si500D at time of shipment.
Configurations are specified using the figure below. Silicon Labs provides a web-based part number utility that can
be used to simplify part number configuration. Refer to www.silabs.com/SiliconXOPartnumber to access this tool.
The Si500D XO series is supplied in a ROHS-compliant, Pb-free, 6-pad, 3.2 x 4.0 mm package. Tape and reel
packaging is available as an ordering option.
500D
X
X
X
XXMXXXX
A
C
X
R
Frequency
Si500
Differential
Oscillator
R = Tape & Reel
Blank = Tubes
xMxxxxx: fOUT < 10 MHz
xxMxxxx: 10 MHz < fOUT < 100 MHz
xxxMxxx: fOUT > 100 MHz
1st Option Code
VDD Format
LVPECL
3rd Option Code
Oper. Temp Range
A
B
C
D
E
F
G
H
J
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
1.8
1.8
1.8
1.8
1.8
1.8
Tri-State/Powerdown/
Output Driver Stopped
F
H
0 to 70 °C
0 to 85 °C
Low Power LVPECL
LVDS
HCSL
Dual Output CMOS
Differential CMOS
Dual Output SSTL
Differential SSTL
LVPECL
Low Power LVPECL
LVDS
HCSL
Dual Output CMOS
Differential CMOS
Dual Output SSTL
Differential SSTL
LVDS
A
B
C
D
E
F
OE active high/tristate
OE active low/tristate
OE active high/powerdown
OE active low/powerdown
OE active high/driver stopped
OE active low/driver stopped
Product Revision = C
K
L
2nd Option Code
Package
Stability (ppm, max)
M
N
P
Q
R
S
T
U
V
W
X
A
3.2 x 4.0 mm SMD
A
B
±150
±250
HCSL
Dual Output CMOS
Differential CMOS
Dual Output SSTL
Differential SSTL
4
Rev. 0.3
Si500D
DOCUMENT CHANGE LIST
Revision 0.2 to Revision 0.3
Revision B to Revision C updated in Ordering Information
0 to 85 C° Operating Temperature Range option added
Rev. 0.3
5
Si500D
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Please visit the Silicon Labs Technical Support web page
and register to submit a technical support request.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
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plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
6
Rev. 0.3
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