501HCA26M0000CAGR [SILICON]
LVCMOS Output Clock Oscillator, 26MHz Nom, DFN-4;
| 型号： | 501HCA26M0000CAGR |
| 厂家： | 
SILICON |
| 描述： | LVCMOS Output Clock Oscillator, 26MHz Nom, DFN-4 机械 振荡器 |
| 文件： | 总22页 (文件大小：460K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si501/2/3
32 KHZ–100 MHZ CMEMS OSCILLATOR
Features
Wide frequency range: 32 kHz to
100 MHz
User selectable tRise/tFall options
Glitchless start and stop
Excellent short-term stability, long-
term aging
Industry standard footprints:
2x2.5, 2.5x3.2, 3.2x5 mm
RoHS compliant, Pb-free
Short lead times: <2 weeks
–20 to +70 °C: Extnd commercial
–40 to +85 °C: Industrial
Contact Silicon Labs for
frequencies above 100 MHz
Si501 single frequency w/ OE
Si502 dual frequency w/ OE/FS
Si503 quad frequency w/ FS
±20/30/50 ppm frequency stability
including 10-year aging
LVCMOS output
Low period jitter
Low power
Continuous supply voltage range:
+1.71 V to +3.63 V
The Si50x family also includes the
Si504 for in-circuit programmability
(See the Si504 Data Sheet)
Applications
Storage (SATA/SAS/PCIe)
General purpose processors
Industrial controllers
Embedded controllers
Motor control
Office/Home automation
IP cameras/surveillance
Display and control panels
Outdoor electronics
Multi-function printers
Office equipment
Flow control
Ordering Information:
Description
See Section 5.
The Si501/2/3 CMEMS oscillator family provides monolithic, MEMS-based IC
replacements for traditional crystal oscillators. Silicon Laboratories’ CMEMS
technology combines standard CMOS + MEMS in a single, monolithic IC to provide
integrated, high-quality and high-reliability oscillators. Each device is factory tested
and configured for guaranteed performance to data sheet specifications across
voltage, process, temperature, shock, vibration, and aging.
Additional information on the Si50x CMEMS oscillator architecture and CMEMS
technology is available in white papers on the Silicon Labs website at
www.siliconlabs.com/cmems.
Pin Assignments
1
4
3
VDD
FS/OE
GND 2
CLK
Functional Block Diagram
Patents pending
VDD
LDO
Digital
Frequency-Locked
Loop (FLL)
Resonator
VCO
÷
& Oscillator
Temperature
Sensor
CLK
Temp Comp /
Digital
Control
NVM RAM ROM
GND
Copyright © 2013 by Silicon Laboratories
Preliminary Rev. 0.72 11/13
Si501/2/3
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si501/2/3
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Si501/2/3 Typical Applications Circuits, AC Waveforms, and Functional
Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.1. Si501/2 Applications Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.2. Si501/2 AC Waveforms and Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . .9
2.3. Si503 Applications Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2.4. Si503 AC Waveform and Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.1. OE Enable and Disable States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.2. Output Rise and Fall settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
4. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
5.1. Si501 Ordering Guide and Part Number Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
5.2. Si502 Ordering Guide and Part Number Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
5.3. Si503 Ordering Guide and Part Number Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
6. Package Dimensions and Land Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
6.1. Package Outline: 3.2 x 5 mm 4-pin DFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
6.2. Package Outline: 2.5 x 3.2 mm 4-pin DFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
6.3. Package Outline: 2 x 2.5 mm 4-pin DFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
7. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
7.1. 3.2 x 5 mm Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
7.2. 3.2 x 5 mm Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
7.3. 2.5 x 3.2 mm Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
7.4. 2.5 x 3.2 mm Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
7.5. 2 x 2.5 mm Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
7.6. 2 x 2.5 mm Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2
Preliminary Rev. 0.72
Si501/2/3
1. Electrical Specifications
Table 1. Recommended Operating Conditions
VDD=1.71 to 3.63 V, TA= –40 to 85 C, unless otherwise specified
Parameter
Symbol
Test Condition
Min
1.71
—
Typ
—
Max
3.63
2.5
Unit
V
1
Supply Voltage
Supply Current
V
DD
I
C =4 pF, 3.3 V , F
=1.0 MHz, low
1.7
mA
DD1
L
DD CLK
power option
C =4 pF, 3.3 V , F
power option
=100 MHz, low
=1.0 MHz, low
=100 MHz, low
DD CLK
—
—
—
—
—
5.3
3.9
7.6
1.7
3.9
6.5
4.9
8.9
2.5
4.9
mA
mA
mA
mA
mA
L
DD CLK
C =4 pF, 3.3 V , F
L
DD CLK
jitter option
C =4 pF, 3.3 V , F
L
jitter option
2
Static Supply
Current
I
Mode=Stop , low power option
DD2
F
=1 MHz
CLK
2
Mode=Stop , low jitter option
F
=1 MHz
CLK
2
Mode=Doze
—
—
670
0.3
—
890
1
µA
µA
V
2
Mode=Sleep
FS/OE pin
Input High Voltage
Input Low Voltage
V
0.70 x
—
IH
V
DD
V
FS/OE pin
—
—
0.30 x
V
IL
V
DD
OE Internal Pull
Resistor
R
Ordering option
40
50
60
kΩ
I
Operating
Temperature
T
Extended commercial grade
Industrial grade
–20
–40
—
—
70
85
C
C
A
Notes:
1. The supply voltage range is continuous from 1.71 to 3.63 V.
2. Si501 and Si502 only. Si503 has FS only and does not support Stop, Doze, or Sleep. See Section 3. Functional
Description for more information on operational modes.
Preliminary Rev. 0.72
3
Si501/2/3
Table 2. Output Clock Characteristics
VDD=1.71 to 3.63 V, TA= –40 to 85 C, unless otherwise specified.
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Frequency
Range
F
0.032
—
100
MHz
CLK
Clock Period
Total Stability
T
1/F
31,250
–20
–30
–50
—
—
—
—
—
±2
10
+20
+30
+50
—
ns
CLK
CLK
1
F
ppm
ppm
ppm
ppm
STAB
Initial
F
Measured at 25 C at the time of
I
Accuracy
shipping
2
Startup Time
T
From V crossing 1.71 V to first
—
2.5
4
ms
SU
DD
clock output
Resume
Time
T
From Sleep mode
From Doze mode
—
—
—
2.5
1.7
—
5
ms
ms
ns
RUN
3,4
2.55
5
From Stop mode
1.5 x T
+
+
CLK
35
OutputDisable
T
To Sleep/Doze mode, from output
running
—
—
—
—
—
—
225
µs
ns
D
3,4
Time
To Stop, from output running
1.5 x T
CLK
35
Frequency
Update
T
5
ms
NEW_FREQ
4,6
Time
Notes:
1. Orderable option. Stability budget consists of initial tolerance, operating temperature range, rated power supply voltage
change, load change, 10-year aging, shock, and vibration.
2. Hold FS/OE high (strong or weak) during powerup for fastest time to clock.
3. Si501 and Si502 only. Si503 has FS only and does not support Stop, Doze, or Sleep.
4. Asserted FS/OE actions must be held stable for the maximum duration of the invoked FS/OE event (e.g., TRUN
,
TNEW_FREQ, TD, etc).
5. If the Si502 frequency is switched while the device is in Stop mode, the frequency prior to Stop will be output briefly until
the glitchless switch to the other frequency. Doze mode and Sleep mode do not have this behavior.
6. Si502 and Si503 only. Si501 is a single frequency device with OE only.
4
Preliminary Rev. 0.72
Si501/2/3
Table 3. Output Clock Levels and Symmetry
VDD = 1.71 to 3.63 V, TA = –40 to 85 C unless otherwise indicated.
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output High Voltage
V
1st ordering option code: A and H
0.90 x
—
—
V
OH
V
I
=–4 mA
DD
OH
Output Low Voltage
V
1st ordering option code: A and H
—
0.4
1
—
0.10 x
V
DD
V
OL
I
=+4 mA
OH
st
2
2
Rise/Fall
tRise
/tFall
1 ordering option code : A and H
0.7
1.2
1.6
1.6
1.6
4
ns
ns
ns
ns
ns
ns
ns
%
1
Time
Z =25 @ 3.3 V
0
st
1 ordering option code: B and J
1.3
1.3
1.3
3
Z = 50 @ 3.3 V
0
st
1 ordering option code: C and K
1
Z = 50 @ 2.5 V
0
st
1 ordering option code: D and L
1
Z = 50 @ 1.8 V
0
st
1 ordering option code: E and M
2
Z = 110 @ 3.3 V
0
st
1 ordering option code: F and N
4
5
7
Z =220 @ 3.3 V
0
st
1 ordering option code: G and P
7
8
11
55
Z =440 @ 3.3 V
0
Duty Cycle
DC
Drive strength selected such that
tRise/tFall (20% to 80%)<10% of
period
45
50
Notes:
1. CL=15 pF, tRise/tFall (20% to 80%), 3.3 V, unless otherwise stated.
2. Recommended series termination resistor (RS) = 24.9 for Z0=50
Preliminary Rev. 0.72
5
Si501/2/3
Table 4. Output Clock Jitter and Phase Noise
VDD = 1.71 to 3.63 V, TA = –40 to 85 C unless otherwise indicated.
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Cycle-to-Cycle Jitter
J
100 MHz, Low Jitter Option
1 ordering option code: H
—
14
25
ps pk-pk
CCPP
st
100 MHz, Low Power Option
1 ordering option code: A
—
—
—
—
16
1
26
1.6
1.9
13
ps pk-pk
ps rms
st
Period Jitter
J
100 MHz, Low Jitter Option
PRMS
st
1 ordering option code: H
100 MHz, Low Power Option
1.3
9
ps rms
st
1 ordering option code: A
Period Jitter Pk-Pk
J
Low Jitter Option
10k samples
ps pk-pk
PPKPK
st
1 ordering option code: H
Low Power Option
10k samples
1 ordering option code: A
—
—
10
1
16
ps pk-pk
ps rms
st
1
Phase Jitter
75 MHz
1.3
F
=900 kHz to 7.5 MHz
OFFSET
Low Jitter Option
st
1 ordering option code: H
75 MHz
—
2.5
3.2
ps rms
F
=900 kHz to 7.5 MHz
OFFSET
Low Power Option
st
1 ordering option code: A
Notes:
1. Integrated phase jitter exceeds the requirements of some high-performance data communications systems. See
AN783 for additional information.
6
Preliminary Rev. 0.72
Si501/2/3
Table 5. Environmental Compliance and Package Information
Parameter
Test Condition
Mechanical Shock
Mechanical Shock High g
Mechanical Vibration
Solderability
MIL-STD-883, Method 2002, Cond B. (1,500 g)
MIL-STD-883, Method 2002, Cond E. (10,000 g)
MIL-STD-883, Method 2007
MIL-STD-883, Method 2003
Temperature Cycle
Resistance to Solder Heat
Contact Pads
JESD22, Method A104
MIL-STD-883, Method 2036
Gold over Nickel/Palladium
Table 6. Thermal Conditions
Parameter
Symbol
Test Condition
3.2x5 mm, still air
2.5x3.2 mm, still air
2x2.5 mm, still air
Value
187
Unit
Thermal Impedance
JA
°C/W
239
241
Table 7. Absolute Maximum Limits1
Parameter
Maximum Operating Temperature
Storage Temperature
Supply Voltage
Symbol
Rating
85
Unit
°C
°C
V
T
MAX
T
–55 to +125
–0.5 to +3.8
S
V
DD
Input Voltage
V
–0.5 to V
+0.3V
V
IN
DD
ESD Sensitivity (JESD22-A114)
ESD Sensitivity (CDM)
HBM
CDM
2000
500
V
V
2
Soldering Temperature (Pb-free profile)
T
260
°C
s
PEAK
Soldering Time at T
T
20–40
PEAK
P
2
(PB-free profile)
Junction Temperature
T
125
°C
J
Notes:
1. Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation
specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended
periods may affect device reliability.
2. The device is compliant with JEDEC J-STD-020.
Preliminary Rev. 0.72
7
Si501/2/3
2. Si501/2/3 Typical Applications Circuits, AC Waveforms, and Functional
Descriptions
The Si501/2/3 family has various applications circuits and ac waveforms depending on the selected device and
ordering configuration options. Pay careful attention when reading the following section to be sure you refer to the
correct diagrams.
2.1. Si501/2 Applications Circuits
VDD
VDD
RUP
VDD
CLK
FS/OE
GND
1
2
4
3
0.1
F
Si501/2
Z= 50
CLK
RS
Figure 1. Si501/2 Applications Circuit with Optional Output Series Resistor
Note: The dotted line box in Figure 1 is an optional component depending on tRise/tFall configuration option. This diagram
applies to all Si50x product drive strength configuration options. See Table 3 for RS recommendations. See Section 5.
"Ordering Guide” for configuration options.
MCU
VDD
VDD
RUP
VDD
VDD
~50K
RUP
FS/OE
OUTPUT
DRIVER
VDD
CLK
4
3
1
2
0.1F
Si501/2
Z0 = 50
CLK
GND
RS
Note: The dotted line boxes in Figure 2 show resistor options depending on MCU pull-up resistors configuration and the
Si501/2 internal resistor configuration options. See Section 5. "Ordering Guide” for configuration options. Users should
design only one of the pin 1 dotted-line options. The series resistor (RS) on pin 3 is also optional. See Table 3 for RS
recommendations.
Figure 2. Si501/2 Applications Circuit with MCU Configuration Options
8
Preliminary Rev. 0.72
Si501/2/3
Table 8. Si502 FS/OE States and Resistor Values
FS/OE Pin State
R
Clock Output
UP
Strong High
Weak High
Low
0 RUP 1 k
20 kRUP 200 k
—
Frequency 1
Frequency 2
Hi-Z
Notes:
1. If the Si502 internal pull-up resistor configuration option is not selected, an
MCU internal pull-up resistor or an external pull-up resistor should be used.
2. The parallel combination of all pull-up resistors on the FS/OE pin, including
the optional internal device pull-up resistor must be > 20 kto select the
Weak High state.
3. If the Si502 internal pull-up resistor is enabled with no other external FS/OE
connections, the FS/OE state will be detected as `Weak High' which selects
the Frequency 2 output by default.
2.2. Si501/2 AC Waveforms and Functional Descriptions
Supply Voltage (VDD)
VDD=1.71V
CLK
TSU
Figure 3. Si501/2 Power On Time (refer to Table 2)
RUP<1k
FS/OE
ꢀ
RUP<1k
ꢀ
RUP>20k
ꢀ
TD
TRUN
TNEW_FREQ
Hi-Z
Hi-Z
CLK
Figure 4. Si501/2 AC Waveform (refer to Table 2)
Preliminary Rev. 0.72
9
Si501/2/3
2.3. Si503 Applications Circuits
VDD
VDD
RUP
VDD
~50K
FS/OE
VDD
CLK
4
3
1
2
0.1 F
Z0 = 50
RDOWN
Si503
CLK
GND
RS
Note: The dotted line boxes show optional components depending on tRise/tFall and internal pull up resistor configuration
options. See Section 5. "Ordering Guide” for configuration options. See Table 3 for RS recommendations.
Figure 5. Si503 Applications Circuit with Configuration Options
Table 9. Si503 Frequency Select with External Resistor Options
FS/OE Pin State
R
R
Clock Output
UP
DOWN
Strong High
Weak High
Weak Low
Strong Low
0 RUP 1 k
20 kRUP 200 k
Do not populate
Do not populate
Do not populate
Frequency 1
Frequency 2
Frequency 3
Frequency 4
20 kRDOWN 200 k
0 RDOWN 1 k
Do not populate
Note: If the Si503 internal pull-up resistor is enabled with no other external FS/OE connections, the FS/OE state will
be detected as `Weak High' which selects the Frequency 2 output by default.
10
Preliminary Rev. 0.72
Si501/2/3
MCU
VDD
RUP
VDD
VDD
VDD
~50K
FS/OE
OUTPUT
DRIVER
VDD
4
3
1
2
0.1 F
VDD
RUP
Si503
6K
Z0 = 50
OUTPUT
DRIVER
CLK
GND
RS
CLK
Note: The dotted line boxes in Figure 6 show resistor options depending on MCU pull-up resistors configuration and the Si503
internal resistor configuration options. See Section 5. "Ordering Guide” for configuration options. Users should design
only one of the pin 1 dotted-line options. The series resistor (RS) on pin 3 is also optional. See Table 3 for RS recommen-
dations.
Figure 6. Si503 Applications Circuit with MCU and Configuration Options
Table 10. Si503 Frequency Select
FS/OE Pin State
Strong High
Weak High
MCU Output 1
MCU Output 2
Clock Output
Frequency 1
Frequency 2
Frequency 3
Frequency 4
High
Hi-Z
Hi-Z
Low
Hi-Z
Hi-Z
Low
Hi-Z
Weak Low
Strong Low
Note: If the Si50x internal pull-up resistor is enabled with no other external OE connections, the OE state will be
detected as `Weak High' which selects the Frequency 2 output by default.
2.4. Si503 AC Waveform and Functional Description
VDD
1.71V
TSU
Figure 7. Si503 Power On Time (refer to Table 2)
Preliminary Rev. 0.72
11
Si501/2/3
RUP < 1kꢀ
RUP > 20kꢀ
FS
RDOWN > 20kꢀ
TNEW_ FREQ
TNEW_ FREQ
Hi-Z
CLK
Hi-Z
Figure 8. Si503 AC Waveform (refer to Table 2)
3. Functional Description
The Si50x series oscillator family includes four base devices. All devices are configurable according to the Section
5. "Ordering Guide”. The four devices each support a single clock output frequency at any one time and are
segmented according to the number of clock frequencies they store in on-chip memory.
The Si501 supports a single stored frequency, enabled with the OE functionality. The Si502 stores two frequencies
that can be selected with FS and enabled/disabled with OE functionality. The Si503 stores four frequencies,
selected with FS functionality. The Si503 does not support OE functionality. The Si501/2/3 are covered in this data
sheet.
The Si504 is a programmable oscillator, controlled through a single pin interface (C1D). It is covered in its own
Si504 data sheet available at www.siliconlabs.com/cmems.
All devices in the Si50x CMEMS series employ a cost-optimized, power-efficient, digital FLL architecture to
produce a highly accurate and stable output clock from a passively compensated MEMS resonator reference
frequency.
The architecture uses the MEMS resonator as its reference frequency along with a divided signal from an on-chip,
digitally-controlled VCO to drive a frequency comparator for the FLL’s digital loop filter. The digital loop filter
accumulates and further processes the frequency error values to produce the target output frequency.
The architecture also uses a high-resolution, low-noise temperature sensor and temperature compensation
algorithm to offset any temperature drift of the passively compensated MEMS resonator. Each device is calibrated
for temperature and MEMS-resonator frequency pairs and derives a device-specific compensation polynomial. As
the temperature changes, this compensation circuitry offsets any frequency drift.
This tightly coupled system is extremely accurate and fast because the MEMS resonator and CMOS compensation
circuitry are in a single, monolithic chip, and, therefore, separated by a few microns.
The complete system process occurs many thousands of times per second, providing excellent frequency
accuracy and stability across temperature changes, including any fast temperature transients. The oscillator also
supports a low-power version that reduces the sampling cycle to a longer period, reducing power consumption for
applications that can tolerate relaxed jitter specifications of approximately 1 ps RMS to reduce power by
approximately 2-3 mA. See Table 1 for exact specifications.
3.1. OE Enable and Disable States
The Si50x CMEMS series supports four operational output states via the FS/OE configuration pin. If enabled, the
Si50x is in Run mode, the clock is output and power is as specified in Table 1. The disable modes are Stop, Sleep,
and Doze. Each of these states has a different power consumption profile as specified in Table 1.
3.1.1. Stop Mode
The Si50x output in Stop mode is high-impedance, also known as High-Z (Hi-Z) or Tri-State. Stop mode disables
the output driver, but the digital core and MEMS resonator remain enabled for fast transition to Run mode. The
output is stopped and held at High-Z after completing the last cycle glitch-free. No other power saving measure is
taken in Stop mode.
12
Preliminary Rev. 0.72
Si501/2/3
3.1.2. Doze Mode
The Si50x output in Doze mode is high-impedance, also known as High-Z (Hi-Z) or Tri-State. Doze mode disables
the output driver, the VCO, and the MEMS resonator, but the digital core remains enabled. The output is stopped
and is held at High-Z after completing the last cycle glitch-free.
3.1.3. Sleep Mode
The Si50x output in Sleep mode is high-impedance, also known as High-Z (Hi-Z) or Tri-State. Sleep mode disables
power to all circuitry except for low-leakage circuitry that retains the last device configuration. The output is stopped
and is held at High-Z after completing the last cycle glitch-free.
3.2. Output Rise and Fall Settings
The Si50x clock output is programmable. This enables reduction of electromagnetic interference (EMI) radiation
from the clock output. The amount of EMI reduction is dependent on the output frequency, the harmonic of interest,
and the board layout. Lab results using a 50 MHz FOUT and changing the clock tRise/tFall time from 0.7 ns to 8 ns
show up to 14 dB of EMI reduction.
The tRise/tFall feature also allows the Si50x to match competing devices’ rise and fall times. Crystal oscillator
tRise/tFall behavior is largely dependent on the supply voltage. In crystal-based oscillators, a higher supply voltage
will generally drive a more rapid tRise/tFall time. The Si50x configuration options allow the user to match the
tRise/tFall to the supply voltage. The Si50x also provides a specified tRise/tFall with a given supply voltage and a
50 trace impedance. See Table 3 for Si50x tRise/tFall specifications.
4. Pin Descriptions
1
4
3
VDD
FS/OE
GND 2
CLK
Figure 9. Si501/2/3
Table 11. Pin Description
Pin
Name
Function
1
FS/OE FS=Frequency Select. Si502 and Si503 only.
OE=Output Enable. Si501 and Si502 only.
2
3
4
GND
CLK
Ground.
Output clock.
V
Power supply.
DD
Bypass with a 0.1F capacitor placed as close to the V pin as possible.
DD
Preliminary Rev. 0.72
13
Si501/2/3
5. Ordering Guide
The Si50x family of CMEMS oscillators are highly configurable. Each orderable part number must be specified
according to the guidelines below. Each customized part’s performance is guaranteed to operate within the data
sheet specifications. An on-line configuration and ordering tool is available at www.siliconlabs.com/cmems.
5.1. Si501 Ordering Guide and Part Number Syntax
OEꢀ
OEꢀ
Internalꢀ
Jitterꢀvs
TYP
Package
Dimension
±.ꢀꢀxꢀ5ꢀmm4
ꢀ.5ꢀxꢀ±.ꢀꢀmm
ꢀꢀxꢀꢀ.5ꢀmm
VDD
High
Low PullꢀResistor
Power
TR/TF
0.7ꢀns1
1.±ꢀnsꢀ
1.±ꢀnsꢀ
1.±ꢀnsꢀ
±ꢀns±
A
B
C
D
E
Enable Stop
Enable Doze
Enable Sleep
Stop Enable PullͲDown
Doze Enable PullͲDown
Sleep Enable PullͲDown
Enable Stop
Enable Doze
Enable Sleep
Stop Enable
Doze Enable
Sleep Enable
PullͲUp
PullͲUp
PullͲUp
A
B
C
D
E
1.7Ͳ±.6
±.±V
ꢀ.5V
B
C
D
Lowꢀ
Power
1.8V
1.7Ͳ±.6
1.7Ͳ±.6
1.7Ͳ±.6
1.7Ͳ±.6
±.±V
ꢀ.5V
1.8V
1.7Ͳ±.6
1.7Ͳ±.6
1.7Ͳ±.6
Temp
Range
Ͳꢀ0ꢀtoꢀ70ꢀ°C
Ͳ40ꢀtoꢀ85ꢀ°C
F
F
5ꢀns±
G
H
J
K
L
None
None
None
None
None
None
G
H
J
K
L
M
N
P
8ꢀns±
F
G
0.7ꢀns1
1.±ꢀnsꢀ
1.±ꢀnsꢀ
1.±ꢀnsꢀ
±ꢀns±
Reel
Low
Jitter
R
Reel
M
CutꢀTape
5ꢀns±
8ꢀns±
501 J C A Ͳ Ͳ Ͳ Ͳ Ͳ Ͳ Ͳ D A G R
Revision
OPNꢀ
Prefix
501
502
503
Frequency
Description
Ppm
Description
Code
Singleꢀfrequency
Dual frequency
Quad frequency
Anyꢀfrequency
A
B
C
± 50
± ±0
± ꢀ0
Mxxxxxx
xMxxxxxꢀ
xxMxxxxꢀ
100M000ꢀ
xxxxxx
f
OUT <ꢀ1ꢀMHzꢀ
1ꢀMHzꢀꢀчꢀfOUT <ꢀ10ꢀMHzꢀ
10ꢀMHzꢀꢀчꢀfOUT <ꢀ100ꢀMHzꢀ
fOUT =ꢀ100ꢀMHz
504
6Ͳdigitꢀcodeꢀforꢀ>ꢀ6ꢀdecimalꢀresolution
Note:
1. Series termination resistor (RS) is recommended for this configuration. See Table 3 and Section 2.
2. Series termination resistor is not needed for this configuration. Output impedance is 50 ꢀ for the indicated supply
condition.
3. Series termination resistor is not needed for this configuration. Reduced EMI setting.
4. Silicon Labs 3.2 x 5 mm package is delivered as 3.2 x 4 mm and accommodates the industry-standard 3.2 x 5 mm
footprint.
Figure 10. Si501 Part Number Syntax
14
Preliminary Rev. 0.72
Si501/2/3
5.2. Si502 Ordering Guide and Part Number Syntax
OEꢀ
Internalꢀ
Jitterꢀvs
TYP
Package
VDD
Low5 PullꢀResistor
Power
TR/TF
Dimension
0.7ꢀns1
1.±ꢀnsꢀ
1.±ꢀnsꢀ
1.±ꢀnsꢀ
±ꢀns±
±.ꢀꢀxꢀ5ꢀmm4
ꢀ.5ꢀxꢀ±.ꢀꢀmm
ꢀꢀxꢀꢀ.5ꢀmm
A
B
C
D
E
Stop
Doze
Sleep
Stop
Doze
Sleep
PullͲUp
PullͲUp
PullͲUp
None
None
None
A
B
C
D
E
1.7Ͳ±.6
±.±V
ꢀ.5V
B
C
D
Lowꢀ
Power
1.8V
1.7Ͳ±.6
1.7Ͳ±.6
1.7Ͳ±.6
1.7Ͳ±.6
±.±V
ꢀ.5V
1.8V
1.7Ͳ±.6
1.7Ͳ±.6
1.7Ͳ±.6
Temp
Range
Ͳꢀ0ꢀtoꢀ70ꢀ°C
Ͳ40ꢀtoꢀ85ꢀ°C
F
F
5ꢀns±
G
H
J
K
L
M
N
P
8ꢀns±
F
G
0.7ꢀns1
1.±ꢀnsꢀ
1.±ꢀnsꢀ
1.±ꢀnsꢀ
±ꢀns±
Reel
Low
Jitter
R
Reel
CutꢀTape
5ꢀns±
8ꢀns±
50ꢀ J C A Ͳ Ͳ Ͳ Ͳ Ͳ Ͳ Ͳ D A G R
Revision
OPNꢀ
Prefix
501
502
503
Frequency
Description
Ppm
Description
Code
Singleꢀfrequency
Dual frequency
Quad frequency
Anyꢀfrequency
A
B
C
± 50
± ±0
± ꢀ0
xxxxxx
6ͲdigitꢀcodeꢀfromꢀSilicon Labs
504
Note:
1. Series termination resistor (RS) is recommended for this configuration. See Table 3 and Section 2.
2. Series termination resistor is not needed for this configuration. Output impedance is 50 ꢀ for the indicated supply
condition.
3. Series termination resistor is not needed for this configuration. Reduced EMI setting.
4. Silicon Labs 3.2 x 5 mm package is delivered as 3.2 x 4 mm and accommodates the industry-standard 3.2 x 5 mm
footprint.
5. The Si502 OE pin has three (3) states: OE High = Freq 1; OE Weak High = Freq 2; OE Low is configurable.
Figure 11. Si502 Part Number Syntax
Preliminary Rev. 0.72
15
Si501/2/3
5.3. Si503 Ordering Guide and Part Number Syntax
Internalꢀ
PullꢀResistor
PullͲUp
Jitterꢀvs
TYP
Package
Dimension
±.ꢀꢀxꢀ5ꢀmm4
ꢀ.5ꢀxꢀ±.ꢀꢀmm
ꢀꢀxꢀꢀ.5ꢀmm
VDD
Power
TR/TF
0.7ꢀns1
1.±ꢀnsꢀ
1.±ꢀnsꢀ
1.±ꢀnsꢀ
±ꢀns±
A
B
A
B
C
D
E
1.7Ͳ±.6
±.±V
ꢀ.5V
B
C
D
None
Lowꢀ
Power
1.8V
1.7Ͳ±.6
1.7Ͳ±.6
1.7Ͳ±.6
1.7Ͳ±.6
±.±V
ꢀ.5V
1.8V
1.7Ͳ±.6
1.7Ͳ±.6
1.7Ͳ±.6
Temp
Range
Ͳꢀ0ꢀtoꢀ70ꢀ°C
Ͳ40ꢀtoꢀ85ꢀ°C
F
5ꢀns±
G
H
J
K
L
M
N
P
8ꢀns±
F
G
0.7ꢀns1
1.±ꢀnsꢀ
1.±ꢀnsꢀ
1.±ꢀnsꢀ
±ꢀns±
Reel
Low
Jitter
R
Reel
CutꢀTape
5ꢀns±
8ꢀns±
50± J C A Ͳ Ͳ Ͳ Ͳ Ͳ Ͳ Ͳ D A G R
Revision
OPNꢀ
Prefix
501
502
503
Frequency
Description
Ppm
Description
Code
Singleꢀfrequency
Dual frequency
Quad frequency
Anyꢀfrequency
A
B
C
± 50
± ±0
± ꢀ0
xxxxxx
6ͲdigitꢀcodeꢀfromꢀSiliconꢀLabs
504
Note:
1. Series termination resistor (RS) is recommended for this configuration. See Table 3 and Section 2.
2. Series termination resistor is not needed for this configuration. Output impedance is 50 ꢀ for the indicated supply
condition.
3. Series termination resistor is not needed for this configuration. Reduced EMI setting.
4. Silicon Labs 3.2 x 5 mm package is delivered as 3.2 x 4 mm and accommodates the industry-standard 3.2 x 5 mm
footprint.
Figure 12. Si503 Part Number Syntax
16
Preliminary Rev. 0.72
Si501/2/3
6. Package Dimensions and Land Patterns
6.1. Package Outline: 3.2 x 5 mm 4-pin DFN
4.00±0.15
#4
#3
2.54
3.20±0.15
0. 90Max
1.20
0.94
2.20
#1
#2
1.60
1.34
1.20
(Top View)
1.50
Note: The 3.2 x 5 mm package is delivered as a 3.2 x 4 mm package and is drop-in compatible to
industry-standard 3.2 x 5 landing patterns.
Figure 13. 3.2 x 5 mm 4-pin DFN
6.2. Package Outline: 2.5 x 3.2 mm 4-pin DFN
3.20±0.15
2.20
#4
#3
2.50±0.15
0.90 Max
0.90
0.70
1.90
1.20
#1
#2
1.20
0.90
1.40
(Top View)
Figure 14. 2.5 x 3.2 mm 4-pin DFN
6.3. Package Outline: 2 x 2.5 mm 4-pin DFN
2.50±0.15
1.90
#4
#3
2.00±0.15
0.70
0.55
1.50
#1
#2
1.00
1.00
0.65
0.90 Max
1.10
(Top View)
Figure 15. 2 x 2.5 mm 4-pin DFN
Preliminary Rev. 0.72
17
Si501/2/3
7. Top Markings
7.1. 3.2 x 5 mm Top Marking
7.2. 3.2 x 5 mm Top Marking Explanation
Mark Method:
Font Size:
Laser
0.60 mm
Right-Justified
Line 1 Marking: TTTTTT=Trace Code
Manufacturing Code from the
Assembly Purchase Order form.
Line 2 Marking Circle=0.5 mm
Diameter
Pin 1 Indicator
Left-Justified
YY=Year
WW=Work Week
Assigned by the Assembly House.
Corresponds to the year and work
week of the build date.
18
Preliminary Rev. 0.72
Si501/2/3
7.3. 2.5 x 3.2 mm Top Marking
7.4. 2.5 x 3.2 mm Top Marking Explanation
Mark Method:
Font Size:
Laser
0.50 mm
Right-Justified
Line 1 Marking: TTTTT=Trace Code
Manufacturing Code from the
Assembly Purchase Order form.
Line 2 Marking: Circle=0.3 mm Diameter
Pin 1 Indicator
Left-Justified
Y=Year
WW=Work Week
Assigned by the Assembly House.
Corresponds to the year and work
week of the build date.
Preliminary Rev. 0.72
19
Si501/2/3
7.5. 2 x 2.5 mm Top Marking
7.6. 2 x 2.5 mm Top Marking Explanation
Mark Method:
Font Size:
Laser
0.50 mm
Right-Justified
Line 1 Marking: TTTT=Trace Code
Manufacturing Code from the
Assembly Purchase Order form.
Line 2 Marking: Circle=0.3 mm Diameter
Pin 1 Indicator
Left-Justified
Y=Year
WW=Work Week
Assigned by the Assembly House.
Corresponds to the year and work
week of the build date.
20
Preliminary Rev. 0.72
Si501/2/3
DOCUMENT CHANGE LIST
Revision 0.2 to Revision 0.3
Combined Si501/2/3 data sheets.
Modified title page.
Modified Table 2.
Modified Table 4.
Modified Section 2.
Modified Section 3.
Modified Section 4.
Modified Section 5.
Revision 0.3 to Revision 0.4
Modified title page.
Modified Table 1.
Modified Table 2.
Modified Table 3.
Modified Table 4.
Modified Table 5.
Modified Table 6.
Modified Table 7.
Modified Section 2.
Modified Section 4.
Modified Section 5.
Modified Section 6.
Revision 0.4 to Revision 0.41
Modified Table 4.
Revision 0.41 to Revision 0.7
Revised supported frequency range.
Added MIN/MAX figures to all relevant tables.
Revision 0.7 to Revision 0.71
Revised Table 3.
Revised Section 5.
Revision 0.71 to Revision 0.72
Revised Table 1.
Revised Table 2.
Revised Table 3.
Revised Table 5.
Modified Section 2.
Added Section 3.
Modified Section 4.
Preliminary Rev. 0.72
21
Si501/2/3
CONTACT INFORMATION
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Austin, TX 78701
Tel: 1+(512) 416-8500
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Please visit the Silicon Labs Technical Support web page:
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and register to submit a technical support request.
Patent Notice
Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analog-
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The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed fea-
tures or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warran-
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22
Preliminary Rev. 0.72
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