501HCF100M000BAG [SILICON]

LVCMOS Output Clock Oscillator, 100MHz Nom, DFN-4;


型号：	501HCF100M000BAG
厂家：	SILICON
描述：	LVCMOS Output Clock Oscillator, 100MHz Nom, DFN-4
文件：	总7页 (文件大小：505K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Si501/2/3/4

LVCMOS CMEMS^®Programmable Oscillator Series

Description

Features

The Si501/2/3/4 CMEMS programmable oscillator series combines

standard CMOS + MEMS in a single, monolithic IC to provide high-quality

and high-reliability oscillators. Each device is specified for guaranteed

performance across voltage, process, temperature, shock, vibration and

aging for 10 years. More information on CMEMS available at

www.silabs.com/cmems.

 Any frequency oscillator from 32 kHz to 100 MHz

Contact Silicon Labs Marketing for frequencies above

100 MHz

 Frequency stability: ±20/±30/±50 ppm including 10-year

aging

 -20 to +70 °C: Extended Commercial

 -40 to +85 °C: Industrial

Applications: General purpose microcontrollers, industrial control, IP

cameras, surveillance systems, metering, home and office automation,

security systems, sleep clocking, 10/100 Ethernet/EtherCAT, SPI, SAS3.0 /

SATA3.0, PCIe ref clock, NVMe, HDD, SSD, hybrid storage, DDR3/3L,

USB2.0, USB OTG/2.0, M2M, HDMI

 Highly configurable: low power vs. low jitter, frequency, F_STAB

T_R/T_F, V_DD, OE/FS functionality (see ordering guide below)

 In-circuit programmable via C1D 1-pin interface (Si504)

 Seamless V_DDfrom +1.71 to +3.63 V

 Low period jitter mode / low power mode

 Glitchless start and stop

Not recommended: Wi-Fi, Bluetooth, USB 3.0, Gigabit Ethernet

 RoHS compliant, Pb-free

Product Selector Guide

Pin-out

Pin Description

Number

Part

Number

Si501

Si502

Si503

Si504

Description

Control

Description

Pin 4

VDD

Pin 3

CLK

Single frequency

Dual frequency

Quad frequency

FS/OE

FS = Frequency Select

OE = Output Enable

C1D = Single wire interface

Pin 1

FS/OE/C1D

Pin 2

GND

Programmable for any C1D 1-pin interface

GND = Ground

CLK = Clock out

VDD = Power Supply

supported frequency

or configuration

(see Si504 data sheet

for details)

(top view)

Ordering Guide

501

502⁶

TYP

T_R/T_F

Jitter vs

Power

VDD

Internal

Low Pull Resistor

1.7-3.6 0.7 ns¹

3.3V 1.3 ns²

2.5V 1.3 ns²

1.8V 1.3 ns²

1.7-3.6 3 ns³

1.7-3.6 5 ns³

1.7-3.6 8 ns³

1.7-3.6 0.7 ns¹

3.3V 1.3 ns²

2.5V 1.3 ns²

High

Low Pull Resistor

Stop

Enable Doze

Sleep

Stop

Doze Enable Pull-Down

Sleep

Pull-Up

Doze

Sleep

Stop

Doze

Sleep

Pull-Up

None

Low

Power

504 only⁵

Stop

Maximum F_OUT

503

Pull-Up

None

Enable Doze

0.032 – 80 MHz

0.032 – 100 MHz

Sleep

None

1.8V 1.3 ns²Low Jitter

1.7-3.6 3 ns³

Stop

Doze Enable

Sleep

Temp

Range

-20 to 70 °C

-40 to 85 °C

504

Pull-Up only

1.7-3.6 5 ns³

1.7-3.6 8 ns³

OPN

Prefix

501

502

503

504

Description

50X - - - - - - - - - - - A - R

Single frequency

Dual frequency

Quad frequency

Any frequency

Reel

Freq

Cut Tape

OPN

Description

Code

Mxxxxxx

xMxxxxx

xxMxxxx

100M000

f_OUT< 1 MHz

1 MHz ≤ f_OUT< 10 MHz

10 MHz ≤ f_OUT< 100 MHz

Package

Dimension

3.2 x 5 mm⁴

2.5 x 3.2 mm

2 x 2.5 mm

ppm

501 only

± 50

± 30

± 20

f_OUT= 100 MHz

501/2/3/4 xxxxxx

Silicon Labs 6-digit code for 502/3/4, or >6-decimal freq on 501

Ordering Guide Notes:

1. Series termination resistor (R_S– see Apps Circuits section) is recommended for this configuration.

2. Series termination resistor (R_S) is not needed for this configuration. Output impedance is 50Ω for the indicated supply condition.

3. Series termination resistor (R_S) is not needed for this configuration. Reduced EMI setting.

4. 3.2 x 5 mm package is delivered as 3.2 x 4 mm and accommodates the industry-standard 3.2 x 5 mm footprint.

5. Select option to support maximum anticipated frequency needed.

Revision 0.72

Si501/2/3/4 CMEMS Oscillator Series

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

www.silabs.com/cmems

Si501/2/3/4

LVCMOS CMEMS^®Programmable Oscillator Series

6. The Si502 OE pin has three (3) states: OE High = Freq 1; OE Weak High = Freq 2; OE Low is configurable.

Selected Electrical Specifications

V_DD= +1.71 V to +3.63 V, T_A= -40 to 85 ºC unless stated otherwise.

Parameter

Frequency Range

Supply Voltage

Symbol

F_CLK

V_DD

Test Condition/Comment

Programmable family range

Min

0.032

1.71

—

-20

-30

-50

0.4

Typ

—

1.7

3.9

1.7

3.9

670

0.3

—

0.7

1.3

Max

100

3.63

2.5

4.9

2.5

4.9

890

+20

+30

+50

1.2

1.6

Unit

MHz

A

Supports continuous V_DDfrom Min to Max

3.3 V_DD, F_CLK= 1 MHz, 4 pF, Low Power mode

3.3 V_DD, F_CLK= 1 MHz, 4 pF, Low Jitter mode

Stop mode, F_CLK= 1 MHz, Low Power mode

Stop mode, F_CLK= 1 MHz, Low Jitter mode

Doze mode

Supply Current

I_DD1

Static Supply Current¹

Frequency Stability²

I_DD2

Sleep mode

A

ppm

F_STAB

TA = -20 ºC to +70 ºC, -40 ºC to +85 ºC

1^stoption code = A⁴or H⁴

1^stoption code = B, C, D, J, K, L

1^stoption code = E, M

CMOS Rise/Fall Time³

T_R/T_F

1^stoption code = F, N

1^stoption code = G, P

F_CLK= 100 MHz, Low Jitter mode

Cycle-to-Cycle Jitter

Period Jitter Pk-Pk

Period Jitter

J_CCPP

J_PPKPK

J_PRMS



—

ps pk-pk

ps rms

1^stoption code = H

F_CLK= 100 MHz, Low Jitter mode

1^stoption code = H

F_CLK= 100 MHz, Low Jitter mode

1.6

1.3

1^stoption code = H

F_CLK= 75 MHz, F_OFFSET= 900 kHz - 7.5 MHz

Low Jitter mode, 1^stoption code = H

Drive strength selected such that T_R/T_F

(20% to 80%) < 10 % of period

Phase Jitter⁵

Duty Cycle

Input High Voltage

Input Low Voltage

Output High Voltage

Output Low Voltage

V_IH

V_IL

V_OH

V_OL

0.7 x V_DD

—

0.9 x V_DD

—

0.3 x V_DD

—

0.1 x V_DD

1. Si501 supports OE/mode functionality. Si502 supports OE/mode and FS functionality. Si503 supports only FS functionality. See data

sheet functional description section for more information.

2. Frequency stability includes initial tolerance, solder shift, operating temp range, rated power supply voltage change, load change, 10-year

aging, shock, and vibration.

3. C_L= 15 pF, T_R/T_F(20% to 80%), 3.3 V unless otherwise stated. See datasheet for additional T_R/T_Foptions.

4. Recommended series termination resistor (R_S) = 24.9  for Z₀=50 .

5. Integrated phase jitter exceeds some high-performance data communications system requirements. See AN783 for more information.

Absolute Maximum Ratings¹

Condition

Parameter

Storage Temperature

Supply Voltage

Symbol

Rating

-55 to 125

-0.5 to 3.8

0.5 to V_DD+0.3

2000

Unit

ºC

T_S

V_DD

Input Voltage

V_IN

ESD HBM (JESD22-A114)

ESD CDM

Solder Temp²

HBM

CDM

T_PEAK

T_P

500

260

ºC

Solder Time at T_PEAK

20-40

Max Junction Temp

T_J

125

ºC

1. Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation specification compliance is not

implied at these conditions. Exposure to maximum rating conditions for extended periods may affect device reliability.

2. The device is compliant with JEDEC J-STD-020.

Revision 0.72

www.silabs.com/cmems

Si501/2/3/4

LVCMOS CMEMS^®Programmable Oscillator Series

Environmental Compliance and Package Information

Thermal Conditions

Parameter Symbol

Parameter

Test Condition

3.2 x 5 mm, still air

2.5 x 3.2 mm, still air

2 x 2.5 mm, still air

Value

187

239

Unit

Mechanical Shock

MIL-STD-883, M2002 Cond B. (1,500g)

Thermal

_JA

Mechanical Shock High g MIL-STD-883, M2002, Cond. E (10,000g)

ºC/W

Impedance

Mechanical Vibration

Solderability

Temperature Cycle

Resistance to Solder Heat

Contact Pads

MIL-STD-883, Method 2007

MIL-STD-883, Method 2003

JESD22, Method A104

MIL-STD-883, Method 2036

Gold over Nickel/Palladium

241

Clock Timing Characteristics

V_DD= +1.71 V to +3.63 V, T_A= -40 to 85 ºC unless stated otherwise.

Parameter

Startup Time¹

Symbol

T_SU

Test Condition/Comment

From V_DDcrossing 1.71 to first clock

From Stop mode

From Sleep mode

From Doze mode

To Stop

Min Typ

Max

Unit

—

2.5

—

2.5

—

1.5 x T_CLK+ 35 ns

Resume Time ^{2, 3}

T_RUN

2.55

1.5 x T_CLK+ 35 ns

Output Disable Time ^{2, 3}

Frequency Update Time ²

T_D

To Sleep/Doze

To New Frequency

225

s

T_{NEW_FREQ}

—

1. Hold FS/OE high (strong or weak) during powerup for fastest time to clock.

2. Si501 and Si502 only. Si503 has frequency select (FS) only and does not support Stop, Doze or Sleep.

3. T_CLK= clock period = 1/ F_CLK

AC Waveforms

V_DD

1.71V

T_SU

Si501/2/3 Power On Time

R_UP<1k

R_UP>20k

T_D

FS/OE

T_RUN

T_{NEW_FREQ}

Hi-Z

CLK

Si501/2 AC Waveform

R_UP< 1k

R_UP> 20k

R_DOWN> 20k

T_{NEW_ FREQ}

CLK

Hi-Z

Si503 AC Waveform

Revision 0.72

www.silabs.com/cmems

Si501/2/3/4

LVCMOS CMEMS^®Programmable Oscillator Series

Applications Circuits

VDD

R_UP

VDD

CLK

FS/OE

~50K

R_UP

0.1uF

FS/OE

R_DOWN

VDD

CLK

Si501/2

0.1uF

Z₀= 50

Si503

CLK

GND

R_S

Z₀= 50

CLK

GND

R_S

Si501/2 Apps Circuit w/ Optional Series Resistor

Notes:

Si503 Apps Circuit w/ Configurable Options

1. Dotted line boxes show optional components depending on configuration options. See data sheet for additional information and for

applications using a microcontroller. Data sheet is available at www.silabs.com/cmems.

2. Recommended series termination resistor (R_S) = 24.9  for Z₀= 50 .

Si502 FS/OE States and Resistor Values

Si503 FS States and Resistor Values

FS/OE State

Strong High

Weak High

Low

R_UP

0  ≤ R_UP≤ 1 k

20 k ≤ R_UP≤ 200 k

—

Clock Output

Frequency 1

Frequency 2

Hi-Z

FS/OE State

Strong High

Weak High

Weak Low

Low

R_UP

0  ≤ R_UP≤ 1 k

20 k ≤ R_UP≤ 200 k

No pop

R_DOWN

No pop

Clock Output

Frequency 1

Frequency 2

Frequency 3

Frequency 4

20 k ≤ R_DOWN≤ 200 k

0  ≤ R_DOWN≤ 1 k

No pop

Notes for both FS/OE tables above:

1. If the internal pull-up resistor order option is NOT selected, an MCU internal pull-up resistor or an external pull-up resistor should be used.

See data sheet for more information.

2. The parallel combination of all pull-up resistors on the FS/OE pin including the optional internal pull-up resistor must be > 20 k to select

Weak High.

3. If the Si50x internal pull-up resistor is enabled with no other external OE connections, the OE state will be detected as “Weak High”,

selecting Frequency 2 by default.

Revision 0.72

www.silabs.com/cmems

Si501/2/3/4

LVCMOS CMEMS^®Programmable Oscillator Series

Package Dimensions and Landing Patterns

3.2 mm x 5 mm 4-pin DFN Dimensions

3.2 mm x 5 mm 4-pin DFN Landing Pattern

4.00±0.15

2.54

3.20±0.15

1.20

2.20

0.94

1.60

1.34

1.20

0.90 Max

1.50

(top view)

Note: The 3.2 x 5 mm package is delivered as a 3.2 x 4 mm package and is drop-in compatible to industry-standard 3.2 x 5 landing patterns.

2.5 mm x 3.2 mm 4-pin DFN Dimensions

2.5 mm x 3.2 mm 4-pin DFN Landing Pattern

2.20

3.20±0.15

2.50±0.15

0.90

0.70

1.90

1.20

1.40

1.20

(top view)

0.90

0.90 Max

2 mm x 2.5 mm 4-pin DFN Dimensions

2 mm x 2.5 mm 4-pin DFN Landing Pattern

1.90

2.50±0.15

2.00±0.15

0.70

1.50

0.55

1.00

0.65

1.10

0.90 Max

(top view)

Revision 0.72

www.silabs.com/cmems

Si501/2/3/4

LVCMOS CMEMS^®Programmable Oscillator Series

Package Top Marks and Explanations

3.2 mm x 5 mm Top Mark

3.2 mm x 5 mm Top Mark Explanation

Mark

Laser

Method:

Font:

0.66 mm

Right-Justified

Line 1

Marking:

TTTTTT=Trace Code

Manufacturing Code from the

Assembly Purchase Order form.

Line 2

Marking:

Circle=0.5mm

diameter

Pin 1 Indicator

Left-Justified

YY = Year

WW = Work Week

Assigned by the Assembly House.

Corresponds to the year and work

week of the build date.

2.5 mm x 3.2 mm Top Mark

2.5 mm x 3.2 mm Top Mark Explanation

Mark

Laser

Method:

Font:

0.50 mm

Right-Justified

Line 1

Marking:

TTTTT=Trace Code

Manufacturing Code from the

Assembly Purchase Order form.

Line 2

Marking:

Circle=0.3 mm

diameter

Pin 1 Indicator

Left-Justified

YY = Year

WW = Work Week

Assigned by the Assembly House.

Corresponds to the year and work

week of the build date.

2 mm x 2.5 mm Top Mark

2 mm x 2.5 mm Top Mark Explanation

Mark

Laser

Method:

Font:

0.50 mm

Right-Justified

Line 1

Marking:

TTTT=Trace Code

Manufacturing Code from the

Assembly Purchase Order form.

Line 2

Marking:

Circle=0.3 mm

diameter

Pin 1 Indicator

Left-Justified

Y = Year

WW = Work Week

Assigned by the Assembly House.

Corresponds to the year and work

week of the build date.

Revision 0.72

www.silabs.com/cmems

Si501/2/3/4

LVCMOS CMEMS^®Programmable Oscillator Series

CONTACT INFORMATION

Silicon Laboratories Inc.

400 West Cesar Chavez

Austin, TX 78701

Tel: 1+(512) 416-8500

Fax: 1+(512) 416-9669

Toll Free: 1+(877) 444-3032

Please visit the Silicon Labs Technical Support web page:

https://www.silabs.com/support/pages/contacttechnicalsupport.aspx

and register to submit a technical support request.

Patent Notice

Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size,

analog-intensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class

engineering team.

The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.

Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the

use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or

parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty,

representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any

liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation

consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended

to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where

personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized

application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.

Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.

Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.

Revision 0.72

www.silabs.com/cmems

501HCF100M000BAG [SILICON]

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