511MBA125M000BAGR [SILICON]
CMOS Output Clock Oscillator,;
| 型号： | 511MBA125M000BAGR |
| 厂家： | 
SILICON |
| 描述： | CMOS Output Clock Oscillator, 机械 振荡器 |
| 文件： | 总31页 (文件大小：687K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si510/511
CRYSTAL OSCILLATOR (XO) 100 kHZ TO 250 MHZ
Features
2
Supports any frequency from
100 kHz to 250 MHz
Low jitter operation
2 to 4 week lead times
Total stability includes 10-year
aging
3.3, 2.5, or 1.8 V operation
Differential (LVPECL, LVDS,
HCSL) or CMOS output options
Optional integrated 1:2 CMOS
fanout buffer
Runt suppression on OE and
power on
Comprehensive production test
2.5x3.2mm
coverage includes crystal ESR and Industry standard 5 x 7, 3.2 x 5,
DLD
and 2.5 x 3.2 mm packages
Pb-free, RoHS compliant
On-chip LDO regulator for power
supply noise filtering
5x7mm and 3.2x5mm
o
–40 to 85 C operation
Ordering Information:
Applications
See page 14.
SONET/SDH/OTN
Gigabit Ethernet
Fibre Channel/SAS/SATA
PCI Express
3G-SDI/HD-SDI/SDI
Telecom
Switches/routers
Pin Assignments:
See page 12.
FPGA/ASIC clock generation
Description
The Si510/511 XO utilizes Silicon Laboratories' advanced DSPLL technology
to provide any frequency from 100 kHz to 250 MHz. Unlike a traditional XO
where a different crystal is required for each output frequency, the Si510/511
uses one fixed crystal and Silicon Labs’ proprietary DSPLL synthesizer to
generate any frequency across this range. This IC-based approach allows
the crystal resonator to provide enhanced reliability, improved mechanical
robustness, and excellent stability. In addition, this solution provides superior
supply noise rejection, simplifying low jitter clock generation in noisy
environments. Crystal ESR and DLD are individually production-tested to
guarantee performance and enhance reliability. The Si510/511 is factory-
configurable for a wide variety of user specifications, including frequency,
supply voltage, output format, output enable polarity, and stability. Specific
configurations are factory-programmed at time of shipment, eliminating long
lead times and non-recurring engineering charges associated with custom
frequency oscillators.
VDD
1
4
OE
GND
2
3
CLK
Si510 (CMOS)
VDD
1
2
3
6
5
4
NC
OE
CLK–
CLK+
GND
Functional Block Diagram
Si510(LVDS/LVPECL/HCSL/
Dual CMOS)
VDD
V
DD
1
6
OE
Low Noise Regulator
OE
Fixed
Frequency
Oscillator
Any-Frequency
0.1 to 250 MHz
CLK+
CLK–
NC
2
5
CLK–
DSPLL® Synthesis
GND
3
4
CLK+
Si511(LVDS/LVPECL/HCSL/
Dual CMOS)
GND
Rev. 1.4 6/18
Copyright © 2018 by Silicon Laboratories
Si510/511
Si510/511
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Solder Reflow and Rework Requirements for 2.5x3.2 mm Packages . . . . . . . . . . . . . .11
3. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.1 Dual CMOS Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
4. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
5. Si510/511 Mark Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
6. Package Outline Diagram: 5 x 7 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
7. PCB Land Pattern: 5 x 7 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
8. Package Outline Diagram: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
9. PCB Land Pattern: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
10. Package Outline Diagram: 3.2 x 5 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
11. PCB Land Pattern: 3.2 x 5 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
12. Package Outline Diagram: 3.2 x 5 mm, 6-Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
13. PCB Land Pattern: 3.2 x 5.0 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
14. Package Outline Diagram: 2.5 x 3.2 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
15. PCB Land Pattern: 2.5 x 3.2 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
16. Package Outline Diagram: 2.5 x 3.2 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
17. PCB Land Pattern: 2.5 x 3.2 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2
Rev. 1.4
Si510/511
1. Electrical Specifications
Table 1. Operating Specifications
VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC
Parameter
Supply Voltage
Symbol
Test Condition
3.3 V option
2.5 V option
1.8 V option
Min
2.97
2.25
1.71
—
Typ
3.3
2.5
1.8
21
Max
3.63
2.75
1.89
26
Unit
V
V
DD
V
V
Supply Current
I
CMOS, 100 MHz,
single-ended
mA
DD
LVDS
(output enabled)
—
—
—
—
19
39
41
—
23
43
44
18
mA
mA
mA
mA
LVPECL
(output enabled)
HCSL
(output enabled)
Tristate
(output disabled)
OE "1" Setting
V
See Note
See Note
0.80 x V
—
—
45
—
0.20 x V
—
V
V
IH
DD
OE "0" Setting
V
—
—
IL
DD
OE Internal Pull-Up/Pull-
Down Resistor
R
k
I
*
o
Operating Temperature
T
–40
—
85
C
A
*Note: Active high and active low polarity OE options available. Active high option includes an internal pull-up.
Active low option includes an internal pull-down. See ordering information on page 14.
Rev. 1.4
3
Si510/511
Table 2. Output Clock Frequency Characteristics
VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC
Parameter
Symbol
Test Condition
Min
0.1
Typ
—
—
—
—
—
—
—
—
—
Max
212.5
250
+30
+50
+100
+20
+25
+50
10
Unit
MHz
MHz
ppm
ppm
ppm
ppm
ppm
ppm
ms
Nominal Frequency
F
F
CMOS, Dual CMOS
O
O
LVDS/LVPECL/HCSL
0.1
Total Stability*
Frequency Stability Grade C
Frequency Stability Grade B
Frequency Stability Grade A
Frequency Stability Grade C
Frequency Stability Grade B
Frequency Stability Grade A
–30
–50
–100
–20
–25
–50
—
Temperature Stability
Startup Time
Disable Time
T
Minimum V until output
DD
SU
frequency (F ) within specification
O
T
F
10 MHz
O
—
—
—
—
—
—
—
—
5
µs
µs
µs
µs
D
E
F < 10 MHz
40
20
60
O
Enable Time
T
F 10 MHz
O
F < 10 MHz
O
*Note: Total stability includes initial accuracy, operating temperature, supply voltage change, load change, shock and vibration
(not under operation), and 10 years aging at 40 oC.
4
Rev. 1.4
Si510/511
Table 3. Output Clock Levels and Symmetry
VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
CMOS Output Logic
High
V
0.85 x V
—
—
V
OH
DD
CMOS Output Logic
Low
V
—
—
0.15 x V
V
OL
DD
CMOS Output Logic
High Drive
I
3.3 V
2.5 V
–8
–6
–4
8
—
—
—
—
—
—
0.8
—
—
—
—
—
—
1.2
mA
mA
mA
mA
mA
mA
ns
OH
1.8 V
CMOS Output Logic
Low Drive
I
3.3 V
OL
2.5 V
6
1.8 V
4
CMOS Output Rise/Fall
Time
T /T
0.1 to 212.5 MHz,
0.45
R
F
F
C = 15 pF
L
(20 to 80% V
)
DD
0.1 to 212.5 MHz,
0.3
0.6
—
0.9
ns
ps
C = no load
L
LVPECL Output
Rise/Fall Time
(20 to 80% VDD)
T /T
100
565
R
HCSL Output Rise/Fall
Time (20 to 80% VDD)
T /T
100
350
—
—
—
470
800
—
ps
ps
V
R
F
F
LVDS Output Rise/Fall
Time (20 to 80% VDD)
T /T
R
LVPECL Output
Common Mode
V
50 to V – 2 V,
V
–
DD
1.4 V
OC
DD
single-ended
LVPECL Output Swing
V
50 to V – 2 V,
0.55
1.13
0.8
0.90
1.33
V
PPSE
O
DD
single-ended
LVDS Output Common
Mode
V
100 line-line
1.23
V
OC
V
= 3.3/2.5 V
DD
100 line-line, V = 1.8 V
0.83
0.25
0.92
0.35
1.00
0.45
V
DD
LVDS Output Swing
V
Single-ended, 100 differential
V
V
O
PPSE
termination
HCSL Output Common
Mode
V
50 to ground
0.35
0.38
0.42
V
OC
HCSL Output Swing
Duty Cycle
V
Single-ended
All formats
0.58
48
0.73
50
0.85
52
O
PPSE
DC
%
Rev. 1.4
5
Si510/511
Table 4. Output Clock Jitter and Phase Noise (LVPECL)
VDD = 2.5 or 3.3 V ±10%, TA = –40 to +85 oC; Output Format = LVPECL
Symbol
Test Condition
Min
Typ
Max
Unit
Parameter
1
Period Jitter
(RMS)
JPRMS
10k samples
—
—
1.3
ps
1
Period Jitter
(Pk-Pk)
JPPKPK
φJ
10k samples
—
—
—
11
ps
ps
Phase Jitter
(RMS)
1.875 MHz to 20 MHz integration
0.31
0.5
2
bandwidth (brickwall)
12 kHz to 20 MHz integration band-
—
0.8
1.0
ps
2
width (brickwall)
Phase Noise,
156.25 MHz
φN
100 Hz
1 kHz
—
—
—
—
—
—
—
—
—
—
–86
–109
–116
–123
–136
3.0
—
—
—
—
—
—
—
—
—
—
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ps
10 kHz
100 kHz
1 MHz
Additive RMS
Jitter Due to
JPSR
SPR
10 kHz sinusoidal noise
100 kHz sinusoidal noise
500 kHz sinusoidal noise
1 MHz sinusoidal noise
3.5
ps
External Power
3
Supply Noise
3.5
ps
3.5
ps
Spurious
LVPECL output, 156.25 MHz,
offset>10 kHz
–75
dBc
Notes:
1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,
212.5, 250 MHz.
2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 and 250 MHz.
3. 156.25 MHz. Increase in jitter on output clock due to sinewave noise added to VDD (2.5/3.3 V = 100 mVPP).
6
Rev. 1.4
Si510/511
Table 5. Output Clock Jitter and Phase Noise (LVDS)
VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC; Output Format = LVDS
Symbol
Test Condition
Min
Typ
Max
Unit
Parameter
1
Period Jitter
(RMS)
JPRMS
10k samples
—
—
2.1
ps
1
Period Jitter
(Pk-Pk)
JPPKPK
φJ
10k samples
—
—
—
18
ps
ps
Phase Jitter
(RMS)
1.875 MHz to 20 MHz integration
0.25
0.55
2
bandwidth (brickwall)
12 kHz to 20 MHz integration band-
—
0.8
1.0
ps
2
width (brickwall)
Phase Noise,
156.25 MHz
φN
100 Hz
1 kHz
—
—
—
—
—
—
–86
–109
–116
–123
–136
–75
—
—
—
—
—
—
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc
10 kHz
100 kHz
1 MHz
Spurious
SPR
LVPECL output, 156.25 MHz,
offset>10 kHz
Notes:
1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,
212.5, 250 MHz.
2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 and 250 MHz.
Rev. 1.4
7
Si510/511
Table 6. Output Clock Jitter and Phase Noise (HCSL)
VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC; Output Format = HCSL
Symbol
Test Condition
Min
Typ
Max
Unit
Parameter
*
Period Jitter
(RMS)
JPRMS
10k samples
—
—
1.2
ps
*
Period Jitter
(Pk-Pk)
JPPKPK
φJ
10k samples
—
—
—
11
ps
ps
Phase Jitter
(RMS)
1.875 MHz to 20 MHz integration
0.25
0.30
*
bandwidth (brickwall)
12 kHz to 20 MHz integration band-
—
0.8
1.0
ps
*
width (brickwall)
Phase Noise,
156.25 MHz
φN
100 Hz
1 kHz
—
—
—
—
—
—
–90
–112
–120
–127
–140
–75
—
—
—
—
—
—
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc
10 kHz
100 kHz
1 MHz
Spurious
SPR
LVPECL output, 156.25 MHz,
offset>10 kHz
*Note: Applies to an output frequency of 100 MHz.
8
Rev. 1.4
Si510/511
Table 7. Output Clock Jitter and Phase Noise (CMOS, Dual CMOS (Complementary))
VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC; Output Format = CMOS, Dual CMOS (Complementary)
Symbol
Test Condition
Min
Typ
Max
Unit
Parameter
Phase Jitter
φJ
1.875 MHz to 20 MHz integration
—
0.25
0.35
ps
2
(RMS)
bandwidth (brickwall)
12 kHz to 20 MHz integration band-
—
0.8
1.0
ps
2
width (brickwall)
Phase Noise,
156.25 MHz
φN
100 Hz
1 kHz
—
—
—
—
—
—
–86
–108
–115
–123
–136
–75
—
—
—
—
—
—
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc
10 kHz
100 kHz
1 MHz
Spurious
SPR
LVPECL output, 156.25 MHz,
offset>10 kHz
Notes:
1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,
212.5 MHz.
2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 MHz.
Table 8. Environmental Compliance and Package Information
Parameter
Conditions/Test Method
MIL-STD-883, Method 2002
MIL-STD-883, Method 2007
MIL-STD-883, Method 2003
MIL-STD-883, Method 1014
MIL-STD-883, Method 2036
Gold over Nickel
Mechanical Shock
Mechanical Vibration
Solderability
Gross and Fine Leak
Resistance to Solder Heat
Contact Pads
Rev. 1.4
9
Si510/511
Table 9. Thermal Characteristics
Parameter
Symbol
Test Condition
Still air
Value
110
Unit
°C/W
°C/W
CLCC, Thermal Resistance Junction to Ambient
JA
2.5x3.2mm, Thermal Resistance Junction to Ambient
Still air
164
JA
Table 10. Absolute Maximum Ratings1
Parameter
Symbol
Rating
85
Unit
o
Maximum Operating Temperature
T
C
AMAX
o
Storage Temperature
T
–55 to +125
–0.5 to +3.8
C
S
Supply Voltage
V
V
V
DD
Input Voltage (any input pin)
ESD Sensitivity (HBM, per JESD22-A114)
V
–0.5 to V + 0.3
I
DD
HBM
2
kV
2
o
Soldering Temperature (Pb-free profile)
T
260
C
PEAK
2
Soldering Temperature Time at T
(Pb-free profile)
T
20–40
sec
PEAK
P
Notes:
1. Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation or
specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended
periods may affect device reliability.
2. The device is compliant with JEDEC J-STD-020E.
10
Rev. 1.4
Si510/511
2. Solder Reflow and Rework Requirements for 2.5x3.2 mm Packages
Reflow of Silicon Labs' components should be done in a manner consistent with the IPC/JEDEC J-STD-20E
standard. The temperature of the package is not to exceed the classification Temperature provided in the standard.
The part should not be within -5°C of the classification or peak reflow temperature (T
) for longer than 30
PEAK
seconds. Key to maintaining the integrity of the component is providing uniform heating and cooling of the part
during reflow and rework. Uniform heating is achieved through having a preheat soak and controlling the
temperature ramps in the process. J-STD-20E provides minimum and maximum temperatures and times for the
preheat/Soak step that need to be followed, even for rework. The entire assembly area should be heated during
rework. Hot air should be flowed from both the bottom of the board and the top of the component. Heating from the
top only will cause un-even heating of component and can lead to part integrity issues. Temperature Ramp-up rate
are not to exceed 3°C/second. Temperature ramp-down rates from peak to final temperature are not to exceed
6°C/second. Time from 25°C to peak temperature is not to exceed 8 min for Pb-free solders.
Rev. 1.4
11
Si510/511
3. Pin Descriptions
VDD
1
2
4
OE
VDD
VDD
1
2
3
6
5
4
1
2
3
6
5
4
OE
NC
NC
OE
CLK–*
CLK+
CLK–*
CLK+
GND
3
CLK
GND
GND
Si510 (CMOS)
Si510 (LVDS/LVPECL/HCSL/Dual CMOS*)
Si511 (LVDS/LVPECL/HCSL/DualCMOS)*)
*Supports integrated 1:2 CMOS buffer. See ordering information and section 2.1“Dual CMOS Buffer”.
Table 11. Si510 Pin Descriptions (CMOS)
Pin
Name
CMOS Function
Output Enable. Includes internal pull-up for OE active high. Includes
internal pull-down for OE active low. See ordering information.
Electrical and Case Ground.
1
OE
2
3
4
GND
CLK
Clock Output.
Power Supply Voltage.
V
DD
Table 12. Si510 Pin Descriptions (LVPECL/LVDS/HCSL, Dual CMOS, OE Pin 2)
Pin
Name
NC
LVPECL/LVDS/HCSL Function
No connect. Make no external connection to this pin.
1
2
Output Enable. Includes internal pull-up for OE active high. Includes
internal pull-down for OE active low. See ordering information.
Electrical and Case Ground.
OE
3
4
5
6
GND
CLK+
CLK–
Clock Output.
Complementary Clock Output.
Power Supply Voltage.
V
DD
Table 13. Si511 Pin Descriptions (LVPECL/LVDS/HCSL, Dual CMOS, OE Pin 1)
Pin
Name
LVPECL/LVDS/HCSL Function
Output Enable. Includes internal pull-up for OE active high. Includes
internal pull-down for OE active low. See ordering information.
No connect. Make no external connection to this pin.
1
OE
2
3
4
5
6
NC
Electrical and Case Ground.
Clock Output.
GND
CLK+
CLK–
Complementary Clock Output.
Power Supply Voltage.
V
DD
12
Rev. 1.4
Si510/511
3.1. Dual CMOS Buffer
Dual CMOS output format ordering options support either complementary or in-phase output signals. This feature
enables replacement of multiple XOs with a single Si510/11 device.
~
Complementary
Outputs
~
In-Phase
Outputs
Figure 1. Integrated 1:2 CMOS Buffer Supports Complementary or In-Phase Outputs
Rev. 1.4
13
Si510/511
4. Ordering Information
The Si510/511 supports a wide variety of options including frequency, stability, output format, and V . Specific
DD
device configurations are programmed into the Si510/511 at time of shipment. Configurations can be specified
using the Part Number Configuration chart below. Silicon Labs provides a web browser-based part number
configuration utility to simplify this process. To access this tool refer to www.silabs.com/oscillators and click
“Customize” in the product table. The Si510/511 XO series is supplied in industry-standard, RoHS compliant, lead-
free, 2.5 x 3.2 mm, 3.2 x 5.0 mm, and 5 x 7 mm packages. Tape and reel packaging is an ordering option.
Series
510
Output Format
CMOS
OE Pin
Package
4-pin
A = Revision: A
G = Temp Range: -40°C to 85°Cꢀ
R = Tape & Reel; Blank = &RLOꢀ7DSH
OE on pin 1
OE on pin 2
OE on pin 1
510
LVPECL, LVDS, HCSL, Dual CMOS
LVPECL, LVDS, HCSL, Dual CMOS
6-pin
511
6-pin
1st Option Code:
Output Format
A
B
C
D
E
F
3.3V
3.3V
3.3V
3.3V
2.5V
2.5V
2.5V
2.5V
1.8V
1.8V
1.8V
3.3V
3.3V
2.5V
2.5V
1.8V
1.8V
LVPECL
LVDS
CMOS
HCSL
LVPECL
3rd Option Code:
Output Enable
Package Option
Dimensions
LVDS
OE Polarity
G
H
J
CMOS
B
OE Active Low
B
&
3.2 x 5 mm
ꢁꢂꢃꢀ[ꢀꢄꢂꢁꢀPP
HCSL
LVDS
K
L
CMOS
Frequency Code
Frequency
2nd Option Code:
Frequency Stability
HCSL
Description
M
N
P
Q
R
S
Dual CMOS (In-phase)
Dual CMOS (Complementary)
Dual CMOS (In-phase)
Dual CMOS (Complementary)
Dual CMOS (In-phase)
Dual CMOS (Complementary)
Mxxxxxx
xMxxxxx
xxMxxxx
xxxMxxx
xxxxxx
fOUT < 1 MHz
Total
Temperature
50ppm
1 MHz fOUT < 10 MHz
A
B
C
100ppm
50ppm
30ppm
10 MHz fOUT < 100 MHz
25ppm
100 MHz fOUT < 250 MHz
20ppm
Code if frequency requires >6 digit resolution
Figure 2. Part Number Syntax
Example orderable part number: 510ECB156M250AAG supports 2.5 V LVPECL, ±30 ppm total stability, OE active
o
o
low in 5 x 7 mm package across –40 C to 85 C temperature range. The output frequency is 156.25 MHz.
Note: CMOS and Dual CMOS maximum frequency is 212.5 MHz.
14
Rev. 1.4
Si510/511
5. Si510/511 Mark Specification
Figure 3 illustrates the mark specification for the Si510/511. Use the part number configuration utility located at:
www.silabs.com/VCXOpartnumber to cross-reference the mark code to a specific device configuration.
0 C CC CC
T T T T T T
Y Y WW
0 = Si510, 1 = Si511
CCCCC = mark code
TTTTTT = assembly manufacturing code
YY = year
WW = work week
Figure 3. Top Mark
Rev. 1.4
15
Si510/511
6. Package Outline Diagram: 5 x 7 mm, 4-pin
Figure 4 illustrates the package details for the 5 x 7 mm Si510/511. Table 14 lists the values for the dimensions
shown in the illustration.
Figure 4. Si510/511 Outline Diagram
Table 14. Package Diagram Dimensions (mm)
Dimension
Min
1.50
1.30
0.50
Nom
1.65
Max
1.80
1.50
0.70
A
b
1.40
c
0.60
D
5.00 BSC
4.40
D1
e
4.30
4.50
5.08 BSC
0.50 TYP
7.00 BSC
6.20
f
E
E1
H
6.10
0.55
1.17
0.05
2.50
6.30
0.75
1.37
0.15
2.70
0.65
L
1.27
L1
p
0.10
2.60
aaa
bbb
ccc
ddd
eee
0.15
0.15
0.10
0.10
0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
16
Rev. 1.4
Si510/511
7. PCB Land Pattern: 5 x 7 mm, 4-pin
Figure 5 illustrates the 5 x 7 mm PCB land pattern for the 5 x 7 mm Si510/511. Table 15 lists the values for the
dimensions shown in the illustration.
Figure 5. Si510/511 PCB Land Pattern
Table 15. PCB Land Pattern Dimensions (mm)
Dimension
(mm)
C1
4.20
E
5.08
1.55
1.95
X1
Y1
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition
(LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
to assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020D specification for
Small Body Components.
Rev. 1.4
17
Si510/511
8. Package Outline Diagram: 5 x 7 mm, 6-pin
Figure 6 illustrates the package details for the Si510/511. Table 16 lists the values for the dimensions shown in the
illustration.
Figure 6. Si510/511 Outline Diagram
Table 16. Package Diagram Dimensions (mm)
Dimension
Min
1.50
1.30
0.50
Nom
1.65
Max
1.80
1.50
0.70
A
b
1.40
c
0.60
D
5.00 BSC
4.40
D1
e
4.30
4.50
2.54 BSC
7.00 BSC
6.20
E
E1
H
6.10
0.55
1.17
0.05
1.80
6.30
0.75
1.37
0.15
2.60
0.65
L
1.27
L1
p
0.10
—
R
0.70 REF
0.15
aaa
bbb
ccc
ddd
eee
0.15
0.10
0.10
0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
18
Rev. 1.4
Si510/511
9. PCB Land Pattern: 5 x 7 mm, 6-pin
Figure 7 illustrates the 5 x 7 mm PCB land pattern for the Si510/511. Table 17 lists the values for the dimensions
shown in the illustration.
Figure 7. Si510/511 PCB Land Pattern
Table 17. PCB Land Pattern Dimensions (mm)
Dimension
(mm)
C1
4.20
E
2.54
1.55
1.95
X1
Y1
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition
(LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to
assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
Body Components.
Rev. 1.4
19
Si510/511
10. Package Outline Diagram: 3.2 x 5 mm, 4-pin
Figure 8 illustrates the package details for the 3.2 x 5 mm Si510/511. Table 18 lists the values for the dimensions
shown in the illustration.
Figure 8. Si510/511 Outline Diagram
Table 18. Package Diagram Dimensions (mm)
Dimension
Min
1.06
1.10
0.70
Nom
1.17
Max
1.28
1.30
0.90
A
b
1.20
c
0.80
D
3.20 BSC
2.60
D1
e
2.55
2.65
2.54 BSC
0.40 TYP
5.00 BSC
4.40
f
E
E1
H
4.35
0.40
0.90
0.05
1.17
4.45
0.60
1.10
0.15
1.37
0.50
L
1.00
L1
p
0.10
1.27
aaa
bbb
ccc
ddd
eee
0.15
0.15
0.10
0.10
0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
20
Rev. 1.4
Si510/511
11. PCB Land Pattern: 3.2 x 5 mm, 4-pin
Figure 9 illustrates the 3.2 x 5 mm PCB land pattern for the Si510/511. Table 19 lists the values for the dimensions
shown in the illustration.
Figure 9. Si510/511 PCB Land Pattern
Table 19. PCB Land Pattern Dimensions (mm)
Dimension
(mm)
C1
2.60
E
2.54
1.35
1.70
X1
Y1
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition
(LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for
Small Body Components.
Rev. 1.4
21
Si510/511
12. Package Outline Diagram: 3.2 x 5 mm, 6-Pin
Figure 10 illustrates the package details for the 3.2 x 5 mm Si510/511. Table 20 lists the values for the dimensions
shown in the illustration.
Figure 10. Si510/511 Outline Diagram
Table 20. Package Diagram Dimensions (mm)
Dimension
Min
1.06
0.54
0.35
Nom
1.17
Max
1.33
0.74
0.55
A
b
0.64
c
0.45
D
3.20 BSC
2.60
D1
e
2.55
2.65
1.27 BSC
5.00 BSC
4.40
E
E1
H
4.35
0.45
0.80
0.05
1.17
4.45
0.65
1.00
0.15
1.37
0.55
L
0.90
L1
p
0.10
1.27
R
0.32 REF
0.15
aaa
bbb
ccc
ddd
eee
0.15
0.10
0.10
0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
22
Rev. 1.4
Si510/511
13. PCB Land Pattern: 3.2 x 5.0 mm, 6-pin
Figure 11 illustrates the 3.2 x 5.0 mm PCB land pattern for the Si510/511. Table 21 lists the values for the
dimensions shown in the illustration.
Figure 11. Si510/511 Recommended PCB Land Pattern
Table 21. PCB Land Pattern Dimensions (mm)
Dimension
(mm)
C1
2.60
E
1.27
0.80
1.70
X1
Y1
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification
for Small Body Components.
Rev. 1.4
23
Si510/511
14. Package Outline Diagram: 2.5 x 3.2 mm, 4-pin
Figure 12 illustrates the package details for the 2.5 x 3.2 mm Si510/511. Table 22 lists the values for the
dimensions shown in the illustration.
Figure 12. Si510/511 Outline Diagram
24
Rev. 1.4
Si510/511
Table 22. Package Diagram Dimensions (mm)
Dimension
Min
Nom
—
Max
A
—
1.1
A1
A2
W
0.26 REF
0.7 REF
0.65
0.85
0.7
0.75
0.95
D
e
3.20 BSC
2.10 BSC
2.50 BSC
0.9
E
L
E1
SE
aaa
bbb
ddd
1.65 BSC
0.825 BSC
0.1
0.2
0.08
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
Rev. 1.4
25
Si510/511
15. PCB Land Pattern: 2.5 x 3.2 mm, 4-pin
Figure illustrates the 2.5 x 3.2 mm PCB land pattern for the Si510/511. Table 23 lists the values for the dimensions
shown in the illustration.
Figure 13. Si510/511 Recommended PCB Land Pattern
Table 23. PCB Land Pattern Dimensions (mm)
Dimension
(mm)
C1
2.0
E
2.10
0.95
1.15
X1
Y1
Notes:
General
1. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
Card Assembly
7. A No-Clean, Type-3 solder paste is recommended.
8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for
Small Body Components.
26
Rev. 1.4
Si510/511
16. Package Outline Diagram: 2.5 x 3.2 mm, 6-pin
Figure 14 illustrates the package details for the 2.5 x 3.2 mm Si510/511. Table 24 lists the values for the
dimensions shown in the illustration.
Figure 14. Si510/511 Outline Diagram
Rev. 1.4
27
Si510/511
Table 24. Package Diagram Dimensions (mm)
Dimension
Min
Nom
—
Max
A
—
1.1
A1
A2
W
0.26 REF
0.7 REF
0.65
0.45
0.7
0.75
0.55
D
e
3.20 BSC
1.25 BSC
2.50 BSC
0.30 BSC
0.5
E
M
L
D1
E1
SE
aaa
bbb
ddd
2.5 BSC
1.65 BSC
0.825 BSC
0.1
0.2
0.08
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
28
Rev. 1.4
Si510/511
17. PCB Land Pattern: 2.5 x 3.2 mm, 6-pin
Figure 15 illustrates the 2.5 x 3.2 mm PCB land pattern for the Si510/511. Table 25 lists the values for the
dimensions shown in the illustration.
Figure 15. Si510/511 Recommended PCB Land Pattern
Table 25. PCB Land Pattern Dimensions (mm)
Dimension
(mm)
C1
1.9
E
2.50
0.70
1.05
X1
Y1
Notes:
General
3. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
4. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification
for Small Body Components.
Rev. 1.4
29
Si510/511
REVISION HISTORY
Revision 1.4
June, 2018
Changed “Trays” to “Coil Tape” in the Ordering Guide.
Revision 1.3
December, 2017
Added new 2.5 x 3.2 mm package options.
Revision 1.2
Updated Table 3.
Separated LVPECL and HCSL output Rise/Fall time specs.
Min Rise/Fall times added.
Revision 1.1
Updated Table 3.
CMOS Output Rise/Fall Time Test Condition updated.
Revision 1.0
Updated Table 1 on page 3.
Updates to supply current typical and maximum values for CMOS, LVDS, LVPECL and HCSL.
CMOS frequency test condition corrected to 100 MHz.
Updates to OE VIH minimum and VIL maximum values.
Updated Table 2 on page 4.
Dual CMOS nominal frequency maximum added.
Total stability footnotes clarified for 10 year aging at 40 °C.
Disable time maximum values updated.
Enable time parameter added.
Updated Table 3 on page 5.
CMOS output rise / fall time typical and maximum values updated.
LVPECL/HCSL output rise / fall time maximum value updated.
LVPECL output swing maximum value updated.
LVDS output common mode typical and maximum values updated.
HCSL output swing maximum value updated.
Duty cycle minimum and maximum values tightened to 48/52%.
Updated Table 4 on page 6.
Phase jitter test condition and maximum value updated.
Phase noise typical values updated.
Additive RMS jitter due to external power supply noise typical values updated.
Footnote 3 updated limiting the VDD to 2.5/3.3V
Added Tables 5, 6, 7 for LVDS, HCSL, CMOS, and Dual CMOS operations.
Moved Absolute Maximum Ratings table.
Added note to Figure 2 clarifying CMOS and Dual CMOS maximum frequency.
Updated Figure 10 outline diagram to correct pinout.
30
Rev. 1.4
ClockBuilder Pro
One-click access to Timing tools,
documentation, software, source
code libraries & more. Available for
Windows and iOS (CBGo only).
www.silabs.com/CBPro
Timing Portfolio
www.silabs.com/timing
SW/HW
www.silabs.com/CBPro
Quality
www.silabs.com/quality
Support and Community
community.silabs.com
Disclaimer
Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or
intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"
parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes
without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included
information. Silicon Labs shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted
hereunder to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any Life Support System without the specific written consent of
Silicon Labs. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant
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destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.
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EFM32®, EFR, Ember®, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZRadio®, EZRadioPRO®,
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