513FBA000576BAG_技术文档

Si512/513

DUAL FREQUENCY CRYSTAL OSCILLATOR (XO)

100 kHZ TO 250 MHZ

Features



Supports any frequency from

100 kHz to 250 MHz

Two selectable output frequencies

Low-jitter operation

2 to 4 week lead times

Total stability includes 10-year

aging

Comprehensive production test

coverage includes crystal ESR and

DLD



3.3, 2.5, or 1.8 V operation

Differential (LVPECL, LVDS,

HCSL) or CMOS output options

Optional integrated 1:2 CMOS

fanout buffer

Runt suppression on OE and

power on

Industry standard 5x7, 3.2x5, and

2.5x3.2 mm packages

Si5602



2.5x3.2mm



Pb-free, RoHS compliant

5x7mm and 3.2x5mm

o

On-chip LDO regulator for power

supply noise filtering

–40 to 85 C operation

Ordering Information:

Applications

See page 13.



SONET/SDH/OTN

Gigabit Ethernet

Fibre Channel/SAS/SATA

PCI Express



Broadcast video

Switches/routers

Telecom



Pin Assignments:

See page 12.

FPGA/ASIC clock generation

Description

V_DD

1

2

3

6

5

4

FS

OE

The Si512/513 dual frequency XO utilizes Silicon Laboratories' advanced

PLL technology to provide any frequency from 100 kHz to 250 MHz. Unlike a

traditional XO where a different crystal is required for each output frequency,

the Si512/513 uses one fixed crystal and Silicon Labs’ proprietary any-

frequency synthesizer to generate any frequency across this range. This IC-

based approach allows the crystal resonator to provide enhanced reliability,

improved mechanical robustness, and excellent stability. In addition, this

solution provides superior supply noise rejection, simplifying low jitter clock

generation in noisy environments. The Si512/513 is factory-configurable for a

wide variety of user specifications, including frequency, supply voltage,

output format, output enable polarity, and stability. Specific configurations are

factory-programmed at time of shipment, eliminating long lead times and

non-recurring engineering charges associated with custom frequency

oscillators.

NC

GND

CLK

Si512 CMOS Dual XO

V_DD

1

2

3

6

5

4

OE

FS

NC

GND

CLK

Si513 CMOS Dual XO

V_DD

1

2

3

6

5

4

FS

OE

CLK–

CLK+

GND

Functional Block Diagram

Si512 LVDS/LVPECL/HCSL/CMOS

Dual XO

V_DD

1

2

3

6

5

4

OE

FS

Power Supply Filtering

OE

CLK–

CLK+

Fixed

Frequency

Oscillator

Any-Frequency

0.1 to 250 MHz

CLK+

CLK–

DSPLL^®Synthesis

GND

Si513 LVDS/LVPECL/HCSL/CMOS

Dual XO

GND

FS

Rev. 1.2 6/18

Si512/13

Si512/513

TABLE OF CONTENTS

Section

Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

2. Solder Reflow and Rework Requirements for 2.5x3.2 mm Packages . . . . . . . . . . . . . .10

3. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.1. Dual CMOS Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

4. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

5. Package Outline Diagram, 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

6. PCB Land Pattern: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

7. Package Outline Diagram: 3.2 x 5.0 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

8. PCB Land Pattern: 3.2 x 5.0 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

9. Package Outline Diagram: 2.5 x 3.2 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

10. PCB Land Pattern: 2.5 x 3.2 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

11. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

11.1. Si512/513 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

11.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

2

Rev. 1.2

Si512/513

1. Electrical Specifications

Table 1. Operating Specifications

V_DD= 1.8 V ±5%, 2.5 or 3.3 V ±10%, T_A= –40 to +85 ^oC

Parameter

Supply Voltage

Symbol

Test Condition

Min

Typ

Max

Units

V

3.3 V option

2.5 V option

1.8 V option

2.97

2.25

1.71

3.3

2.5

1.8

3.63

2.75

1.89

V

DD

V

I

mA

Supply Current

CMOS, 100 MHz,

single-ended

—

21

26

DD

LVDS

(output enabled)

—

19

39

41

—

23

43

44

18

mA

LVPECL

(output enabled)

HCSL

(output enabled)

Tristate

(output disabled)

V

See Note

0.80 x V

—

45

—

0.20 x V

—

V

FS, OE "1" Setting

FS, OE "0" Setting

IH

DD

V

—

IL

DD

R

k

FS, OE Internal Pull-

Up/Pull-Down Resistor

I

*

o

T

–40

—

85

C

Operating Temperature

A

Note: Active high and active low polarity OE options available. Active high uses internal pull-up. Active low uses internal pull-

down. See ordering information on page 12.

Rev. 1.2

3

Si512/513

Table 2. Output Clock Frequency Characteristics

V_DD= 1.8 V ±5%, 2.5 or 3.3 V ±10%, T_A= –40 to +85 ^oC

Parameter

Symbol

Test Condition

Min

0.1

Typ

—

Max

212.5

250

+30

+50

+100

+20

+25

+50

10

Units

MHz

ppm

ms

Nominal Frequency

F

CMOS, Dual CMOS

O

LVDS/LVPECL/HCSL

0.1

—

Total Stability*

Frequency Stability Grade C

Frequency Stability Grade B

Frequency Stability Grade A

Frequency Stability Grade C

Frequency Stability Grade B

Frequency Stability Grade A

–30

–50

–100

–20

–25

–50

—

Temperature Stability

Startup Time

Disable Time

T

Minimum V to output

—

SU

DD

frequency (F ) within specification

O

T

F 10 MHz

—

5

µs

ms

D

E

O

F < 10 MHz

40

20

60

10

O

Enable Time

T

F 10 MHz

O

F < 10 MHz

O

Settling Time after FS

Change

t

FRQ

*Note: Total stability includes initial accuracy, operating temperature, supply voltage change, load change, shock and

vibration (not under operation), and 10 years aging at 40 ^°C.

4

Rev. 1.2

Si512/513

Table 3. Output Clock Levels and Symmetry

V_DD= 1.8 V ±5%, 2.5 or 3.3 V ±10%, T_A= –40 to +85 ^oC

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

V

0.85 x V

—

V

CMOS Output Logic

High

OH

DD

V

—

0.15 x V

V

CMOS Output Logic

Low

OL

DD

I

3.3 V

2.5 V

–8

–6

–4

8

—

0.8

—

1.2

mA

ns

CMOS Output Logic

High Drive

OH

1.8 V

I

3.3 V

CMOS Output Logic

Low Drive

OL

2.5 V

6

1.8 V

4

T /T

0.1 to 125 MHz,

—

CMOS Output Rise/Fall

Time

R

F

C = 15 pF

L

(20 to 80% V

)

DD

0.1 to 212.5 MHz,

—

0.6

—

0.9

ns

ps

C = no load

L

T /T

565

LVPECL/HCSL Output

Rise/Fall Time

R

F

(20 to 80% V

)

DD

T /T

—

800

ps

V

LVDS Output Rise/Fall

Time

R

(20 to 80% V

)

DD

V

—

V

–

—

LVPECL Output

Common Mode

50  to V – 2 V,

OC

DD

1.4 V

single-ended

V

0.55

0.8

0.90

V

PPSE

LVPECL Output Swing

50  to V – 2 V,

O

DD

single-ended

V

100  line-line, V = 3.3/2.5 V

1.13

0.83

0.25

1.23

0.92

0.35

1.33

1.00

0.45

V

LVDS Output Common

Mode

OC

DD

100  line-line, V = 1.8 V

DD

V

Single-ended, 100  differential

V

LVDS Output Swing

O

PPSE

termination

50 to ground

0.35

0.38

0.42

V

HCSL Output Common

Mode

OC

V

Single-ended

0.58

48

0.73

50

0.85

52

HCSL Output Swing

Duty Cycle

O

PPSE

DC

All Output Formats

%

Rev. 1.2

5

Si512/513

Table 4. Output Clock Jitter and Phase Noise (LVPECL)

V_DD= 2.5 or 3.3 V ±10%, T_A= –40 to +85 ^oC; Output Format = LVPECL

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

1

Period Jitter

(RMS)

JPRMS

10k samples

—

1.3

ps

1

Period Jitter

(Pk-Pk)

JPPKPK

φJ

10k samples

—

0.31

0.8

11

ps

Phase Jitter

(RMS)

1.875 MHz to 20 MHz integration

0.5

1.0

2

bandwidth (brickwall)

12 kHz to 20 MHz integration band-

2

width (brickwall)

Phase Noise,

156.25 MHz

φN

100 Hz

1 kHz

—

–86

–109

–116

–123

–136

3.0

—

dBc/Hz

ps

10 kHz

100 kHz

1 MHz

Additive RMS

Jitter Due to

JPSR

SPR

10 kHz sinusoidal noise

100 kHz sinusoidal noise

500 kHz sinusoidal noise

1 MHz sinusoidal noise

3.5

ps

External Power

3

Supply Noise

3.5

ps

3.5

ps

Spurious

LVPECL output, 156.25 MHz,

offset > 10 kHz

–75

dBc

Notes:

1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,

212.5, 250 MHz.

2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 and 250 MHz.

3. 156.25 MHz. Increase in jitter on output clock due to sinewave noise added to VDD (2.5/3.3 V = 100 mVPP).

6

Rev. 1.2

Si512/513

Table 5. Output Clock Jitter and Phase Noise (LVDS)

V_DD= 1.8 V ±5%, 2.5 or 3.3 V ±10%, T_A= –40 to +85 ^oC; Output Format = LVDS

Symbol

Test Condition

Min

Typ

Max

Unit

Parameter

1

Period Jitter

(RMS)

JPRMS

10k samples

—

2.1

ps

1

Period Jitter

(Pk-Pk)

JPPKPK

φJ

10k samples

—

18

ps

Phase Jitter

(RMS)

1.875 MHz to 20 MHz integration

0.25

0.55

2

bandwidth (brickwall)

12 kHz to 20 MHz integration band-

—

0.8

1.0

ps

2

width (brickwall)

Phase Noise,

156.25 MHz

φN

100 Hz

1 kHz

—

–86

–109

–116

–123

–136

–75

—

dBc/Hz

dBc

10 kHz

100 kHz

1 MHz

Spurious

SPR

LVPECL output, 156.25 MHz,

offset>10 kHz

Notes:

1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,

212.5, 250 MHz.

2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 and 250 MHz.

Rev. 1.2

7

Si512/513

Table 6. Output Clock Jitter and Phase Noise (HCSL)

V_DD= 1.8 V ±5%, 2.5 or 3.3 V ±10%, T_A= –40 to +85 ^oC; Output Format = HCSL

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

*

Period Jitter

(RMS)

JPRMS

10k samples

—

1.2

ps

*

Period Jitter

(Pk-Pk)

JPPKPK

φJ

10k samples

—

0.25

0.8

11

0.30

1.0

ps

Phase Jitter

(RMS)

1.875 MHz to 20 MHz integration

*

bandwidth (brickwall)

12 kHz to 20 MHz integration band-

*

width (brickwall)

Phase Noise,

156.25 MHz

φN

100 Hz

1 kHz

—

–90

–112

–120

–127

–140

–75

—

dBc/Hz

dBc

10 kHz

100 kHz

1 MHz

Spurious

SPR

LVPECL output, 156.25 MHz,

offset>10 kHz

*Note: Applies to an output frequency of 100 MHz.

Table 7. Output Clock Jitter and Phase Noise (CMOS, Dual CMOS)

V_DD= 1.8 V ±5%, 2.5 or 3.3 V ±10%, T_A= –40 to +85 ^oC; Output Format = CMOS, Dual CMOS

Parameter

Phase Jitter

Symbol

Test Condition

Min

Typ

Max

Unit

φJ

1.875 MHz to 20 MHz integration

—

0.25

0.35

ps

2

(RMS)

bandwidth (brickwall)

12 kHz to 20 MHz integration band-

—

0.8

1.0

ps

2

width (brickwall)

Phase Noise,

156.25 MHz

φN

100 Hz

1 kHz

—

–86

–108

–115

–123

–136

–75

—

dBc/Hz

dBc

10 kHz

100 kHz

1 MHz

Spurious

SPR

LVPECL output, 156.25 MHz,

offset>10 kHz

Notes:

1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,

212.5 MHz.

2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 MHz.

8

Rev. 1.2

Si512/513

Table 8. Environmental Compliance and Package Information

Parameter

Conditions/Test Method

MIL-STD-883, Method 2002

MIL-STD-883, Method 2007

MIL-STD-883, Method 2003

MIL-STD-883, Method 1014

MIL-STD-883, Method 2036

Gold over Nickel

Mechanical Shock

Mechanical Vibration

Solderability

Gross and Fine Leak

Resistance to Solder Heat

Contact Pads

Table 9. Thermal Characteristics

Parameter

Symbol

Test Condition

Still air

Value

110

Unit

°C/W

CLCC, Thermal Resistance Junction to Ambient



JA

2.5x3.2mm, Thermal Resistance Junction to Ambient



Still air

164

JA

Table 10. Absolute Maximum Ratings¹

Parameter

Symbol

Rating

Units

o

T

85

C

Maximum Operating Temperature

Storage Temperature

AMAX

o

T

–55 to +125

–0.5 to +3.8

C

S

V

Supply Voltage

DD

V

–0.5 to V + 0.3

Input Voltage (any input pin)

ESD Sensitivity (HBM, per JESD22-A114)

I

DD

HBM

2

kV

o

2

T

260

C

Soldering Temperature (Pb-free profile)

PEAK

2

T

20–40

sec

Soldering Temperature Time at T

(Pb-free profile)

P

PEAK

Notes:

1. Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation or

specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended

periods may affect device reliability.

2. The device is compliant with JEDEC J-STD-020E.

Rev. 1.2

9

Si512/513

2. Solder Reflow and Rework Requirements for 2.5x3.2 mm Packages

Reflow of Silicon Labs' components should be done in a manner consistent with the IPC/JEDEC J-STD-20E

standard. The temperature of the package is not to exceed the classification Temperature provided in the standard.

The part should not be within -5°C of the classification or peak reflow temperature (T

) for longer than 30

PEAK

seconds. Key to maintaining the integrity of the component is providing uniform heating and cooling of the part

during reflow and rework. Uniform heating is achieved through having a preheat soak and controlling the

temperature ramps in the process. J-STD-20E provides minimum and maximum temperatures and times for the

preheat/Soak step that need to be followed, even for rework. The entire assembly area should be heated during

rework. Hot air should be flowed from both the bottom of the board and the top of the component. Heating from the

top only will cause un-even heating of component and can lead to part integrity issues. Temperature Ramp-up rate

are not to exceed 3°C/second. Temperature ramp-down rates from peak to final temperature are not to exceed

6°C/second. Time from 25°C to peak temperature is not to exceed 8 min for Pb-free solders.

10

Rev. 1.2

Si512/513

3. Pin Descriptions

V_DD

1

2

3

6

5

4

V_DD

1

2

3

6

5

4

FS

OE

1

2

3

6

5

4

FS

OE

FS

V_DD

1

2

3

6

5

4

OE

FS

NC

CLK–

CLK+

CLK–

CLK+

GND

CLK

GND

CLK

GND

Si512 CMOS

Si513 CMOS

Si513 LVDS/LVPECL/

HCSL/Dual CMOS*

Si512 LVDS/LVPECL/

HCSL/ Dual CMOS*

*Note: Supports integrated 1:2 CMOS buffer. See section 2.1 “3.1. Dual CMOS Buffer” and section 3 “4. Ordering Information”.

Table 11. Si512 Pin Descriptions (CMOS, OE Pin 2)

Name

CMOS Function

1

FS

Frequency Selected.

0 = First frequency selected.

1 = Second frequency selected.

2

OE

Output Enable. Internal pull-up for OE active high. Pull-

down for OE active low. See ordering information.

3

4

5

6

GND

CLK

NC

Electrical and Case Ground.

Clock Output.

No connect. Make no external connection to this pin.

Power Supply Voltage.

V

DD

Table 12. Si513 Pin Descriptions (CMOS, OE Pin 1)

Name

CMOS Function

1

OE

Output Enable. Internal pull-up for OE active high. Pull-

down for OE active low. See ordering information.

2

FS

Frequency Selected.

0 = First frequency selected.

1 = Second frequency selected.

3

4

5

6

GND

CLK

NC

Electrical and Case Ground.

Clock Output.

No connect. Make no external connection to this pin.

Power Supply Voltage.

V

DD

Table 13. Si512 Pin Descriptions (OE Pin 2)

Name

LVPECL/LVDS/HCSL/Dual CMOS Function

1

FS

Frequency Selected.

0 = First frequency selected.

1 = Second frequency selected.

2

OE

Output Enable. Internal pull-up for OE active high. Pull-

down for OE active low. See ordering information.

3

4

5

6

GND

CLK+

CLK–

Electrical and Case Ground.

Clock Output.

Complementary Clock Output.

Power Supply Voltage.

V

DD

Rev. 1.2

11

Si512/513

Table 14. Si513 Pin Descriptions (OE Pin 1)

Name

LVPECL/LVDS/HCSL/Dual CMOS Function

1

OE

FS

Output Enable. Internal pull-up for OE active high. Pull-

down for OE active low. See ordering information.

2

Frequency Selected.

0 = First frequency selected.

1 = Second frequency selected.

3

4

5

6

GND

CLK+

CLK–

Electrical and Case Ground.

Clock Output.

Complementary Clock Output.

Power Supply Voltage.

V

DD

3.1. Dual CMOS Buffer

Dual CMOS output format ordering options support either complementary or in-phase output signals. This feature

enables replacement of multiple XOs with a single Si512/13 device.

~

Complementary

Outputs

~

In-Phase

Outputs

Figure 1. Integrated 1:2 CMOS Buffer Supports Complementary or In-Phase Outputs

12

Rev. 1.2

Si512/513

4. Ordering Information

The Si512/513 supports a wide variety of options including frequency, stability, output format, and V . Specific

DD

device configurations are programmed into the Si512/513 at time of shipment. Configurations can be specified

using the Part Number Configuration chart below. Silicon Labs provides a web browser-based part number

configuration utility to simplify this process. To access this tool refer to www.silabs.com/oscillators and click

“Customize” in the product table. The Si512/513 XO series is supplied in industry-standard, RoHS compliant, lead-

free, 2.5 x 3.2 mm, 3.2 x 5.0 mm, and 5 x 7 mm packages. Tape and reel packaging is an ordering option.

Series

512

Output Format

CMOS

OE Pin

Package

6-pin

A = Revision: A

G = Temp Range: -40°C to 85°Cꢀ

R = Tape & Reel; Blank = &RLOꢀ7DSH

OE on pin 2

OE on pin 1

OE on pin 2

OE on pin 1

513

CMOS

6-pin

512

LVPECL, LVDS, HCSL, Dual CMOS

6-pin

513

6-pin

1^stOption Code:

Output Format

VDD

Output Format

51X X X X

XXXXXX X

AGR

A

B

C

D

E

F

3.3V

2.5V

1.8V

3.3V

2.5V

1.8V

LVPECL

LVDS

CMOS

3^rdOption Code:

FS Function and Output Enable

HCSL

LVPECL

FS Functionality

OE Polarity

OE Active High

OE Active Low

OE Active High

OE Active Low

Package Option

Dimensions

LVDS

A

C

B

D

Frequencies in ascending order

(FS = 0 selects lower frequency)

G

H

J

CMOS

A

B

&

5 x 7 mm

3.2 x 5 mm

ꢁꢂꢃꢀ[ꢀꢄꢂꢁꢀPP

HCSL

Frequencies in descending order

(FS = 0 selects higher frequency)

LVDS

K

L

CMOS

2^ndOption Code:

Frequency Stability

HCSL

6-digit Frequency Designator Code

M

N

P

Q

R

S

Dual CMOS (In-phase)

Dual CMOS (Complementary)

Dual CMOS (In-phase)

Dual CMOS (Complementary)

Dual CMOS (In-phase)

Dual CMOS (Complementary)

Code

Description

Total

Temperature

50ppm

A

B

C

100ppm

50ppm

30ppm

This 6-digit code represents a unique

combination of two frequencies. Frequencies

from 100 kHz to 250 MHz (differential) or 212.5

MHz (CMOS) are supported. For more info:

www.silabs.com/VCXOPartNumber.

xxxxxx

25ppm

20ppm

Figure 2. Part Number Convention

Example part number: 512PCA000104BAGR:

The series prefix, 512, indicates the device is a Dual CMOS XO with the OE function on pin 2. The output format

code P specifies the outputs are dual in-phase CMOS with a 2.5 V supply. The frequency stability code C indicates

a total stability of ± 30 ppm. The frequency select and output enable code A specifies that the two frequencies are

listed in ascending order, with the output frequency f0 (the lower frequency) selected when FS=0, and f1 (the

higher frequency) selected when FS = 1. The device’s output enable polarity is active High.

The six-digit code is 000104. As specified by the part number lookup utility at www.silabs.com/VCXOpartnumber,

f0 is 155.52 MHz (the lower frequency) and f1 is 156.25 MHz (the higher frequency). The package code B refers to

the 3.2 x 5 mm footprint with six pins. The last A refers to the product revision, G indicates the temperature range

o

(–40 to +85 C), and R means the device ships in tape and reel format.

Note: CMOS and Dual CMOS maximum frequency is 212.5 MHz.

Rev. 1.2

13

Si512/513

5. Package Outline Diagram, 5 x 7 mm, 6-pin

Figure 3 illustrates the package details for the 5 x 7 mm Si512/513. Table 15 lists the values for the dimensions

shown in the illustration.

Figure 3. Si512/513 Outline Diagram

Table 15. Package Diagram Dimensions (mm)

Dimension

Min

1.50

1.30

0.50

Nom

1.65

Max

1.80

1.50

0.70

A

b

1.40

c

0.60

D

5.00 BSC.

4.40

D1

e

4.30

4.50

2.54 BSC.

7.00 BSC.

6.20

E

E1

H

6.10

0.55

1.17

0.05

1.80

6.30

0.75

1.37

0.15

2.60

0.65

L

1.27

L1

p

0.10

—

R

0.70 REF.

0.15

aaa

bbb

ccc

ddd

eee

0.15

0.10

0.05

Notes:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

14

Rev. 1.2

Si512/513

6. PCB Land Pattern: 5 x 7 mm, 6-pin

Figure 4 illustrates the 5 x 7 mm PCB land pattern for the Si512/513. Table 16 lists the values for the dimensions

shown in the illustration.

Figure 4. Si512/513 PCB Land Pattern

Table 16. PCB Land Pattern Dimensions (mm)

Dimension

(mm)

4.20

2.54

1.55

1.95

C1

E

X1

Y1

Notes:

General

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.

3. This Land Pattern Design is based on the IPC-7351 guidelines.

4. All dimensions shown are at Maximum Material Condition (MMC). Least Material

Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.

Solder Mask Design

5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the

solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.

Stencil Design

6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be

used to assure good solder paste release.

7. The stencil thickness should be 0.125 mm (5 mils).

8. The ratio of stencil aperture to land pad size should be 1:1.

Card Assembly

9. A No-Clean, Type-3 solder paste is recommended.

10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification

for Small Body Components.

Rev. 1.2

15

Si512/513

7. Package Outline Diagram: 3.2 x 5.0 mm, 6-pin

Figure 5 illustrates the package details for the 3.2 x 5.0 mm Si512/513. Table 17 lists the values for the dimensions

shown in the illustration.

Figure 5. Si512/513 Outline Diagram

Table 17. Package Diagram Dimensions (mm)

Dimension

Min

Nom

Max

A

1.06

1.17

1.33

b

c

0.54

0.35

0.64

0.45

0.74

0.55

D

3.20 BSC

2.60

D1

e

2.55

2.65

1.27 BSC

5.00 BSC

4.40

E

E1

H

4.35

0.45

0.80

0.05

1.17

4.45

0.65

1.00

0.15

1.37

0.55

L

0.90

L1

p

0.10

1.27

R

0.32 REF

0.15

aaa

bbb

ccc

ddd

eee

0.15

0.10

0.05

Notes:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

16

Rev. 1.2

Si512/513

8. PCB Land Pattern: 3.2 x 5.0 mm

Figure 6 illustrates the 3.2 x 5.0 mm PCB land pattern for the Si512/513. Table 18 lists the values for the

dimensions shown in the illustration.

Figure 6. Si512/513 Recommended PCB Land Pattern

Table 18. PCB Land Pattern Dimensions (mm)

Dimension

(mm)

2.60

1.27

0.80

1.70

C1

E

X1

Y1

Notes:

General

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.

3. This Land Pattern Design is based on the IPC-7351 guidelines.

4. All dimensions shown are at Maximum Material Condition (MMC). Least Material

Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.

Solder Mask Design

5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the

solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.

Stencil Design

6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be

used to assure good solder paste release.

7. The stencil thickness should be 0.125 mm (5 mils).

8. The ratio of stencil aperture to land pad size should be 1:1.

Card Assembly

9. A No-Clean, Type-3 solder paste is recommended.

10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification

for Small Body Components.

Rev. 1.2

17

Si512/513

9. Package Outline Diagram: 2.5 x 3.2 mm, 6-pin

Figure 7 illustrates the package details for the 2.5 x 3.2 mm Si512/513. Table 19 lists the values for the dimensions

shown in the illustration.

Figure 7. Si512/513 Outline Diagram

18

Rev. 1.2

Si512/513

Table 19. Package Diagram Dimensions (mm)

Dimension

Min

Nom

—

Max

A

—

1.1

A1

A2

W

0.26 REF

0.7 REF

0.65

0.45

0.7

0.75

0.55

D

e

3.20 BSC

1.25 BSC

2.50 BSC

0.30 BSC

0.5

E

M

L

D1

E1

SE

aaa

bbb

ddd

2.5 BSC

1.65 BSC

0.825 BSC

0.1

0.2

0.08

Notes:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

Rev. 1.2

19

Si512/513

10. PCB Land Pattern: 2.5 x 3.2 mm, 6-pin

Figure 8 illustrates the 2.5 x 3.2 mm PCB land pattern for the Si512/513. Table 20 lists the values for the

dimensions shown in the illustration.

Figure 8. Si512/513 Recommended PCB Land Pattern

Table 20. PCB Land Pattern Dimensions (mm)

Dimension

(mm)

C1

1.9

E

2.50

0.70

1.05

X1

Y1

Notes:

General

3. All dimensions shown are at Maximum Material Condition (MMC). Least Material

Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.

4. This Land Pattern Design is based on the IPC-7351 guidelines.

Solder Mask Design

5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the

solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.

Stencil Design

6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be

used to assure good solder paste release.

7. The stencil thickness should be 0.125 mm (5 mils).

8. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.

Card Assembly

9. A No-Clean, Type-3 solder paste is recommended.

10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification

for Small Body Components.

20

Rev. 1.2

Si512/513

11. Top Marking

Use the part number configuration utility located at: www.silabs.com/VCXOpartnumber to cross-reference the mark

code to a specific device configuration.

11.1. Si512/513 Top Marking

2 C CC CC

T T T T T T

Y Y WW

11.2. Top Marking Explanation

Mark Method:

Laser

Line 1 Marking:

2 = Si512

2CCCCC

3 = Si513

CCCCC = Mark Code

Line 2 Marking:

Line 3 Marking:

TTTTTT = Assembly Manufacturing Code TTTTTT

Pin 1 indicator.

Circle with 0.5 mm diameter;

left-justified

YY = Year.

YYWW

WW = Work week.

Characters correspond to the year and

work week of package assembly.

Rev. 1.2

21

Si512/513

REVISION HISTORY

Revision 1.2

June, 2018

 Changed “Trays” to “Coil Tape” in Ordering Guide.

Revision 1.1

December, 2017

 Add 2.5 x 3.2 mm package.

Revision 1.0

 Updated Table 1 on page 3.

Updates to supply current typical and maximum values for CMOS, LVDS, LVPECL and HCSL.

CMOS frequency test condition corrected to 100 MHz.

Updates to OE VIH minimum and VIL maximum values.

 Updated Table 2 on page 4.

Dual CMOS nominal frequency maximum added.

Total stability footnotes clarified for 10 year aging at 40 °C.

Disable time maximum values updated.

Enable time parameter added.

 Updated Table 3 on page 5.

CMOS output rise / fall time typical and maximum values updated.

LVPECL/HCSL output rise / fall time maximum value updated.

LVPECL output swing maximum value updated.

LVDS output common mode typical and maximum values updated.

HCSL output swing maximum value updated.

Duty cycle minimum and maximum values tightened to 48/52%.

 Updated Table 4 on page 6.

Phase jitter test condition and maximum value updated.

Phase noise typical values updated.

Additive RMS jitter due to external power supply noise typical values updated.

Footnote 3 updated limiting the VDD to 2.5/3.3V

 Added Tables 5, 6, 7 for LVDS, HCSL, CMOS, and Dual CMOS operations.

 Moved Absolute Maximum Ratings table.

 Added note to Figure 2 clarifying CMOS and Dual CMOS maximum frequency.

 Updated Figure 5 outline diagram to correct pinout.

 Updated Table 17 on page 16.

 Updated “11. Top Marking” section and moved to page 21.

22

Rev. 1.2

ClockBuilder Pro

One-click access to Timing tools,

documentation, software, source

code libraries & more. Available for

Windows and iOS (CBGo only).

www.silabs.com/CBPro

Timing Portfolio

www.silabs.com/timing

SW/HW

www.silabs.com/CBPro

Quality

www.silabs.com/quality

Support and Community

community.silabs.com

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intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"

parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes

without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included

information. Silicon Labs shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted

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型号：	513FBA000576BAG
厂家：	SILICON
描述：	LVDS Output Clock Oscillator, 振荡器
文件：	总23页 (文件大小：604K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

513FBA000576BAG [SILICON]

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