515ABA170M240AAGR [SILICON]

Oscillator, 0.1MHz Min, 250MHz Max, 170.24MHz Nom;


型号：	515ABA170M240AAGR
厂家：	SILICON
描述：	Oscillator, 0.1MHz Min, 250MHz Max, 170.24MHz Nom
文件：	总22页 (文件大小：160K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Si515

VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR (VCXO)

100 kHZ TO 250 MHZ

Features



Supports any frequency from

100 kHz to 250 MHz



Optional integrated 1:2 CMOS

fanout buffer

Si5602



Low-jitter operation



3.3 and 2.5 V supply options

Industry-standard 3.2 x 5.0 mm

and 5 x 7 mm package/pinouts

Pb-free/RoHS-compliant

Short lead times: <2 weeks

AT-cut fundamental mode crystal

ensures high reliability/low aging

Ordering Information:



See page 14.



High power supply noise rejection  Selectable Kv (60, 90, 120,

1% control voltage linearity

Available CMOS, LVPECL, LVDS,

and HCSL outputs

150 ppm/V)

Pin Assignments:

See page 12.

Applications



SONET/SDH/OTN

PON

Low Jitter PLLs

xDSL



Broadcast video

Telecom

Switches/routers

FPGA/ASIC clock generation

V_DD

CLK

GND

Description

CMOS VCXO

The Si515 VCXO utilizes Silicon Laboratories' advanced PLL technology to

provide any frequency from 100 kHz to 250 MHz. Unlike a traditional VCXO where

a different crystal is required for each output frequency, the Si515 uses one fixed

crystal and Silicon Labs’ proprietary synthesizer to generate any frequency across

this range. This IC-based approach allows the crystal resonator to provide

enhanced reliability, improved mechanical robustness, and excellent stability. In

addition, this solution provides superior control voltage linearity and supply noise

rejection, improving PLL stability and simplifying low jitter PLL design in noisy

environments. The Si515 is factory-configurable for a wide variety of user

specifications, including frequency, supply voltage, output format, tuning slope and

stability. Specific configurations are factory-programmed at time of shipment,

eliminating long lead times and non-recurring engineering charges associated with

custom frequency oscillators.

V_DD

CLK–

CLK+

GND

LVPECL/LVDS/HCSL/

Dual CMOS VCXO

Functional Block Diagram

V_DD

Power Supply Filtering

Fixed

Frequency

Oscillator

Any-Frequency

0.1 to 250 MHz

Clock Synthesis

CLK+

CLK–

ADC

GND

Rev. 1.0 6/12

Si515

Rev. 1.0

Si515

TABLE OF CONTENTS

Section

Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

2.1. Dual CMOS Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

4. Package Outline Diagram: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

5. PCB Land Pattern: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

6. Package Outline Diagram: 3.2 x 5.0 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

7. PCB Land Pattern: 3.2 x 5.0 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

8. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

8.1. Si515 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

8.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Rev. 1.0

Si515

1. Electrical Specifications

Table 1. Recommended Operating Conditions

V_DD= 2.5 or 3.3 V ±10%, T_A= –40 to +85 ^oC

Parameter

Symbol

Test Condition

3.3 V option

2.5 V option

Min

2.97

2.25

—

Typ

3.3

2.5

Max

3.63

2.75

Unit

Supply Voltage

Supply Current

CMOS, 100 MHz,

single-ended

LVDS

(output enabled)

—

LVPECL

(output enabled)

HCSL

(output enabled)

Tristate

(output disabled)

OE “1” Setting

See Note

0.80 x V

—

0.20 x V

—

OE “0” Setting

—

OE Internal Pull-Up/

Pull-Down Resistor

k

Operating Temperature

–40

—

*Note: Active high and active low polarity OE options available. Active high uses internal pull-up. Active low uses internal pull-

down. See ordering information on page 13.

Rev. 1.0

Si515

Table 2. Vc Control Voltage Input

V_DD= 2.5 or 3.3 V ±10%, T_A= –40 to +85 ^oC

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Control Voltage Range

0.1 x V

0.9 x V

Control Voltage Tuning Slope

Positive slope,

ordering option

60, 90, 120, 150

ppm/V

(10 to 90% V

Kv Variation

)

Kv_var

—

±10

Control Voltage Linearity

Modulation Bandwidth

Vc Input Impedance

BSL

–5

—

±1

—

kHz

k

100

Table 3. Output Clock Frequency Characteristics

V_DD= 2.5 or 3.3 V ±10%, T_A= –40 to +85 ^oC

Parameter

Symbol

Test Condition

Min

0.1

–20

—

Typ

—

Max

Unit

MHz

ppm

Nominal Frequency

CMOS, Dual CMOS

212.5

250

LVDS/LVPECL/HCSL

—

Temperature Stability

Aging

T = –40 to +85 C

—

+20

Frequency drift over 10 year life

Ordering option

—

±8.5

Minimum Absolute Pull Range APR

±30, ±50,±80, ±100

Startup Time

Minimum V to output fre-

—

quency (F ) within specification

Disable Time

10 MHz

—

µs

F < 10 MHz

Enable Time

 10 MHz

—

F < 10 MHz

Rev. 1.0

Si515

Table 4. Output Clock Levels and Symmetry

V_DD= 2.5 or 3.3 V ±10%, T_A= –40 to +85 ^oC

Parameter

Symbol

Test Condition

Min

Typ

—

Max

Unit

CMOS Output Logic High

CMOS Output Logic Low

0.85 x V

—

0.15 x V

—

–8

–6

—

CMOS Output Logic High

Drive

3.3 V

2.5 V

—

CMOS Output Logic Low

Drive

3.3 V

—

2.5 V

—

CMOS Output Rise/Fall Time

0.1 to 125 MHz,

—

0.8

0.6

1.2

0.9

(20 to 80% V

)

C = 15 pF

T /T

0.1 to 212.5 MHz,

C = no load

LVPECL/HCSL Output

Rise/Fall Time

T /T

—

565

(20 to 80% V

)

LVDS Output Rise/Fall Time

(20 to 80% V

T /T

—

800

—

)

LVPECL Output Common

Mode

50  to V – 2 V,

–

1.4 V

—

single-ended

LVPECL Output Swing

LVDS Output Common Mode

LVDS Output Swing

50  to V – 2 V,

0.55

1.13

0.25

0.8

0.90

1.33

0.42

PPSE

single-ended

100  line-line,

1.23

0.38

= 3.3/2.5 V

Single-ended 100 

differential termination

PPSE

HCSL Output Common Mode

HCSL Output Swing

Duty Cycle

50 to ground

0.35

0.58

0.38

0.73

0.42

0.85

Single-ended

PPSE

Rev. 1.0

Si515

Table 5. Output Clock Jitter and Phase Noise (LVPECL)

V_DD= 2.5 or 3.3 V ±10%, T_A= –40 to +85 ^oC; Output Format = LVPECL

Parameter

Symbol

Test Condition

Min

—

Typ

—

Max

1.3

Unit

Period Jitter (RMS)

Period Jitter (PK-PK)

Phase Jitter (RMS)

10 k samples

PRMS

10 k samples

—

PPKPK

12 kHz to 20 MHz (brickwall)

0.9

1.3

0.5

—

φJ

1.875 MHz to 20 MHz (brickwall)

0.25

–71

–93

–113

–124

–136

4.0

Phase Noise, 155.52 MHz

100 Hz offset

1 kHz offset

dBc/Hz

—

φN

10 kHz offset

—

100 kHz offset

—

1 MHz offset

—

Additive RMS Jitter Due to

External Power Supply

100 kHz sinusoidal noise

200 kHz sinusoidal noise

500 kHz sinusoidal noise

1 MHz sinusoidal noise

—

3.5

—

Noise

PSRR

3.5

—

3.5

—

Spurious Performance

F = 156.25 MHz,

Offset > 10 kHz

SPR

—

–75

—

dBc

Notes:

1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,

212.5, 250 MHz.

2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5, 250 MHz.

3. 156.25 MHz. Increase in jitter on output clock due to spurs introduced by sinewave noise added to VDD (100 mV_PP).

Rev. 1.0

Si515

Table 6. Output Clock Jitter and Phase Noise (LVDS)

V_DD= 1.8 V ±5%, 2.5 or 3.3 V ±10%, T_A= –40 to +85 ^oC; Output Format = LVDS

Symbol

Test Condition

Min

Typ

Max

Unit

Parameter

Period Jitter

(RMS)

JPRMS

10k samples

—

2.1

Period Jitter

(Pk-Pk)

JPPKPK

10k samples

—

Phase Jitter

(RMS)

φJ

1.875 MHz to 20 MHz integration

0.25

0.55

bandwidth (brickwall)

12 kHz to 20 MHz integration

—

0.8

1.1

bandwidth (brickwall)

Phase Noise,

156.25 MHz

φN

100 Hz

1 kHz

—

–72

–93

—

dBc/Hz

dBc

10 kHz

100 kHz

1 MHz

–114

–123

–136

–75

Spurious

SPR

LVPECL output, 156.25 MHz,

offset>10 kHz

Notes:

1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,

212.5, 250 MHz.

2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 and 250 MHz.

Rev. 1.0

Si515

Table 7. Output Clock Jitter and Phase Noise (HCSL)

V_DD= 1.8 V ±5%, 2.5 or 3.3 V ±10%, T_A= –40 to +85 ^oC; Output Format = HCSL

Symbol

Test Condition

Min

Typ

Max

Unit

Parameter

Period Jitter

(RMS)

JPRMS

10k samples

—

1.2

Period Jitter

(Pk-Pk)

JPPKPK

10k samples

—

Phase Jitter

(RMS)

φJ

1.875 MHz to 20 MHz integration

0.25

0.30

bandwidth (brickwall)

12 kHz to 20 MHz integration band-

—

0.8

1.0

width (brickwall)

Phase Noise,

156.25 MHz

φN

100 Hz

1 kHz

—

–75

–98

—

dBc/Hz

dBc

10 kHz

100 kHz

1 MHz

–117

–127

–136

–75

Spurious

SPR

LVPECL output, 156.25 MHz,

offset>10 kHz

*Note: Applies to an output frequency of 100 MHz.

Rev. 1.0

Si515

Table 8. Output Clock Jitter and Phase Noise (CMOS, Dual CMOS)

V_DD= 1.8 V ±5%, 2.5 or 3.3 V ±10%, T_A= –40 to +85 ^oC; Output Format = CMOS, Dual CMOS

Symbol

Test Condition

Min

Typ

Max

Unit

Parameter

Phase Jitter

(RMS)

φJ

1.875 MHz to 20 MHz integration

—

0.25

0.35

bandwidth (brickwall)

12 kHz to 20 MHz integration

—

0.8

1.1

bandwidth (brickwall)

Phase Noise,

156.25 MHz

φN

100 Hz

1 kHz

—

–71

–93

—

dBc/Hz

dBc

10 kHz

100 kHz

1 MHz

–113

–123

–136

–75

Spurious

SPR

LVPECL output, 156.25 MHz,

offset>10 kHz

Notes:

1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,

212.5 MHz.

2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 MHz.

Table 9. Environmental Compliance and Package Information

Parameter

Conditions/Test Method

MIL-STD-883, Method 2002

MIL-STD-883, Method 2007

MIL-STD-883, Method 2003

MIL-STD-883, Method 1014

MIL-STD-883, Method 2036

MSL 1

Mechanical Shock

Mechanical Vibration

Solderability

Gross and Fine Leak

Resistance to Solder Heat

Moisture Sensitivity Level

Contact Pads

Gold over Nickel

Rev. 1.0

Si515

Table 10. Thermal Characteristics

Parameter

Symbol

Test Condition

Value

Unit

Thermal Resistance Junction to Ambient



Still air

110

°C/W

Table 11. Absolute Maximum Ratings¹

Parameter

Symbol

Rating

Unit

Maximum Operating Temperature

Storage Temperature

AMAX

–55 to +125

–0.5 to +3.8

Supply Voltage

Input Voltage (any input pin)

ESD Sensitivity (HBM, per JESD22-A114)

–0.5 to V + 0.3

HBM

Soldering Temperature (Pb-free profile)

260

PEAK

Soldering Temperature Time at T

(Pb-free profile)

20–40

sec

PEAK

Notes:

1. Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation or

specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended

periods may affect device reliability.

2. The device is compliant with JEDEC J-STD-020.

Rev. 1.0

Si515

2. Pin Descriptions

V_DD

CLK–

CLK+

GND

CLK

GND

LVPECL/LVDS/HCSL/

Dual CMOS VCXO

CMOS VCXO

Table 12. Si515 Pin Descriptions (CMOS)

Name

CMOS Function

Control Voltage Input.

Output Enable. Internal pull-up for OE active high. Pull-

down for OE active low. See ordering information.

GND

CLK

Electrical and Case Ground.

Clock Output.

No connect. Make no external connection to this pin.

Power Supply Voltage.

Table 13. Si515 Pin Descriptions (LVPECL/LVDS/HCSL/Dual CMOS)

Name

LVPECL/LVDS/HCSL/Dual CMOS Function

Control Voltage Input.

Output Enable. Internal pull-up for OE active high. Pull-

down for OE active low. See ordering information.

GND

CLK+

CLK–

Electrical and Case Ground.

Clock Output.

Complementary Clock Output.

Power Supply Voltage.

Rev. 1.0

Si515

2.1. Dual CMOS Buffer

Dual CMOS output format ordering options support either complementary or in-phase output signals. This feature

enables replacement of multiple VCXOs with a single Si515 device.

Complementary

Outputs

In-Phase

Outputs

Figure 1. Integrated 1:2 CMOS Buffer Supports Complementary or In-Phase Outputs

Rev. 1.0

Si515

3. Ordering Information

The Si515 supports a variety of options including frequency, stability, tuning slope, output format, and V . Specific

device configurations are programmed into the Si515 at time of shipment. Configurations are specified using the

Part Number Configuration chart shown below. Silicon Labs provides a web browser-based part number

configuration utility to simplify this process. Refer to www.silabs.com/VCXOPartNumber to access this tool. The

Si515 VCXO series is supplied in industry-standard, RoHS compliant, lead-free, 3.2 x 5.0 mm and 5 x 7 mm

packages. Tape and reel packaging is an ordering option.

Series

Output Format

Package

6-pin

A = Revision: A

G = Temp Range: -40°C to 85°C

R = Tape & Reel; Blank = Trays.

515

LVPECL, LVDS, HCSL,

CMOS, Dual CMOS

Single Frequency VCXO

1^stOption Code:

Output Format

VDD

Output Format

3.3V

2.5V

3.3V

2.5V

LVPECL

515 X X X XXXMXXX X AGR

LVDS

CMOS

HCSL

LVPECL

LVDS

3^rdOption Code:

CMOS

Output Enable

Package Option

Dimensions

HCSL

OE Polarity

Dual CMOS (In-phase)

Dual CMOS (Complementary)

Dual CMOS (In-phase)

Dual CMOS (Complementary)

5 x 7 mm

OE Active High

OE Active Low

3.2 x 5 mm

^nd

Option Code: Stability & APR

Frequency Code

Frequency

Minimum APR

Description

Temp

Stability

Mxxxxxx

xMxxxxx

xxMxxxx

xxxMxxx

xxxxxx

f_OUT< 1 MHz

1 MHz ꢀ f_OUT< 10 MHz

3.3 V

±100ppm

±80ppm

±50ppm

±30ppm

2.5 V

±20ppm

±150ppm/V

±120ppm/V

±±0ppm/V

±60ppm/V

±80ppm

±50ppm

±30ppm

10 MHz ꢀ f_OUT< 100 MHz

100 MHz ꢀ f_OUT< 250 MHz

Code if frequency requires >6 digit resolution

Not Supported

Figure 2. Part Number Convention

Example ordering part number: 515BBB212M500BAGR.

The series prefix, 515, indicates the device is a single frequency VCXO.

The 1st option code B specifies the output format is LVDS and powered from a 3.3 V supply. The stability and APR

code B indicates a temperature stability of ±20 ppm with a tuning slope of ±120 ppm/V. The 3rd option code B

specifies the OE pin is active low.

The frequency code is 212M500. Per this convention, and as indicated by the part number lookup utility at

www.silabs.com/VCXOpartnumber, the output frequency is 212.5 MHz. The package code B refers to the

3.2 x 5 mm footprint with six pins. The last A refers to the product revision, G indicates the temperature range (–40

to +85 °C), and R specifies the device ships in tape and reel format.

Note: CMOS and Dual CMOS maximum frequency is 212.5 MHz.

Rev. 1.0

Si515

4. Package Outline Diagram: 5 x 7 mm, 6-pin

Figure 3 illustrates the package details for the Si515. Table 14 lists the values for the dimensions shown in the

illustration.

Figure 3. Si515 Outline Diagram

Table 14. Package Diagram Dimensions (mm)

Dimension

Min

1.50

1.30

0.50

Nom

1.65

Max

1.80

1.50

0.70

1.40

0.60

5.00 BSC.

4.40

4.30

4.50

2.54 BSC.

7.00 BSC.

6.20

6.10

0.55

1.17

0.05

1.80

6.30

0.75

1.37

0.15

2.60

0.65

1.27

0.10

—

0.7 REF.

0.15

aaa

bbb

ccc

ddd

eee

0.15

0.10

0.05

Notes:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

Rev. 1.0

Si515

5. PCB Land Pattern: 5 x 7 mm, 6-pin

Figure 4 illustrates the 5 x 7 mm PCB land pattern for the Si515. Table 15 lists the values for the dimensions shown

in the illustration.

Figure 4. Si515 PCB Land Pattern

Table 15. PCB Land Pattern Dimensions (mm)

Dimension

(mm)

4.20

5.08

1.55

1.95

Notes:

General

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.

3. This Land Pattern Design is based on the IPC-7351 guidelines.

4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition

(LMC) is calculated based on a Fabrication Allowance of 0.05 mm.

Solder Mask Design

5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder

mask and the metal pad is to be 60 µm minimum, all the way around the pad.

Stencil Design

6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used

to assure good solder paste release.

7. The stencil thickness should be 0.125 mm (5 mils).

8. The ratio of stencil aperture to land pad size should be 1:1.

Card Assembly

9. A No-Clean, Type-3 solder paste is recommended.

10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for

Small Body Components.

Rev. 1.0

Si515

6. Package Outline Diagram: 3.2 x 5.0 mm, 6-pin

Figure 5 illustrates the package details for the 3.2 x 5 mm Si510/511. Table 16 lists the values for the dimensions

shown in the illustration.

Figure 5. Si510/511 Outline Diagram

Table 16. Package Diagram Dimensions (mm)

Dimension

Min

1.06

0.54

0.35

Nom

1.17

Max

1.28

0.74

0.55

0.64

0.45

3.20 BSC

2.60

2.55

2.65

1.27 BSC

5.00 BSC

4.40

4.35

0.45

0.90

0.05

1.17

4.45

0.65

1.10

0.15

1.37

0.55

1.00

0.10

1.27

0.32 REF

0.15

aaa

bbb

ccc

ddd

eee

0.15

0.10

0.05

Notes:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

Rev. 1.0

Si515

7. PCB Land Pattern: 3.2 x 5.0 mm, 6-pin

Figure 6 illustrates the recommended 3.2 x 5 mm PCB land pattern for the Si515. Table 17 lists the values for the

dimensions shown in the illustration.

Figure 6. Si515 PCB Land Pattern

Table 17. PCB Land Pattern Dimensions (mm)

Dimension

(mm)

2.60

1.27

0.80

1.70

Notes:

General

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.

3. This Land Pattern Design is based on the IPC-7351 guidelines.

4. All dimensions shown are at Maximum Material Condition (MMC). Least Material

Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.

Solder Mask Design

5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the

solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.

Stencil Design

6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be

used to assure good solder paste release.

7. The stencil thickness should be 0.125 mm (5 mils).

8. The ratio of stencil aperture to land pad size should be 1:1.

Card Assembly

9. A No-Clean, Type-3 solder paste is recommended.

10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification

for Small Body Components.

Rev. 1.0

Si515

8. Top Marking

Use the part number configuration utility located at: www.silabs.com/VCXOPartNumber to cross-reference the

mark code to a specific device configuration.

8.1. Si515 Top Marking

5 C CC CC

T T T T T T

Y Y WW

8.2. Top Marking Explanation

Mark Method:

Laser

Line 1 Marking:

5 = Si515

5CCCCC

CCCCC = Mark Code

Line 2 Marking:

Line 3 Marking:

TTTTTT = Assembly Manufacturing Code TTTTTT

Pin 1 indicator.

Circle with 0.5 mm diameter;

left-justified

YY = Year.

YYWW

WW = Work week.

Characters correspond to the year and

work week of package assembly.

Rev. 1.0

Si515

DOCUMENT CHANGE LIST

Revision 0.9 to Revision 1.0

 Updated Table 1 on page 4.

Updates to supply current typical and maximum values

for CMOS, LVDS, LVPECL and HCSL.

CMOS frequency test condition corrected to 100 MHz.

Updates to OE VIH minimum and VIL maximum values.

 Updated Table 3 on page 5.

Dual CMOS nominal frequency maximum added.

Disable time maximum values updated.

Enable time parameter added.

 Updated Table 4 on page 6.

CMOS output rise / fall time typical and maximum

values updated.

LVPECL/HCSL output rise / fall time maximum value

updated.

LVPECL output swing maximum value updated.

LVDS output common mode typical and maximum

values updated.

HCSL output swing maximum value updated.

Duty cycle minimum and maximum values tightened to

48/52%.

 Updated Table 5 on page 7.

Phase jitter test condition, typical and maximum value

updated.

Phase noise typical values updated.

Additive RMS jitter due to external power supply noise

typical values updated.

 Added Tables 6, 7, 8 for LVDS, HCSL, CMOS and

Dual CMOS operations.

 Added note to Figure 2 clarifying CMOS and Dual

CMOS maximum frequency.

 Updated Figure 5 outline diagram to correct pinout.

 Updated “8. Top Marking” section and moved to

page 19.

Rev. 1.0

Si515

NOTES:

Rev. 1.0

Si515

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The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.

Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from

the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features

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Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.

Rev. 1.0

515ABA170M240AAGR [SILICON]

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