532AA622M080BGR [SILICON]
DUAL FREQUENCY XO (10 MHZ TO 1.4 GHZ); 双频XO （ 10 MHz至1.4 GHz）的
| 型号： | 532AA622M080BGR |
| 厂家： | 
SILICON |
| 描述： | DUAL FREQUENCY XO (10 MHZ TO 1.4 GHZ) |
| 文件： | 总10页 (文件大小：174K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si532
PRELIMINARY DATA SHEET
DUAL FREQUENCY XO (10 MHZ TO 1.4 GHZ)
Features
ꢀ
Available with any-rate output
ꢀ
3x better frequency stability than
SAW based oscillators
frequencies from 10 to 945 MHz and
selected frequencies to 1.4 GHz
Two selectable output frequencies
Industry standard 7x5 mm package
Available CMOS, LVPECL, LVDS &
CML outputs
Si5602
®
ꢀ
ꢀ
3rd generation DSPLL with
ꢀ
ꢀ
ꢀ
superior jitter performance
Internal fixed crystal frequency
ensures high reliability and low
aging
ꢀ
3.3, 2.5, and 1.8 V supply options
ꢀ
Lead-free/RoHS-compliant
Applications
Ordering Information:
ꢀ
ꢀ
ꢀ
SONET/SDH
xDSL
10 GbE LAN/WAN
ꢀ
ꢀ
ꢀ
Low jitter clock generation
Optical modules
Test and measurement
See page 7.
Description
The Si532 dual frequency XO utilizes Silicon Laboratories advanced
®
DSPLL circuitry to provide a very low jitter clock for all output frequencies.
The Si532 is available with any-rate output frequency from 10 to 945 MHz
and selected frequencies to 1400 MHz. Unlike traditional XOs where a
different crystal is required for each output frequency, the Si532 uses one
fixed crystal frequency to provide a wide range of output frequencies. This
IC based approach allows the crystal resonator to be optimized for superior
frequency, stability, and reliability. In addition, DSPLL clock synthesis
provides superior supply noise rejection, simplifying the task of generating
low jitter clocks in noisy environments often found in communication
systems. The Si532 IC based XO is factory configurable for a wide variety of
user specifications including frequency, supply voltage, and output format.
Specific configurations are factory programmed into the Si532 at the time of
shipment, thereby eliminating the long lead times associated with custom
oscillators.
Functional Block Diagram
VDD
CLK–
CLK+
Any-rate
10–1400 MHz
DSPLL®
Fixed
Frequency XO
Clock
Synthesis
OE
FS
GND
Preliminary Rev. 0.3 12/05
Copyright © 2005 by Silicon Laboratories
Si532
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si532
1. Electrical Specifications
Table 1. Si532 Electrical Specifications
Parameter
Min
Typ
Max
Units
Notes
Frequency
Nominal Frequency
LVDS/CML/LVPECL
CMOS
Specified at time of order by P/N.
Also available in bands from
970 to 1134 MHz and 1213 to
1417 MHz.
10
10
—
—
945
160
MHz
Initial Accuracy
–1.5
—
1.5
Measured at +25 °C at time of ship-
ping
ppm
ppm
ppm
Selectable option by P/N. See
Section 4. "Ordering Information" on
page 7.
–20
–50
—
—
+20
+50
Temperature Stability
Aging
—
—
±10
Frequency drift over projected 15 year
life
Outputs
LVPECL:
LVDS:
CMOS:
V
– 1.3 V (differential)
DD
45
—
55
%
Symmetry
1.25 V (differential)
/2
V
DD
RMS Jitter for F
> 500 MHz
F
> 500 MHz
OUT
OUT
12 kHz to 20 MHz
50 kHz to 80 MHz
—
—
0.27
0.30
—
—
ps
Differential Modes:
LVPECL/LVDS/CML
RMS Jitter for F
500 MHz
of 125 to
125 < F
Differential Modes:
LVPECL/LVDS/CML
< 500 MHz
OUT
OUT
12 kHz to 20 MHz
—
0.5
—
ps
ps
Period Jitter for F
Peak-to-Peak
RMS
<160 MHz
Any output
N = 1000 cycles
OUT
—
—
5
1
—
—
LVPECL Output Option
V
DD – 1.42
1.1
0.50
—
—
—
VDD – 1.25
1.9
V
VPP
VPP
mid-level
swing (diff)
50 Ω to VDD – 2.0 V
0.93
swing (single-ended)
LVDS Output Option
mid-level
swing (diff)
1.125
0.32
1.2
0.40
1.275
0.50
V
VPP
Rterm = 100 Ω (differential)
Rterm = 100 Ω (differential)
CML Output Option
mid-level
swing
—
0.70
V
– 0.75
—
1.20
V
VPP
DD
0.95
2
Preliminary Rev. 0.3
Si532
Table 1. Si532 Electrical Specifications (Continued)
Parameter
Min
Typ
Max
Units
Notes
CMOS Output Option
0.8xVDD
—
—
—
VDD
0.4
V
CL = 15 pF
V
VOL
OH
—
—
—
1
350
—
ps
ns
CML/LVPECL/LVDS at 20% / 80%
CMOS with CL = 15 pF
Rise/Fall time
Inputs
Voltage (V
)
DD
3.3 V option
2.5 V option
1.8 V option
2.97
2.25
1.71
3.3
2.5
1.8
3.63
2.75
1.89
V
Optional parameter specified by P/N
Current
—
—
90
60
—
—
mA
V
Output enabled
TriState mode
Frequency Select (FS)
V
V
0.75 x V
0
—
—
V
DD
0.5
FS = “0” selects F0
FS = “1” selects F1
IH
IL
DD
DD
Output Enable
V
V
0.75 x V
—
—
—
V
V
IH
IL
DD
0.5
Table 2. Absolute Maximum Ratings
Parameter
Symbol
Rating
Units
V
Supply Voltage
V
–0.5 to +3.8
–55 to +125
DD
Storage Temperature
T
°C
S
Preliminary Rev. 0.3
3
Si532
Table 3. Environmental Conditions
Parameter
Conditions/Test Method
–40 to +85 °C
Operating Temperature
Mechanical Shock
Mechanical Vibration
Solderability
MIL-STD-883F, Method 2002.3 B
MIL-STD-883F, Method 2007.3 A
MIL-STD-883F, Method 203.8
MIL-STD-883F, Method 1014.7
MIL-STD-883F, Method 2016
Gross & Fine Leak
Resistance to Solvents
Table 4. Pinout
Pin
Symbol
Function
Frequency Select
Output Enable
Ground
1
2
3
4
FS
OE
GND
CLK+
Oscillator Output
CLK–
(N/A for CMOS)
Complementary Output
(N/C for CMOS)
5
6
V
Power Suppy Voltage
DD
4
Preliminary Rev. 0.3
Si532
2. Outline Diagram and Suggested Pad Layout
Figure 1 illustrates the package details for the Si532. Table 5 lists the values for the dimensions shown in the
illustration.
Figure 1. Si532 Outline Diagram
Table 5. Package Diagram Dimensions (mm)
Dimension
Min
1.45
1.2
Nom
1.65
Max
1.85
1.6
A
b
1.4
c
0.60 TYP.
7.00 BSC.
6.2
D
D1
e
6.10
6.30
2.54 BSC.
5.00 BSC.
4.40
E
E1
L
4.30
1.07
4.50
1.47
1.27
S
1.815 BSC.
0.7 REF.
—
R
aaa
bbb
ccc
ddd
—
—
—
—
0.15
0.15
0.10
0.10
—
—
—
Preliminary Rev. 0.3
5
Si532
3. 6-Pin PCB Land Pattern
Figure 2 illustrates the 6-pin PCB land pattern for the Si532. Table 6 lists the values for the dimensions shown in
the illustration.
Figure 2. Si530 PCB Land Pattern
Table 6. PCB Land Pattern Dimensions (mm)
Dimension
Min
Max
D2
e
5.08 REF
2.54 BSC
4.15 REF
E2
GD
GE
VD
VE
X
0.84
2.00
—
—
8.20 REF
7.30 REF
1.70 TYP
2.15 REF
Y
ZD
ZE
—
—
6.78
6.30
Notes:
1. Dimensioning and tolerancing per the ANSI Y14.5M-1994 specification.
2. Land pattern design based on IPC-7351 guidelines.
3. All dimensions shown are at maximum material condition (MMC).
4. Controlling dimension is in millimeters (mm).
6
Preliminary Rev. 0.3
Si532
4. Ordering Information
The Si532 was designed to support a variety of options including frequency, tuning slope, output format, and V
.
DD
Specific device configurations are programmed into the Si532 at time of shipment. A unique part number
associated with these options and frequencies will be assigned. The Si532 XO series is supplied in an industry-
standard, 7x5 mm package.
Part numbers for the Si532 Dual Frequency XO are determined by following configuration tables. Silicon Labs
provides a web browser-based part number configuration tool to simplify this process. Refer to www.silabs.com/
VCXO to access this tool and for further ordering instructions.
X
X
532
G
R
B
X X X X X X
Tape & Reel Packaging
532 XO
Product
Family
Operating Temp Range (°C)
-40 to +85°C
G
Part Revision Letter
Frequency Designator Code
Two unique frequencies can be specified within the following bands of frequencies:
1st Option Code
10 to 945 MHz
970 to 1134 MHz
1213 to 1417 MHz
VDD Output Format
3.3 LVPECL
3.3 LVDS
3.3 CMOS
3.3 CML
2.5 LVPECL
2.5 LVDS
2.5 CMOS
2.5 CML
A
B
C
D
E
F
G
H
J
A six digit code will be assigned by SiLabs for the specified combination of frequencies.
Note:
Six digit codes > 000100 refer to dual XOs programmed with the lower frequency value
selected when FS = 0, and the higher value when FS = 1; six digit codes < 000100 refer
to dual XOs programmed with the higher frequency value selected when FS = 0, and the
lower value when FS = 1.
2nd Option Code
1.8 CMOS
1.8 CML
K
Temp Stability (ppm, max, ±)
Note:
CMOS available to 160 MHz.
A
B
50
20
Figure 3. Part Number Convention
Preliminary Rev. 0.3
7
Si532
DOCUMENT CHANGE LIST
Revision 0.2 to Revision 0.3
ꢀ Updated the “Features” section.
ꢀ Updated Table 1, “Si532 Electrical Specifications,”
on page 2.
ꢁ Updated LVDS, CML, and CMOS electric specifications.
ꢀ Updated Figure 1, “Si532 Outline Diagram,” on page
5.
ꢀ Updated 4. "Ordering Information" on page 7.
ꢁ Updated Figure 3, “Part Number Convention,” on page
7.
8
Preliminary Rev. 0.3
Si532
NOTES:
Preliminary Rev. 0.3
9
Si532
CONTACT INFORMATION
Silicon Laboratories Inc.
4635 Boston Lane
Austin, TX 78735
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email:VCXOinfo@silabs.com
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-
plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
10
Preliminary Rev. 0.3
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