536AB125M000DG [SILICON]

LVPECL Output Clock Oscillator, 125MHz Nom,;


型号：	536AB125M000DG
厂家：	SILICON
描述：	LVPECL Output Clock Oscillator, 125MHz Nom, 机械输出元件振荡器
文件：	总12页 (文件大小：479K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Si535/536

REVISION D

ULTRA LOW JITTER CRYSTAL OSCILLATOR (XO)

Features

Si5602



Available with select frequencies from  Available with LVPECL and

100 MHz to 312.5 MHz

LVDS outputs



3.3 and 2.5 V supply options

Industry-standard 5 x 7 mm

package and pinout

generation DSPLL with superior

jitter performance and high-power

supply noise rejection



Pb-free/RoHS-compliant



3x better frequency stability than

SAW-based oscillators

Ordering Information:

Applications

See page 7.



10/40/100G data centers

10G Ethernet switches/routers

Fibre channel/SAS/storage



Enterprise servers

Networking

Telecommunications

Pin Assignments:

See page 6.

Description

The Si535/536 XO utilizes Silicon Labs’ advanced DSPLL circuitry to

provide an ultra low jitter clock at high-speed differential frequencies. Unlike a

traditional XO, where a different crystal is required for each output frequency,

the Si535/536 uses one fixed crystal to provide a wide range of output

frequencies. This IC based approach allows the crystal resonator to provide

exceptional frequency stability and reliability. In addition, DSPLL clock

synthesis provides superior supply noise rejection, simplifying the task of

generating low jitter clocks in noisy environments typically found in

communication systems. The Si535/536 IC based XO is factory programmed

at time of shipment, thereby eliminating long lead times associated with

custom oscillators.

(Top View)

V_DD

CLK–

CLK+

GND

Si535

Functional Block Diagram

V_DD

CLK– CLK+

CLK–

CLK+

GND

Si536

Fixed

Frequency

100–312.5 MHz

DSPLL^®

Clock Synthesis

GND

Rev. 1.2 5/16

Si535/536

1. Electrical Specifications

Table 1. Recommended Operating Conditions

Parameter

Symbol

Test Condition

3.3 V option

2.5 V option

Min

2.97

2.25

Typ

3.3

2.5

Max

3.63

2.75

Unit

Supply Voltage

Supply Current

Output enabled

LVPECL

—

111

121

LVDS

Tristate mode

—

0.75 x V

—

Output Enable (OE)²

—

0.5

Operating Temperature Range

–40

°C

Notes:

1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 7 for further details.

2. OE pin includes a 17 k pullup resistor to V_DD

Table 2. CLK± Output Frequency Characteristics

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Nominal Frequency¹

Initial Accuracy

LVPECL/LVDS

100

—

312.5

MHz

Measured at +25 °C at time of

shipping

f_i

—

±1.5

—

ppm

Temperature Stability^1,2

Aging

–7

–20

—

+20

ppm

Frequency drift over first year

—

±3

f_a

Frequency drift over 20 year

life

±10

Total Stability²

Temp stability = ±20 ppm

Temp stability = ±7 ppm

T_A= –40°C — +85°C

—

±31.5

ppm

Powerup Time³

t_OSC

Notes:

1. See Section 3. "Ordering Information" on page 7 for the list of available frequencies.

2. Selectable parameter specified by part number.

3. Time from powerup or tristate mode to f_O.

Rev. 1.2

Si535/536

Table 3. CLK± Output Levels and Symmetry

Parameter

Symbol

Test Condition

Mid-level

Min

V_DD– 1.42

1.1

Typ

—

Max

V_DD– 1.25

1.9

Unit

LVPECL Output Option¹

V_OD

V_SE

Swing (diff)

V_PP

—

Swing (Single-ended)

Mid-level

0.55

—

0.95

LVDS Output Option²

1.125

1.20

1.275

Swing (diff)

V_OD

0.5

—

0.7

—

0.9

350

V_PP

Rise/Fall time (20/80%)

Symmetry (duty cycle)

t_{R, F}

SYM

Differential

—

Notes:

1. 50  to V_DD– 2.0 V.

2. R_term= 100  (differential).

Rev. 1.2

Si535/536

Table 4. CLK± Output Phase Jitter

Parameter

Symbol

Test Condition

Min

—

Typ

0.19

0.25

Max

0.35

0.40

Unit

LVPECL/LVDS Phase Jitter*

(RMS)

_J

10 kHz to 1 MHz (data center)

12 kHz to 20 MHz brickwall

—

*Note: Applies to output frequencies: 156.25 MHz.

Table 5. CLK± Output Period Jitter

Parameter

Symbol

Test Condition

RMS

Min

—

Typ

Max

—

Unit

LVPECL/LVDS Period Jitter*

PER

Peak-to-Peak

—

*Note: N = 1000 cycles.

Figure 1. Si535/536 Typical Phase Noise at 156.25 MHz

Rev. 1.2

Si535/536

Table 6. Environmental Compliance

The Si535/536 meets the following qualification test requirements.

Parameter

Mechanical Shock

Conditions/Test Method

MIL-STD-883, Method 2002

MIL-STD-883, Method 2007

MIL-STD-883, Method 2003

MIL-STD-883, Method 1014

MIL-STD-883, Method 2036

J-STD-020, MSL1

Mechanical Vibration

Solderability

Gross & Fine Leak

Resistance to Solder Heat

Moisture Sensitivity Level

Contact Pads

Gold over Nickel

Table 7. Thermal Characteristics

(Typical values TA = 25 ºC, V_DD= 3.3 V)

Parameter

Symbol

Test Condition

Still Air

Min

—

Typ

84.6

38.8

—

Max

—

Unit

°C/W

°C

Thermal Resistance Junction to Ambient

Thermal Resistance Junction to Case

Ambient Temperature



Still Air

—

–40

—

Junction Temperature

—

125

°C

Table 8. Absolute Maximum Ratings¹

Parameter

Maximum Operating Temperature

Supply Voltage, 2.5/3.3 V Option

Input Voltage (any input pin)

Symbol

Rating

–0.5 to +3.8

Unit

°C

AMAX

–0.5 to V + 0.3

Storage Temperature

–55 to +125

2500

°C

ESD Sensitivity (HBM, per JESD22-A114)

Soldering Temperature (Pb-free profile)²

ESD

260

°C

PEAK

Soldering Temperature Time @ T_PEAK(Pb-free profile)²

20–40

seconds

Notes:

1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional

operation or specification compliance is not implied at these conditions. Exposure to maximum rating conditions for

extended periods may affect device reliability.

2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download at

www.silabs.com/VCXO for further information, including soldering profiles.

Rev. 1.2

Si535/536

2. Pin Descriptions

(Top View)

V_DD

CLK–

CLK+

CLK–

CLK+

GND

Si536

Si535

Table 9. Pinout for Si535 Series

Symbol

Function

No connection

Output enable

0 = clock output disabled (outputs tristated)

1 = clock output enabled

GND

CLK+

CLK–

Electrical and Case Ground

Oscillator Output

Complementary Output

Power Supply Voltage

*Note: OE includes a 17 k pullup resistor to V_DD

Table 10. Pinout for Si536 Series

Symbol

Function

Output enable

0 = clock output disabled (outputs tristated)

1 = clock output enabled

No connection

GND

No connection

Electrical and Case Ground

Oscillator Output

CLK+

CLK–

Complementary output

Power Supply Voltage

*Note: OE includes a 17 k pullup resistor to V_DD

Rev. 1.2

Si535/536

3. Ordering Information

The Si535/536 XO supports a variety of options including frequency, temperature stability, output format, and V

The Si535 and Si536 XO series are supplied in an industry-standard, RoHS compliant, 6-pad, 5 x 7 mm package.

The Si536 Series supports an alternate OE pinout (pin #1) for the LVPECL and LVDS output formats. See Tables 9

and 10 for the pinout differences between the Si535 and Si536 series.

53x

XXXMXXX

Tape & Reel Packaging

Blank = Trays

Device Output Enable

535

536

pin 2

pin 1

Operating Temp Range (°C)

-40 to +85 °C

1^stOption Code

Part Revision Letter

V_DDOutput Format Output Enable Polarity

Frequency (e.g., 156M250 is 156.250 MHz)

3.3 LVPECL

3.3 LVDS

High

Select frequencies available in the frequency range 100 to 312.5 MHz

are listed below. Frequencies requiring greater than 6 digit resolution

are assigned a six digit code.

2.5 LVPECL

2.5 LVDS

Available Frequencies Frequency Order Code

100.000 MHz

100M000

106M250

125M000

150M000

155M520

156M250

000305

000335

000338

159M375

000292

106.250 MHz

125.000 MHz

150.000 MHz

155.520 MHz

156.250 MHz

156.2578 MHz

156.2539 MHz

156.26953 MHz

159.375 MHz

161.1328 MHz

166.6286 MHz

167.3316 MHz

212.500 MHz

312.500 MHz

000172

000175

212M500

312M500

2^ndOption Code

Code Temperature Stability (ppm, max, ±) Total Stablility (ppm, max, ±)

31.5

Example P/N: 535AB156M250DGR is a 5 x 7 XO in a 6 pad package. The frequency is 156.250 MHz, with a 3.3 V supply, LVPECL output,

and Output Enable active high polarity. Temperature stability is specifed as ±20 ppm. The part is specified for –40 to +85 °C ambient

temperature range operation and is shipped in tape and reel format.

Figure 2. Part Number Convention

Rev. 1.2

Si535/536

4. Package Outline

Figure 3 illustrates the package details for the Si535/536. Table 11 lists the values for the dimensions shown in the

illustration.

Figure 3. Si535/536 Outline Diagram

Table 11. Package Diagram Dimensions (mm)

Dimension

Min

1.50

1.30

0.50

Nom

1.65

Max

1.80

1.50

0.70

1.40

0.60

5.00 BSC

4.40

4.30

4.50

2.54 BSC

7.00 BSC

6.20

6.10

0.55

1.17

1.80

6.30

0.75

1.37

2.60

0.65

1.27

—

0.70 REF

0.15

aaa

bbb

ccc

ddd

eee

0.15

0.10

0.05

Rev. 1.2

Si535/536

5. 6-Pin PCB Land Pattern

Figure 4 illustrates the 6-pin PCB land pattern for the Si535/536. Table 12 lists the values for the dimensions shown

in the illustration.

Figure 4. Si535/536 PCB Land Pattern

Table 12. PCB Land Pattern Dimensions (mm)

Dimension

Min

4.20

2.54

1.55

1.95

Notes:

General

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.

3. This Land Pattern Design is based on the IPC-7351 guidelines.

4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based

on a Fabrication Allowance of 0.05 mm.

Solder Mask Design

1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to

be 60 µm minimum, all the way around the pad.

Stencil Design

1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder

paste release.

2. The stencil thickness should be 0.125 mm (5 mils).

3. The ratio of stencil aperture to land pad size should be 1:1.

Card Assembly

1. A No-Clean, Type-3 solder paste is recommended.

2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

Rev. 1.2

Si535/536

6. Si535/Si536 Mark Specification

Figure 5 illustrates the mark specification for the Si535/Si536. Table 13 lists the line information.

Figure 5. Mark Specification

Table 13. Si53x Top Mark Description

Line

Position

Description

1–10

“SiLabs"+ Part Family Number, 53x (First 3 characters in part number where x = 5

indicates a 535 device and x = 6 indicates a 536 device).

1–10

Si535, Si536: Option1 + Option2 + Freq(7) + Temp

Si535/Si536 w/ 8-digit resolution: Option1 + Option2 + ConfigNum(6) + Temp

Trace Code

Position 1

Pin 1 orientation mark (dot)

Position 2

Product Revision (D)

Position 3–6

Position 7

Tiny Trace Code (4 alphanumeric characters per assembly release instructions)

Year (least significant year digit), to be assigned by assembly site (ex: 2013 = 3)

Calendar Work Week number (1–53), to be assigned by assembly site

“+” to indicate Pb-Free and RoHS-compliant

Position 8–9

Position 10

Rev. 1.2

Si535/536

DOCUMENT CHANGE LIST

Revision 0.2 to Revision 0.3

 Updated Table 7 on page 5.

Revision 0.3 to Revision 0.5

 Updated Note 1 in Table 2 on page 2.

 Updated Symmetry Test Condition in Table 3 on

page 3.

 Updated Table 4 on page 4.

 Updated Table 5 on page 4.

 Updated XXXMXXX text in Figure 2 on page 7.

 Updated 4. "Package Outline" on page 8.

Revision 0.5 to Revision 0.6

 Updated Figure 2 on page 7.

 Updated Land Pattern information on page 10.

Revision 0.6 to Revision 0.7

 Updated Powerup Time’s test condition in Table 2 on

page 2.

 Added new frequency option to Figure 2 on page 7.

Revision 0.7 to Revision 1.0

 Updated Table 4 Phase Jitter's test condition and

maximum values.

Revision 1.0 to Revision 1.1

 Added 100 MHz ordering option.

Revision 1.1 to Revision 1.2

May 13, 2016

 Updated Figure 2 for frequencies: 161.1328 MHz,

166.6286 MHz, 167.3316 MHz.

Rev. 1.2

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One-click access to Timing tools,

documentation, software, source

code libraries & more. Available for

Windows and iOS (CBGo only).

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www.silabs.com/quality

Support and Community

community.silabs.com

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"Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories reserves the right to

make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the

included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses

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536AB125M000DG [SILICON]

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