550DA1417M000GR [SILICON]

Oscillator;


型号：	550DA1417M000GR
厂家：	SILICON
描述：	Oscillator
文件：	总8页 (文件大小：181K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Si550

PRELIMINARY DATA SHEET

VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR (VCXO)

(10 MHZ TO 1.4 GHZ)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and selected frequencies to 1.4 GHz

Industry-standard 7x5 mm package

Available CMOS, LVPECL, & CML

outputs

3rd generation DSPLL with

superior jitter performance

Internal fixed crystal frequency

ensures high reliability and low

aging

Si5602

Lead-free/RoHS-compliant

3x better frequency stability than

SAW based oscillators

Applications

Ordering Information:

SONET / SDH

xDSL

10 GbE LAN / WAN

Low-jitter clock generation

Optical modules

Clock and data recovery

See page 7.

Description

The Si550 VCXO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low-jitter clock at high frequencies. The Si550 is available with

any-rate output frequency from 10 to 945 MHz and selected frequencies to

1400 MHz. Unlike a traditional VCXO, the crystal frequency inside the Si550

is fixed for a wide range of output frequencies. The control voltage is

digitized and used as a numerical input to the DSPLL clock synthesis

engine. This IC-based approach eliminates the varactor and its associated

noise and non-linear performance drawbacks, allowing the crystal resonator

to be optimized for superior frequency stability, reliability, and mechanical

integrity. In addition, DSPLL clock synthesis provides superior supply noise

rejection, simplifying the task of generating low-jitter clocks in noisy

environments typically found in communication systems. The Si550 IC-

based VCXO is factory configurable for a wide variety of user specifications

including frequency, supply voltage, output, and tuning slope. Specific

configurations are factory programmed into the Si550 at time of shipment,

thereby eliminating the long lead times associated with custom oscillators.

Functional Block Diagram

CLK- CLK+

V_DD

Any-rate

10-1400 MHz

DSPLL™

Clock

Fixed

Frequency

Synthesis

ADC

GND

Preliminary Rev. 0.2 8/05

Si550

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

Si550

1. Electrical Specifications

Table 1. Si550 Electrical Specifications

Parameter

Min

Typ

Frequency

Max

Units

Notes

Nominal Frequency

Specified at time of order by

P/N. Also available in frequencies

from 970 to 1134 MHz and 1213 to

1417 MHz.

—

945

160

LVDS/CML/LVPECL

CMOS

MHz

Initial Accuracy

–1.5

—

+1.5

Measured at +25 °C at time of ship-

ppm

ping and V = V /2.

Temperature Stability

–20

–50

–100

—

+20

+50

+100

Selectable option by P/N. See

Section 4. "Ordering Information" on

page 7. Measured at V = V /2.

C DD

Linearity

BSL

BSL determined from deviation from

best straight line fit with V ranging

–5

–10

±1

±5

+10

from 10 to 90% of V . Incremental

Incremental

slope determined with V ranging

from 10 to 90% of V

Tuning Slope (kV) from 10 to 90%

—

180

—

Positive slope; selectable option by

part number. See Section 4. "Order-

ing Information" on page 7.

of V

ppm/V

Modulation Bandwidth

—

500

—

kHz

kΩ

—

V Input Impedance

Absolute Pull Range (APR)

Aging

See Notes

See Section 4. "Ordering Informa-

tion" on page 7.

—

±10

ppm Projected frequency drift over 15

year life.

Outputs

Measured at:

LVPECL:

LVDS:

CMOS:

– 1.3 V (differential)

—

Symmetry

1.25 V (differential)

RMS Jitter for F

> 500 MHz

OUT

Kv = 180 ppm/V

12 kHz to 20 MHz

50 kHz to 80 MHz

—

0.42

0.34

—

> 500 MHz

OUT

Differential Modes:

LVPECL/LVDS/CML

Kv = 45, 90 ppm/V

12 kHz to 20 MHz

50 kHz to 80 MHz

—

0.28

0.31

—

Preliminary Rev. 0.2

Si550

Table 1. Si550 Electrical Specifications (Continued)

Parameter

RMS Jitter for F of 125 to

Min

Typ

Max

Units

Notes

< 500 MHz

Differential Modes:

LVPECL/LVDS/CML

OUT

125 < F

OUT

500 MHz

12 kHz to 20 MHz

50 kHz to 80 MHz

—

0.61

0.52

—

Period Jitter for F

Peak-to-Peak

RMS

< 160 MHz

OUT

Any output

N = 1000 cycles

—

LVPECL Output Option

_DD– 1.42

1.1

—

V_DD– 1.25

1.9

V_PP

mid-level

swing (diff)

50 Ω to V_DD– 2.0 V

0.5

0.93

swing (single-ended)

LVDS Output Option

mid-level

swing (diff)

1.125

0.5

1.2

0.7

1.275

0.9

V_PP

R_term= 100 Ω (differential)

Rterm = 100 Ω (differential)

C_L= 15 pF

CML Output Option

mid-level

swing

—

0.35

– 0.36

—

0.5

V_PP

0.425

CMOS Output Option

0.8xV_DD

—

V_DD

0.4

V_OL

—

350

—

CML/LVPECL/LVDS

CMOS with CL = 15 pF

Rise/Fall time (20%/80%)

Inputs

Supply Voltage (V

)

2.97

2.25

1.71

3.3

2.5

1.8

3.63

2.75

1.89

3.3 V option

2.5 V option

1.8 V option

Optional parameter specified by P/N

Supply Current

Output enabled

TriState mode

—

Control Voltage (V )

Tuning range for control voltage

Output Enable

0.75xV

—

0.5

Preliminary Rev. 0.2

Si550

Table 2. Absolute Maximum Ratings

Parameter

Supply Voltage (V

Symbol

Rating

Units

Volts

°C

)

–0.5 to +3.8

–55 to +125

Storage Temperature

Table 3. Environmental Conditions

Parameter

Conditions/ Test Method

Operating Temperature

Mechanical Shock

Mechanical Vibration

Solderability

–40 to +85 °C

MIL-STD-883F, Method 2002.3 B

MIL-STD-883F, Method 2007.3 A

MIL-STD-883F, Method 203.8

MIL-STD-883F, Method 1014.7

MIL-STD-883F, Method 2016

Gross & Fine Leak

Resistance to Solvents

Table 4. Pinout

Symbol

Function

Control Voltage

Tri-state Output Enable

Disabled = logic “0”

Enable = logic “1”

GND

Electrical and Case Ground

Oscillator Output

CLK+

CLK–

(N/A for CMOS)

Complementary Output

(N/C for CMOS)

Power Supply Voltage

Preliminary Rev. 0.2

Si550

2. Outline Diagram and Suggested Pad Layout

Figure 1 illustrates the package details for the Si550. Table 5 lists the values for the dimensions shown in the

illustration.

Figure 1. Si550 Outline Diagram

Table 5. Package Diagram Dimensions (mm)

Dimension

Min

1.45

1.2

Nom

1.65

Max

1.85

1.6

1.4

0.60 TYP.

7.00 BSC.

6.2

6.10

6.30

2.54 BSC.

5.00 BSC.

4.40

4.30

1.07

4.50

1.47

1.27

1.815 BSC.

0.7 REF.

—

aaa

bbb

ccc

ddd

—

0.15

0.10

—

Preliminary Rev. 0.2

Si550

3. 6-Pin PCB Land Pattern

Figure 2 illustrates the 6-pin PCB land pattern for the Si550. Table 6 lists the values for the dimensions shown in

the illustration.

Figure 2. Si530 PCB Land Pattern

Table 6. PCB Land Pattern Dimensions (mm)

Dimension

Min

Max

5.08 REF

2.54 BSC

4.15 REF

0.84

2.00

—

8.20 REF

7.30 REF

1.70 TYP

2.15 REF

—

6.78

6.30

Notes:

1. Dimensioning and tolerancing per the ANSI Y14.5M-1994 specification.

2. Land pattern design based on IPC-7351 guidelines.

3. All dimensions shown are at maximum material condition (MMC).

4. Controlling dimension is in millimeters (mm).

Preliminary Rev. 0.2

Si550

4. Ordering Information

The Si550 was designed to support a variety of options including frequency, tuning slope, output format, and V

Specific device configurations are programmed into the Si550 at time of shipment. Configurations can be specified

using the Part Number Configuration chart shown below. The Si550 VCXO series is supplied in an industry-

standard 6-pad, 7x5 mm package.

Part numbers for the Si550 VCXO are determined by following configuration tables. Silicon Labs provides a

Windows-based part number configuration tool to simplify this process. Refer to www.silabs.com/VCXO to access

this tool and for further ordering instructions.

550

XXXMXXX

Tape & Reel Packaging

550 VCXO

Product Family

Operating Temp Range (°C)

-40 to +85 °C

Part Revision Letter

Frequency (e.g. 622M080 is 622.080 MHz)

Available frequency range is 10 to 945 MHz, 970 to 1134, and 1213

to 1417 MHz. The position of “M” shifts to denote higher or lower

frequencies

1^stOption Code

2^ndOption Code

V_DDOutput Format

3.3 LVPECL

3.3 LVDS

3.3 CMOS

3.3 CML

2.5 LVPECL

2.5 LVDS

2.5 CMOS

2.5 CML

1.8 CMOS

1.8 CML

Temperature Stability

Tuning Slope

(ppm, max, ±) (Kv,ppm/V, typ,) APR(typ)@3.3V APR(typ)@2.5V APR(typ)@1.8V

100

180

185

235

115

Note 3

165

Note 3

100

Note 3

Notes:

1. Pull range (±) = 0.5 x V_DDx tuning slope.

2. Absolute Pull Range (±APR) = Pull range – stability – lifetime aging

=0.5 x V_DDx tuning slope – stability – 10 ppm

Notes:

CMOS available to 160 MHz.

3. Combination not available.

APR is the ability of a VCXO to track a signal over the product lifetime. Thus, a VCXO

with an APR of 50 ppm is able to lock to a clock with 50 ppm stability, for a 15 year life.

Example P/N: 550AA622M080AGR is a 7x5 VCXO in a 6 pad package. The frequency is 622.080 MHz, with a 3.3 V supply and LVPECL

output. Stability is specifed as ± 100 ppm and tuning slope is 180 ppm/V. The part is specified for -40 to +85 C° operation and will be

shipped in tape and reel format.

Preliminary Rev. 0.2

Si550

CONTACT INFORMATION

Silicon Laboratories Inc.

4635 Boston Lane

Austin, TX 78735

Tel: 1+(512) 416-8500

Fax: 1+(512) 416-9669

Toll Free: 1+(877) 444-3032

Email: VCXOinfo@silabs.com

Internet: www.silabs.com

The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.

Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from

the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features

or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-

resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-

quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to

support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-

sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-

plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.

Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc.

Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.

Preliminary Rev. 0.2

550DA1417M000GR [SILICON]

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