550GC38M7853DGR [SILICON]

Oscillator, 10MHz Min, 160MHz Max, 38.7853MHz Nom;


型号：	550GC38M7853DGR
厂家：	SILICON
描述：	Oscillator, 10MHz Min, 160MHz Max, 38.7853MHz Nom
文件：	总15页 (文件大小：108K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Si550

REVISION D

VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR (VCXO)

10 MHZ TO 1.4 GHZ

Features



Available with any frequency from

10 to 945 MHz and select

frequencies to 1.4 GHz



Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Si5602



3rd generation DSPLL with

superior jitter performance (0.5 ps)

3x better temperature stability than

SAW-based oscillators



Excellent PSRR performance



Pb-free/RoHS-compliant

Ordering Information:

Applications

See page 10.



SONET/SDH

xDSL

10 GbE LAN/WAN



Low-jitter clock generation

Optical modules

Clock and data recovery



Pin Assignments:

See page 9.

Description

(Top View)

The Si550 VCXO utilizes Silicon Laboratories’ advanced DSPLL circuitry to

provide a low-jitter clock at high frequencies. The Si550 supports any

frequency from 10 to 945 MHz and select frequencies to 1417 MHz. Unlike

traditional VCXOs, where a different crystal is required for each output

frequency, the Si550 uses one fixed crystal to provide a wide range of output

frequencies. This IC-based approach allows the crystal resonator to provide

exceptional frequency stability and reliability. In addition, DSPLL clock

synthesis provides superior supply noise rejection, simplifying the task of

generating low-jitter clocks in noisy environments typically found in

communication systems. The Si550 IC-based VCXO is factory-configurable

for a wide variety of user specifications, including frequency, supply voltage,

output format, tuning slope, and temperature stability. Specific configurations

are factory programmed at time of shipment, thereby eliminating the long

lead times associated with custom oscillators.

V_C

V_DD

CLK–

CLK+

GND

Functional Block Diagram

V_DD

Any-Frequency

Fixed

Frequency

10 MHz–1.4 GHz

CLK+

CLK–

DSPLL^®

Clock Synthesis

ADC

GND

Rev. 1.1 4/13

Si550

1. Electrical Specifications

Table 1. Recommended Operating Conditions

Parameter

Symbol

Test Condition

3.3 V option

2.5 V option

1.8 V option

Min

2.97

2.25

1.71

Typ

3.3

2.5

1.8

Max

3.63

2.75

1.89

Units

Supply Voltage

Supply Current

Output enabled

LVPECL

CML

—

130

117

108

120

108

LVDS

CMOS

tristate mode

—

0.75 x V

—

Output Enable (OE)

0.5

Operating Temperature Range

–40

°C

Notes:

1. Selectable parameter specified by part number. See 3. "Ordering Information" on page 10 for further details.

2. OE pin includes a 17 k resistor to V_DD

Table 2. V_CControl Voltage Input

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

1,2,3

Control Voltage Tuning Slope

10 to 90% of V

—

135

180

356

—

ppm/V

Control Voltage Linearity

BSL

–5

–10

9.3

500

—

±1

±5

+10

10.7

—

Incremental

Modulation Bandwidth

10.0

—

kHz

k

V Input Impedance

Nominal Control Voltage

@ f

V /2

—

CNOM

Control Voltage Tuning Range

Notes:

1. Positive slope; selectable option by part number. See 3. "Ordering Information" on page 10.

2. For best jitter and phase noise performance, always choose the smallest K_Vthat meets the application’s minimum APR

requirements. See “AN266: VCXO Tuning Slope (K_V), Stability, and Absolute Pull Range (APR)” for more information.

3. K_Vvariation is ±10% of typical values.

4. BSL determined from deviation from best straight line fit with V_Cranging from 10 to 90% of V_DD. Incremental slope

determined with V_Cranging from 10 to 90% of V_DD

Rev. 1.1

Si550

Table 3. CLK± Output Frequency Characteristics

Parameter

Symbol

Test Condition

LVDS/CML/LVPECL

CMOS

Min

Typ

—

Max

Units

MHz

1,2,3

945

160

Nominal Frequency

—

1,4

Temperature Stability

T = –40 to +85 ºC

–20

–50

–100

—

+20

+50

+100

ppm

1,4

Absolute Pull Range

Aging

APR

t_OSC

±12

—

±375

±3

ppm

Frequency drift over first year.

Frequency drift over 15 year life.

—

±10

Power up Time

—

Notes:

1. See Section 3. "Ordering Information" on page 10 for further details.

2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.

3. Nominal output frequency set by V_CNOM= V_DD/2.

4. Selectable parameter specified by part number.

5. Time from power up or tristate mode to f_O.

Table 4. CLK± Output Levels and Symmetry

Parameter

Symbol

Test Condition

mid-level

Min

V_DD– 1.42

1.1

Typ

—

Max

V_DD– 1.25

1.9

Units

LVPECL Output Option

V_OD

V_SE

swing (diff)

—

V_PP

swing (single-ended)

mid-level

0.55

—

0.95

LVDS Output Option

1.125

0.5

1.20

0.7

1.275

0.9

swing (diff)

V_OD

V_O

V_PP

2.5/3.3 V option mid-level

1.8 V option mid-level

—

– 1.30

—

– 0.36

CML Output Option

2.5/3.3 V option swing (diff)

1.8 V option swing (diff)

1.10

0.35

0.8 x V_DD

—

1.50

1.90

0.50

V_DD

0.4

350

—

V_PP

V_OD

0.425

—

V_OH

V_OL

CMOS Output Option

= 32 mA

I_OL= 32 mA

—

Rise/Fall time (20/80%)

Symmetry (duty cycle)

t_{R, F}

LVPECL/LVDS/CML

—

CMOS with C = 15 pF

—

SYM

LVPECL:

LVDS:

CMOS:

– 1.3 V (diff)

1.25 V (diff)

—

Notes:

1. 50  to V_DD– 2.0 V.

2. R_term= 100  (differential).

3. C_L= 15 pF

Rev. 1.1

Si550

Table 5. CLK± Output Phase Jitter

Parameter

Symbol

Test Condition

Kv = 33 ppm/V

Min

Typ

Max

Units

1,2,3

Phase Jitter (RMS)

for F > 500 MHz

_J

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.26

—

OUT

Kv = 45 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.27

0.26

—

Kv = 90 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.32

0.26

—

Kv = 135 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.40

0.27

—

Kv = 180 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.49

0.28

—

Kv = 356 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.87

0.33

—

Notes:

1. Refer to AN255, AN256, and AN266 for further information.

2. For best jitter and phase noise performance, always choose the smallest K_Vthat meets the application’s minimum APR

requirements. See “AN266: VCXO Tuning Slope (K_V), Stability, and Absolute Pull Range (APR)” for more information.

3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply

rejection (PSR) advantage of Si55x versus SAW-based solutions.

4. Max jitter for LVPECL output with V_C=1.65V, V_DD=3.3V, 155.52 MHz.

5. Max offset frequencies: 80 MHz for F_OUT> 250 MHz, 20 MHz for 50 MHz < F_OUT<250 MHz,

2 MHz for 10 MHz < F_OUT<50 MHz.

Rev. 1.1

Si550

Table 5. CLK± Output Phase Jitter (Continued)

Parameter

Symbol

Test Condition

Kv = 33 ppm/V

Min

Typ

Max

Units

1,2,3,4,5

Phase Jitter (RMS)

for F of 125 to 500 MHz

_J

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.37

0.33

—

OUT

Kv = 45 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.37

0.33

0.4

—

Kv = 90 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.43

0.34

—

Kv = 135 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.50

0.34

—

Kv = 180 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.59

0.35

—

Kv = 356 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

1.00

0.39

—

Notes:

1. Refer to AN255, AN256, and AN266 for further information.

2. For best jitter and phase noise performance, always choose the smallest K_Vthat meets the application’s minimum APR

requirements. See “AN266: VCXO Tuning Slope (K_V), Stability, and Absolute Pull Range (APR)” for more information.

3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply

rejection (PSR) advantage of Si55x versus SAW-based solutions.

4. Max jitter for LVPECL output with V_C=1.65V, V_DD=3.3V, 155.52 MHz.

5. Max offset frequencies: 80 MHz for F_OUT> 250 MHz, 20 MHz for 50 MHz < F_OUT<250 MHz,

2 MHz for 10 MHz < F_OUT<50 MHz.

Rev. 1.1

Si550

Table 5. CLK± Output Phase Jitter (Continued)

Parameter

Symbol

Test Condition

Kv = 33 ppm/V

Min

Typ

Max

Units

1,2,5

Phase Jitter (RMS)

for F 10 to 160 MHz

_J

12 kHz to 20 MHz (OC-48)

50 kHz to 20 MHz

—

0.63

0.62

—

OUT

CMOS Output Only

Kv = 45 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 20 MHz

—

0.63

0.62

—

Kv = 90 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 20 MHz

—

0.67

0.66

—

Kv = 135 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 20 MHz

—

0.74

0.72

—

Kv = 180 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 20 MHz

—

0.83

0.8

—

Kv = 356 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 20 MHz

—

1.26

1.2

—

Notes:

1. Refer to AN255, AN256, and AN266 for further information.

2. For best jitter and phase noise performance, always choose the smallest K_Vthat meets the application’s minimum APR

requirements. See “AN266: VCXO Tuning Slope (K_V), Stability, and Absolute Pull Range (APR)” for more information.

3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply

rejection (PSR) advantage of Si55x versus SAW-based solutions.

4. Max jitter for LVPECL output with V_C=1.65V, V_DD=3.3V, 155.52 MHz.

5. Max offset frequencies: 80 MHz for F_OUT> 250 MHz, 20 MHz for 50 MHz < F_OUT<250 MHz,

2 MHz for 10 MHz < F_OUT<50 MHz.

Table 6. CLK± Output Period Jitter

Parameter

Period Jitter*

Symbol

Test Condition

RMS

Min

—

Typ

Max

—

Units

PER

Peak-to-Peak

—

*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.

Rev. 1.1

Si550

Table 7. CLK± Output Phase Noise (Typical)

Offset Frequency

74.25 MHz

90 ppm/V

LVPECL

155.52 MHz

45 ppm/V

LVPECL

491.52 MHz

45 ppm/V

LVPECL

622.08 MHz

135 ppm/V

LVPECL

Units

100 Hz

1 kHz

10 kHz

100 kHz

1 MHz

–87

–114

–132

–142

–148

–150

n/a

–86

–111

–128

–133

–144

–147

n/a

–75

–65

–90

–100

–116

–124

–135

–146

–147

–109

–121

–134

–146

–147

dBc/Hz

10 MHz

100 MHz

Table 8. Environmental Compliance

The Si550 meets the following qualification test requirements.

Parameter

Mechanical Shock

Conditions/Test Method

MIL-STD-883, Method 2002

MIL-STD-883, Method 2007

MIL-STD-883, Method 203

MIL-STD-883, Method 1014

MIL-STD-883, Method 2036

J-STD-020, MSL 1

Mechanical Vibration

Solderability

Gross & Fine Leak

Resistance to Solder Heat

Moisture Sensitivity Level

Contact Pads

J-STD-020, MSL 1

Table 9. Thermal Characteristics

(Typical values TA = 25 ºC, V_DD= 3.3 V)

Parameter

Symbol

Test Condition

Still Air

Min

—

Typ

84.6

38.8

—

Max

Unit

°C/W

°C

Thermal Resistance Junction to Ambient

Thermal Resistance Junction to Case

Ambient Temperature



—



Still Air

—

–40

—

Junction Temperature

—

125

°C

Rev. 1.1

Si550

Table 10. Absolute Maximum Ratings¹

Parameter

Maximum Operating Temperature

Supply Voltage, 1.8 V Option

Supply Voltage, 2.5/3.3 V Option

Input Voltage

Symbol

Rating

Units

ºC

AMAX

–0.5 to +1.9

–0.5 to +3.8

–0.5 to V + 0.3

ºC

Storage Temperature

–55 to +125

2500

ESD Sensitivity (HBM, per JESD22-A114)

ESD

Soldering Temperature (Pb-free profile)

260

ºC

PEAK

Soldering Temperature Time @ T

(Pb-free profile)

20–40

seconds

PEAK

Notes:

1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional

operation or specification compliance is not implied at these conditions. Exposure to maximum rating conditions for

extended periods may affect device reliability.

2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download from

www.silabs.com/VCXO for further information, including soldering profiles.

Rev. 1.1

Si550

2. Pin Descriptions

(Top View)

V_C

V_DD

CLK–

CLK+

GND

Table 11. Si550 Pin Descriptions

Type

Name

Function

Analog Input

Control Voltage

Output Enable (Polarity = High):

0 = clock output disabled (outputs tri-stated)

1 = clock output enabled

Output Enable (Polarity = Low):

0 = clock output enabled

OE*

Input

1 = clock output disabled (outputs tri-stated)

GND

Ground

Output

Electrical and Case Ground

Oscillator Output

CLK+

CLK–

(N/A for CMOS)

Complementary Output

(N/C for CMOS, make no external connection)

Power

Power Supply Voltage

*Note: OE includes 17 k pullup resistor to V_DD. See Section 3. "Ordering Information" on page 10 for details on OE polarity

ordering options.

Rev. 1.1

Si550

3. Ordering Information

The Si550 supports a variety of options including frequency, temperature stability, tuning slope, output format, and

. Specific device configurations are programmed into the Si550 at time of shipment. Configurations are

specified using the Part Number Configuration chart shown below. Silicon Labs provides a web browser-based part

number configuration utility to simplify this process. Refer to www.silabs.com/VCXOPartNumber to access this tool

and for further ordering instructions. The Si550 VCXO series is available in an industry-standard, RoHS compliant,

lead-free, 6-pad, 5 x 7 mm package. Tape and reel packaging is an ordering option.

550

XXXMXXX

R = Tape & Reel

Blank = Trays

550 VCXO

Product Family

Operating Temp Range (°C)

–40 to +85 °C

Device Revision Letter

Frequency (e.g. 622M080 is 622.080 MHz)

Available frequency range is 10 to 945 MHz, 970 to 1134, and 1213 to

1417 MHz. The position of “M” shifts to denote higher or lower

frequencies. If the frequency of interest requires greater than 6 digit

resolution, a six digit code will be assigned for the specific frequency.

1^stOption Code

V_DDOutput Format Output Enable Polarity

2^ndOption Code

Temperature

Stability

± ppm (max)

Tuning Slope

Minimum APR

3.3 LVPECL

3.3 LVDS

3.3 CMOS

3.3 CML

2.5 LVPECL

2.5 LVDS

2.5 CMOS

2.5 CML

1.8 CMOS

1.8 CML

3.3 LVPECL

3.3 LVDS

3.3 CMOS

3.3 CML

2.5 LVPECL

2.5 LVDS

2.5 CMOS

2.5 CML

1.8 CMOS

1.8 CML

High

Low

ppm/V (typ)

180

(±ppm) for VDD @

Code

3.3 V

100

2.5 V

Note 6

125

Note 6

300

145

104

220

1.8 V

Note 6

235

105

155

100

180

135

356

180

135

150

100

375

185

130

295

100

356

Note 6

Notes:

1. For best jitter and phase noise performance, always choose the smallest Kv that meets

the application’s minimum APR requirements. Unlike SAW-based solutions which

require higher higher Kv values to account for their higher temperature dependence,

the Si55x series provides lower Kv options to minimize noise coupling and jitter in real-

world PLL designs. See AN255 and AN266 for more information.

2. APR is the ability of a VCXO to track a signal over the product lifetime. A VCXO with an

APR of ±25 ppm is able to lock to a clock with a ±25 ppm stability over 15 years over all

operating conditions.

Note:

CMOS available to 160 MHz.

3. Nominal Pull range (±) = 0.5 x V_DDx tuning slope.

4. Nominal Absolute Pull Range (±APR) = Pull range – stability – lifetime aging

=0.5 x V_DDx tuning slope – stability – 10 ppm

5. Minimum APR values noted above include worst case values for all parameters.

6. Combination not available.

Example Part Number: 550AF622M080DGR is a 5 x 7 mm VCXO in a 6 pad package. The nominal frequency is 622.080 MHz, with a 3.3 V supply,

LVPECL output, and Output Enable active high polarity. Temperature stability is specified as ±50 ppm and the tuning slope is 135 ppm/V. The part

is specified for a –40 to +85 C° ambient temperature range operation and is shipped in tape and reel format.

Figure 1. Part Number Convention

Rev. 1.1

Si550

4. Package Outline and Suggested Pad Layout

Figure 2 illustrates the package details for the Si550. Table 12 lists the values for the dimensions shown in the

illustration.

Figure 2. Si550 Outline Diagram

Table 12. Package Diagram Dimensions (mm)

Dimension

Min

1.50

1.30

0.50

Nom

1.65

Max

1.80

1.50

0.70

1.40

0.60

5.00 BSC

4.40

4.30

4.50

2.54 BSC.

7.00 BSC.

6.20

6.10

0.55

1.17

1.80

6.30

0.75

1.37

2.60

0.65

1.27

—

0.70 REF

0.15

aaa

bbb

ccc

ddd

eee

0.15

0.10

0.50

Rev. 1.1

Si550

5. 6-Pin PCB Land Pattern

Figure 3 illustrates the 6-pin PCB land pattern for the Si550. Table 13 lists the values for the dimensions shown in

the illustration.

Figure 3. Si550 PCB Land Pattern

Table 13. PCB Land Pattern Dimensions (mm)

Dimension

Min

Max

5.08 REF

2.54 BSC

4.15 REF

0.84

2.00

—

8.20 REF

7.30 REF

1.70 TYP

2.15 REF

—

6.78

6.30

Notes:

1. Dimensioning and tolerancing per the ANSI Y14.5M-1994 specification.

2. Land pattern design based on IPC-7351 guidelines.

3. All dimensions shown are at maximum material condition (MMC).

4. Controlling dimension is in millimeters (mm).

Rev. 1.1

Si550

6. Top Marking

6.1. Si550 Top Marking

6.2. Top Marking Explanation

Line

Position

1–10

Description

“SiLabs”+ Part Family Number, 550 (First 3 characters in part number)

Si550: Option1+Option2+Freq(6007)+Temp

1–10

Trace Code

Position 1

Pin 1 orientation mark (dot)

Product Revision (D)

Position 2

Tiny Trace Code (4 alphanumeric characters per assembly release instructions)

Year (least significant year digit), to be assigned by assembly site (ex: 2010 = 0)

Calendar Work Week number (1–53), to be assigned by assembly site

“+” to indicate Pb-Free and RoHS-compliant

Position 3–6

Position 7

Position 8–9

Position 10

Rev. 1.1

Si550

DOCUMENT CHANGE LIST

Revision 0.6 to Revision 1.0

 Updated Table 4 on page 3.

Updated 2.5 V/3.3 V and 1.8 V CML output level

specifications.

 Updated Table 5 on page 4.

Removed the words “Differential Modes:

LVPECL/LVDS/CML” in the footnote referring to AN256.

Added footnotes clarifying max offset frequency test

conditions.

Added CMOS phase jitter specs.

 Updated Table 10 on page 8.

Separated 1.8 V, 2.5 V/3.3 V supply voltage

specifications.

 Updated and clarified Table 8 on page 7

Added “Moisture Sensitivity Level” and “Contact Pads”

rows.

 Updated 6. "Top Marking" on page 13 to reflect

specific marking information (previously, figure was

generic).

 Updated 4. "Package Outline and Suggested Pad

Layout" on page 11.

Added cyrstal impedance pin in Figure 2 on page 11 and

Table 12 on page 11.

 Reordered spec tables and back matter to conform

to data sheet quality conventions.

Revision 1.0 to Revision 1.1

 Added Table 9, “Thermal Characteristics,” on

page 7.

Rev. 1.1

Si550

CONTACT INFORMATION

Silicon Laboratories Inc.

400 West Cesar Chavez

Austin, TX 78701

Tel: 1+(512) 416-8500

Fax: 1+(512) 416-9669

Toll Free: 1+(877) 444-3032

Please visit the Silicon Labs Technical Support web page:

https://www.silabs.com/support/pages/contacttechnicalsupport.aspx

and register to submit a technical support request.

The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.

Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from

the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features

or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-

resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-

quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to

support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-

sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-

plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.

Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc.

Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.

Rev. 1.1

550GC38M7853DGR [SILICON]

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