550HB1417M000BGR [SILICON]

Oscillator;


型号：	550HB1417M000BGR
厂家：	SILICON
描述：	Oscillator
文件：	总12页 (文件大小：207K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Si550

PRELIMINARY DATA SHEET

VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR (VCXO)

10 MHZ TO 1.4 GHZ

Features

ꢀ

Available with any-rate output ꢀ Internal fixed crystal frequency

Si5602

frequencies from 10 MHz to

945 MHz and selected frequencies

to 1.4 GHz

ensures high reliability and low

aging

ꢀ

Available CMOS, LVPECL,

LVDS, & CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

ꢀ

3rd generation DSPLL with

ꢀ

superior jitter performance

3x better frequency stability than

SAW based oscillators

ꢀ

Lead-free/RoHS-compliant

Ordering Information:

Applications

See page 8.

ꢀ

SONET / SDH

xDSL

10 GbE LAN / WAN

ꢀ

Low-jitter clock generation

Optical modules

Clock and data recovery

ꢀ

Pin Assignments:

See page 7.

Description

(Top View)

The Si550 VCXO utilizes Silicon Laboratories’ advanced DSPLL circuitry to

provide a low-jitter clock at high frequencies. The Si550 is available with

any-rate output frequency from 10 to 945 MHz and selected frequencies to

1400 MHz. Unlike traditional VCXO’s where a different crystal is required for

each output frequency, the Si550 uses one fixed crystal to provide a wide

range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In

addition, DSPLL clock synthesis provides superior supply noise rejection,

simplifying the task of generating low-jitter clocks in noisy environments

typically found in communication systems. The Si550 IC-based VCXO is

factory configurable for a wide variety of user specifications, including

frequency, supply voltage, output format, tuning slope, and temperature

stability. Specific configurations are factory programmed at time of shipment,

thereby eliminating long lead times associated with custom oscillators.

V_C

V_DD

CLK–

CLK+

GND

Functional Block Diagram

CLK– CLK+

V_DD

Any-rate

10-1400 MHz

DSPLL^®

Fixed

Frequency

Clock Synthesis

ADC

GND

Preliminary Rev. 0.3 4/06

Si550

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

Si550

1. Electrical Specifications

Table 1. Recommended Operating Conditions

Parameter

Symbol

Test Condition

3.3 V option

Min

2.97

2.25

1.71

—

Typ

3.3

2.5

1.8

Max

3.63

2.75

1.89

—

Units

Supply Voltage

2.5 V option

1.8 V option

Supply Current

Output enabled

TriState mode

—

Output Enable (OE)

0.75 x V

—

0.5

Operating Temperature Range

–40

—

ºC

Notes:

1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 8 for further details.

2. OE pin includes a 17 kΩ pullup resistor to VDD. Pulling OE to ground causes outputs to tristate.

Table 2. V_CControl Voltage Input

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

1,2,3

Control Voltage Tuning Slope

10 to 90% of V

—

ppm/V

135

180

Control Voltage Linearity

BSL

–5

–10

9.3

500

—

±1

±5

+10

10.7

—

Incremental

Modulation Bandwidth

10.0

—

kHz

kΩ

V Input Impedance

Nominal Control Voltage

@ f

3/8 x V

—

CNOM

Control Voltage Tuning Range

Notes:

1. Positive slope; selectable option by part number. See Section 3. "Ordering Information" on page 8.

2. For best jitter and phase noise performance, always choose the smallest K_Vthat meets the application’s minimum APR

requirements. See “AN266: VCXO Tuning Slope (K_V), Stability, and Absolute Pull Range (APR)” for more information.

3. K_Vvariation is ±28% of typical values.

4. BSL determined from deviation from best straight line fit with V_Cranging from 10 to 90% of V_DD. Incremental slope

determined with V_Cranging from 10 to 90% of V_DD

Preliminary Rev. 0.3

Si550

Table 3. CLK± Output Frequency Characteristics

Parameter

Symbol

Test Condition

LVDS/CML/LVPECL

CMOS

Min

Typ

—

Max

945

160

Units

1,2,3

Nominal Frequency

MHz

—

1,4

Temperature Stability

∆f/f

T = –40 to +85 ºC

–20

–50

–100

—

+20

+50

+100

ppm

1,4

Absolute Pull Range

Aging

APR

±25

—

±150

±10

ppm

Frequency drift over

15 year life.

Power up Time

t_OSC

—

Notes:

1. See Section 3. "Ordering Information" on page 8 for further details.

2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.

3. Nominal output frequency set by V_CNOM= 3/8 x V_DD

4. Selectable parameter specified by part number.

5. Time from power up or tristate mode to f_O.

Table 4. CLK± Output Levels and Symmetry

Parameter

Symbol

Test Condition

mid-level

Min

_DD– 1.42

1.1

Typ

—

Max

V_DD– 1.25

1.9

Units

LVPECL Output Option

V_OD

V_SE

swing (diff)

—

V_PP

swing (single-ended)

mid-level

0.5

—

0.93

1.275

0.50

—

LVDS Output Option

1.125

0.32

—

1.20

0.40

swing (diff)

V_OD

V_O

V_PP

CML Output Option

mid-level

– 0.75

V_OD

V_OH

V_OL

swing (diff)

0.70

0.95

—

1.20

V_DD

V_PP

0.8 x V_DD

CMOS Output Option

= 32 mA

—

I_OL= 32 mA

0.4

Rise/Fall time (20/80%)

t_{R, F}

LVPECL/LVDS/CML

CMOS with CL = 15 pF

—

350

—

Preliminary Rev. 0.3

Si550

Table 4. CLK± Output Levels and Symmetry (Continued)

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

Symmetry (duty cycle)

SYM

LVPECL:

LVDS:

CMOS:

– 1.3 V (diff)

—

1.25 V (diff)

Notes:

1. 50 Ω to V_DD– 2.0 V.

2. R_term= 100 Ω (differential).

3. C_L= 15 pF

Table 5. CLK± Output Phase Jitter

Parameter

Symbol

Test Condition

Kv = 45 ppm/V

Min

Typ

Max

Units

1,2,3

Phase Jitter (RMS)

for F > 500 MHz

φ_J

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.35

0.38

—

OUT

Kv = 90 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.43

0.41

—

Kv = 135 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.52

0.46

—

Kv = 180 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.64

0.52

—

1,2,3

Phase Jitter (RMS)

for F of 125 to 500 MHz

φ_J

Kv = 45 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.42

0.58

—

OUT

Kv = 90 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.48

0.60

—

Kv = 135 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.57

0.64

—

Kv = 180 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.67

0.68

—

Notes:

1. Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information.

2. For best jitter and phase noise performance, always choose the smallest K_Vthat meets the application’s minimum APR

requirements. See “AN266: VCXO Tuning Slope (K_V), Stability, and Absolute Pull Range (APR)” for more information.

3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply

rejection (PSR) advantage of Si55x versus SAW-based solutions.

Preliminary Rev. 0.3

Si550

Table 6. CLK± Output Period Jitter

Parameter

Period Jitter*

Symbol

Test Condition

RMS

Min

—

Typ

Max

Units

—

PER

for F < 160 MHz

OUT

Peak-to-Peak

—

*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles.

Table 7. CLK± Output Phase Noise (Typical)

Configuration

74.25 MHz

45 ppm/V

CMOS

300 MHz

622.08 MHz

45 ppm/V

LVPECL

Units

90 ppm/V

LVPECL

Output

Offest Frequency (f)

L (f)

100 Hz

1 kHz

10 kHz

100 kHz

1 MHz

–94

–117

–128

–135

–138

–143

n/a

–74

–98

–77

–101

–114

–118

–128

–144

–147

–112

–122

–134

–144

–147

dBc/Hz

10 MHz

100 MHz

Preliminary Rev. 0.3

Si550

Table 8. Absolute Maximum Ratings

Parameter

Supply Voltage

Symbol

Rating

Units

Volts

ºC

–0.5 to +3.8

Input Voltage

–0.5 to V + 0.3

Storage Temperature

–55 to +125

>2500

260

ESD Sensitivity (HBM, per JESD22-A114)

Soldering Temperature (lead-free profile)

ESD

Volts

ºC

PEAK

Soldering Temperature Time @ T

(lead-free profile)

seconds

PEAK

Note: Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional

operation or specification compliance is not implied at these conditions.

Table 9. Environmental Compliance

The Si550 meets the following qualification test requirements.

Parameter

Conditions/ Test Method

MIL-STD-883F, Method 2002.3 B

MIL-STD-883F, Method 2007.3 A

MIL-STD-883F, Method 203.8

MIL-STD-883F, Method 1014.7

MIL-STD-883F, Method 2016

Mechanical Shock

Mechanical Vibration

Solderability

Gross & Fine Leak

Resistance to Solvents

Preliminary Rev. 0.3

Si550

2. Pin Descriptions

(Top View)

V_C

V_DD

CLK–

CLK+

GND

Table 10. Si550 Pin Descriptions

Type

Name

Function

Analog Input

Control Voltage

Output Enable:

OE*

Input

0 = clock output disabled (outputs tri-stated)

1 = clock output enabled

GND

Ground

Output

Electrical and Case Ground

Oscillator Output

CLK+

CLK–

(N/A for CMOS)

Complementary Output

(N/C for CMOS)

Power

Power Supply Voltage

*Note: OE includes 17 kΩ pullup resistor to V_DD

Preliminary Rev. 0.3

Si550

3. Ordering Information

The Si550 was designed to support a variety of options including frequency, temperature stability, tuning slope,

output format, and V

Specific device configurations are programmed into the Si550 at time of shipment.

Configurations are specified using the Part Number Configuration chart shown below. Silicon Labs provides a web

browser-based part number configuration utility to simplify this process. Refer to www.silabs.com/

VCXOPartNumber to access this tool and for further ordering instructions. The Si550 VCXO series is supplied in

an industry-standard, RoHS compliant, lead-free, 6-pad, 5 x 7 mm package. Tape and reel packaging is an

ordering option.

550

XXXMXXX

R = Tape & Reel

Blank = Trays

550 VCXO

Product Family

Operating Temp Range (°C)

–40 to +85 °C

Device Revision Letter

Frequency (e.g. 622M080 is 622.080 MHz)

Available frequency range is 10 to 945 MHz, 970 to 1134, and 1213

to 1417 MHz. The position of “M” shifts to denote higher or lower

frequencies.

1^stOption Code

2^ndOption Code

Code

VDD

3.3

Output Format

LVPECL

LVDS

CMOS

CML

LVPECL

LVDS

CMOS

CML

Temperature

Stability

± ppm (max)

Tuning Slope

Minimum APR

(±ppm)

@ 2.5 V

3.3

ppm/V (typ)

180

3.3

Code

@ 3.3 V

100

@ 1.8 V

3.3

2.5

1.8

100

180

Note 6

125

Note 6

150

Note 6

CMOS

CML

135

100

Notes:

1. For best jitter and phase noise performance, always choose the smallest Kv that

meets the application’s minimum APR requirements. Unlike SAW-based solutions

which require higher higher Kv values to account for their higher temperature

dependence, the Si55x series provides lower Kv options to minimize noise coupling

and jitter in real-world PLL designs. See AN255 and AN266 for more information.

2. APR is the ability of a VCXO to track a signal over the product lifetime. A VCXO with

an APR of ±25 ppm is able to lock to a clock with a ±25 ppm stability, over 15 years.

3. Nominal Pull range (±) = 0.5 x V_DDx tuning slope.

CMOS available to 160 MHz.

4. Nominal Absolute Pull Range (±APR) = Pull range – stability – lifetime aging

=0.5 x V_DDx tuning slope – stability – 10 ppm

5. Minimum APR values noted above include worst case values for all parameters.

6. Combination not available.

Example Part Number: 550AF622M080BGR is a 5 x 7 mm VCXO in a 6 pad package. The nominal frequency is 622.080 MHz, with

a 3.3 V supply and LVPECL output. Temperature stability is specified as ±50 ppm and the tuning slope is 135 ppm/V. The part is

specified for a –40 to +85 C° ambient temperature range operation and is shipped in tape and reel format.

Preliminary Rev. 0.3

Si550

4. Outline Diagram and Suggested Pad Layout

Figure 1 illustrates the package details for the Si550. Table 11 lists the values for the dimensions shown in the

illustration.

Figure 1. Si550 Outline Diagram

Table 11. Package Diagram Dimensions (mm)

Dimension

Min

1.45

1.2

Nom

1.65

Max

1.85

1.6

1.4

0.60 TYP.

7.00 BSC.

6.2

6.10

6.30

2.54 BSC.

5.00 BSC.

4.40

4.30

1.07

4.50

1.47

1.27

1.815 BSC.

0.7 REF.

—

aaa

bbb

ccc

ddd

—

0.15

0.10

—

Preliminary Rev. 0.3

Si550

5. 6-Pin PCB Land Pattern

Figure 2 illustrates the 6-pin PCB land pattern for the Si550. Table 12 lists the values for the dimensions shown in

the illustration.

Figure 2. Si550 PCB Land Pattern

Table 12. PCB Land Pattern Dimensions (mm)

Dimension

Min

Max

5.08 REF

2.54 BSC

4.15 REF

0.84

2.00

—

8.20 REF

7.30 REF

1.70 TYP

2.15 REF

—

6.78

6.30

Notes:

1. Dimensioning and tolerancing per the ANSI Y14.5M-1994 specification.

2. Land pattern design based on IPC-7351 guidelines.

3. All dimensions shown are at maximum material condition (MMC).

4. Controlling dimension is in millimeters (mm).

Preliminary Rev. 0.3

Si550

DOCUMENT CHANGE LIST

Revision 0.2 to Revision 0.3

ꢀ Updated 1. "Electrical Specifications" on page 2.

ꢁ Updated ordering and format of Table 1 through Table 9.

ꢁ Updated LVDS and CML in Table 4, “CLK± Output

Levels and Symmetry,” on page 3.

ꢁ Updated RMS jitter values in Table 5, “CLK± Output

Phase Jitter,” on page 4.

ꢁ Added Typical Phase Noise performance data in

Table 5, “CLK± Output Phase Jitter,” on page 4.

ꢀ Updated 3. "Ordering Information" on page 8.

ꢁ Removed ordering option E at V_DD= 2.5 V in table for

the 2nd Option Code.

ꢁ Typical APRs replaced with minimum APR values.

ꢁ New 135 ppm/V K_Voption included.

Preliminary Rev. 0.3

Si550

CONTACT INFORMATION

Silicon Laboratories Inc.

4635 Boston Lane

Austin, TX 78735

Tel: 1+(512) 416-8500

Fax: 1+(512) 416-9669

Toll Free: 1+(877) 444-3032

Email: VCXOinfo@silabs.com

Internet: www.silabs.com

The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.

Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from

the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features

or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-

resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-

quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to

support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-

sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-

plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.

Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc.

Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.

Preliminary Rev. 0.3

550HB1417M000BGR [SILICON]

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