552BC622M080BGR [SILICON]

DUAL FREQUENCY VCXO (10 MHZ TO 1.4 GHZ); 双频VCXO （ 10 MHz至1.4 GHz）的


型号：	552BC622M080BGR
厂家：	SILICON
描述：	DUAL FREQUENCY VCXO (10 MHZ TO 1.4 GHZ) 双频VCXO （ 10 MHz至1.4 GHz）的石英晶振压控振荡器
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中文：	中文翻译
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Si552

PRELIMINARY DATA SHEET

DUAL FREQUENCY VCXO (10 MHZ TO 1.4 GHZ)

Features

Available with any-rate output

3x better frequency stability than

SAW-based oscillators

frequencies from 10 to 945 MHz and

selected frequencies to 1.4 GHz

Two selectable output frequencies

Industry-standard 7x5 mm package

Available CMOS, LVPECL, LVDS &

CML outputs

Si5602

3rd generation DSPLL with

superior jitter performance

Internal fixed crystal frequency

ensures high reliability and low

aging

Lead-free/RoHS-compliant

Applications

Ordering Information:

SONET / SDH

xDSL

10 GbE LAN / WAN

Low jitter clock generation

Optical Modules

Test and Measurement

See page 7.

Description

The Si552 dual frequency VCXO utilizes Silicon Laboratories advanced

DSPLL circuitry to provide a very low jitter clock for all output frequencies.

The Si552 is available with any-rate output frequency from 10 to 945 MHz

and selected frequencies to 1400 MHz. Unlike traditional VCXO’s where a

different crystal is required for each output frequency, the Si552 uses one

fixed crystal frequency to provide a wide range of output frequencies. This

IC based approach allows the crystal resonator to be optimized for superior

frequency stability and reliability. In addition, DSPLL clock synthesis

provides superior supply noise rejection, simplifying the task of generating

low jitter clocks in noisy environments often found in communication

systems. The Si552 IC based VCXO is factory configurable for a wide

variety of user specifications including frequency, supply voltage and output

format. Specific configurations are factory programmed into the Si552 at

time of shipment, thereby eliminating the long lead times associated with

custom oscillators.

Functional Block Diagram

V_DD

CLK-

CLK+

Any-rate

10–1400 MHz

DSPLL™

Fixed

Frequency XO

Clock Synthesis

ADC

V_C

GND

Preliminary Rev. 0.2 8/05

Si552

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

Si552

1. Electrical Specifications

Table 1. Si552 Electrical Specifications

Parameter

Min

Typ

Max

Units

Notes

Frequency

Nominal Frequency

LVDS/CML/LVPECL

CMOS

Specified at time of order by P/N.

Also available in bands from

970 to 1134 MHz and 1213 to

1417 MHz.

—

945

160

MHz

Initial Accuracy

–1.5

—

1.5

Measured at +25 °C at time of ship-

ppm

ping and at V = V /2.

Temperature Stability

–20

–50

–100

—

+20

+50

+100

Selectable option by P/N. See

Section 4. "Ordering Information" on

page 7. Measured at V = V /2.

C DD

Linearity

BSL

BSL determined from deviation from

best straight line fit with V ranging

–5

–10

±1

±5

+10

from 10 to 90% of V . Incremental

Incremental

slope determined with V ranging

from 10 to 90% of V

Tuning Slope (kV) from 10 to

—

180

—

Positive slope; selectable option by

P/N. See Section 4. "Ordering Infor-

mation" on page 7.

90% of V

ppm/V

Modulation Bandwidth

—

500

—

kHz

V Input Impedance

kΩ

Absolute Pull Range (APR)

Aging

See Notes

See Section 4. "Ordering Information"

on page 7.

—

±10

Projected frequency drift over 15 year

life.

ppm

Outputs

LVPECL:

LVDS:

CMOS:

– 1.3 V (differential)

Symmetry

1.25 V (differential)

RMS Jitter for F

> 500 MHz

OUT

Kv = 180 ppm/V

12 kHz to 20 MHz

50 kHz to 80 MHz

—

0.42

0.34

—

> 500 MHz

OUT

Differential Modes:

LVPECL/LVDS/CML

Kv = 45, 90 ppm/V

12 kHz to 20 MHz

50 kHz to 80 MHz

—

0.28

0.31

—

Preliminary Rev. 0.2

Si552

Table 1. Si552 Electrical Specifications (Continued)

Parameter

RMS Jitter for F of 125 to

Min

Typ

Max

Units

Notes

< 500 MHz

Differential Modes:

LVPECL/LVDS/CML

OUT

125 < F

OUT

500 MHz

12 kHz to 20 MHz

50 kHz to 80 MHz

—

0.61

0.52

—

Period Jitter for F

Peak-to-Peak

RMS

< 160 MHz

OUT

Any output

N = 1000 cycles

—

LVPECL Output Option

mid-level

_DD– 1.42

1.1

—

V_DD– 1.25

1.9

50 Ω to V_DD– 2.0 V

swing (diff)

0.5

0.93

swing (single-ended)

LVDS Output Option

mid-level

1.125

0.5

1.2

0.7

1.275

0.9

R_term= 100 Ω (differential)

swing (diff)

CML Output Option

mid-level

swing

—

0.35

– 0.36

0.425

—

0.5

Rterm = 100 Ω (differential)

CMOS Output Option

0.8xV_DD

—

V_DD

0.4

C_L= 15 pF

V_OL

350

—

CML/LVPECL/LVDS at 20% / 80%

CMOS

Rise/Fall time

—

Inputs

Voltage

3.3 V option

2.5 V option

1.8 V option

2.97

2.25

1.71

3.3

2.5

1.8

3.63

2.75

1.89

Optional parameter specified by P/N

Tuning range for control voltage

Supply Current

—

Control Voltage (V )

Frequency Select

—

0.5

“0” selects F1

“1” selects F2

0.75 x V

Table 2. Absolute Maximum Ratings

Parameter

Supply Voltage

Symbol

Rating

Units

–0.5 to +3.8

–55 to +125

Storage Temperature

°C

Preliminary Rev. 0.2

Si552

Table 3. Environmental Conditions

Parameter

Conditions/ Test Method

–40 to +85 °C

Operating Temperature

Mechanical Shock

Mechanical Vibration

Solderability

MIL-STD-883F, Method 2002.3 B

MIL-STD-883F, Method 2007.3 A

MIL-STD-883F, Method 203.8

MIL-STD-883F, Method 1014.7

MIL-STD-883F, Method 2016

Gross & Fine Leak

Resistance to Solvents

Table 4. Pinout

Symbol

Function

Control Voltage

Frequency Select

Ground

Gnd

Output

Oscillator Output

Coutput

(N/A for CMOS)

Complementary Output

(N/C for CMOS)

Power Suppy Voltage

Preliminary Rev. 0.2

Si552

2. Outline Diagram and Suggested Pad Layout

Figure 1 illustrates the package details for the Si552. Table 5 lists the values for the dimensions shown in the

illustration.

Figure 1. Si550 Outline Diagram

Table 5. Package Diagram Dimensions (mm)

Dimension

Min

1.45

1.2

Nom

1.65

Max

1.85

1.6

1.4

0.60 TYP.

7.00 BSC.

6.2

6.10

6.30

2.54 BSC.

5.00 BSC.

4.40

4.30

1.07

4.50

1.47

1.27

1.815 BSC.

0.7 REF.

—

aaa

bbb

ccc

ddd

—

0.15

0.10

—

Preliminary Rev. 0.2

Si552

3. 6-Pin PCB Land Pattern

Figure 2 illustrates the 6-pin PCB land pattern for the Si552. Table 6 lists the values for the dimensions shown in

the illustration.

Figure 2. Si530 PCB Land Pattern

Table 6. PCB Land Pattern Dimensions (mm)

Dimension

Min

Max

5.08 REF

2.54 BSC

4.15 REF

0.84

2.00

—

8.20 REF

7.30 REF

1.70 TYP

2.15 REF

—

6.78

6.30

Notes:

1. Dimensioning and tolerancing per the ANSI Y14.5M-1994 specification.

2. Land pattern design based on IPC-7351 guidelines.

3. All dimensions shown are at maximum material condition (MMC).

4. Controlling dimension is in millimeters (mm).

Preliminary Rev. 0.2

Si552

4. Ordering Information

The Si552 was designed to support a variety of options including frequency, tuning slope, output format, and V

Specific device configurations are programmed into the Si552 at time of shipment. A unique part number

associated with these options and frequencies will be assigned. The Si552 Dual Frequency VCXO is provided in

an industry-standard, 7x5 package.

Part numbers for the Si552 Dual Frequency VCXO are determined by following configuration tables. Silicon Labs

provides a Windows-based part number configuration tool to simplify this process. Refer to www.silabs.com/VCXO

to access this tool and for further ordering instructions.

552

X X X X X X

Tape & Reel Packaging

552 VCXO

Product Family

Operating Temp Range(°C)

-40 to +85°C

Part Revision Letter

Frequency Designator Code

Two unique frequencies can be specified within the following bands of frequencies:

10 to 945 MHz

970 to 1134 MHz

1213 to 1417 MHz

A six digit code will be assigned by SiLabs for the specified combination of frequencies .

1^stOption Code

2^ndOption Code (VCXO)

V_DDOutput Format

3.3 LVPECL

3.3 LVDS

3.3 CMOS

3.3 CML

2.5 LVPECL

2.5 LVDS

2.5 CMOS

2.5 CML

1.8 CMOS

1.8 CML

Temp Stability Tuning Slope

(ppm, max, ±) (Kv,ppm/V, typ,) APR(typ)@3.3V APR(typ)@2.5V APR(typ)@1.8V

100

180

185

235

115

Note 3

165

Note 3

100

Note 3

Notes:

1. Pull range (±) = 0.5 x V_DDx tuning slope.

2. Absolute Pull Range (±APR) = Pull range – stability – lifetime aging

=0.5xV_DDx tuning slope – stability – 10 ppm

Notes:

CMOS available to 160 MHz.

3. Combination not available.

APR is the ability of a VCXO to track a signal over the product lifetime . Thus, a VCXO

with an APR of 50 ppm is able to lock to a clock with 50 ppm stability, for a 15 year life.

Preliminary Rev. 0.2

Si552

CONTACT INFORMATION

Silicon Laboratories Inc.

4635 Boston Lane

Austin, TX 78735

Tel: 1+(512) 416-8500

Fax: 1+(512) 416-9669

Toll Free: 1+(877) 444-3032

Email: VCXOinfo@silabs.com

Internet: www.silabs.com

The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.

Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from

the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features

or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-

resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-

quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to

support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-

sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-

plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.

Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc.

Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.

Preliminary Rev. 0.2

552BC622M080BGR [SILICON]

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