560BAA150M000BBGR [SILICON]
LVDS Output Clock Oscillator,;
| 型号： | 560BAA150M000BBGR |
| 厂家： | 
SILICON |
| 描述： | LVDS Output Clock Oscillator, 机械 输出元件 振荡器 |
| 文件： | 总17页 (文件大小：925K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
™
Ultra Series Crystal Oscillator
Si560 Data Sheet
Ultra Low Jitter Any-Frequency XO (90 fs), 0.2 to 3000 MHz
KEY FEATURES
The Si560 Ultra Series™ oscillator utilizes Silicon Laboratories’ advanced 4th genera-
tion DSPLL® technology to provide an ultra-low jitter, low phase noise clock at any
output frequency. The device is factory-programmed to any frequency from 0.2 to
3000 MHz with <1 ppb resolution and maintains exceptionally low jitter for both inte-
ger and fractional frequencies across its operating range. The Si560 offers excellent
reliability and frequency stability as well as guaranteed aging performance. On-chip
power supply filtering provides industry-leading power supply noise rejection, simplify-
ing the task of generating low jitter clocks in noisy systems that use switched-mode
power supplies. Offered in industry-standard 3.2x5 mm and 5x7 mm footprints, the
Si560 has a dramatically simplified supply chain that enables Silicon Labs to ship cus-
tom frequency samples 1-2 weeks after receipt of order. Unlike a traditional XO,
where a different crystal is required for each output frequency, the Si560 uses one
simple crystal and a DSPLL IC-based approach to provide the desired output frequen-
cy. This process also guarantees 100% electrical testing of every device. The Si560 is
factory-configurable for a wide variety of user specifications, including frequency, out-
put format, and OE pin location/polarity. Specific configurations are factory-program-
med at time of shipment, eliminating the long lead times associated with custom oscil-
lators.
• Available with any frequency from 0.2
MHz to 3000 MHz
• Ultra low jitter: 90 fs RMS typical
(12 kHz – 20 MHz)
• Excellent PSRR and supply noise
immunity: –80 dBc Typ
• 20 ppm temp stability (–40 to 85 °C)
• 3.3 V, 2.5 V and 1.8 V V supply
DD
operation from the same part number
• LVPECL, LVDS, CML, HCSL, CMOS,
and Dual CMOS output options
• 3.2x5, 5x7 mm package footprints
• Samples available with 1-2 week lead
times
APPLICATIONS
Pin Assignments
• 100G/200G/400G OTN, coherent optics
• 10G/40G/100G optical ethernet
• 56G/112G PAM4 clocking
1
2
3
6
5
4
VDD
CLK-
CLK+
OE/NC
NC/OE
GND
• 3G-SDI/12G-SDI/24G-SDI broadcast
video
• Datacenter
• Test and measurement
• FPGA/ASIC clocking
(Top View)
Fixed
Frequency
Crystal
Frequency
Flexible
DSPLL
Pin #
Descriptions
Low
Noise
Driver
1, 2
Selectable via ordering option
DCO
Digital
Phase
Detector
Digital
Phase Error
Loop
OE = Output enable; NC = No connect
OSC
Cancellation
Filter
Flexible
Formats,
1.8V – 3.3V
3
4
5
6
GND = Ground
Phase Error
Fractional
Operation
Divider
CLK+ = Clock output
NVM
Control
CLK- = Complementary clock output. Not used for CMOS.
VDD = Power supply
Power Supply Regulation
Output Enable
(Pin Control)
Built-in Power Supply
Noise Rejection
silabs.com | Building a more connected world.
Rev. 1.0
Si560 Data Sheet
Ordering Guide
1. Ordering Guide
The Si560 XO supports a variety of options including frequency, output format, and OE pin location/polarity, as shown in the chart
below. Specific device configurations are programmed into the part at time of shipment, and samples are available in 1-2 weeks. Silicon
Laboratories provides an online part number configuration utility to simplify this process. Refer to www.silabs.com/oscillators to access
this tool and for further ordering instructions.
XO Series
Description
Temp Stability Total Stability2
± 20 ppm
± 50 ppm
Package
5x7 mm
Temperature Grade
560
Single Frequency
A
A
B
G
-40 to 85 °C
3.2x5 mm
560
A
A
A
-
-
-
-
-
-
-
A
B
G
R
Device Revision
Order
Option
Signal Format
VDD Range
OE Pin OE Polarity
Reel
LVPECL
LVDS
2.5, 3.3 V
A
B
C
D
E
A
B
C
D
Pin 1
Pin 1
Pin 2
Pin 2
Active High
Active Low
Active High
Active Low
R
Tape and Reel
Coil Tape
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
<Blank>
CMOS
CML
Frequency Code3
Mxxxxxx
Description
HCSL
FCLK < 1 MHz
Dual CMOS
(In-Phase)
Dual CMOS
1.8, 2.5, 3.3 V
F
xMxxxxx
1 MHz ≤ FCLK < 10 MHz
xxMxxxx
10 MHz ≤ FCLK < 100 MHz
100 MHz ≤ FCLK < 1000 MHz
1000 MHz ≤ FCLK ≤ 3000 MHz
Custom code if FCLK > 6 digits
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
G
X
xxxMxxx
(Complementary)
Custom1
xxxxMxx
xxxxxx
Notes:
1. Contact Silicon Labs for non-standard configurations.
2. Total stability includes temp stability, initial accuracy, load pulling, VDD variation, and 20 year aging at 70 °C.
3. For example: 156.25 MHz = 156M250; 25 MHz = 25M0000. Create custom part numbers at www.silabs.com/oscillators.
1.1 Technical Support
Frequently Asked Questions (FAQ)
Oscillator Phase Noise Lookup Utility
Quality and Reliability
www.silabs.com/Si560-FAQ
www.silabs.com/oscillator-phase-noise-lookup
www.silabs.com/quality
Development Kits
www.silabs.com/oscillator-tools
silabs.com | Building a more connected world.
Rev. 1.0 | 2
Si560 Data Sheet
Electrical Specifications
2. Electrical Specifications
Table 2.1. Electrical Specifications
Test Condition/Comment
VDD = 1.8 V, 2.5 or 3.3 V ± 5%, TA = –40 to 85 ºC
Parameter
Temperature Range
Frequency Range
Symbol
TA
Min
–40
0.2
0.2
0.2
3.135
2.375
1.71
—
Typ
—
Max
85
Unit
ºC
FCLK
LVPECL, LVDS, CML
HCSL
—
3000
400
250
3.465
2.625
1.89
160
157
130
135
145
—
MHz
MHz
MHz
V
—
CMOS, Dual CMOS
3.3 V
—
Supply Voltage
Supply Current
VDD
3.3
2.5
1.8
110
90
85
85
95
73
—
2.5 V
V
1.8 V
V
IDD
LVPECL (output enabled)
LVDS/CML (output enabled)
HCSL (output enabled)
CMOS (output enabled)
Dual CMOS (output enabled)
Tristate Hi-Z (output disabled)
Frequency stability Grade A
Frequency stability Grade A
mA
mA
mA
mA
mA
mA
ppm
ppm
—
—
—
—
—
Temperature Stability
–20
–50
20
Total Stability1
FSTAB
TR/TF
—
50
Rise/Fall Time
LVPECL/LVDS/CML
CMOS / Dual CMOS, (CL = 5 pF)
HCSL, FCLK >50 MHz
All formats
—
—
0.5
—
—
—
—
—
—
—
350
ps
ns
ps
%
(20% to 80% VPP
Duty Cycle
)
—
1.5
—
550
DC
VIH
VIL
TD
45
55
Output Enable (OE)2
0.7 × VDD
—
V
—
—
—
—
0.3 × VDD
V
Output Disable Time, FCLK > 10 MHz
Output Enable Time, FCLK > 10 MHz
3
µs
µs
ms
TE
20
10
Powerup Time
tOSC
Time from 0.9 × VDD until output fre-
quency (FCLK) within spec
LVPECL Output Option3
VOC
VO
Mid-level
VDD – 1.42
1.1
—
—
—
VDD – 1.25
1.9
V
Swing (diff, FCLK < 1.5 GHz)
VPP
VPP
Swing (diff, FCLK > 1.5 GHz)6
Mid-level (2.5 V, 3.3 V VDD)
Mid-level (1.8 V VDD)
0.55
1.7
LVDS Output Option4
VOC
1.125
0.8
1.20
0.9
0.7
0.5
1.275
1.0
V
V
VO
Swing (diff, FCLK < 1.5 GHz)
0.5
0.9
VPP
VPP
Swing (diff, FCLK > 1.5 GHz) 6
0.25
0.8
silabs.com | Building a more connected world.
Rev. 1.0 | 3
Si560 Data Sheet
Electrical Specifications
Parameter
Symbol
VOH
VOL
Test Condition/Comment
Output voltage high
Min
660
–150
250
0.6
Typ
800
0
Max
850
150
550
1.0
Unit
mV
HCSL Output Option5
Output voltage low
mV
VC
Crossing voltage
410
0.8
0.55
mV
CML Output Option
(AC-Coupled)
VO
Swing (diff, FCLK ≤ 1.5 GHz)
VPP
VPP
Swing (diff, FCLK > 1.5 GHz)6
0.3
0.9
CMOS Output Option
VOH
VOL
IOH = 8/6/4 mA for 3.3/2.5/1.8 V VDD 0.85 × VDD
IOL = 8/6/4 mA for 3.3/2.5/1.8 V VDD
—
—
—
V
V
—
0.15 × VDD
Notes:
1. Total Stability includes temperature stability, initial accuracy, load pulling, VDD variation, and aging for 20 yrs at 70 ºC.
2. OE includes a 50 kΩ pull-up to VDD for OE active high, or includes a 50 kΩ pull-down to GND for OE active low.
3. Rterm = 50 Ω to VDD – 2.0 V (see Figure 4.1).
4. Rterm = 100 Ω (differential) (see Figure 4.2).
5. Rterm = 50 Ω to GND (see Figure 4.2).
6. Refer to the figure below for Typical Clock Output Swing Amplitudes vs Frequency.
Figure 2.1. Typical Clock Output Swing Amplitudes vs. Frequency
silabs.com | Building a more connected world.
Rev. 1.0 | 4
Si560 Data Sheet
Electrical Specifications
Table 2.2. Clock Output Phase Jitter and PSRR
VDD = 1.8 V, 2.5 or 3.3 V ± 5%, TA = –40 to 85 ºC
Parameter
Symbol
Test Condition/Comment
FCLK ≥ 200 MHz
Min
—
Typ
90
Max
140
160
125
Unit
fs
Phase Jitter (RMS, 12 kHz - 20 MHz)1
All Differential Formats
ϕJ
100 MHz ≤ FCLK < 200 MHz
LVPECL @ 156.25 MHz
—
105
95
fs
—
fs
Phase Jitter (RMS, 12 kHz - 20 MHz)1
CMOS / Dual CMOS Formats
ϕJ
10 MHz ≤ FCLK < 250 MHz
—
200
—
fs
Spurs Induced by External Power Supply
Noise, 50 mVpp Ripple. LVDS 156.25 MHz
Output
PSRR
100 kHz sine wave
200 kHz sine wave
500 kHz sine wave
1 MHz sine wave
-83
-83
-82
-85
dBc
Note:
1. Jitter inclusive of any spurs.
Table 2.3. 3.2 x 5 mm Clock Output Phase Noise (Typical)
Offset Frequency (f)
100 Hz
156.25 MHz LVDS
200 MHz LVDS
–100
644.53125 MHz LVDS
Unit
–105
–129
–136
–142
–150
–159
–160
–92
1 kHz
–126
–116
–125
–131
–138
–153
–154
10 kHz
–133
100 kHz
–140
dBc/Hz
1 MHz
–148
10 MHz
–161
20 MHz
–162
Offset Frequency (f)
156.25 MHz
LVPECL
200 MHz
LVPECL
644.53125 MHz
LVPECL
Unit
100 Hz
1 kHz
–109
–131
–135
–143
–150
–160
–161
–102
–126
–134
–141
–148
–162
–163
–92
–119
–124
–130
–138
–154
–155
10 kHz
100 kHz
1 MHz
dBc/Hz
10 MHz
20 MHz
silabs.com | Building a more connected world.
Rev. 1.0 | 5
Si560 Data Sheet
Electrical Specifications
Figure 2.2. Phase Jitter vs. Output Frequency
Phase jitter measured with Agilent E5052 using a differential-to-single ended converter (balun or buffer). Measurements collected for
>700 commonly used frequencies. Phase noise plots for specific frequencies are available using our free, online Oscillator Phase Noise
Lookup Tool at www.silabs.com/oscillators.
silabs.com | Building a more connected world.
Rev. 1.0 | 6
Si560 Data Sheet
Electrical Specifications
Table 2.4. Environmental Compliance and Package Information
Parameter
Test Condition
Mechanical Shock
Mechanical Vibration
Solderability
MIL-STD-883, Method 2002
MIL-STD-883, Method 2007
MIL-STD-883, Method 2003
MIL-STD-883, Method 1014
MIL-STD-883, Method 2036
1
Gross and Fine Leak
Resistance to Solder Heat
Moisture Sensitivity Level (MSL)
Contact Pads
Gold over Nickel
Note:
1. For additional product information not listed in the data sheet (e.g. RoHS Certifications, MDDS data, qualification data, REACH
Declarations, ECCN codes, etc.), refer to our "Corporate Request For Information" portal found here: www.silabs.com/support/
quality/Pages/RoHSInformation.aspx.
Table 2.5. Thermal Conditions
Package
Parameter
Symbol
ΘJA
ΘJB
TJ
Test Condition
Still Air, 85 °C
Still Air, 85 °C
Still Air, 85 °C
Still Air, 85 °C
Still Air, 85 °C
Still Air, 85 °C
Value
80.3
50.8
125
Unit
ºC/W
ºC/W
ºC
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Board
Max Junction Temperature
3.2 × 5 mm
6-pin CLCC
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Board
Max Junction Temperature
ΘJA
ΘJB
TJ
68.4
52.9
125
ºC/W
ºC/W
ºC
5 × 7 mm
6-pin CLCC
Table 2.6. Absolute Maximum Ratings1
Parameter
Symbol
TAMAX
TS
Rating
95
Unit
Maximum Operating Temp.
Storage Temperature
Supply Voltage
ºC
ºC
ºC
V
–55 to 125
–0.5 to 3.8
–0.5 to VDD + 0.3
2.0
VDD
Input Voltage
VIN
ESD HBM (JESD22-A114)
Solder Temperature2
HBM
TPEAK
kV
ºC
260
2
TP
20–40
sec
Solder Time at TPEAK
Notes:
1. Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation specification
compliance is not implied at these conditions. Exposure to maximum rating conditions for extended periods may affect device
reliability.
2. The device is compliant with JEDEC J-STD-020.
silabs.com | Building a more connected world.
Rev. 1.0 | 7
Si560 Data Sheet
Dual CMOS Buffer
3. Dual CMOS Buffer
Dual CMOS output format ordering options support either complementary or in-phase signals for two identical frequency outputs. This
feature enables replacement of multiple XOs with a single Si560 device.
~
Complementary
Outputs
~
In-Phase
Outputs
Figure 3.1. Integrated 1:2 CMOS Buffer Supports Complementary or In-Phase Outputs
silabs.com | Building a more connected world.
Rev. 1.0 | 8
Si560 Data Sheet
Recommended Output Terminations
4. Recommended Output Terminations
The output drivers support both AC-coupled and DC-coupled terminations as shown in figures below.
VDD
VDD
R1
VDD (3.3V, 2.5V)
CLK+
VDD (3.3V, 2.5V)
CLK+
R1
R1
R1
50 Ω
50 Ω
50 Ω
50 Ω
CLK-
CLK-
LVPECL
Receiver
LVPECL
Receiver
Rp
Rp
Si56x
Si56x
R2
R2
R2
R2
AC-Coupled LVPECL – Thevenin Termination
DC-Coupled LVPECL – Thevenin Termination
VDD (3.3V, 2.5V)
50 Ω
VDD (3.3V, 2.5V)
50 Ω
CLK+
CLK+
R1
R2
R1
50 Ω
50 Ω
50 Ω
50 Ω
VDD
VDD
VTT
VTT
CLK-
Rp
CLK-
R2
50 Ω
50 Ω
LVPECL
Receiver
LVPECL
Receiver
Si56x
Si56x
Rp
AC-Coupled LVPECL - 50 Ω w/VTT Bias
DC-Coupled LVPECL - 50 Ω w/VTT Bias
Figure 4.1. LVPECL Output Terminations
AC-Coupled LVPECL
Termination Resistor Values
DC-Coupled LVPECL
Termination Resistor Values
VDD
R1
R2
Rp
VDD
3.3 V
2.5 V
R1
R2
3.3 V
2.5 V
127 Ω
250 Ω
82.5 Ω
62.5 Ω
130 Ω
90 Ω
127 Ω
250 Ω
82.5 Ω
62.5 Ω
silabs.com | Building a more connected world.
Rev. 1.0 | 9
Si560 Data Sheet
Recommended Output Terminations
(3.3V, 2.5V, 1.8V)
VDD
(3.3V, 2.5V, 1.8V)
VDD
50 Ω
50 Ω
33 Ω
CLK+
CLK-
CLK+
50 Ω
50 Ω
100 Ω
33 Ω
50 Ω
CLK-
50 Ω
LVDS
Receiver
HCSL
Receiver
Si56x
Si56x
DC-Coupled LVDS
Source Terminated HCSL
(3.3V, 2.5V, 1.8V)
(3.3V, 2.5V, 1.8V)
VDD
VDD
50 Ω
CLK+
CLK+
50 Ω
100 Ω
CLK-
CLK-
50 Ω
50 Ω
50 Ω
50 Ω
LVDS
Receiver
HCSL
Receiver
Si56x
Si56x
AC-Coupled LVDS
Destination Terminated HCSL
Figure 4.2. LVDS and HCSL Output Terminations
(3.3V, 2.5V, 1.8V)
VDD
(3.3V, 2.5V, 1.8V)
VDD
CLK
50 Ω
50 Ω
CLK+
CLK-
50 Ω
10 Ω
100 Ω
NC
CMOS
Receiver
CML
Receiver
Si56x
Si56x
CML Termination without VCM
Single CMOS Termination
(3.3V, 2.5V, 1.8V)
VDD
(3.3V, 2.5V, 1.8V)
VDD
CLK+
50 Ω
50 Ω
CLK+
50 Ω
50 Ω
50 Ω
50 Ω
VCM
10 Ω
10 Ω
CLK-
CLK-
CML
Receiver
CMOS
Receivers
Si56x
Si56x
CML Termination with VCM
Dual CMOS Termination
Figure 4.3. CML and CMOS Output Terminations
silabs.com | Building a more connected world.
Rev. 1.0 | 10
Si560 Data Sheet
Package Outline
5. Package Outline
5.1 Package Outline (5×7 mm)
The figure below illustrates the package details for the 5×7 mm Si560. The table below lists the values for the dimensions shown in the
illustration.
Figure 5.1. Si560 (5×7 mm) Outline Diagram
Table 5.1. Package Diagram Dimensions (mm)
Dimension
Min
1.13
0.50
0.50
1.30
0.50
Nom
1.28
Max
1.43
0.60
0.60
1.50
0.70
Dimension
Min
1.17
0.05
1.70
Nom
1.27
Max
1.37
0.15
1.90
A
L
A2
0.55
L1
0.10
A3
0.55
p
—
b
1.40
R
0.70 REF
0.15
c
0.60
aaa
bbb
ccc
ddd
eee
D
5.00 BSC
4.40
0.15
D1
4.30
4.50
0.08
e
E
2.54 BSC
7.00 BSC
6.20
0.10
0.05
E1
6.10
6.30
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
silabs.com | Building a more connected world.
Rev. 1.0 | 11
Si560 Data Sheet
Package Outline
5.2 Package Outline (3.2×5 mm)
The figure below illustrates the package details for the 3.2×5 mm Si560. The table below lists the values for the dimensions shown in
the illustration.
Figure 5.2. Si560 (3.2×5 mm) Outline Diagram
Table 5.2. Package Diagram Dimensions (mm)
Dimension
Min
1.06
0.54
0.35
Nom
1.17
Max
1.33
0.74
0.55
A
b
0.64
c
0.45
D
3.20 BSC
2.60
D1
e
2.55
2.65
1.27 BSC
5.00 BSC
4.40
E
E1
H
4.35
0.45
0.80
0.05
1.36
4.45
0.65
1.00
0.15
1.56
0.55
L
0.90
L1
p
0.10
1.46
R
0.32 REF
0.15
aaa
bbb
ccc
ddd
eee
0.15
0.08
0.10
0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
silabs.com | Building a more connected world.
Rev. 1.0 | 12
Si560 Data Sheet
PCB Land Pattern
6. PCB Land Pattern
6.1 PCB Land Pattern (5×7 mm)
The figure below illustrates the 5×7 mm PCB land pattern for the Si560. The table below lists the values for the dimensions shown in
the illustration.
Figure 6.1. Si560 (5×7 mm) PCB Land Pattern
Table 6.1. PCB Land Pattern Dimensions (mm)
Dimension
(mm)
4.20
2.54
1.55
1.95
C1
E
X1
Y1
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a
Fabrication Allowance of 0.05 mm.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
silabs.com | Building a more connected world.
Rev. 1.0 | 13
Si560 Data Sheet
PCB Land Pattern
6.2 PCB Land Pattern (3.2×5 mm)
The figure below illustrates the 3.2×5.0 mm PCB land pattern for the Si560. The table below lists the values for the dimensions shown
in the illustration.
Figure 6.2. Si560 (3.2×5 mm) PCB Land Pattern
Table 6.2. PCB Land Pattern Dimensions (mm)
Dimension
(mm)
2.60
1.27
0.80
1.70
C1
E
X1
Y1
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a
Fabrication Allowance of 0.05 mm.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
silabs.com | Building a more connected world.
Rev. 1.0 | 14
Si560 Data Sheet
Top Marking
7. Top Marking
The figure below illustrates the mark specification for the Si560. The table below lists the line information.
Figure 7.1. Mark Specification
Table 7.1. Si560 Top Mark Description
Line
Position
1–8
Description
1
2
"Si560", xxx = Ordering Option 1, Option 2, Option 3 (e.g. Si560AAA)
1–7
Frequency Code
(e.g. 100M000 or 6-digit custom code as described in the Ordering Guide)
3
Trace Code
Pin 1 orientation mark (dot)
Product Revision (B)
Position 1
Position 2
Position 3–5
Position 6–7
Position 8–9
Tiny Trace Code (3 alphanumeric characters per assembly release instructions)
Year (last two digits of the year), to be assigned by assembly site (ex: 2017 = 17)
Calendar Work Week number (1–53), to be assigned by assembly site
silabs.com | Building a more connected world.
Rev. 1.0 | 15
Si560 Data Sheet
Revision History
8. Revision History
Revision 1.0
June, 2018
• Initial release.
silabs.com | Building a more connected world.
Rev. 1.0 | 16
ClockBuilder Pro
One-click access to Timing tools,
documentation, software, source
code libraries & more. Available for
Windows and iOS (CBGo only).
www.silabs.com/CBPro
Timing Portfolio
www.silabs.com/timing
SW/HW
www.silabs.com/CBPro
Quality
www.silabs.com/quality
Support and Community
community.silabs.com
Disclaimer
Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or
intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"
parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes
without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included
information. Silicon Labs shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted
hereunder to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any Life Support System without the specific written consent of
Silicon Labs. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant
personal injury or death. Silicon Labs products are not designed or authorized for military applications. Silicon Labs products shall under no circumstances be used in weapons of mass
destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.
Trademark Information
Silicon Laboratories Inc.® , Silicon Laboratories®, Silicon Labs®, SiLabs® and the Silicon Labs logo®, Bluegiga®, Bluegiga Logo®, Clockbuilder®, CMEMS®, DSPLL®, EFM®,
EFM32®, EFR, Ember®, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZRadio®, EZRadioPRO®,
Gecko®, ISOmodem®, Micrium, Precision32®, ProSLIC®, Simplicity Studio®, SiPHY®, Telegesis, the Telegesis Logo®, USBXpress®, Zentri, Z-Wave, and others are trademarks or
registered trademarks of Silicon Labs. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited.
All other products or brand names mentioned herein are trademarks of their respective holders.
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
USA
http://www.silabs.com
相关型号：
©2020 ICPDF网 联系我们和版权申明