571AJA001757DGR_技术文档

Si570/Si571

10 MHZ TO 1.4 GHZ I²C PROGRAMMABLE XO/VCXO

Features



Any programmable output

frequencies from 10 to 945 MHz and

select frequencies to 1.4 GHz



Internal fixed crystal frequency

ensures high reliability and low

aging

Si5602

2



Available LVPECL, CMOS,

LVDS, and CML outputs

Industry-standard 5x7 mm

package

Pb-free/RoHS-compliant

1.8, 2.5, or 3.3 V supply



I C serial interface

®

3rd generation DSPLL with superior

jitter performance

3x better frequency stability than

SAW-based oscillators



Applications

Ordering Information:



SONET/SDH

xDSL

10 GbE LAN/WAN

ATE



High performance

instrumentation

Low-jitter clock generation

Optical modules

Clock and data recovery

See page 32.



Pin Assignments:

See page 31.

Description

(Top View)

®

The Si570 XO/Si571 VCXO utilizes Silicon Laboratories’ advanced DSPLL

circuitry to provide a low-jitter clock at any frequency. The Si570/Si571 are user-

programmable to any output frequency from 10 to 945 MHz and select frequencies

SDA

7

2

NC

V_DD

1

2

3

6

5

4

to 1400 MHz with <1 ppb resolution. The device is programmed via an I C serial

interface. Unlike traditional XO/VCXOs where a different crystal is required for

each output frequency, the Si57x uses one fixed-frequency crystal and a DSPLL

clock synthesis IC to provide any-frequency operation. This IC-based approach

allows the crystal resonator to provide exceptional frequency stability and

reliability. In addition, DSPLL clock synthesis provides superior supply noise

rejection, simplifying the task of generating low-jitter clocks in noisy environments

typically found in communication systems.

OE

CLK–

CLK+

GND

8

SCL

Functional Block Diagram

Si570

CLK- CLK+

V_DD

SDA

7

OE

V_C

V_DD

1

2

3

6

5

4

10-1400 MHz

DSPLL^Clock

Synthesis

Fixed

Frequency

XO

SDA

SCL

OE

CLK–

CLK+

Si571 only

GND

ADC

8

SCL

GND

Si571

V_C

Rev. 1.5 4/14

Si570/Si571

2

Rev. 1.5

Si570/Si571

TABLE OF CONTENTS

Section

Page

1. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.1. Programming a New Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.2. Si570 Programming Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

3.3. Si570 Troubleshooting FAQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

3.4. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

4. Serial Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

5. Si570 (XO) Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

6. Si571 (VCXO) Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

7. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

8. Si57x Mark Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

9. Outline Diagram and Suggested Pad Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

10. 8-Pin PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Rev. 1.5

3

Si570/Si571

1. Detailed Block Diagrams

V_DD

GND

f_XTAL

M

CLKOUT+

CLKOUT–

DCO

÷HS_DIV

÷N1

+

f_osc

RFREQ

Frequency

Control

OE

Control

Interface

SDA

SCL

NVM

RAM

Figure 1. Si570 Detailed Block Diagram

V_DD

GND

f_XTAL

M

CLKOUT+

CLKOUT–

V_C

ADC

DCO

÷HS_DIV

÷N1

+

f_osc

VCADC

RFREQ

Frequency

Control

OE

SDA

SCL

Control

Interface

NVM

RAM

Figure 2. Si571 Detailed Block Diagram

4

Rev. 1.5

Si570/Si571

2. Electrical Specifications

Table 1. Recommended Operating Conditions

Symbol

Test Condition

3.3 V option

2.5 V option

1.8 V option

Min

2.97

2.25

1.71

Typ

3.3

2.5

1.8

Max

3.63

2.75

1.89

Unit

Parameter

Supply Voltage¹

V_DD

V

Output enabled

LVPECL

CML

—

130

117

108

98

120

108

99

Supply Current

I_DD

mA

LVDS

CMOS

90

TriState mode

—

0.75 x V_DD

—

60

—

75

—

Output Enable (OE)²,

Serial Data (SDA),

Serial Clock (SCL)

V_IH

V_IL

V

0.5

Operating Temperature Range

T_A

–40

—

85

ºC

Notes:

1. Selectable parameter specified by part number. See Section "7. Ordering Information" on page 32 for further details.

2. OE pin includes a 17 k pullup resistor to V_DD. See “7.Ordering Information”.

Table 2. V_CControl Voltage Input (Si571)

Symbol

Test Condition

Min

Typ

Max

Unit

Parameter

33

45

90

Control Voltage Tuning Slope^1,2,3

K_V

V_C10 to 90% of V_DD

—

ppm/V

135

180

356

BSL

–5

–10

9.3

500

—

±1

±5

+5

+10

10.7

—

Control Voltage Linearity⁴

L_VC

%

Incremental

Modulation Bandwidth

V_CInput Impedance

Nominal Control Voltage⁵

Control Voltage Tuning Range

Notes:

BW

Z_VC

10.0

—

kHz

k

V

V_CNOM

V_C

@ f_O

V_DD/2

—

0

V_DD

V

1. Positive slope; selectable option by part number. See "7. Ordering Information" on page 32.

2. For best jitter and phase noise performance, always choose the smallest K_Vthat meets the application’s minimum APR

requirements. See “AN266: VCXO Tuning Slope (K_V), Stability, and Absolute Pull Range (APR)” for more information.

3. K_Vvariation is ±10% of typical values.

4. BSL determined from deviation from best straight line fit with V_Cranging from 10 to 90% of V_DD. Incremental slope is

determined with V_Cranging from 10 to 90% of V_DD

.

5. Nominal output frequency set by V_CNOM= 1/2 x V_DD

.

Rev. 1.5

5

Si570/Si571

Table 3. CLK± Output Frequency Characteristics

Parameter

Symbol

Test Condition

LVPECL/LVDS/CML

CMOS

Min

10

Typ

—

Max

1417.5

160

Unit

Programmable Frequency

Range^1,2

f_O

MHz

10

—

–7

–20

–50

–100

—

7

+20

+50

+100

Temperature Stability^1,3

T_A= –40 to +85 ºC

ppm

—

1.5

—

±3

ppm

ms

Initial Accuracy

Aging

Frequency drift over first year

Frequency drift over 20-year life

Temp stability = ±7 ppm

f_a

—

±10

±20

±31.5

±61.5

±375

10

—

Total Stability

Temp stability = ±20 ppm

Temp stability = ±50 ppm

—

Absolute Pull Range^1,3

APR

t_OSC

±12

—

Power up Time⁴

Notes:

1. See Section "7. Ordering Information" on page 32 for further details.

2. Specified at time of order by part number. Three speed grades available:

Grade A covers 10 to 945 MHz, 970 to 1134 MHz, and 1213 to 1417.5 MHz.

Grade B covers 10 to 810 MHz.

Grade C covers 10 to 280 MHz.

3. Selectable parameter specified by part number.

4. Time from power up or tristate mode to f_O.

6

Rev. 1.5

Si570/Si571

Table 4. CLK± Output Levels and Symmetry

Parameter

Symbol

V_O

Test Condition

mid-level

Min

V_DD– 1.42

1.1

Typ

—

Max

V_DD– 1.25

1.9

Unit

V

LVPECL Output Option¹

—

V_OD

V_SE

swing (diff)

V_PP

swing (single-ended)

mid-level

0.55

—

0.95

V_O

1.125

0.5

1.20

0.7

1.275

0.9

V

LVDS Output Option²

CML Output Option²

swing (diff)

V_OD

V_O

V_PP

2.5/3.3 V option mid-level

1.8 V option mid-level

2.5/3.3 V option swing (diff)

1.8 V option swing (diff)

I_OH= 32 mA

—

V_DD– 1.30

—

V

V_DD– 0.36

1.10

0.35

0.8 x V_DD

—

1.50

0.425

—

1.90

0.50

V_DD

0.4

350

—

V_PP

V

V_OD

V_OH

V_OL

CMOS Output Option³

Rise/Fall time (20/80%)

I_OL= 32 mA

—

V

LVPECL/LVDS/CML

CMOS with C_L= 15 pF

—

ps

ns

t

_R,t_F

—

1

LVPECL:

LVDS:

V

_DD– 1.3 V (diff)

SYM

45

—

55

%

Symmetry (duty cycle)

1.25 V (diff)

CMOS:

V

_DD/2

Notes:

1. R_term= 50  to V_DD– 2.0 V.

2. R_term= 100  (differential).

3. C_L= 15 pF

Rev. 1.5

7

Si570/Si571

Table 5. CLK± Output Phase Jitter (Si570)

Parameter

Symbol

Test Condition

Min

—

Typ

0.25

0.26

0.36

0.34

0.62

0.61

Max

0.40

0.37

0.50

0.42

—

Unit

Phase Jitter (RMS)¹

for F_OUT> 500 MHz

_J

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)²

12 kHz to 20 MHz (OC-48)²

50 kHz to 20 MHz²

ps

—

Phase Jitter (RMS)¹

for F_OUTof 125 to 500 MHz

_J

—

ps

—

Phase Jitter (RMS)

for F_OUTof 10 to 160 MHz

CMOS Output Only

—

Notes:

1. Refer to AN256 for further information.

2. Max offset frequencies:

80 MHz for FOUT > 250 MHz

20 MHz for 50 MHz < FOUT <250 MHz

2 MHz for 10 MHz < FOUT <50 MHz.

8

Rev. 1.5

Si570/Si571

Table 6. CLK± Output Phase Jitter (Si571)

Parameter

Phase Jitter (RMS)^1,2,3

for F_OUT> 500 MHz

Symbol

Test Condition

Kv = 33 ppm/V

Min

Typ

Max

Unit

_J

ps

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.26

—

Kv = 45 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.27

0.26

—

Kv = 90 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.32

0.26

—

Kv = 135 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.40

0.27

—

Kv = 180 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.49

0.28

—

Kv = 356 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.87

0.33

—

Notes:

1. Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information.

2. For best jitter and phase noise performance, always choose the smallest K_Vthat meets the application’s minimum APR

requirements. See “AN266: VCXO Tuning Slope (kV), Stability, and Absolute Pull Range (APR)” for more information.

3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply

rejection (PSR) advantage of Si55x versus SAW-based solutions.

4. Single ended mode: CMOS. Refer to the following application notes for further information:

“AN255: Replacing 622 MHz VCSO Devices with the Si55x VCXO”

“AN256: Integrated Phase Noise”

“AN266: VCXO Tuning Slope (kV), Stability, and Absolute Pull Range (APR)”

5. Max offset frequencies:

80 MHz for F_OUT> 250 MHz

20 MHz for 50 MHz < F_OUT<250 MHz

2 MHz for 10 MHz < F_OUT<50 MHz.

Rev. 1.5

9

Si570/Si571

Table 6. CLK± Output Phase Jitter (Si571) (Continued)

Parameter

Symbol

Test Condition

Kv = 33 ppm/V

Min

Typ

Max

Unit

Phase Jitter (RMS)^2,4,5

for F_OUT10 to 160 MHz

CMOS Output Only

_J

ps

12 kHz to 20 MHz (OC-48)

50 kHz to 20 MHz

—

0.63

0.62

—

Kv = 45 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 20 MHz

—

0.63

0.62

—

Kv = 90 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 20 MHz

—

0.67

0.66

—

Kv = 135 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 20 MHz

—

0.74

0.72

—

Kv = 180 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 20 MHz

—

0.83

0.8

—

Kv = 356 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 20 MHz

—

1.26

1.2

—

Notes:

1. Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information.

2. For best jitter and phase noise performance, always choose the smallest K_Vthat meets the application’s minimum APR

requirements. See “AN266: VCXO Tuning Slope (kV), Stability, and Absolute Pull Range (APR)” for more information.

3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply

rejection (PSR) advantage of Si55x versus SAW-based solutions.

4. Single ended mode: CMOS. Refer to the following application notes for further information:

“AN255: Replacing 622 MHz VCSO Devices with the Si55x VCXO”

“AN256: Integrated Phase Noise”

“AN266: VCXO Tuning Slope (kV), Stability, and Absolute Pull Range (APR)”

5. Max offset frequencies:

80 MHz for F_OUT> 250 MHz

20 MHz for 50 MHz < F_OUT<250 MHz

2 MHz for 10 MHz < F_OUT<50 MHz.

10

Rev. 1.5

Si570/Si571

Table 6. CLK± Output Phase Jitter (Si571) (Continued)

Parameter

Symbol

Test Condition

Kv = 33 ppm/V

Min

Typ

Max

Unit

Phase Jitter (RMS)^1,2,3,5

for F_OUTof 125 to

500 MHz

_J

ps

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.37

0.33

—

Kv = 45 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.37

0.33

—

Kv = 90 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.43

0.34

—

Kv = 135 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.50

0.34

—

Kv = 180 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

0.59

0.35

—

Kv = 356 ppm/V

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

1.00

0.39

—

Notes:

1. Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information.

2. For best jitter and phase noise performance, always choose the smallest K_Vthat meets the application’s minimum APR

requirements. See “AN266: VCXO Tuning Slope (kV), Stability, and Absolute Pull Range (APR)” for more information.

3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply

rejection (PSR) advantage of Si55x versus SAW-based solutions.

4. Single ended mode: CMOS. Refer to the following application notes for further information:

“AN255: Replacing 622 MHz VCSO Devices with the Si55x VCXO”

“AN256: Integrated Phase Noise”

“AN266: VCXO Tuning Slope (kV), Stability, and Absolute Pull Range (APR)”

5. Max offset frequencies:

80 MHz for F_OUT> 250 MHz

20 MHz for 50 MHz < F_OUT<250 MHz

2 MHz for 10 MHz < F_OUT<50 MHz.

Table 7. CLK± Output Period Jitter

Parameter

Symbol

Test Condition

RMS

Min

—

Typ

2

Max

—

Unit

J_PER

ps

Period Jitter*

Peak-to-Peak

—

14

—

*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to “AN279: Estimating Period Jitter

from Phase Noise” for further information.

Rev. 1.5

11

Si570/Si571

Table 8. Typical CLK± Output Phase Noise (Si570)

Offset Frequency (f)

120.00 MHz

LVDS

156.25 MHz

LVPECL

622.08 MHz

LVPECL

Unit

100 Hz

1 kHz

10 kHz

100 kHz

1 MHz

–112

–122

–132

–137

–144

–150

n/a

–105

–122

–128

–135

–144

–147

n/a

–97

–107

–116

–121

–134

–146

–148

dBc/Hz

10 MHz

100 MHz

Table 9. Typical CLK± Output Phase Noise (Si571)

Offset Frequency (f)

74.25 MHz

90 ppm/V

LVPECL

491.52 MHz

45 ppm/V

LVPECL

622.08 MHz

135 ppm/V

LVPECL

Unit

100 Hz

1 kHz

10 kHz

100 kHz

1 MHz

–87

–114

–132

–142

–148

–150

n/a

–75

–65

–90

–100

–116

–124

–135

–146

–147

–109

–121

–134

–146

–147

dBc/Hz

10 MHz

100 MHz

Table 10. Environmental Compliance

(The Si570/571 meets the following qualification test requirements.)

Parameter

Conditions/Test Method

MIL-STD-883, Method 2002

MIL-STD-883, Method 2007

MIL-STD-883, Method 2003

MIL-STD-883, Method 1014

MIL-STD-883, Method 2036

J-STD-020, MSL1

Mechanical Shock

Mechanical Vibration

Solderability

Gross and Fine Leak

Resistance to Solder Heat

Moisture Sensitivity Level

Contact Pads

Gold over Nickel

12

Rev. 1.5

Si570/Si571

Table 11. Programming Constraints and Timing

(V_DD= 3.3 V ±10%, T_A= –40 to 85 ºC)

Parameter

Symbol

CKO_F

M_RES

Test Condition

Min

10

Typ

—

Max

945

Unit

MHz

HS_DIV x N1 > = 6

HS_DIV = 5

N1 = 1

970

—

1134

Output Frequency Range

HS_DIV = 4

N1 = 1

1.2125

—

1.4175

—

GHz

ppb

Frequency Reprogramming

Resolution

f_xtal= 114.285 MHz

0.09

Internal Oscillator Frequency

f_OSC

4850

—

5670

—

MHz

Internal Crystal Frequency

Accuracy

f_XTAL

Maximum variation is

±2000 ppm

114.285

Delta Frequency for

Continuous Output

From center frequency –3500

—

+3500

10

ppm

ms

µs

Unfreeze to NewFreq

Timeout

—

Settling Time for Small

Frequency Change

<±3500 ppm from

center frequency

—

100

10

Settling Time for Large

Frequency Change

>±3500 ppm from

center frequency after

setting NewFreq bit

ms

Table 12. Thermal Characteristics

(Typical values TA = 25 ºC, V_DD= 3.3 V)

Parameter

Symbol

Test Condition

Min

Typ

84.6

38.8

—

Max

Unit

Thermal Resistance Junction to Ambient

Thermal Resistance Junction to Case

Ambient Temperature



Still Air

—

°C/W

°C

JA



JC

T_A

T_J

–40

—

85

Junction Temperature

—

125

°C

Rev. 1.5

13

Si570/Si571

Table 13. Absolute Maximum Ratings^1,2

Parameter

Symbol

V_DD

V_I

Rating

–0.5 to +1.9

–0.5 to +3.8

–0.5 to V_DD+ 0.3

–55 to +125

>2000

Unit

Supply Voltage, 1.8 V Option

Supply Voltage, 2.5/3.3 V Option

Input Voltage

V

ºC

Storage Temperature

T_S

ESD Sensitivity (HBM, per JESD22-A114)

Soldering Temperature (Lead-free Profile)

Soldering Temperature Time @ T_PEAK(Lead-free Profile)

Notes:

ESD

T_PEAK

t_P

V

260

ºC

20–40

seconds

1. Stresses beyond the absolute maximum ratings may cause permanent damage to the device. Functional operation or

specification compliance is not implied at these conditions.

2. The device is compliant with JEDEC J-STD-020. Refer to packaging FAQ available for download at

www.siliconlabs.com/VCXO for further information, including soldering profiles.

14

Rev. 1.5

Si570/Si571

As shown in Figure 3, the device allows reprogramming

of the DCO frequency up to ±3500 ppm from the center

3. Functional Description

The Si570 XO and the Si571 VCXO are low-jitter frequency configuration without interruption to the

oscillators ideally suited for applications requiring output clock. Changes greater than the ±3500 ppm

programmable frequencies. The Si57x can be window will cause the device to recalibrate its internal

programmed to generate virtually any output clock in tuning circuitry, forcing the output clock to momentarily

the range of 10 MHz to 1.4 GHz. Output jitter stop and start at any arbitrary point during a clock cycle.

performance complies with and exceeds the strict This re-calibration process establishes a new center

requirements of high-speed communication systems frequency and can take up to 10 ms. Circuitry receiving

including OC-192/STM-64 and 10 Gigabit Ethernet a clock from the Si57x device that is sensitive to glitches

(10 GbE).

or runt pulses may have to be reset once the

recalibration process is complete.

The Si57x consists of a digitally-controlled oscillator

(DCO) based on Silicon Laboratories' third-generation 3.1.1. Reconfiguring the Output Clock for a Small

DSPLL technology, which is driven by an internal fixed- Change in Frequency

frequency crystal reference.

For output changes less than ±3500 ppm from the

The device's default output frequency is set at the center frequency configuration, the DCO frequency is

factory and can be reprogrammed through the two-wire the only value that needs reprogramming. Since

I²C serial port. Once the device is powered down, it will f_DCO= f_XTALx RFREQ, and that f_XTALis fixed, changing

return to its factory-set default output frequency.

the DCO frequency is as simple as reconfiguring the

RFREQ value as outlined below:

While the Si570 outputs a fixed frequency, the Si571

has a pullable output frequency using the voltage 1. Using the serial port, read the current RFREQ value

control input pin. This makes the Si571 an ideal choice

for high-performance, low-jitter, phase-locked loops.

(addresses 7–12 for all Si571 devices and Si570

devices with 20 ppm and 50 ppm temperature

stability; or addresses 13–18 for Si570 devices with

7 ppm temperature stability).

3.1. Programming a New Output

Frequency

2. Calculate the new value of RFREQ given the change

in frequency.

The output frequency (f_out

)

is determined by

programming the DCO frequency (f_DCO) and the

device's output dividers (HS_DIV, N1). The output

frequency is calculated using the following equation:

f_{out_new}

------------------------



RFREQ_new= RFREQ_current

f_{out_current}

f_DCO

f_XTAL RFREQ

------------------------------------------

HSDIV  N1

3. Using the serial port, write the new RFREQ value

(addresses 7–12 for all Si571 devices and Si570

devices with 20 ppm and 50 ppm temperature

stability; or addresses 13–18 for Si570 devices with

7 ppm temperature stability).

----------------------------------------

Output Dividers

f_out

=

The DCO frequency is adjustable in the range of 4.85 to

5.67 GHz by setting the high-resolution 38-bit fractional

multiplier (RFREQ). The DCO frequency is the product

of the internal fixed-frequency crystal (f_XTAL) and

RFREQ.

Example:

An Si570 generating a 148.35 MHz clock must be

reconfigured "on-the-fly" to generate a 148.5 MHz clock.

This represents a change of +1011.122 ppm, which is

well within the ±3500 ppm window.

The 38-bit resolution of RFREQ allows the DCO

frequency to have a programmable frequency resolution

of 0.09 ppb.

Center

Frequency

Configuration

small frequency changes can be made

“on-the-fly” without interruption to the

output clock

-3500 ppm

+3500 ppm

5.67 GHz

4.85 GHz

Figure 3. DCO Frequency Range

Rev. 1.5

15

Si570/Si571

A typical frequency configuration for this example:

RFREQ_current= 0x2EBB04CE0

F_out HSDIV  N1

--------------------------------------------------

RFREQ

f_XTAL

=

F

_{out_current}= 148.35 MHz

_{out_new}= 148.50 MHz

Once f_XTALhas been determined, new values for

RFREQ, HSDIV, and N1 are calculated to generate a

new output frequency (f_{out_new}). New values can be

calculated manually or with the Si57x-EVB software,

which provides a user-friendly application to help find

the optimum values.

Calculate RFREQ_newto change the output frequency

from 148.35 MHz to 148.5 MHz:

148.50 MHz

148.35 MHz

-------------------------------

RFREQ_new= 0x2EBB04CE0 

= 0x2EC71D666

The first step in manually calculating the frequency

configuration is to determine new frequency divider

values (HSDIV, N1). Given the desired output frequency

(fout_new), find the frequency divider values that will

keep the DCO oscillation frequency in the range of 4.85

to 5.67 GHz.

Note: Performing calculations with RFREQ requires a mini-

mum of 38-bit arithmetic precision.

Even relatively small changes in output frequency may

require writing more than 1 RFREQ register. Such multi-

register RFREQ writes can impact the output clock

f_{DCO_new}= f_{out_new} HSDIV_new N1_new

frequency on

updating.

a

register-by-register basis during

Valid values of HSDIV are 4, 5, 6, 7, 9 or 11. N1 can be

selected as 1 or any even number up to 128 (i.e. 1, 2, 4,

6, 8, 10 … 128). To help minimize the device's power

consumption, the divider values should be selected to

keep the DCO's oscillation frequency as low as

possible. The lowest value of N1 with the highest value

of HS_DIV also results in the best power savings.

Interim changes to the output clock during RFREQ

writes can be prevented by using the following

procedure:

1. Freeze the “M” value (Set Register 135 bit 5 = 1).

2. Write the new frequency configuration (RFREQ).

3. Unfreeze the “M” value (Set Register 135 bit 5 = 0)

Once HS_DIV and N1 have been determined, the next

step is to calculate the reference frequency multiplier

(RFREQ).

3.1.2. Reconfiguring the Output Clock for Large

Changes in Output Frequency

For output frequency changes outside of ±3500 ppm

from the center frequency, it is likely that both the DCO

frequency and the output dividers need to be

reprogrammed. Note that changing the DCO frequency

outside of the ±3500 ppm window will cause the output

to momentarily stop and restart at any arbitrary point in

a clock cycle. Devices sensitive to glitches or runt

pulses may have to be reset once reconfiguration is

complete.

f_{DCO_new}

----------------------

=

RFREQ_new

f_XTAL

RFREQ is programmable as a 38-bit binary fractional

frequency multiplier with the first 10 most significant bits

(MSBs) representing the integer portion of the multiplier,

and the 28 least significant bits (LSBs) representing the

fractional portion.

Before entering a fractional number into the RFREQ

register, it must be converted to a 38-bit integer using a

bitwise left shift operation by 28 bits, which effectively

multiplies RFREQ by 2²⁸.

The process for reconfiguring the output frequency

outside of a ±3500 ppm window first requires reading

the current RFREQ, HSDIV, and N1 values. Next,

calculate fXTAL for the device. Note that, due to slight

variations of the internal crystal frequency from one

device to another, each device may have a different

RFREQ value or possibly even different HSDIV or N1

values to maintain the same output frequency. It is

necessary to calculate fXTAL for each device. Third,

write the new values back to the device using the

appropriate registers (addresses 7–12 for all Si571

devices and Si570 devices with 20 ppm and 50 ppm

temperature stability; or addresses 13–18 for Si570

devices with 7 ppm temperature stability) sequencing as

described in “3.1.2.1.Writing the New Frequency

Configuration”.

Example:

RFREQ = 46.043042064d

Multiply RFREQ by 2²⁸= 12359584992.1

Discard the fractional portion = 12359584992

Convert to hexadecimal = 02E0B04CE0h

In the example above, the multiplication operation

requires 38-bit precision. If 38-bit arithmetic precision is

not available, then the fractional portion can be

separated from the integer and shifted to the left by 28-

bits. The result is concatenated with the integer portion

16

Rev. 1.5

Si570/Si571

to form a full 38-bit word. An example of this operation is shown in Figure 4.

46.043042064

Multiply the fractional portion by 2²⁸

.043042064 x 2²⁸= 11554016.077

Truncate the remaining fractional portion

= 11554016

Convert integer portion to a 10-bit binary number

46 = 00 0010 1110b

Convert to a 28-bit binary number (pad 0s on the left)

0000 1011 0000 0100 1100 1110 0000

Concatenate the two results

00 0010 1110 0000 1011 0000 0100 1100 1110 0000b

Convert to Hex

02E0B04CE0h

Figure 4. Example of RFREQ Decimal to Hexadecimal Conversion

3.1.2.1. Writing the New Frequency Configuration

Once the new values for RFREQ, HSDIV, and N1 are determined, they can be written directly into the device from

the serial port using the following procedure:

1. Freeze the DCO (bit 4 of Register 137)

2. Write the new frequency configuration (RFREQ, HSDIV, and N1) to addresses 7–12 for all Si571 devices and

Si570 devices with 20 ppm and 50 ppm temperature stability; or addresses 13–18 for Si570 devices with 7 ppm

temperature stability.

3. Unfreeze the DCO and assert the NewFreq bit (bit 6 of Register 135) within the maximum Unfreeze to NewFreq

Timeout specified in Table 11, “Programming Constraints and Timing,” on page 13.

The process of freezing and unfreezing the DCO will cause the output clock to momentarily stop and start at any

arbitrary point during a clock cycle. This process can take up to 10 ms. Circuitry that is sensitive to glitches or runt

pulses may have to be reset after the new frequency configuration is written.

Example:

An Si570 generating 156.25 MHz must be re-configured to generate a 161.1328125 MHz clock (156.25 MHz x 66/

64). This frequency change is greater than ±3500 ppm.

f_out= 156.25 MHz

Read the current values for RFREQ, HS_DIV, N1:

RFREQ_current= 0x2BC011EB8h = 11744124600d, 11744124600d x 2²⁸= 43.7502734363d

HS_DIV = 4

N1 = 8

Calculate f_XTAL, f_{DCO_current}

f_{DCO_current}= f_out HSDV  N1 = 5.000000000 GHz

f_{DCO_current}

--------------------------------------

= 114.285 MHz

f_XTAL

=

RFREQ_current

Rev. 1.5

17

Si570/Si571

Given f_{out_new}= 161.1328125 MHz, choose output dividers that will keep f_DCOwithin the range of 4.85 to

5.67 GHz. In this case, keeping the same output dividers will still keep f_DCOwithin its range limits:

f_{DCO_new}= f_{out_new} HSDV_new N1_new

= 161.1328125 MHz  4  8 = 5.156250000 GHz

Calculate the new value of RFREQ given the new DCO frequency:

f_{DCO_new}

----------------------

= 45.11746948

RFREQ_new

=

f_XTAL

= 0x2D1E127AD

18

Rev. 1.5

Si570/Si571

3.2. Si570 Programming Procedure

This following example was generated using Si514/70/71/98/99 Programmable Oscillator Software V4.0.1 found

under the Tools tab at the following web page.

http://www.siliconlabs.com/products/clocksoscillators/oscillators/Pages/i2c-oscillator.aspx

On that same web page, the AN334 Si57x I2C XO/VCXO ANSI C Reference Design contains example C code for

calculating register settings on the fly.

1. Read start-up frequency configuration (RFREQ, HS_DIV, and N1) from the device after power-up or register

reset.

Registers for the Current Configuration

Register

Data

0x01

0xC2

0xBC

0x01

0x1E

0xB8

7

8

9

10

11

12

RFREQ = 0x2BC011EB8

= 0x2BC011EB8 / (2^28) = 43.75027344

HS_DIV = 0x0 = 4

N1 = 0x7 = 8

2. Calculate the actual nominal crystal frequency where f0 is the start-up output frequency.

fxtal = ( f0 x HS_DIV x N1 ) / RFREQ

= (156.250000000 MHz x 4 x 8) / 43.750273436

= 114.285000000 MHz

3. Choose the new output frequency (f1).

Output Frequency (f1) = 161.132812000 MHz

4. Choose the output dividers for the new frequency configuration (HS_DIV and N1) by ensuring the DCO

oscillation frequency (fdco) is between 4.85 GHz and 5.67 GHz where fdco = f1 x HS_DIV x N1. See the Divider

Combinations tab for more options.

HS_DIV = 0x0 = 4

N1

= 0x7 = 8

fdco = f1 x HS_DIV x N1

= 161.132812000 MHz x 4 x 8

= 5.156249984 GHz

Rev. 1.5

19

Si570/Si571

5. Calculate the new crystal frequency multiplication ratio (RFREQ) as RFREQ = fdco / fxtal

RFREQ = fdco / fxtal

= 5.156249984 GHz / 114.285000000 MHz

= 45.11746934

= 45.11746934 x (2^28) = 0x2D1E12788

6. Freeze the DCO by setting Freeze DCO = 1 (bit 4 of register 137).

7. Write the new frequency configuration (RFREQ, HS_DIV, and N1)

Registers for the New Configuration

Register

Data

0x01

0xC2

0xD1

0xE1

0x27

0x88

7

8

9

10

11

12

8. Unfreeze the DCO by setting Freeze DCO = 0 and assert the NewFreq bit (bit 6 of register 135) within 10 ms.

20

Rev. 1.5

Si570/Si571

3.3. Si570 Troubleshooting FAQ

2

1. Is the I C bus working correctly and using the correct I C address?

Probing the device I²C pins with an oscilloscope can sometimes reveal signal integrity problems. Si570/Si571 I²C

communication is normally very robust, so if other devices on the I²C bus are communicating successfully, then the

Si570/Si571 should also work.

You can confirm the specific I²C address expected by an Si570/Si571 device by using the part number lookup

utility available on the Silicon Laboratories web site.

http://www.silabs.com/custom-timing

2. Is the correct register bank being written based on device stability?

Si570/Si571 devices use different configuration registers for 7 ppm temperature stability devices than they do for

20 ppm or 50 ppm temperature stability devices. The temperature stability of a Si570/Si571 device can be

confirmed using the part number lookup utility available on the Silicon Laboratories web site or by referencing the

2nd ordering option code in the part number.

http://www.silabs.com/custom-timing

2nd Ordering Option Code:

A : 50 ppm temperature stability, 61.5 ppm total stability => Configuration Registers 7-12

B : 20 ppm temperature stability, 31.5 ppm total stability => Configuration Registers 7-12

C : 7 ppm temperature stability, 20 ppm total stability => Configuration Registers 13-18

3. Is the part-to-part variation in FXTAL included in calculations?

It is required that one determine the internal crystal frequency for each individual part before calculating a new

output frequency. The procedure for determining the internal crystal frequency from the register values of a device

is described elsewhere in this data sheet. See Section 3.2.

FXTAL = (FOUT x HSDIV x N1) / RFREQ <= note that RFREQ used here is the

register value divided by 2^28

It is a common error to calculate the internal crystal frequency for one device and then use that same crystal

frequency for all later devices. This will lead to offset errors in the output frequency accuracy from part-to-part. The

internal crystal frequency must be calculated for each individual device.

4. Is the Unfreeze to NewFreq timeout spec being exceeded?

The Si570/Si571 requires the DCO to be 'frozen' when changing register values and then 'unfrozen' and a

calibration initiated by writing the 'NewFreq' bit to restart it properly. If the 'unfreeze' and 'NewFreq' writes are

delayed by 10 ms or more, the internal state machine can timeout and cause the configuration to revert to default

values.

This 'unfreeze' and 'NewFreq' timing requirement is not usually a problem since the writes are done back-to-back,

but if there is an interrupt or other system delay that may cause this 10 ms timing to be exceeded, it should be

considered as a possible source of issues reprogramming the Si570/Si571.

Rev. 1.5

21

Si570/Si571

2

3.4. I C Interface

The control interface to the Si570 is an I²C-compatible 2-wire bus for bidirectional communication. The bus

consists of a bidirectional serial data line (SDA) and a serial clock input (SCL). Both lines must be connected to the

positive supply via an external pullup. Fast mode operation is supported for transfer rates up to 400 kbps as

specified in the I²C-Bus Specification standard.

Figure 5 shows the command format for both read and write access. Data is always sent MSB. Data length is 1

byte. Read and write commands support 1 or more data bytes as illustrated. The master must send a Not

Acknowledge and a Stop after the last read data byte to terminate the read command. The timing specifications

and timing diagram for the I²C bus can be found in the I²C-Bus Specification standard (fast mode operation). The

device I²C address is specified in the part number.

S Slave Address

0

A Byte Address

A

Data

A

Data

P

Write Command

(Optional 2^nddata byte and acknowledge illustrated)

A Byte Address

Data

S Slave Address

0

A

Data

A

Slave Address

N

P

S

1

A

Read Command

(Optional data byte and acknowledge before the last data byte and not acknowledge illustrated)

From master to slave

From slave to master

A – Acknowledge (SDA LOW)

N – Not Acknowledge (SDA HIGH).

Required after the last data byte to signal the end of the read comand to the slave.

S – START condition

P – STOP condition

Figure 5. I²C Command Format

22

Rev. 1.5

Si570/Si571

4. Serial Port Registers

Note: Any register not listed here is reserved and must not be written. All bits are R/W unless otherwise noted.

Register

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

7

High Speed/

N1 Dividers

HS_DIV[2:0]

N1[6:2]

8

9

Reference

Frequency

N1[1:0]

RFREQ[37:32]

Reference

Frequency

RFREQ[31:24]

RFREQ[23:16]

RFREQ[15:8]

RFREQ[7:0]

10

11

Reference

Frequency

Reference

Frequency

12

13

14

15

16

17

18

135

137

Reference

Frequency

High Speed/

N1 Dividers

HS_DIV_7PPM[2:0]

N1_7PPM[1:0]

N1_7PPM[6:2]

Reference

Frequency

RFREQ_7PPM[37:32]

Reference

Frequency

RFREQ_7PPM[31:24]

Reference

Frequency

RFREQ_7PPM[23:16]

RFREQ_7PPM[15:8]

RFREQ_7PPM[7:0]

Reference

Frequency

Reference

Frequency

Reset/Freeze/ RST_REG NewFreq Freeze M Freeze

Memory Control

RECALL

VCADC

Freeze DCO

Freeze

DCO

Rev. 1.5

23

Si570/Si571

Register 7. High Speed/N1 Dividers

Bit

D7

D6

HS_DIV[2:0]

R/W

D5

D4

D3

D2

N1[6:2]

R/W

D1

D0

Name

Type

Bit

Name

Function

7:5

HS_DIV[2:0] DCO High Speed Divider.

Sets value for high speed divider that takes the DCO output f_OSCas its clock input.

000 = 4

001 = 5

010 = 6

011 = 7

100 = Not used.

101 = 9

110 = Not used.

111 = 11

4:0

N1[6:2]

CLKOUT Output Divider.

Sets value for CLKOUT output divider. Allowed values are [1] and [2, 4, 6, ..., 2⁷]. Illegal

odd divider values will be rounded up to the nearest even value. The value for the N1 reg-

ister can be calculated by taking the divider ratio minus one. For example, to divide by 10,

write 0001001 (9 decimal) to the N1 registers.

0000000 = 1

1111111 = 2⁷

Register 8. Reference Frequency

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

N1[1:0]

R/W

RFREQ[37:32]

R/W

Bit

Name

Function

7:6

N1[1:0]

CLKOUT Output Divider.

Sets value for CLKOUT output divider. Allowed values are [1, 2, 4, 6, ..., 2⁷]. Illegal odd

divider values will be rounded up to the nearest even value. The value for the N1 regis-

ter can be calculated by taking the divider ratio minus one. For example, to divide by

10, write 0001001 (9 decimal) to the N1 registers.

0000000 = 1

1111111 = 2⁷

5:0

RFREQ[37:32] Reference Frequency.

Frequency control input to DCO.

24

Rev. 1.5

Si570/Si571

Register 9. Reference Frequency

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

RFREQ[31:24]

R/W

Bit

Name

Function

7:0

RFREQ[31:24]

Reference Frequency.

Frequency control input to DCO.

Register 10. Reference Frequency

Bit

D7

D6

D5

D4

D3

Name

Type

RFREQ[23:16]

R/W

Bit

Name

Function

7:0

RFREQ[23:16] Reference Frequency.

Frequency control input to DCO.

Register 11. Reference Frequency

Bit

D7

D6

D5

D4

RFREQ[15:8]

R/W

D3

Name

Type

Bit

Name

Function

7:0

RFREQ[15:8] Reference Frequency.

Frequency control input to DCO.

Rev. 1.5

25

Si570/Si571

Register 12. Reference Frequency

Bit

D7

D6

D5

D4

RFREQ[7:0]

R/W

D3

D2

D1

D0

Name

Type

Bit

Name

Function

7:0

RFREQ[7:0]

Reference Frequency.

Frequency control input to DCO.

Register 13. High Speed/N1 Dividers

Bit

D7

D6

HS_DIV_7PPM[2:0]

R/W

D5

D4

D3

D2

D1

D0

Name

Type

N1_7PPM[6:2]

R/W

Bit

Name

Function

7:5 HS_DIV_7PPM[2:0] DCO High Speed Divider.

Sets value for high speed divider that takes the DCO output f_OSCas its clock input.

000 = 4

001 = 5

010 = 6

011 = 7

100 = Not used.

101 = 9

110 = Not used.

111 = 11

4:0

N1_7PPM[6:2]

CLKOUT Output Divider.

Sets value for CLKOUT output divider. Allowed values are [1] and [2, 4, 6, ..., 2⁷]. Ille-

gal odd divider values will be rounded up to the nearest even value. The value for the

N1 register can be calculated by taking the divider ratio minus one. For example, to

divide by 10, write 0001001 (9 decimal) to the N1 registers.

0000000 = 1

1111111 = 2⁷

Register 14. Reference Frequency

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

N1_7PPM[1:0]

R/W

RFREQ_7PPM[37:32]

R/W

26

Rev. 1.5

Si570/Si571

Bit

Name

Function

7:6

N1_7PPM[1:0]

CLKOUT Output Divider.

Sets value for CLKOUT output divider. Allowed values are [1, 2, 4, 6, ..., 2⁷]. Illegal

odd divider values will be rounded up to the nearest even value. The value for the

N1 register can be calculated by taking the divider ratio minus one. For example, to

divide by 10, write 0001001 (9 decimal) to the N1 registers.

0000000 = 1

1111111 = 2⁷

5:0 RFREQ_7PPM[37:32] Reference Frequency.

Frequency control input to DCO.

Register 15. Reference Frequency

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

RFREQ_7PPM[31:24]

R/W

Bit

Name

Function

7:0 RFREQ_7PPM[31:24] Reference Frequency.

Frequency control input to DCO.

Register 16. Reference Frequency

Bit

D7

D6

D5

D4

D3

Name

Type

RFREQ_7PPM[23:16]

R/W

Bit

Name

Function

7:0 RFREQ_7PPM[23:16] Reference Frequency.

Frequency control input to DCO.

Register 17. Reference Frequency

Bit

D7

D6

D5

D4

D3

Name

Type

RFREQ_7PPM[15:8]

R/W

Rev. 1.5

27

Si570/Si571

Bit

7:0 RFREQ_7PPM[15:8] Reference Frequency.

Frequency control input to DCO.

Name

Function

Register 18. Reference Frequency

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

RFREQ_7PPM[7:0]

R/W

Bit

Name

Function

7:0 RFREQ_7PPM[7:0] Reference Frequency.

Frequency control input to DCO.

28

Rev. 1.5

Si570/Si571

Register 135. Reset/Freeze/Memory Control

Bit

Name RST_REG NewFreq

Type R/W R/W

Reset settings = 00xx xx00

D7

D6

D5

D4

D3

D2

N/A

R/W

D1

D0

RECALL

R/W

Freeze M Freeze VCADC

R/W

Bit

Name

Function

7

RST_REG

Internal Reset.

0 = Normal operation.

1 = Reset of all internal logic. Output tristated during reset.

Upon completion of internal logic reset, RST_REG is internally reset to zero.

Note: Asserting RST_REG will interrupt the I²C state machine. It is not the recommended

approach for starting from initial conditions.

6

NewFreq

Freeze M

New Frequency Applied.

Alerts the DSPLL that a new frequency configuration has been applied. This bit will

clear itself when the new frequency is applied.

5

4

Freezes the M Control Word.

Prevents interim frequency changes when writing RFREQ registers.

Freezes the VC ADC Output Word.

Freeze

VCADC

May be used to hold the nominal output frequency of an Si571.

3:1

0

N/A

Always Zero.

RECALL

Recall NVM into RAM.

0 = No operation.

1 = Write NVM bits into RAM. Bit is internally reset following completion of operation.

Note: Asserting RECALL reloads the NVM contents in to the operating registers without

interrupting the I²C state machine. It is the recommended approach for starting from

initial conditions.

Register 137. Freeze DCO

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Freeze

DCO

Type

R/W

Reset settings = 00xx xx00

Bit

Name

Function

7:5

4

Reserved

Freeze DCO Freeze DCO.

Freezes the DSPLL so the frequency configuration can be modified.

3:0

Reserved

Rev. 1.5

29

Si570/Si571

5. Si570 (XO) Pin Descriptions

(Top View)

SDA

7

NC

V_DD

1

2

3

6

5

4

OE

CLK–

CLK+

GND

8

SCL

Table 14. Si570 Pin Descriptions

Type

Name

Function

1

NC

N/A

No Connect. Make no external connection to this pin.

Output Enable:

See "7. Ordering Information" on page 32.

2

OE

Input

3

4

GND

Ground

Output

Electrical and Case Ground.

Oscillator Output.

CLK+

CLK–

(NC for CMOS*)

Complementary Output.

5

(N/A for CMOS*) (NC for CMOS*).

6

7

V_DD

Power

Power Supply Voltage.

SDA

Bidirectional

Open Drain

I²C Serial Data.

8

SCL

Input

I²C Serial Clock.

*Note: CMOS output option only: make no external connection to this pin.

30

Rev. 1.5

Si570/Si571

6. Si571 (VCXO) Pin Descriptions

(Top View)

SDA

7

V_C

V_DD

1

6

5

4

OE

2

3

CLK–

CLK+

GND

8

SCL

Table 15. Si571 Pin Descriptions

Type

Name

Function

1

V_C

Analog Input

Input

Control Voltage

Output Enable:

2

OE

See "7. Ordering Information" on page 32.

Electrical and Case Ground

3

4

GND

Ground

Output

CLK+

Oscillator Output

CLK–

(NC for CMOS*)

Complementary Output.

(N/A for CMOS*) (NC for CMOS*).

5

6

7

V_DD

Power

Power Supply Voltage

I²C Serial Data

SDA

Bidirectional

Open Drain

8

SCL

Input

I²C Serial Clock

*Note: CMOS output option only: make no external connection to this pin.

Rev. 1.5

31

Si570/Si571

7. Ordering Information

The Si570/Si571 supports a wide variety of options including frequency range, start-up frequency, temperature

stability, tuning slope, output format, and V_DD. Specific device configurations are programmed into the Si570/Si571

at time of shipment. Configurations are specified using the Part Number Configuration chart shown below. Silicon

Labs provides a web browser-based part number configuration utility to simplify this process. Refer to

www.siliconlabs.com/VCXOPartNumber to access this tool and for further ordering instructions. The Si570/Si571

XO/VCXO series is supplied in an industry-standard, RoHS compliant, 8-pad, 5 x 7 mm package. Tape and reel

packaging is an ordering option.

57x

X

D

G

R

XXX XXX

X

R = Tape & Reel

Blank = Trays

Operating Temp Range (°C)

–40 to +85 °C

570 Programmable

XO Product Family

G

Device Revision Letter

571 Programmable

VCXO Product Family

Six-Digit Start-up Frequency/I²C Address Designator

The Si57x supports a user-defined start-up frequency within the following

bands of frequencies: 10–945 MHz, 970–1134 MHz, and 1213–1417 MHz.

The start-up frequency must be in the same frequency range as that

specified by the Frequency Grade 3^rdoption code.

1^stOption Code

The Si57x supports a user-defined I²C 7-bit address. Each unique start-up

frequency/I²C address combination is assigned a six-digit numerical code.

This code can be requested during the part number request process. Refer

to www.silabs.com/VCXOPartNumber to request an Si57x part number.

V_DDOutput Format Output Enable Polarity

A

B

C

D

E

F

G

H

J

K

M

N

P

Q

R

S

T

3.3 LVPECL

3.3 LVDS

3.3 CMOS

3.3 CML

2.5 LVPECL

2.5 LVDS

2.5 CMOS

2.5 CML

1.8 CMOS

1.8 CML

3.3 LVPECL

3.3 LVDS

3.3 CMOS

3.3 CML

2.5 LVPECL

2.5 LVDS

2.5 CMOS

2.5 CML

1.8 CMOS

1.8 CML

High

Low

3^rdOption Code

Frequency Grade

Code

Frequency Range Supported (MHz)

10-945, 970-1134, 1213-1417.5

10-810

A

B

C

10-280 (CMOS available to 160 MHz)

2^ndOption Code

Code Temperature Stability (ppm, max, ±) Total Stablility (ppm, max, ±)

Si570

A

B

C

50

20

7

61.5

31.5

20

U

V

W

2^ndOption Code

Temperature

Stability

± ppm (max)

Tuning Slope

Minimum APR

(±ppm) for VDD @

Note:

Kv

ppm/V (typ)

180

CMOS available to 160 MHz.

Code

A

B

C

3.3 V

100

30

150

80

2.5 V

75

Note 6

125

1.8 V

25

Note 6

75

100

50

90

180

90

D

50

30

25

E

F

G

H

J

K

M

20

50

20

100

20

45

135

356

180

135

356

33

25

Note 6

75

300

145

104

Note 6

50

235

105

70

100

375

185

130

295

12

220

Note 6

155

Note 6

Si571

Notes:

1. For best jitter and phase noise performance, always choose the smallest Kv that meets

the application’s minimum APR requirements. Unlike SAW-based solutions which

require higher higher Kv values to account for their higher temperature dependence,

the Si55x series provides lower Kv options to minimize noise coupling and jitter in real-

world PLL designs. See AN255 and AN266 for more information.

2. APR is the ability of a VCXO to track a signal over the product lifetime. A VCXO with an

APR of ±25 ppm is able to lock to a clock with a ±25 ppm stability over 15 years over all

operating conditions.

3. Nominal Pull range (±) = 0.5 x V_DDx tuning slope.

4. Nominal Absolute Pull Range (±APR) = Pull range – stability – lifetime aging

= 0.5 x V_DDx tuning slope – stability – 10 ppm

5. Minimum APR values noted above include worst case values for all parameters.

6. Combination not available.

Figure 6. Part Number Convention

32

Rev. 1.5

Si570/Si571

8. Si57x Mark Specification

Figure 7 illustrates the mark specification for the Si57x. Table 16 lists the line information.

Figure 7. Mark Specification

Table 16. Si57x Top Mark Description

Line

Position

Description

1

1–10

“SiLabs”+ Part Family Number, 57x (First 3 characters in part number where x = 0

indicates a 570 device and x = 1 indicates a 571 device)

2

3

1–10

Si570, Si571: Option1 + Option2 + Option3 + ConfigNum(6) + Temp

Trace Code

Pin 1 orientation mark (dot)

Position 1

Position 2

Product Revision (D)

Tiny Trace Code (4 alphanumeric characters per assembly release instructions)

Year (least significant year digit), to be assigned by assembly site (ex: 2007 = 7)

Calendar Work Week number (1–53), to be assigned by assembly site

“+” to indicate Pb-Free and RoHS-compliant

Position 3–6

Position 7

Position 8–9

Position 10

Rev. 1.5

33

Si570/Si571

9. Outline Diagram and Suggested Pad Layout

Figure 8 illustrates the package details for the Si570/Si571. Table 17 lists the values for the dimensions shown in

the illustration.

Figure 8. Si570/Si571 Outline Diagram

Table 17. Package Diagram Dimensions (mm)

Dimension

Min

1.50

1.30

0.90

0.50

0.30

Nom

1.65

1.40

1.00

0.60

—

Max

1.80

1.50

1.10

0.70

0.60

A

b

b1

c

c1

D

D1

e

E

E1

H

L

L1

p

5.00 BSC

4.40

2.54 BSC

7.00 BSC

6.20

4.30

4.50

6.10

0.55

1.17

1.07

1.80

6.30

0.75

1.37

1.27

2.60

0.65

1.27

1.17

—

R

0.70 REF

—

aaa

bbb

ccc

ddd

eee

—

0.15

0.10

0.05

—

Note:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

34

Rev. 1.5

Si570/Si571

10. 8-Pin PCB Land Pattern

Figure 9 illustrates the 8-pin PCB land pattern for the Si570/Si571. Table 18 lists the values for the dimensions

shown in the illustration.

Figure 9. Si570/Si571 PCB Land Pattern

Table 18. PCB Land Pattern Dimensions (mm)

Dimension

Min

Max

D2

D3

5.08 REF

5.705 REF

2.54 BSC

4.20 REF

e

E2

GD

GE

VD

VE

0.84

2.00

—

8.20 REF

7.30 REF

1.70 TYP

1.545 TYP

2.15 REF

1.3 REF

X1

X2

Y1

Y2

ZD

—

6.78

6.30

ZE

Note:

1. Dimensioning and tolerancing per the ANSI Y14.5M-1994

specification.

2. Land pattern design follows IPC-7351 guidelines.

3. All dimensions shown are at maximum material condition

(MMC).

4. Controlling dimension is in millimeters (mm).

Rev. 1.5

35

Si570/Si571

 Added text to "3. Functional Description" on page 15,

paragraph 1, to state that the total output jitter

complies to and exceeds strict requirements of

various high-speed communication systems.

DOCUMENT CHANGE LIST

Revision 1.0 to Revision 1.1

 Restored programming constraint information on

page 15 and in Table 12, page 12.

Revision 1.3 to Revision 1.4

 Clarified NC (No Connect) pin designations in Tables

 Added Table 12, “Thermal Characteristics,” on

13–14 on pages 22–23.

page 13.

Revision 1.1 to Revision 1.2

Revision 1.4 to Revision 1.5

 Replaced “Unfreeze to Newfreq Delay” with the

clearer terminology “Unfreeze to Newfreq Timeout”

on page 15 and in Table 11 on page 13.

 Added Section 3.2 and 3.3.

 Added Freeze M procedure on page 14 for

preventing output clock changes during small

frequency change multi-register RFREQ writes.

 Added Freeze M, Freeze VCADC, and RST_REG

versus RECALL information to Register 135

references in "4. Serial Port Registers" on pages 17

and 20.

 Added Si570 20 ppm Total Stability Ordering Option

to Figure 6 on page 32.

 Updated Figure 8 and Table 17 on page 34 to

include production test sidepads. This change is for

reference only as the sidepads are raised above the

seating plane and do not impact PCB layout.

 Corrected errors in Table 10 on page 12.

Revision 1.2 to Revision 1.3

 Updated Table 3 on page 6 to include 7 ppm

temperature stability and 20 ppm to stability

parameters. Also changed aging test condition

(frequency drift over life) from 15 years to 20 years.

 Updated 2.5 V/3.3 V and 1.8 V CML output level

specification for Table 4 on page 7.

 Added footnotes clarifying max offset frequency test

conditions in Table 5 on page 8.

 Updated ESD HBM sensitivity rating and the JEDEC

standard in Note 2 in Table 13 on page 14.

 Updated Table 10 on page 12 to include "Moisture

Sensitivity Level" and "Contact Pads" rows.

 Added Si570 7 ppm Total Stability Ordering Option to

Figure 6 on page 32.

 Updated Figure 7 and Table 16 on page 33 to reflect

specific marking information. Previously, Figure 7

was generic.

 Clarified "3.1.2. Reconfiguring the Output Clock for

Large Changes in Output Frequency" on page 16

and added new registers 13-18 in "4. Serial Port

Registers" on page 23 for the Si570 7 ppm

temperature stability / 20 ppm total stability ordering

option.

36

Rev. 1.5

ClockBuilder Pro

One-click access to Timing tools,

documentation, software, source

code libraries & more. Available for

Windows and iOS (CBGo only).

www.silabs.com/CBPro

Timing Portfolio

www.silabs.com/timing

SW/HW

www.silabs.com/CBPro

Quality

www.silabs.com/quality

Support and Community

community.silabs.com

Disclaimer

Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using

or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and

"Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories reserves the right to

make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the

included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses

granted hereunder to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any Life Support System without the specific written consent

of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant

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型号：	571AJA001757DGR
厂家：	SILICON
描述：	LVPECL Output Clock Oscillator, 振荡器
文件：	总37页 (文件大小：552K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

571AJA001757DGR [SILICON]

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