590AA810M000DGR [SILICON]

LVPECL Output Clock Oscillator;


型号：	590AA810M000DGR
厂家：	SILICON
描述：	LVPECL Output Clock Oscillator 机械输出元件振荡器
文件：	总12页 (文件大小：313K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Si590/591

1 ps MAX JITTER CRYSTAL OSCILLATOR (XO)

(10 MHZ TO 810 MHZ)

Features

Si5602



Available with any-frequency output

frequencies from 10 to 810 MHz



Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

–40 to +85 ºC operating

temperature range



3rd generation DSPLL with superior

jitter performance: 1 ps max jitter

Better frequency stability than SAW-

based oscillators



Internal fundamental mode crystal

ensures high reliability

Ordering Information:

Applications

See page 7.



SONET/SDH (OC-3/12/48)

Networking

SD/HD SDI/3G SDI video



Test and measurement

Storage

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

Description

(Top View)

The Si590/591 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si590/591 supports any

frequency from 10 to 810 MHz. Unlike a traditional XO, where a unique

crystal is required for each output frequency, the Si590/591 uses one fixed

crystal to provide a wide range of output frequencies. This IC based

approach allows the crystal resonator to provide exceptional frequency

stability and reliability. In addition, DSPLL clock synthesis provides superior

supply noise rejection, simplifying the task of generating low jitter clocks in

noisy environments typically found in communication systems. The

Si590/591 IC based XO is factory configurable for a wide variety of user

specifications including frequency, supply voltage, output format, and

stability. Specific configurations are factory programmed at time of shipment,

thereby eliminating long lead times associated with custom oscillators.

V_DD

CLK–

CLK+

GND

Si590 (LVDS/LVPECL/CML)

V_DD

Functional Block Diagram

V_DD

CLK– CLK+

GND

CLK

Si590 (CMOS)

17 k*

Any-rate

10–810 MHz

DSPLL^®

Clock

Synthesis

Fixed

Frequency

V_DD

CLK–

CLK+

17 k*

GND

Si591 (LVDS/LVPECL/CML)

*Note: Output Enable High/Low Options Available – See Ordering Information

GND

Rev. 1.0 8/11

Si590/591

1. Electrical Specifications

Table 1. Recommended Operating Conditions

Symbol

Test Condition

Min

Typ

Max

Units

Parameter

3.3 V option

2.5 V option

1.8 V option

2.97

2.25

1.71

3.3

2.5

1.8

3.63

2.75

1.89

Supply Voltage

Supply Current

Output enabled

LVPECL

CML

—

110

100

125

110

100

LVDS

CMOS

Tristate mode

—

0.75 x V

—

Output Enable (OE)

0.5

Operating Temperature Range

–40

ºC

Notes:

1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 7 for further details.

2. OE pin includes an internal 17 k pullup resistor to V_DDfor output enable active high or a 17 k pull-down resistor to

GND for output enable active low. See 3. "Ordering Information" on page 7.

Table 2. CLK± Output Frequency Characteristics

Symbol

Test Condition

Min

Typ

Max

Units

Parameter

Nominal Frequency^1,2

LVPECL/LVDS/CML

CMOS

—

810

160

MHz

Initial Accuracy

Total Stability

Measured at +25 °C at time of

shipping

f_i

—

±1.5

—

ppm

Note 3, second option code “D”

Note 3, second option code “C”

Note 4, second option code “B”

Note 4, second option code “A”

second option code “D”

—

±20

±30

±50

±100

±7

ppm

Temperature Stability

second option code “C”

±20

±25

±50

second option code “B”

second option code “A”

Powerup Time⁵

t_OSC

Notes:

1. See Section 3. "Ordering Information" on page 7 for further details.

2. Specified at time of order by part number.

3. Includes initial accuracy, temperature, shock, vibration, power supply and load drift, and 10 years aging at 40 °C. See

3. "Ordering Information" on page 7.

4. Includes initial accuracy, temperature, shock, vibration, power supply and load drift, and 15 years aging at 70 °C. See

3. "Ordering Information" on page 7.

5. Time from powerup or tristate mode to f_O.

Rev. 1.0

Si590/591

Table 3. CLK± Output Levels and Symmetry

Symbol

Test Condition

Min

Typ

Max

Units

Parameter

mid-level

swing (diff)

V_DD– 1.42

1.1

—

V_DD– 1.25

1.9

LVPECL Output Option

V_OD

V_SE

V_PP

swing (single-ended)

mid-level

0.55

0.95

LVDS Output Option

1.125

0.5

1.20

0.7

1.275

0.9

swing (diff)

V_OD

V_O

V_PP

2.5/3.3 V option mid-level

1.8 V option mid-level

—

– 1.30

—

– 0.36

CML Output Option

2.5/3.3 V option swing (diff)

1.8 V option swing (diff)

1.10

1.50

1.90

V_OD

V_PP

0.35

0.425

—

0.50

V_DD

0.4

CMOS Output Option

V_OH

V_OL

0.8 x V_DD

—

Rise/Fall time (20/80%)

Symmetry (duty cycle)

t_{R, F}

LVPECL/LVDS/CML

—

350

—

CMOS with C = 15 pF

SYM

LVPECL:

LVDS:

CMOS:

– 1.3 V (diff)

1.25 V (diff)

—

Notes:

1. 50  to V_DD– 2.0 V.

2. R_term= 100  (differential).

3. C_L= 15 pF. Sinking or sourcing 12 mA for V_DD= 3.3 V, 6 mA for V_DD= 2.5 V, 3 mA for V_DD= 1.8 V.

Table 4. CLK± Output Phase Jitter

Parameter

Symbol

Test Condition

Min

Typ

Max Units

Phase Jitter (RMS)

_J

12 kHz to 20 MHz

—

0.5

1.0

for 50 MHz < F

< 810 MHz

OUT

(LVPECL/LVDS/CML)

Phase Jitter (RMS)

_J

12 kHz to 20 MHz,

155.52 MHz output frequency

—

0.4

0.6

0.7

1.0

(LVPECL/LVDS/CML)

Phase Jitter (RMS)

12 kHz to 20 MHz

for 50 MHz < F

(CMOS)

< 160 MHz

OUT

Notes:

1. Refer to AN256 for further information.

2. Single-ended CMOS output phase jitter measured using 33  series termination into 50  phase noise test equipment.

3.3 V supply voltage option only.

Rev. 1.0

Si590/591

Table 5. CLK± Output Period Jitter

Parameter

Symbol

Test Condition

RMS

Min

—

Typ

—

Max

Units

Period Jitter*

PER

Peak-to-Peak

—

*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.

^\Table 6. Environmental Compliance and Package Information

Parameter

Conditions/Test Method

MIL-STD-883, Method 2002

MIL-STD-883, Method 2007

MIL-STD-883, Method 2003

MIL-STD-883, Method 1014

MIL-STD-883, Method 2036

J-STD-020, MSL1

Mechanical Shock

Mechanical Vibration

Solderability

Gross and Fine Leak

Resistance to Solder Heat

Moisture Sensitivity Level

Contact Pads

Gold over Nickel

Table 7. Thermal Characteristics

(Typical values T_A= 25 ºC, V_DD= 3.3 V)

Parameter

Symbol

Test Condition

Still Air

Min

—

Typ

84.6

38.8

—

Max

—

Unit

°C/W

°C

Thermal Resistance Junction to Ambient

Thermal Resistance Junction to Case

Ambient Temperature



Still Air

—

–40

—

Junction Temperature

—

125

°C

Rev. 1.0

Si590/591

Table 8. Absolute Maximum Ratings¹

Symbol

Rating

Units

Parameter

Maximum Operating Temperature

Supply Voltage, 1.8 V Option

Supply Voltage, 2.5/3.3 V Option

Input Voltage (any input pin)

Storage Temperature

ºC

AMAX

–0.5 to +1.9

–0.5 to +3.8

–0.5 to V + 0.3

ºC

–55 to +125

2500

ESD Sensitivity (HBM, per JESD22-A114)

ESD

Soldering Temperature (Pb-free profile)

260

ºC

PEAK

Soldering Temperature Time @ T

(Pb-free profile)

20–40

seconds

PEAK

Notes:

1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional

operation or specification compliance is not implied at these conditions. Exposure to maximum rating conditions for

extended periods may affect device reliability.

2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download at

www.silabs.com/VCXO for further information, including soldering profiles.

Rev. 1.0

Si590/591

2. Pin Descriptions

(Top View)

V_DD

CLK–

CLK+

CLK–

CLK+

GND

CLK

Si591

LVDS/LVPECL/CML

Si590

LVDS/LVPECL/CML

CMOS

Table 9. Pinout for Si590 Series

Symbol

LVDS/LVPECL/CML Function

No connection

Make no external connection to this pin

CMOS Function

Output enable

OE*

Output enable

No connection

OE*

Make no external connection to this pin

Electrical and Case Ground

Oscillator Output

GND

CLK+

CLK–

Electrical and Case Ground

Oscillator Output

Complementary Output

No connection

Make no external connection to this pin

Power Supply Voltage

*Note: OE pin includes an internal 17 k pullup resistor to V_DDfor output enable active high or a 17 k pulldown resistor to

GND for output enable active low. See 3. "Ordering Information" on page 7.

Table 10. Pinout for Si591 Series

Symbol

LVDS/LVPECL/CML Function

OE*

Output enable

No connection

Make no external connection to this pin

No connection

Make no external connection to this pin

GND

CLK+

CLK–

Electrical and Case Ground

Oscillator Output

Complementary output

Power Supply Voltage

*Note: OE pin includes an internal 17 k pullup resistor to V_DDfor output enable active high or a 17 k pulldown resistor to

GND for output enable active low. See 3. "Ordering Information" on page 7.

Rev. 1.0

Si590/591

3. Ordering Information

The Si590/591 XO supports a variety of options including frequency, temperature stability, output format, and V

Specific device configurations are programmed into the Si590/591 at time of shipment. Configurations can be

specified using the Part Number Configuration chart below. Silicon Laboratories provides a web browser-based

part number configuration utility to simplify this process. Refer to www.silabs.com/VCXOPartNumber to access this

tool and for further ordering instructions. The Si590 and Si591 XO series are supplied in an industry-standard,

RoHS compliant, 6-pad, 5 x 7 mm package. The Si591 Series supports an alternate OE pinout (pin #1) for

LVPECL, LVDS, and CML output formats. See Tables 9 and 10 for the pinout differences between the Si590 and

Si591 series.

59x

XXXMXXX

Tape & Reel Packaging

Blank = Trays

590 or 591 XO

Product Family

Operating Temp Range (°C)

–40 to +85°C

1^stOption Code

V_DDOutput Format Output Enable Polarity

Part Revision Letter

Frequency (e.g., 148M352 is 148.352 MHz)

3.3 LVPECL

3.3 LVDS

3.3 CMOS

3.3 CML

High

Low

Available frequency range is 10 to 810 MHz. The position of “M” shifts

to denote higher or lower frequencies. If the frequency of interest

requires greater than 6 digit resolution, a six digit code will be

assigned for the specific frequency.

2.5 LVPECL

2.5 LVDS

2.5 CMOS

2.5 CML

2^ndOption Code

1.8 CMOS

1.8 CML

Code

Total Stablility (ppm, max, ±) Temperature Stablility (ppm, max, ±)

3.3 LVPECL

3.3 LVDS

3.3 CMOS

3.3 CML

100

2.5 LVPECL

2.5 LVDS

2.5 CMOS

2.5 CML

1.8 CMOS

1.8 CML

Note:

CMOS available to 160 MHz.

Example P/N: 590BB148M352DGR is a 5 x 7 XO in a 6 pad package. The frequency is 148.352 MHz, with a 3.3 V supply, LVDS output, and

Output Enable active high polarity. Overall stability is specifed as ±50 ppm. The device is specified for –40 to +85 °C ambient temperature

range operation and is shipped in tape and reel format.

Figure 1. Part Number Convention

Rev. 1.0

Si590/591

4. Outline Diagram and Suggested Pad Layout

Figure 2 illustrates the package details for the Si590/591. Table 11 lists the values for the dimensions shown in the

illustration.

Figure 2. Si590/591 Outline Diagram

Table 11. Package Diagram Dimensions (mm)

Dimension

Min

1.50

1.30

0.50

Nom

1.65

Max

1.80

1.50

0.70

1.40

0.60

5.00 BSC

4.40

4.30

4.50

2.54 BSC

7.00 BSC

6.20

6.10

0.55

1.17

1.80

6.30

0.75

1.37

2.60

0.65

1.27

—

0.70 REF

0.15

aaa

bbb

ccc

ddd

eee

0.15

0.10

0.50

Rev. 1.0

Si590/591

5. 6-Pin PCB Land Pattern

Figure 3 illustrates the 6-pin PCB land pattern for the Si590/591. Table 12 lists the values for the dimensions shown

in the illustration.

Figure 3. Si590/591 PCB Land Pattern

Table 12. PCB Land Pattern Dimensions (mm)

Dimension

Min

Max

5.08 REF

2.54 BSC

4.15 REF

0.84

2.00

—

8.20 REF

7.30 REF

1.70 TYP

2.15 REF

—

6.78

6.30

Notes:

1. Dimensioning and tolerancing per the ANSI Y14.5M-1994 specification.

2. Land pattern design based on IPC-7351 guidelines.

3. All dimensions shown are at maximum material condition (MMC).

4. Controlling dimension is in millimeters (mm).

Rev. 1.0

Si590/591

6. Si590/Si591 Top Marking

Figure 4 illustrates the mark specification for the Si590/Si591. Table 13 lists the line information.

Figure 4. Top Mark Specification

Table 13. Si59x Top Mark Description

Line

Position

Description

1–10

“SiLabs”+ Part Family Number, 59x (First 3 characters in part number where x = 0

indicates a 590 device and x = 1 indicates a 591 device)

1–10

Si590, Si591: Option1 + Option2 + Freq(7) + Temp

Si590/Si591 w/ 8-digit resolution: Option1 + Option2 + ConfigNum(6) + Temp

Trace Code

Position 1

Pin 1 orientation mark (dot)

Product Revision (D)

Position 2

Tiny Trace Code (4 alphanumeric characters per assembly release instructions)

Year (least significant year digit), to be assigned by assembly site (ex: 2009 = 9)

Calendar Work Week number (1–53), to be assigned by assembly site

“+” to indicate Pb-Free and RoHS-compliant

Position 3–6

Position 7

Position 8–9

Position 10

Rev. 1.0

Si590/591

DOCUMENT CHANGE LIST

Revision 0.2 to Revision 0.25



Total Stability Maximum changed to ±30 in Table 2

on page 2.



Total Stability Maximum changed to ±30 in Figure 1

on page 7.

Revision 0.25 to Revision 0.3



Updated Table 4 on page 3 by adding the

155.51 MHz “Phase Jitter (RMS)

(LVPECL/LVDS/CML)” row.

Updated and clarified Table 6 on page 4 to correct

typos and include the “Moisture Sensitivity Level”

and “Contact Pads” rows.

Corrected BSC value in rows D and E in Table 11 on

page 8.

Revision 0.3 to Revision 0.4



Added ±7 ppm temperature stability ordering option

in Table 4 on page 3 and Figure 1 on page 7.

Revision 0.4 to Revision 1.0



Updated 2.5 V/3.3 V and 1.8 V CML output level

specifications in Table 3 on page 3.



Updated Si590/591 devices to support frequencies

up to 810 MHz for LVPECL, LVDS, and CML

outputs.



Separated 1.8 V, 2.5 V/3.3 V supply voltage.

specifications for CML output in Table 3 on page 3.

Updated Note 1 of Table 4 on page 3 to refer to

AN256.

Updated Table 4 on page 3.

Updated phase jitter specification.

Updated Table 6 on page 4 to include the "Moisture

Sensitivity Level" and "Contact Pads" rows.

Updated Figure 3 and Table 13 on page 10 to reflect

specific marking information.

Added Table 7, “Thermal Characteristics,” on

page 4.

Rearranged sections to conform to new quality

standard.

Rev. 1.0

ClockBuilder Pro

One-click access to Timing tools,

documentation, software, source

code libraries & more. Available for

Windows and iOS (CBGo only).

www.silabs.com/CBPro

Timing Portfolio

www.silabs.com/timing

SW/HW

www.silabs.com/CBPro

Quality

www.silabs.com/quality

Support and Community

community.silabs.com

Disclaimer

Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using

or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and

"Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories reserves the right to

make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the

included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses

granted hereunder to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any Life Support System without the specific written consent

of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant

personal injury or death. Silicon Laboratories products are not designed or authorized for military applications. Silicon Laboratories products shall under no circumstances be used in

weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.

Trademark Information

Silicon Laboratories Inc.® , Silicon Laboratories®, Silicon Labs®, SiLabs® and the Silicon Labs logo®, Bluegiga®, Bluegiga Logo®, Clockbuilder®, CMEMS®, DSPLL®, EFM®, EFM32®,

EFR, Ember®, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZRadio®, EZRadioPRO®, Gecko®,

ISOmodem®, Precision32®, ProSLIC®, Simplicity Studio®, SiPHY®, Telegesis, the Telegesis Logo®, USBXpress® and others are trademarks or registered trademarks of Silicon Laborato-

ries Inc. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited. All other products or brand

names mentioned herein are trademarks of their respective holders.

Silicon Laboratories Inc.

400 West Cesar Chavez

Austin, TX 78701

USA

http://www.silabs.com

590AA810M000DGR [SILICON]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E