591FC148M352DGR [SILICON]

1 ps MAX JITTER CRYSTAL OSCILLATOR; 1个PS MAX抖动晶体振荡器


型号：	591FC148M352DGR
厂家：	SILICON
描述：	1 ps MAX JITTER CRYSTAL OSCILLATOR 1个PS MAX抖动晶体振荡器振荡器晶体振荡器
文件：	总12页 (文件大小：95K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Si590/591

1 ps MAX JITTER CRYSTAL OSCILLATOR (XO)

(10 MHZ TO 525 MHZ)

Features

Si5602



Available with any-rate output



Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

–40 to +85 ºC operating

temperature range

frequencies from 10 MHz to 525 MHz



3rd generation DSPLL with superior

jitter performance: 1 ps max jitter

Better frequency stability than SAW-

based oscillators



Internal fundamental mode crystal

ensures high reliability

Ordering Information:

Applications

See page 6.



SONET/SDH (OC-3/12/48)

Networking

SD/HD SDI/3G SDI video



Test and measurement

Storage

FPGA/ASIC clock generation

Pin Assignments:

See page 5.

Description

(Top View)

The Si590/591 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si590/591 is available

with any-rate output frequency from 10 to 525 MHz. Unlike a traditional XO,

where a unique crystal is required for each output frequency, the Si590/591

uses one fixed crystal to provide a wide range of output frequencies. This IC

based approach allows the crystal resonator to provide exceptional

frequency stability and reliability. In addition, DSPLL clock synthesis provides

superior supply noise rejection, simplifying the task of generating low jitter

clocks in noisy environments typically found in communication systems. The

Si590/591 IC based XO is factory configurable for a wide variety of user

specifications including frequency, supply voltage, output format, and

temperature stability. Specific configurations are factory programmed at time

of shipment, thereby eliminating long lead times associated with custom

oscillators.

V_DD

CLK–

CLK+

GND

Si590 (LVDS/LVPECL/CML)

V_DD

Functional Block Diagram

V_DD

CLK– CLK+

GND

CLK

Si590 (CMOS)

17 k*

V_DD

Any-rate

10–525 MHz

DSPLL^®

Clock

Synthesis

Fixed

Frequency

CLK–

CLK+

GND

17 k*

Si591 (LVDS/LVPECL/CML)

*Note: Output Enable High/Low Options Available – See Ordering Information

GND

Preliminary Rev. 0.25 7/09

Si590/591

1. Electrical Specifications

Table 1. Recommended Operating Conditions

Parameter

Symbol

Test Condition

3.3 V option

2.5 V option

1.8 V option

Min

2.97

2.25

1.71

Typ

3.3

2.5

1.8

Max

3.63

2.75

1.89

Units

Supply Voltage

Supply Current

Output enabled

LVPECL

CML

—

110

100

125

110

100

LVDS

CMOS

Tristate mode

—

0.75 x V

—

Output Enable (OE)

0.5

Operating Temperature Range

–40

ºC

Notes:

1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 6 for further details.

2. OE pin includes an internal 17 k pullup resistor to V_DDfor output enable active high or a 17 k pull-down resistor to

GND for output enable active low. See 3. "Ordering Information" on page 6.

Table 2. CLK± Output Frequency Characteristics

Parameter

Symbol

Test Condition

LVPECL/LVDS/CML

CMOS

Min

Typ

—

Max

525

160

Units

Nominal Frequency^1,2

MHz

—

Initial Accuracy

Total Stability

Measured at +25 °C at time of

shipping

f_i

—

±1.5

—

ppm

Note 3, second option code “C”

Note 4, second option code “B”

Note 4, second option code “A”

second option code “C”

—

±30

±50

±100

±20

±25

±50

ppm

Temperature Stability

second option code “B”

second option code “A”

Powerup Time⁵

t_OSC

Notes:

1. See Section 3. "Ordering Information" on page 6 for further details.

2. Specified at time of order by part number.

3. Includes initial accuracy, temperature, shock, vibration, power supply and load drift, and 10 years aging at 40 °C. See

3. "Ordering Information" on page 6.

4. Includes initial accuracy, temperature, shock, vibration, power supply and load drift, and 15 years aging at 70 °C. See

3. "Ordering Information" on page 6.

5. Time from powerup or tristate mode to f_O.

Preliminary Rev. 0.25

Si590/591

Table 3. CLK± Output Levels and Symmetry

Parameter

Symbol

Test Condition

mid-level

Min

V_DD– 1.42

1.1

Typ

—

Max

V_DD– 1.25

1.9

Units

LVPECL Output Option

V_OD

V_SE

swing (diff)

V_PP

—

swing (single-ended)

mid-level

0.55

—

0.95

LVDS Output Option

1.125

1.20

1.275

swing (diff)

V_OD

V_O

0.5

—

0.7

0.9

—

V_PP

CML Output Option

mid-level

– 0.75

V_OD

V_OH

V_OL

swing (diff)

0.70

0.8 x V_DD

—

0.95

—

1.20

V_DD

0.4

350

—

V_PP

CMOS Output Option

—

Rise/Fall time (20/80%)

Symmetry (duty cycle)

t_{R, F}

LVPECL/LVDS/CML

—

CMOS with C = 15 pF

—

SYM

LVPECL:

LVDS:

CMOS:

– 1.3 V (diff)

—

1.25 V (diff)

Notes:

1. 50  to V_DD– 2.0 V.

2. R_term= 100  (differential).

3. C_L= 15 pF. Sinking or sourcing 12 mA for V_DD= 3.3 V, 6 mA for V_DD= 2.5 V, 3 mA for V_DD= 1.8 V.

Table 4. CLK± Output Phase Jitter

Parameter

Symbol

Test Condition

Min

Typ

Max Units

Phase Jitter (RMS)

for 50 MHz < F

_J

12 kHz to 20 MHz

—

0.5

1.0

< 525 MHz

OUT

(LVPECL/LVDS/CML)

Phase Jitter (RMS)

_J

12 kHz to 20 MHz

—

0.6

1.0

for 50 MHz < F

(CMOS)

< 160 MHz

OUT

Notes:

1. Differential Modes LVPECL/LVDS/CML. 3.3 and 2.5 V supply voltage options only.

2. Single-ended CMOS output phase jitter measured using 33  series termination into 50  phase noise test equipment.

3.3 V supply voltage option only.

Table 5. CLK± Output Period Jitter

Parameter

Period Jitter*

Symbol

Test Condition

RMS

Min

—

Typ

—

Max

Units

PER

Peak-to-Peak

—

*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.

Preliminary Rev. 0.25

Si590/591

Table 6. Absolute Maximum Ratings¹

Parameter

Maximum Operating Temperature

Supply Voltage, 1.8 V Option

Supply Voltage, 2.5/3.3 V Option

Input Voltage (any input pin)

Symbol

Rating

Units

ºC

AMAX

–0.5 to +1.9

–0.5 to +3.8

–0.5 to V + 0.3

Volts

ºC

Storage Temperature

–55 to +125

2500

ESD Sensitivity (HBM, per JESD22-A114)

ESD

Soldering Temperature (Pb-free profile)

260

ºC

PEAK

Soldering Temperature Time @ T

(Pb-free profile)

20–40

seconds

PEAK

Notes:

1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional

operation or specification compliance is not implied at these conditions. Exposure to maximum rating conditions for

extended periods may affect device reliability.

2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download at

www.silabs.com/VCXO for further information, including soldering profiles.

Table 7. Environmental Compliance

The Si590/591 meets the following qualification test requirements.

Parameter

Conditions/Test Method

MIL-STD-883G, Method 2002.3 B

MIL-STD-883G, Method 2007.3 A

MIL-STD-883G, Method 203.8

MIL-STD-883G, Method 1014.7

MIL-STD-883G, Method 2015

Mechanical Shock

Mechanical Vibration

Solderability

Gross & Fine Leak

Resistance to Solvents

Preliminary Rev. 0.25

Si590/591

2. Pin Descriptions

(Top View)

V_DD

CLK–

CLK+

CLK–

GND

CLK

CLK+

Si591

Si590

LVDS/LVPECL/CML

CMOS

Table 8. Pinout for Si590 Series

Symbol

LVDS/LVPECL/CML Function

No connection

Make no external connection to this pin

CMOS Function

Output enable

OE*

Output enable

No connection

Make no external connection to this pin

OE*

GND

CLK+

CLK–

Electrical and Case Ground

Oscillator Output

Electrical and Case Ground

Oscillator Output

Complementary Output

No connection

Make no external connection to this pin

Power Supply Voltage

*Note: OE pin includes an internal 17 k pullup resistor to V_DDfor output enable active high or a 17 k pulldown resistor to

GND for output enable active low. See 3. "Ordering Information" on page 6.

Table 9. Pinout for Si591 Series

Symbol

LVDS/LVPECL/CML Function

OE*

Output enable

No connection

Make no external connection to this pin

No connection

Make no external connection to this pin

GND

CLK+

CLK–

Electrical and Case Ground

Oscillator Output

Complementary output

Power Supply Voltage

*Note: OE pin includes an internal 17 k pullup resistor to V_DDfor output enable active high or a 17 k pulldown resistor to

GND for output enable active low. See 3. "Ordering Information" on page 6.

Preliminary Rev. 0.25

Si590/591

3. Ordering Information

The Si590/591 XO supports a variety of options including frequency, temperature stability, output format, and V

Specific device configurations are programmed into the Si590/591 at time of shipment. Configurations can be

specified using the Part Number Configuration chart below. Silicon Laboratories provides a web browser-based

part number configuration utility to simplify this process. Refer to www.silabs.com/VCXOPartNumber to access this

tool and for further ordering instructions. The Si590 and Si591 XO series are supplied in an industry-standard,

RoHS compliant, 6-pad, 5 x 7 mm package. The Si591 Series supports an alternate OE pinout (pin #1) for

LVPECL, LVDS, and CML output formats. See Tables 8 and 9 for the pinout differences between the Si590 and

Si591 series.

59x

XXXMXXX

Tape & Reel Packaging

Blank = Trays

590 or 591 XO

Product Family

Operating Temp Range (°C)

–40 to +85°C

1^stOption Code

V_DDOutput Format Output Enable Polarity

Part Revision Letter

Frequency (e.g., 148M352 is 148.352 MHz)

3.3 LVPECL

3.3 LVDS

3.3 CMOS

3.3 CML

High

Low

Available frequency range is 10 to 525 MHz. The position of “M” shifts

to denote higher or lower frequencies. If the frequency of interest

requires greater than 6 digit resolution, a six digit code will be

assigned for the specific frequency.

2.5 LVPECL

2.5 LVDS

2.5 CMOS

2.5 CML

2^ndOption Code

1.8 CMOS

1.8 CML

Code

Total Stablility (ppm, max, ±) Temperature Stablility (ppm, max, ±)

3.3 LVPECL

3.3 LVDS

3.3 CMOS

3.3 CML

100

2.5 LVPECL

2.5 LVDS

2.5 CMOS

2.5 CML

1.8 CMOS

1.8 CML

Note:

CMOS available to 160 MHz.

Example P/N: 590BB148M352DGR is a 5 x 7 XO in a 6 pad package. The frequency is 148.352 MHz, with a 3.3 V supply, LVDS output, and

Output Enable active high polarity. Overall stability is specifed as ±50 ppm. The device is specified for –40 to +85 °C ambient temperature

range operation and is shipped in tape and reel format.

Figure 1. Part Number Convention

Preliminary Rev. 0.25

Si590/591

4. Outline Diagram and Suggested Pad Layout

Figure 2 illustrates the package details for the Si590/591. Table 10 lists the values for the dimensions shown in the

illustration.

Figure 2. Si590/591 Outline Diagram

Table 10. Package Diagram Dimensions (mm)

Dimension

Min

1.50

1.30

0.50

Nom

1.65

Max

1.80

1.50

0.70

1.40

0.60

7.00 BSC

4.40

4.30

4.50

2.54 BSC.

5.00 BSC.

6.20

6.10

0.55

1.17

1.80

6.30

0.75

1.37

2.60

0.65

1.27

—

0.70 REF

0.15

aaa

bbb

ccc

ddd

eee

0.15

0.10

0.50

Preliminary Rev. 0.25

Si590/591

5. Si590/Si591 Mark Specification

Figure 3 illustrates the mark specification for the Si590/Si591. Table 11 lists the line information.

SiLabs 123

1 2 3 4 5 6 7 8 9 0

R T T T T Y W W +

Figure 3. Mark Specification

Table 11. Si53x Top Mark Description

Line

Position

1–10

Description

“SiLabs”+ Part Family Number, 59x (First 3 characters in part number)

1–10

Si590, Si591: Option1 + Option2 + Freq(7) + Temp

Si590/Si591 w/ 8-digit resolution: Option1 + Option2 + ConfigNum(6) + Temp

Trace Code

Position 1

Pin 1 orientation mark (dot)

Product Revision (D)

Position 2

Tiny Trace Code (4 alphanumeric characters per assembly release instructions)

Year (least significant year digit), to be assigned by assembly site (ex: 2009 = 9)

Calendar Work Week number (1–53), to be assigned by assembly site

“+” to indicate Pb-Free and RoHS-compliant

Position 3–6

Position 7

Position 8–9

Position 10

Preliminary Rev. 0.25

Si590/591

6. 6-Pin PCB Land Pattern

Figure 4 illustrates the 6-pin PCB land pattern for the Si590/591. Table 12 lists the values for the dimensions shown

in the illustration.

Figure 4. Si590/591 PCB Land Pattern

Table 12. PCB Land Pattern Dimensions (mm)

Dimension

Min

Max

5.08 REF

2.54 BSC

4.15 REF

0.84

2.00

—

8.20 REF

7.30 REF

1.70 TYP

2.15 REF

—

6.78

6.30

Notes:

1. Dimensioning and tolerancing per the ANSI Y14.5M-1994 specification.

2. Land pattern design based on IPC-7351 guidelines.

3. All dimensions shown are at maximum material condition (MMC).

4. Controlling dimension is in millimeters (mm).

Preliminary Rev. 0.25

Si590/591

DOCUMENT CHANGE LIST

Revision 0.2 to Revision 0.25

 Total Stability Maximum changed to ±30 in Table 2

on page 2.

 Total Stability Maximum changed to ±30 in Figure 1

on page 6.

Preliminary Rev. 0.25

Si590/591

NOTES:

Preliminary Rev. 0.25

Si590/591

CONTACT INFORMATION

Silicon Laboratories Inc.

400 West Cesar Chavez

Austin, TX 78701

Tel: 1+(512) 416-8500

Fax: 1+(512) 416-9669

Toll Free: 1+(877) 444-3032

Please visit the Silicon Labs Technical Support web page:

https://www.silabs.com/support/pages/contacttechnicalsupport.aspx

and register to submit a technical support request.

The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.

Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from

the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features

or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-

resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-

quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to

support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-

sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-

plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.

Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc.

Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.

Preliminary Rev. 0.25

591FC148M352DGR [SILICON]

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