595CD148M500DG [SILICON]

CMOS Output Clock Oscillator, 10MHz Min, 160MHz Max, 148.5MHz Nom;


型号：	595CD148M500DG
厂家：	SILICON
描述：	CMOS Output Clock Oscillator, 10MHz Min, 160MHz Max, 148.5MHz Nom 振荡器
文件：	总15页 (文件大小：295K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Si595

REVISION D

VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR (VCXO)

10 TO 810 MHZ

Features



Available with any-rate output

frequencies from 10 to 810 MHz



Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry standard 5x7 and

3.2x5 mm packages

Si5602



3rd generation DSPLL with

superior jitter performance

Internal fixed fundamental mode

crystal frequency ensures high

reliability and low aging



Pb-free/RoHS-compliant

–40 to +85 ºC operating range

Applications

Ordering Information:

See page 8.



SONET/SDH (OC-3/12/48)

Networking

SD/HD SDI/3G SDI video



FTTx

Clock recovery and jitter cleanup PLLs

FPGA/ASIC clock generation

Pin Assignments:

Description

See page 7.

The Si595 VCXO utilizes Silicon Laboratories’ advanced DSPLL circuitry to

provide a low-jitter clock at high frequencies. The Si595 is available with

any-rate output frequency from 10 to 810 MHz. Unlike traditional VCXOs,

where a different crystal is required for each output frequency, the Si595

uses one fixed crystal to provide a wide range of output frequencies. This IC-

based approach allows the crystal resonator to provide exceptional

frequency stability and reliability. In addition, DSPLL clock synthesis

provides supply noise rejection, simplifying the task of generating low-jitter

clocks in noisy environments. The Si595 IC-based VCXO is factory-

configurable for a wide variety of user specifications including frequency,

supply voltage, output format, tuning slope, and absolute pull range (APR).

Specific configurations are factory programmed at time of shipment, thereby

eliminating the long lead times associated with custom oscillators.

(Top View)

V_C

V_DD

CLK–

CLK+

GND

Functional Block Diagram

CLK– CLK+

V_DD

Any-rate

10–810 MHz

DSPLL^®

Fixed

Frequency

Clock Synthesis

ADC

GND

Rev. 1.3 12/17

Si595

1. Electrical Specifications

Table 1. Recommended Operating Conditions

Parameter

Symbol

Test Condition

3.3 V option

2.5 V option

1.8 V option

Min

2.97

2.25

1.71

Typ

3.3

2.5

1.8

Max

3.63

2.75

1.89

Units

Supply Voltage

Supply Current

Output enabled

LVPECL

CML

—

135

120

110

100

120

110

100

LVDS

CMOS

Tristate mode

—

0.75 x V

—

Output Enable (OE)

0.5

Operating Temperature Range

–40

°C

Notes:

1. Selectable parameter specified by part number. See 3. "Ordering Information" on page 8 for further details.

2. OE pin includes an internal 17 k pullup resistor to V_DDfor output enable active high or a 17 k pull-down resistor to

GND for output enable active low. See 3. "Ordering Information" on page 8.

Table 2. V_CControl Voltage Input

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

1,2,3

Control Voltage Tuning Slope

10 to 90% of V

—

ppm/V

125

185

380

Control Voltage Linearity

BSL

–5

–10

9.3

500

—

±1

±5

+10

10.7

—

Incremental

Modulation Bandwidth

10.0

—

kHz

k

V Input Impedance

V Input Capacitance

—

Nominal Control Voltage

@ f

—

V /2

—

CNOM

Control Voltage Tuning Range

Notes:

1. Positive slope; selectable option by part number. See 3. "Ordering Information" on page 8.

2. For best jitter and phase noise performance, always choose the smallest K_Vthat meets the application’s minimum APR

requirements. See “AN266: VCXO Tuning Slope (K_V), Stability, and Absolute Pull Range (APR)” for more information.

3. K_Vvariation is ±10% of typical values.

4. BSL determined from deviation from best straight line fit with V_Cranging from 10 to 90% of V_DD. Incremental slope

determined with V_Cranging from 10 to 90% of V_DD

Rev. 1.3

Si595

Table 3. CLK± Output Frequency Characteristics

Parameter

Symbol

Test Condition

LVDS/CML/LVPECL

CMOS

Min

Typ

—

Max

Units

1,2,3

1,4

810

160

Nominal Frequency

MHz

—

Temperature Stability

T = –40 to +85 ºC

–20

–50

—

+20

+50

ppm

1,4

Absolute Pull Range

APR

t_OSC

±10

—

±370

ppm

Power up Time

Notes:

1. See Section 3. "Ordering Information" on page 8 for further details.

2. Specified at time of order by part number.

3. Nominal output frequency set by V_CNOM= V_DD/2.

4. Selectable parameter specified by part number.

5. Time from power up or tristate mode to f_O.

Table 4. CLK± Output Levels and Symmetry

Parameter

Symbol

Test Condition

mid-level

Min

Typ

Max

V_DD– 1.25

1.9

Units

LVPECL Output Option

V_DD– 1.42

1.1

—

V_OD

V_SE

swing (diff)

V_PP

swing (single-ended)

mid-level

0.55

0.95

LVDS Output Option

1.125

0.5

1.20

0.7

1.275

0.9

swing (diff)

V_OD

V_O

V_PP

2.5/3.3 V option mid-level

1.8 V option mid-level

—

– 1.30

—

V_PP

– 0.36

CML Output Option

2.5/3.3 V option swing (diff)

1.8 V option swing (diff)

1.10

0.35

0.8 x V_DD

—

1.50

1.90

0.50

V_DD

0.4

350

—

V_OD

0.425

—

CMOS Output Option

V_OH

V_OL

—

Rise/Fall time (20/80%)

Symmetry (duty cycle)

t_{R, F}

LVPECL/LVDS/CML

—

CMOS with C = 15 pF

—

SYM

LVPECL:

LVDS:

CMOS:

– 1.3 V (diff)

1.25 V (diff)

—

Notes:

1. 50  to V_DD– 2.0 V.

2. R_term= 100  (differential).

3. C_L= 15 pF. Sinking or sourcing 12 mA for V_DD= 3.3 V, 6 mA for V_DD= 2.5 V, 3 mA for V_DD= 1.8 V.

Rev. 1.3

Si595

Table 5. CLK± Output Phase Jitter

Parameter

Symbol

Test Condition

Kv = 45 ppm/V

Min

—

Typ

0.5

0.7

Max

—

Units

1,2

Phase Jitter (RMS)

_J

for F

810 MHz

of 50 MHz < F

12 kHz to 20 MHz

OUT

Kv = 95 ppm/V

12 kHz to 20 MHz

—

Kv = 125 ppm/V

12 kHz to 20 MHz

—

Kv = 185 ppm/V

12 kHz to 20 MHz

—

Kv = 380 ppm/V

12 kHz to 20 MHz

—

Notes:

1. Refer to AN256 for further information.

2. For best jitter and phase noise performance, always choose the smallest K_Vthat meets the application’s minimum APR

requirements. See “AN266: VCXO Tuning Slope (K_V), Stability, and Absolute Pull Range (APR)” for more information.

Table 6. CLK± Output Period Jitter

Parameter

Period Jitter*

Symbol

Test Condition

RMS

Min

—

Typ

Max

—

Units

PER

Peak-to-Peak

—

*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.

Table 7. CLK± Output Phase Noise (Typical)

Offset Frequency

74.25 MHz

185 ppm/V

LVPECL

148.5 MHz

185 ppm/V

LVPECL

155.52 MHz

95 ppm/V

LVPECL

Units

100 Hz

1 kHz

10 kHz

100 kHz

1 MHz

–77

–68

–95

–77

–101

–121

–134

–149

–151

–150

–101

–119

–127

–144

–147

–148

–116

–128

–144

–147

–148

dBc/Hz

10 MHz

20 MHz

Rev. 1.3

Si595

Table 8. Environmental Compliance and Package Information

Parameter

Mechanical Shock

Conditions/Test Method

MIL-STD-883, Method 2002

MIL-STD-883, Method 2007

MIL-STD-883, Method 2003

MIL-STD-883, Method 1014

MIL-STD-883, Method 2036

Gold over Nickel

Mechanical Vibration

Solderability

Gross and Fine Leak

Resistance to Solder Heat

Contact Pads

Table 9. Thermal Characteristics

(Typical values TA = 25 ºC, V_DD= 3.3 V)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

5x7mm, Thermal Resistance Junction to

Ambient



Still Air

—

84.6

—

°C/W

5x7mm, Thermal Resistance Junction to

Case



Still Air

—

38.8

31.1

13.3

°C/W

3.2x5mm, Thermal Resistance Junction to

Ambient



3.2x5mm, Thermal Resistance Junction to

Case



Ambient Temperature

Junction Temperature

–40

—

°C

125

Table 10. Absolute Maximum Ratings¹

Parameter

Maximum Operating Temperature

Supply Voltage

Symbol

Rating

–0.5 to +3.8

Units

ºC

AMAX

Input Voltage

–0.5 to V + 0.3

Storage Temperature

–55 to +125

2500

ºC

ESD Sensitivity (HBM, per JESD22-A114)

ESD

Soldering Temperature (Pb-free profile)

260

ºC

PEAK

Rev. 1.3

Si595

Table 10. Absolute Maximum Ratings¹

Parameter

Symbol

Rating

Units

Soldering Temperature Time @ T

(Pb-free profile)

20–40

seconds

PEAK

Notes:

1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional

operation or specification compliance is not implied at these conditions. Exposure to maximum rating conditions for

extended periods may affect device reliability.

2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download from

www.silabs.com/VCXO for further information, including soldering profiles.

Rev. 1.3

Si595

2. Pin Descriptions

(Top View)

V_C

V_DD

CLK–

CLK+

GND

Table 11. Si595 Pin Descriptions

Type

Name

Function

Analog Input

Input

Control Voltage

Output Enable

OE*

GND

CLK+

Ground

Output

Electrical and Case Ground

Oscillator Output

CLK–

(N/C for CMOS)

Output

Complementary Output

(N/C for CMOS, do not make external connection)

Power

Power Supply Voltage

*Note: OE pin includes a 17 k resistor to V_DDfor OE active high option or 17 k to GND for OE active low option.

See 3. "Ordering Information" on page 8.

Rev. 1.3

Si595

3. Ordering Information

The Si595 supports a variety of options including frequency, temperature stability, tuning slope, output format, and

. Specific device configurations are programmed into the Si595 at time of shipment. Configurations are

specified using the Part Number Configuration chart shown below. Silicon Labs provides a web browser-based part

number configuration utility to simplify this process. To access this tool refer to www.silabs.com/oscillators and click

“Customize” in the product table. The Si595 VCXO series is supplied in industry-standard, RoHS compliant, lead-

free, 6-pad, 5 x 7 mm and 3.2 x 5 mm package. Tape and reel packaging is an ordering option.

595

XXXMXXX

R = Tape & Reel

Blank = Trays

595 VCXO

Product Family

Operating Temp Range (°C)

–40 to +85 °C

Device Revision Letter

Frequency (e.g., 148M500 is 148.5 MHz)

Available frequency range is 10 to 810 MHz. The position of “M” shifts

to denote higher or lower frequencies. If the frequency of interest

requires greater than 6 digit resolution, a six digit code will be

assigned for the specific frequency.

1^stOption Code

V_DDOutput Format Output Enable Polarity

2^ndOption Code

Temperature

Tuning Slope

Minimum APR

(±ppm) for VDD @

3.3 LVPECL

3.3 LVDS

3.3 CMOS

3.3 CML

High

Low

Stability

ppm/V (typ)

380

185

125

Code

Package

5x7 mm

3.2x5 mm

± ppm (max)

3.3 V

370

160

130

100

370

160

130

100

2.5 V

275

110

N/A

275

110

1.8 V

200

N/A

200

N/A

2.5 LVPECL

2.5 LVDS

2.5 CMOS

2.5 CML

125

380

185

125

1.8 CMOS

1.8 CML

3.3 LVPECL

3.3 LVDS

3.3 CMOS

3.3 CML

2.5 LVPECL

2.5 LVDS

2.5 CMOS

2.5 CML

125

N/A

1.8 CMOS

1.8 CML

Notes:

1. For best jitter and phase noise performance, always choose the smallest Kv that meets

the application’s minimum APR requirements. Lower Kv options minimize noise

coupling and jitter in real-world PLL designs. See AN266 for more information.

2. APR is the ability of a VCXO to track a signal over the product lifetime. A VCXO with an

APR of ±100 ppm is able to lock to a clock with a ±100 ppm stability over 15 years over

all operating conditions.

Note:

CMOS available to 160 MHz.

3. Nominal Pull range (±) = 0.5 x V_DDx tuning slope.

4. Minimum APR values noted above include worst case values for all parameters.

Example Part Number: 595AE148M500DGR is a 5 x 7 mm VCXO in a 6 pad package. The nominal frequency is 148.5 MHz, with a 3.3 V supply,

LVPECL output, and Output Enable active high polarity. Temperature stability is specified as ±20 ppm and the tuning slope is 95 ppm/V. The part is

specified for a –40 to +85 C° ambient temperature range operation and is shipped in tape and reel format.

Figure 1. Part Number Convention

Rev. 1.3

Si595

4. Package Outline Diagram: 5 x 7 mm, 6-pin

Figure 2 illustrates the package details for the 5 x 7 mm Si595. Table 12 lists the values for the dimensions shown

in the illustration.

Figure 2. Si595 Outline Diagram

Table 12. Package Diagram Dimensions (mm)

Dimension

Min

1.50

1.30

0.50

Nom

1.65

Max

1.80

1.50

0.70

1.40

0.60

5.00 BSC

4.40

4.30

4.50

2.54 BSC.

7.00 BSC.

6.20

6.10

0.55

1.17

0.05

1.80

6.30

0.75

1.37

0.15

2.60

0.65

1.27

0.10

—

0.70 REF

0.15

aaa

bbb

ccc

ddd

eee

0.15

0.10

0.05

Note:

1. All dimensions shown are in millimeters (mm) unless

otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994

Rev. 1.3

Si595

5. PCB Land Pattern: 5 x 7 mm, 6-pin

Figure 3 illustrates the 6-pin PCB land pattern for the 5 x 7 mm Si595. Table 13 lists the values for the dimensions

shown in the illustration.

Figure 3. Si595 PCB Land Pattern

Table 13. PCB Land Pattern Dimensions (mm)

Dimension

(mm)

4.20

2.54

1.55

1.95

Notes:

General

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.

3. This Land Pattern Design is based on the IPC-7351 guidelines.

4. All dimensions shown are at Maximum Material Condition (MMC). Least Material

Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.

Solder Mask Design

1. All metal pads are to be non-solder mask defined (NSMD). Clearance between

the solder mask and the metal pad is to be 60 µm minimum, all the way around

the pad.

Stencil Design

1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls

should be used to assure good solder paste release.

2. The stencil thickness should be 0.125 mm (5 mils).

3. The ratio of stencil aperture to land pad size should be 1:1.

Card Assembly

1. A No-Clean, Type-3 solder paste is recommended.

2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020

specification for Small Body Components.

Rev. 1.3

Si595

6. Package Outline Drawing: 3.2 x 5 mm, 6-pin

Figure 4 illustrates the package details for the 3.2 x 5 mm Si595. Table 14 lists the values for the dimensions

shown in the illustration.

Figure 4. Si595 Outline Diagram

Table 14. Package Diagram Dimensions (mm)

Dimension

Min

1.02

0.99

Nom

1.17

1.10

Max

1.32

1.21

Dimension

Min

Nom

2.85 BSC

1.91 BSC

0.45

0.10

0.10 REF

0.15

Max

0.5 BSC

0.30 BSC

0.35

0.05

0.55

0.15

0.54

0.35

aaa

bbb

ccc

ddd

eee

0.64

0.45

5.00 BSC

0.74

0.55

0.15

4.65 BSC

3.38 BSC

1.27 BSC

3.20 BSC

0.08

0.10

0.05

Notes:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

Rev. 1.3

Si595

7. PCB Land Pattern: 3.2 x 5 mm, 6-pin

Figure 5 illustrates the 6-pin PCB land pattern for the 3.2 x 5 mm Si595. Table 15 lists the values for the

dimensions shown in the illustration.

Figure 5. Si595 PCB Land Pattern

Table 15. PCB Land Pattern Dimensions (mm)

Dimension

(mm)

2.91

1.27

0.80

1.10

Notes:

General

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.

3. This Land Pattern Design is based on the IPC-7351 guidelines.

4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition

(LMC) is calculated based on a Fabrication Allowance of 0.05 mm.

Solder Mask Design

1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder

mask and the metal pad is to be 60 µm minimum, all the way around the pad.

Stencil Design

1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used

to assure good solder paste release.

2. The stencil thickness should be 0.125 mm (5 mils).

3. The ratio of stencil aperture to land pad size should be 1:1.

Card Assembly

1. A No-Clean, Type-3 solder paste is recommended.

2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for

Small Body Components.

Rev. 1.3

Si595

8. Si5xx Mark Specification: 5 x 7 mm

Figure 6 illustrates the mark specification for the 5 x 7 mm Si595. Table 16 lists the line information.

Figure 6. Mark Specification

Table 16. Si595 Top Mark Description

Line

Position

1–10

Description

“SiLabs”+ Part Family Number, 595 (First 3 characters in part number)

1–10

Si595: Option1+Option2+Freq(7)+Temp

Si595 w/ 8-digit resolution: Option1+Option2+ConfigNum(6)+Temp

Trace Code

Position 1

Pin 1 orientation mark (dot)

Product Revision (D)

Position 2

Tiny Trace Code (4 alphanumeric characters per assembly release instructions)

Year (least significant year digit), to be assigned by assembly site (ex: 2009 = 9)

Calendar Work Week number (1–53), to be assigned by assembly site

“+” to indicate Pb-Free and RoHS-compliant

Position 3–6

Position 7

Position 8–9

Position 10

Rev. 1.3

Si595

9. Si5xx Mark Specification:

3.2 x 5 mm

Figure 7 illustrates the mark specification for the

3.2 x 5 mm Si595. Table 17 lists the line information.

Figure 7. Mark Specification

Table 17. Si595 Top Mark Description

Line

Position

1–5

Description

“Si”+ Part Family Number, 595 (First 3 characters in part number)

Crystal trace code (3 alphanumeric characters assigned by assembly site)

6–8

1–9

Si595: Option1+Option2+Freq(7)

Si595 w/ 8-digit resolution: Option1+Option2+ConfigNum(6)

Trace Code

Position 1

Pin 1 orientation mark (dot)

Product Revision (D)

Position 2

Tiny Trace Code (3 alphanumeric characters per assembly release instructions)

Year (last two digits of year), to be assigned by assembly site (ex: 2017 = 17)

Calendar Work Week number (1–53), to be assigned by assembly site

Position 3–5

Position 6–7

Position 8–9

Rev. 1.3

Si595

REVISION HISTORY

Revision 1.3

December, 2017

 Added 3.2 x 5 mm package.

Revision 1.2

 Added Table 9, “Thermal Characteristics,” on page 5.

Revision 1.1

 Swapped D and E values in Table 12 on page 9.

Revision 1.0

 Updated 2.5 V/3.3 V and 1.8 V CML output level specifications in Table 4 on page 3.

 Updated Si595 device to support frequencies up to 810 MHz for LVPECL, LVDS, and CML outputs.

 Separated 1.8 V, 2.5 V/3.3 V supply voltage. specifications for CML output in Table 3 on page 5.

 Updated Note 1 of Table 5 on page 4 to refer to AN256.

 Updated Table 8 on page 5 to include the "Moisture Sensitivity Level" and "Contact Pads" rows.

 Updated Figure 3 and Table 16 on page 13 to reflect specific marking information.

Revision 0.2

 Updated Table 5, “CLK± Output Phase Jitter,” on page 4.

Updated typical phase jitter from 0.6 to 0.7 ps for kV = 380 ppm/V.

Rev. 1.3

595CD148M500DG [SILICON]

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