C8051F043 [SILICON]
25 MIPS, 64 kB Flash, 10-Bit ADC, 64-Pin Mixed-Signal MCU; 25 MIPS ， 64 KB闪存， 10位ADC ， 64引脚混合信号MCU
| 型号： | C8051F043 |
| 厂家： | 
SILICON |
| 描述： | 25 MIPS, 64 kB Flash, 10-Bit ADC, 64-Pin Mixed-Signal MCU |
| 文件： | 总2页 (文件大小：418K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
C8051F043
25 MIPS, 64 kB Flash, 10-Bit ADC, 64-Pin Mixed-Signal MCU
Analog Peripherals
High-Speed 8051 µC Core
10-Bit ADC
-
Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
-
-
-
-
-
-
±1 LSB INL; guaranteed monotonic
-
-
Up to 25 MIPS throughput with 25 MHz system clock
Expanded interrupt handler
Programmable throughput up to 100 ksps
13 external inputs; programmable as single-ended or differential
Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5
Data-dependent windowed interrupt generator
Built-in temperature sensor (±3 °C)
Memory
-
-
-
4352 bytes data RAM
64 kB Flash; in-system programmable in 512-byte sectors (512 bytes
are reserved)
High-Voltage Differential Amplifier
External parallel data memory interface
-
-
-
60 V common mode input range
Offset adjust from –60 to +60 V
16 gain settings from 0.05 to 16
CAN Bus 2.0B
-
-
32 message objects
”Mailbox" implementation only interrupts CPU when needed
8-Bit ADC
Digital Peripherals
-
-
-
Programmable throughput up to 500 ksps
-
-
32 port I/O; all are 5 V tolerant
8 external inputs; programmable as single-ended or differential
Programmable amplifier gain: 4, 2, 1, 0.5
Hardware SMBus™ (I2C™ compatible), SPI™, and two UART serial
ports available concurrently
Two 12-Bit DACs
-
-
-
-
Programmable 16-bit counter array with 6 capture/compare modules
Three Comparators
Internal Voltage Reference
5 general-purpose 16-bit counter/timers
Dedicated watchdog timer; bidirectional reset
Real-time clock mode using timer 3 or PCA
Precision V Monitor/Brown-out Detector
DD
On-Chip JTAG Debug & Boundary Scan
Clock Sources
-
-
-
-
On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
-
-
Internal programmable 2% oscillator: up to 25 MHz
Provides breakpoints, single stepping, watchpoints, stack monitor, pro-
gram trace memory
SuEpxptelrynaVl ooslctaillgateor:: C2r.y7sttaol, R3C.6, CV, or Clock
Inspect/modify memory and registers
-
-
Typical operating current: 10 mA at 25 MHz
Multiple power saving sleep and shutdown mode
Superior performance to emulation systems using ICE-chips, target
pods, and sockets
-
IEEE1149.1 compliant boundary scan
64-Pin TQFP
- Temperature Range: –40 to +85 °C
VDD
Digital Power
Analog Power
VDD
VDD
UART0
UART1
SMBus
SPI Bus
PCA
P0.0
P0.7
P0
Drv
DGND
DGND
DGND
8
0
5
1
C
R
O
S
S
B
A
R
SFR Bus
P1.0/AIN1.0
P1.7/AIN1.7
AV+
AV+
P1
Drv
AGND
AGND
Timers
P2.0/CPx
P2.7/CPx
TCK
TMS
TDI
P2
0,1,2,3,4
Boundary Scan
Debug HW
JTAG
Logic
Drv
Port
0,1,2,3
&4
TDO
64 kB
Reset
RST
P3.0/AIN0.6
P3.7/AIN0.7
P3
FLASH
Latches
Drv
VDD
WDT
MONEN
C
o
r
Monitor
32x136
CTX0
CRX0
CAN
2.0B
CANRAM
External
Oscillator
Circuit
XTAL1
XTAL2
System
Clock
256 byte
RAM
A
ADC
M
U
X
Prog
Gain
8:1
500 ksps
(8-Bit)
VREF
DAC1
VREF
4 kB
e
DAC1
P2.0
P2.1
VREFA
Internal
2%
+
-
XRAM
(12-Bit)
CP0
P2.2
P2.3
Oscillator
+
-
CP1
DAC0
DAC0
P2.4
P2.5
(12-Bit)
+
-
CP2
VREFA
AIN0.0
AIN0.1
AIN0.2
AIN0.3
A
ADC
P4
Port 4 <from crossbar>
Bus Control
M
U
X
Prog
Gain
DRV
100 ksps
(10-Bit)
External Data Memory Bus
Ctrl Latch
P5 Latch
Addr [7:0]
P6 Latch
Addr [15:8]
P7 Latch
P5
Address [15:0]
TEMP
DRV
SENSOR
A
P6
M
U
X
8:2
DRV
P7
HVAIN+
HVAIN-
Data [7:0]
DRV
Data Latch
HVAMP
HVREF
HVCAP
CAN 2.0B
Copyright © 2004 by Silicon Laboratories
6.15.2004
C8051F043
25 MIPS, 64 kB Flash, 10-Bit ADC, 64-Pin Mixed-Signal MCU
Selected Electrical Specifications
(TA = –40 to +85 C°, VDD = 2.7 V unless otherwise specified)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
GLOBAL CHARACTERISTICS
Supply Voltage
2.7
3.6
V
Supply Current (CPU
active)
Clock = 25 MHz
Clock = 1 MHz
10
0.5
20
mA
mA
µA
µA
Clock = 32 kHz; VDD Monitor Enabled
Oscillator not running; VDD Monitor
Disabled
Supply Current
0.1
(shutdown)
Clock Frequency Range
A/D CONVERTER
Resolution
DC
25
MHz
10
bits
LSB
LSB
dB
Integral Nonlinearity
Differential Nonlinearity
Signal-to-Noise Plus
Distortion
±1
±1
Guaranteed Monotonic
59
0
Throughput Rate
Input Voltage Range
D/A CONVERTERS
Resolution
100
ksps
V
VREF
12
10
LSB
LSB
µs
Differential Nonlinearity
Output Settling Time
COMPARATORS
Supply Current
±1
(each Comparator)
1.5
4
µA
µs
Response Time
| CP+ – CP- | = 100 mV
C8051F040DK Development Kit
Package Information
D
D1
MIN NOM MAX
(mm) (mm) (mm)
A
-
-
-
-
1.20
0.15
1.05
A1 0.05
A2 0.95
E1
E
b
D
0.17 0.22 0.27
-
-
-
-
-
12.00
10.00
0.50
-
-
-
-
-
64
D1
e
PIN 1
DESIGNATOR
1
e
A2
E
12.00
10.00
A
E1
b
A1
CAN 2.0B
Copyright © 2004 by Silicon Laboratories
6.15.2004
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders
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