C8051F912-GDI [SILICON]
Microcontroller;
| 型号： | C8051F912-GDI |
| 厂家： | 
SILICON |
| 描述： | Microcontroller 微控制器 外围集成电路 |
| 文件： | 总13页 (文件大小：235K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
C8051F912-GDI
Tested Single/Dual Battery, 0.9–3.6 V, 16 kB Flash,
SmaRTClock, 12/10-Bit ADC MCU Die in Wafer Form
Ultra-Low Power
-
-
-
-
-
-
160 µA/MHz in active mode (24.5 MHz clock)
2 µs wake-up time (two-cell mode)
10 nA sleep mode with memory retention
50 nA sleep mode with brownout detector
300 nA sleep mode with LFO
-
600 nA sleep mode with external crystal
Supply Voltage 0.9 to 3.6 V
-
-
-
One-cell mode supports 0.9 to 3.6 V operation
Two-cell mode supports 1.8 to 3.6 V operation
Built-in dc-dc converter with 1.8 to 3.3 V output for use
in one-cell mode
TM
,
-
Built-in LDO regulator allows a high analog supply volt-
age and low digital core voltage
-
2 built-in supply monitors (brownout detectors)
12 or 10-Bit Analog-to-Digital Converter
-
-
±1 LSB INL no missing codes (10-bit mode)
Programmable throughput up to 300 ksps
(10-bit mode)
-
12-bit extended resolution mode provides ±1.5 LSB
INL at up to 75 ksps throughput
-
-
-
15 external inputs
On-chip voltage reference
On-chip PGA allows measuring voltages up to twice
the reference voltage
-
16-bit auto-averaging accumulator with burst mode
provides increased ADC resolution
Data dependent windowed interrupt generator
Built-in temperature sensor
-
On-chip debug circuitry facilitates full-speed, non-intru-
sive in-system debug (no emulator required)
Provides 4 breakpoints, single stepping
-
-
-
-
-
Inspect/modify memory and registers
Two Comparators
Complete development kit
o
-
Programmable hysteresis and response time
Configurable as wake-up or reset source
Temperature range: –40 to +85 C
Full Technical Data Sheet
-
-
6-Bit Programmable Current Reference
C8051F91x-C8051F90x
-
Up to ± 500 A. Can be used as a bias or for generat-
ing a custom reference voltage
-
PWM Enhanced Mode provides additional resolution
ANALOG
PERIPHERALS
DIGITAL I/O
UART
Port 0
Port 1
Port 2
SMBus
2 x SPI
PCA
Timer 0
Timer 1
Timer 2
Timer 3
CRC
A
12/10-bit
75/300 ksps
ADC
IREF
M
U
X
+
+
VREF
VREG
TEMP
SENSOR
–
–
VOLTAGE
COMPARATORS
24.5 MHz PRECISION
20 MHz LOW POWER
INTERNAL OSCILLATOR
INTERNAL OSCILLATOR
External Oscillator
HARDWARE smaRTClock
HIGH-SPEED CONTROLLER CORE
16 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
8051 CPU
(25 MIPS)
DEBUG
768 B SRAM
POR WDT
CIRCUITRY
Rev. 1.2 12/13
Copyright © 2013 by Silicon Laboratories
C8051F912-GDI
C8051F912-GDI
1. Ordering Information
Table 1.1. Product Selection Guide
28.54 mil /
725 µm
(no back-
grind)
C8051F912-D-G1DI 25 16 768
1
1
1
1
2
2
4 16 2
12 mil
(backgrind)
C8051F912-D-GDI 25 16 768
*Note: 1024 bytes reserved for factory use
4 16 2
2
Rev. 1.2
C8051F912-GDI
2. Pin Definitions
Table 2.1. Pin Definitions for C8051F912-GDI
Physical
Name
Pad
Type
Description
Number
VBAT
6
P In
Battery Supply Voltage.
C8051F912 devices:
Must be 0.9 to 3.6 V in single-cell battery mode and 1.8 to 3.6 V in dual-cell
battery mode.
VDD
/
4
P In
Power Supply Voltage. Must be 1.8 to 3.6 V. This supply voltage is not
required in low power sleep mode. This voltage must always be > VBAT.
DC+
P Out
Positive output of the dc-dc converter. In single-cell battery mode, a 1uF
ceramic capacitor is required between DC+ and DC–. This pin can supply
power to external devices when operating in single-cell battery mode.
DC– /
2
P In
DC-DC converter return current path. In single-cell battery mode, this pin is
typically not connected to ground.
GND
GND
G
G
In dual-cell battery mode, this pin must be connected directly to ground.
Required Ground.
3
5
DCEN
P In
DC-DC Enable Pin. In single-cell battery mode, this pin must be connected
to VBAT through a 0.68 µH inductor.
G
In dual-cell battery mode, this pin must be connected directly to ground.
RST/
7
8
D I/O
Device Reset. Open-drain output of internal POR or VDD monitor. An exter-
nal source can initiate a system reset by driving this pin low for at least
15 µs. A 1 k to 5 k pullup to VDD is recommended.
C2CK
P2.7/
D I/O
D I/O
Clock signal for the C2 Debug Interface.
Port 2.7. This pin can only be used as GPIO. The Crossbar cannot route
signals to this pin and it cannot be configured as an analog input. See Port
I/O Section of C8051F91x-C8051F90x data sheet for a complete descrip-
tion.
C2D
XTAL3
XTAL4
P0.0
D I/O
A In
Bi-directional data signal for the C2 Debug Interface.
SmaRTClock Oscillator Crystal Input.
10
9
A Out
SmaRTClock Oscillator Crystal Output.
32
D I/O or A Port 0.0.
In
External VREF Input.
VREF
A In
A Out
Internal VREF Output. External VREF decoupling capacitors are recom-
mended.
Rev. 1.2
3
C8051F912-GDI
Table 2.1. Pin Definitions for C8051F912-GDI (Continued)
Physical
Pad
Name
Type
Description
Number
P0.1
31
D I/O or A Port 0.1.
In
AGND
P0.2
G
Optional Analog Ground.
30
D I/O or A Port 0.2. See Port I/O Section of the C8051F91x-C8051F90x data sheet
In
for a complete description.
XTAL1
A In
External Clock Input. This pin is the external oscillator return for a crystal or
resonator.
Buffered SmaRTClock oscillator output.
P0.3
29
D I/O or A Port 0.3.
In
External Clock Output. This pin is the excitation driver for an external crys-
XTAL2
A Out
D In
tal or resonator.
External Clock Input. This pin is the external clock input in external CMOS
clock mode.
External Clock Input. This pin is the external clock input in capacitor or RC
oscillator configurations.
A In
P0.4
28
26
25
24
D I/O or A Port 0.4.
In
TX
D Out
UART TX Pin.
P0.5
D I/O or A Port 0.5.
In
RX
D In
UART RX Pin.
P0.6
D I/O or A Port 0.6.
In
CNVSTR
P0.7
D In
External Convert Start Input for ADC0.
D I/O or A Port 0.7.
In
IREF0
A Out
IREF0 Output. See IREF Section of the C8051F91x-C8051F90x data
sheet for complete description.
P1.0
P1.1
P1.2
19
18
17
D I/O or Port 1.0.
A In May also be used as SCK for SPI1.
D I/O or Port 1.1.
A In
May also be used as MISO for SPI1.
D I/O or Port 1.2.
A In
May also be used as MOSI for SPI1.
4
Rev. 1.2
C8051F912-GDI
Table 2.1. Pin Definitions for C8051F912-GDI (Continued)
Physical
Pad
Number
Name
P1.3
P1.4
P1.5
P1.6
Type
Description
16
D I/O or Port 1.3.
A In
May also be used as NSS for SPI1.
13
12
11
D I/O or Port 1.4.
A In
D I/O or Port 1.5.
A In
D I/O or Port 1.6.
A In
Rev. 1.2
5
C8051F912-GDI
3. Bonding Instructions
Table 3.1. Bond Pad Coordinates
Physical Pad
Number
Example
Package Pin
Number
Package Pin Name
Pad Coordinates Relative to Center
X (µm)
Y (µm)
(QFN-24)
1
Reserved*
—
DC–/GND
GND
–836
–836
–836
–836
–836
–836
–836
–633
–348
–126
134
600
480
2
1
3
2
233
4
3
VDD/DC+
DCEN
VBAT
RST/C2CK
P2.7/C2D
XTAL4
XTAL3
P1.6
78
5
4
–105
–329
–688
–891
–891
–891
–891
–891
–891
–891
–891
–688
–545
–389
–226
–103
–13
6
5
7
6
8
7
9
8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
9
10
11
P1.5
290
12
P1.4
433
Reserved*
Reserved*
13
—
577
—
667
P1.3
836
14
P1.2
836
15
P1.1
836
16
P1.0
836
Reserved*
Reserved*
Reserved*
Reserved*
17
—
836
—
836
—
836
77
—
836
167
P0.7/IREF0
836
369
*Note: Pins marked “Reserved” should not be connected.
6
Rev. 1.2
C8051F912-GDI
Table 3.1. Bond Pad Coordinates (Continued)
Physical Pad
Number
Example
Package Pin
Number
Package Pin Name
Pad Coordinates Relative to Center
X (µm)
Y (µm)
(QFN-24)
25
26
27
28
29
30
31
32
18
P0.6/CNVSTR
P0.5/RX
836
836
525
688
883
891
891
891
891
891
19
Reserved*
—
745
20
21
22
23
24
P0.4/TX
641
P0.3/XTAL2
P0.2/XTAL1
P0.1/AGND
P0.0/VREF
484
342
–490
–633
*Note: Pins marked “Reserved” should not be connected.
Rev. 1.2
7
C8051F912-GDI
C8051F911D
Figure 3.1. Die Bonding (QFN-24)
8
Rev. 1.2
C8051F912-GDI
Table 3.2. Wafer and Die Information
Wafer ID
C8051F911D
Wafer Dimensions
Die Dimensions
8 in.
1.9256 mm x 2.0366 mm
28.54 mil ±1 mil
(725 µm)
Wafer Thickness (No backgrind)
12 mil ±1 mil
Wafer Thickness (With backgrind)
Wafer Identification
Notch
80 µm
Scribe Line Width
Die per Wafer*
Contact Sales for info
Standard
Passivation
Wafer Packaging Detail
Bond Pad Dimensions
Maximum Processing Temperature
Electronic Die Map Format
Bond Pad Pitch Minimum
Wafer Jar
60 µm x 60 µm
250 °C
.txt
142 µm
*Note: This is the Expected Known Good Die yielded per wafer and
represents the batch order quantity (one wafer).
Rev. 1.2
9
C8051F912-GDI
4. Wafer Storage Guidelines
It is necessary to conform to appropriate wafer storage practices to avoid product degradation or contami-
nation.
Wafers may be stored for up to 18 months in the original packaging supplied by Silicon Labs.
Wafers must be stored at a temperature of 18–24 °C.
Wafers must be stored in a humidity-controlled environment with a relative humidity of <30%.
Wafers should be stored in a clean, dry, inert atmosphere (e.g. nitrogen or clean, dry air).
10
Rev. 1.2
C8051F912-GDI
5. Failure Analysis (FA) Guidelines
Certain conditions must be met for Silicon Laboratories to perform Failure Analysis on devices sold in
wafer form.
In order to conduct failure analysis on a device in a customer-provided package, Silicon
Laboratories must be provided with die assembled in an industry standard package that is pin
compatible with existing packages Silicon Laboratories offers for the device. Initial response time
for FA requests that meet this requirements will follow the standard FA guidelines for packaged
parts.
If retest of the entire wafer is requested, Silicon Laboratories must be provided with the whole
wafer. Silicon Laboratories cannot retest any wafers that have been sawed, diced, backgrind or
are on tape. Initial response time for FA requests that meet this requirements will be 3 weeks.
Rev. 1.2
11
C8051F912-GDI
DOCUMENT CHANGE LIST
Revision 1.0 to Revision 1.1
Changed Wafer Packaging Detail to “Wafer Jar”
in Table 3.2 on page 9.
Revision 1.1 to Revision 1.2
Replaced “C8051F912-GDI” with “C8051F912-D-GDI” (except in title).
Updated Table 1.1, “Product Selection Guide,” on page 2.
Added C8051F912-D-G1DI row to Table 1.1.
Changed “Package” column heading to “Wafer Thickness” in Table 1.1.
Updated label in Figure 3.1 on page 8 to read “C8051F911D”.
Updated Table 3.2 on page 11 with new Wafer Thickness (no backgrind) row.
Added “5. Failure Analysis (FA) Guidelines” on page 11.
12
Rev. 1.2
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device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories
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