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CP2114-B01-GM [SILICON]

SINGLE-CHIP USB AUDIO TO I2S DIGITAL AUDIO BRIDGE;
CP2114-B01-GM
型号： CP2114-B01-GM
厂家： SILICON    SILICON
描述：

SINGLE-CHIP USB AUDIO TO I2S DIGITAL AUDIO BRIDGE
文件： 总44页 (文件大小：420K)
中文：  中文翻译
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CP2114  
SINGLE-CHIP USB AUDIO TO I2S DIGITAL AUDIO BRIDGE  
2
USB Peripheral Function Controller  
Single-Chip USB Audio to I S Digital Audio Bridge  
USB Specification 2.0 compliant; full-speed (12 Mbps)  
USB Suspend states supported via SUSPEND pins  
USB HID to I2C to communicate with DAC/codec  
Supports USB HID Consumer Controls for Volume and  
Mute Synchronization  
Integrated USB transceiver; no external resistors  
required  
Integrated clock; no external crystal required  
Integrated One-Time Programmable ROM for product  
customization  
USB HID to UART Auxiliary Communication  
Interface  
APIs for quick application development  
Supports Windows 8, 7, Vista, XP, Server 2003, 2000  
Supports Mac OS-X  
12 Configurable GPIO Pins with Alternate Functions  
Usable as inputs, open-drain or push-pull outputs  
UART signals, audio playback controls, DAC select pins  
Configurable clock output  
On-chip voltage regulator: 3.45 V output  
Supports a Wide Range of codecs/DACs  
Out-of-box support for three major codecs/DACs  
Internal programmable memory supports additional  
codec/DAC configurations  
Toggle LEDs upon UART transmission or reception  
Supply Voltage  
USB Audio Class v1.0 support  
Self-powered: 3.0 to 3.6 V  
USB bus powered: 4.0 to 5.25 V  
I/O voltage: 1.8 V to VDD  
I2S Master mode, I2S and left justified PCM outputs  
Supports 48 kHz,16-bit stereo digital audio  
No custom driver required  
Supports Windows 7, Vista, XP, Mac OS-X, Linux  
Supports iPad/iOS (with USB camera kit connector)  
Open access to interface specification  
Package  
RoHS-compliant 32-pin QFN (5 x 5 mm)  
Ordering Part Number  
CP2114-B01-GM  
Temperature Range: –40 to +85 °C  
CP2114  
Connect to  
VBUS or  
External Supply  
GPIO.10_TX  
REGIN  
VDD  
UART  
Controller  
Voltage  
Regulator  
Internal  
Oscillator  
Baud Rate  
Generator  
UART  
GPIO.11_RX  
GND  
GPIO.0_RMUTE  
GPIO.1_PMUTE  
USB Interface  
USB  
Connector  
Data FIFOs  
GPIO.2_VOL+  
Volume/Mute Controls  
VBUS  
D+  
VBUS  
D+  
GPIO.3_VOL-  
Full-Speed  
12 Mbps  
Transceiver  
Peripheral  
Function  
Controller  
256 B RX  
256 B TX  
GPIO.4_RMUTELED  
D-  
GPIO and  
D-  
GPIO.5_TXT_DACSEL0  
Suspend  
GND  
GPIO.6_RXT_DACSEL1  
Controller  
CODEC/DAC Selector  
GPIO.7_RTS_DACSEL2  
GPIO.8_CTS_DACSEL3  
RST  
VPP  
352 Byte PROM  
(USB Customization)  
GPIO.9_CLKOUT  
Clock Output (optional)  
SUSPEND  
Suspend Signals  
SUSPEND  
Logic Level  
Supply  
(1.8V to VDD)  
SDA  
I/O Power and  
Logic Levels  
VIO  
Audio Controller  
SCL  
MCLK  
SCK  
CS42L55 Configuration  
PCM1774 Configuration  
WM8523 Configuration  
I2S and I2C Signals to  
CODEC/DAC  
Support for 32 Audio  
CODEC//DAC Configurations  
5.5 kByte PROM  
LRCK  
SDIN  
(Audio Customization)  
SDOUT  
EXTCLK  
Clock Input (optional)  
Figure 1. Example System Diagram  
Rev. 1.1 1/14  
Copyright © 2014 by Silicon Laboratories  
CP2114  
CP2114  
2
Rev. 1.1  
CP2114  
TABLE OF CONTENTS  
Section  
Page  
1. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4  
2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5  
3. Pinout and Package Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13  
4. QFN-32 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16  
5. Audio (I2S and I2C) Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18  
5.1. One-Time Programmable ROM Configuration Programming . . . . . . . . . . . . . . . . . .18  
5.2. Real-Time Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18  
5.3. CP2114 I2S and Left-Justified Digital Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18  
5.4. USB and Digital Audio Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19  
5.5. USB Audio Synchronization Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20  
5.6. CP2114 Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21  
6. USB Function Controller and Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23  
7. Asynchronous Serial Data Bus (UART) Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23  
8. GPIO Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24  
8.1. GPIO.0-4—Audio Playback and Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25  
8.2. GPIO.5-8—DAC Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25  
8.3. GPIO.5-6—UART Transmit and Receive Toggle . . . . . . . . . . . . . . . . . . . . . . . . . . .26  
8.4. GPIO.7-8—Hardware Flow Control (RTS and CTS) . . . . . . . . . . . . . . . . . . . . . . . . .27  
8.5. GPIO.9—Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27  
9. One-Time Programmable ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28  
9.1. Audio Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29  
9.2. USB and GPIO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39  
10. Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40  
11. CP2114 Interface Specification and Windows Interface DLL . . . . . . . . . . . . . . . . . . . .42  
12. Relevant Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42  
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43  
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44  
Rev. 1.1  
3
CP2114  
1. System Overview  
All major commercial operating systems (Windows, Linux, Mac, iOS) support the standard USB Audio Device  
2
class. Codecs and DACs typically have only an I S (Inter-IC Sound) digital interface, and thus cannot connect  
directly to a host system. In addition, when a DAC is powered on, it typically needs to be configured by the host via  
2
an I C (inter-integrated-circuit) digital interface, with a non-standard protocol. Finally, in order to support push  
button volume and mute synchronization with the host system, the target USB device must support the standard  
USB-HID Consumer Control interface. Thus, adding USB digital audio to an embedded system or as dongle or  
2
2
appliance typically involves complex USB protocol programming as well as I S and I C programming capability,  
prototyping, integration and testing. The CP2114 USB Audio Bridge is specifically designed to overcome all these  
issues and commoditize USB Audio and DAC configuration for turn-key product development.  
Note: Use with an iPad requires a camera kit connector to get USB from the Apple 30-pin connector. USB Audio is not sup-  
ported on the iPhone.  
The CP2114 includes a USB 2.0 full-speed function controller, USB transceiver, oscillator, one-time programmable  
2
2
read-only memory (ROM), I S (audio) interface, I C (control) interface, and UART interface in a compact 5 x 5 mm  
QFN-32 package (sometimes called “MLF” or “MLP”). The one-time programmable ROM on the device may be  
used to customize both product information (including USB fields such as Vendor ID, Product ID, Strings, etc...)  
and external DAC configuration strings. By default, the CP2114 provides the following features  
Enumerates to the host as a Standard USB Audio Device and HID Consumer Control supporting:  
USB Digital Audio Out (Audio Playback Device)  
USB Digital Audio In (Microphone/Recording Device)  
HID Consumer Control handling standard volume and mute functionality  
Pre-configured support for 3 commercial DACs  
Handles all I2C configuration of the DAC automatically at boot  
2
Handles all volume and mute traffic converting from USB to I C messages to the DAC  
Tested for USB plug & play and audio quality on all major operating systems  
UART interface using standard USB HID device class which is natively supported by most operating  
systems  
No custom driver installation needed  
Windows and MAC DLLs provided and interface specification is available for development on any operating  
system  
Implements transmit (TX), receive (RX), hardware flow control (CTS, RTS)  
Baud rate support from 300 to 1 Mbps, support for 5-8 data bits, 5 parity options, 3 types of stop bits  
Note: The CP2114 devices will not enumerate as a standard HID mouse or keyboard.  
12 GPIO signals which support alternate functions  
Volume control, UART transmit and receive, UART hardware flow control, UART transmit/receive toggle,  
configurable clock output, and DAC selection  
Support for I/O interface voltages down to 1.8 V is provided via a VIO pin.  
An evaluation kit for the CP2114 (Part Number: CP2114EK) is available. It includes a CP2114-based USB-to-Audio  
motherboard, a USB cable, and full documentation. Additional kits with daughtercards are available as well:  
CP2114-CS42L55 evaluation kit (Part Number: CP2114-CS42L55EK) includes:  
2
CP2114 USB-to-I S Digital Audio motherboard  
Cirrus Logic CS42L55 Codec daughtercard (includes a 3.5mm male-to-male audio cable)  
CP2114-WM8523 evaluation kit (Part Number: CP2114-WM8523EK)  
2
CP2114 USB-to-I S Digital Audio motherboard  
Wolfson Microelectronics WM8523 DAC daughtercard  
CP2114-PCM1774 evaluation kit (Part Number: CP2114-PCM1774EK)  
2
CP2114 USB-to-I S Digital Audio motherboard  
Texas Instruments PCM1774 DAC daughtercard  
All kits with daughtercards include a USB cable, ear bud headphones, and full documentation.  
Contact a Silicon Labs sales representatives or go to www.silabs.com to order a CP2114 Evaluation Kit.  
4
Rev. 1.1  
CP2114  
2. Electrical Characteristics  
Table 1. Global DC Electrical Characteristics  
VDD = 3.0 to 3.6 V, –40 to +85 °C unless otherwise specified.  
Parameter  
Test Condition  
Min  
3.0  
1.8  
—
Typ  
—
Max  
3.6  
Unit  
V
Digital Supply Voltage (V  
)
DD  
Digital Port I/O Supply Voltage (V )  
—
V
V
IO  
DD  
Digital Supply Current  
Bus Powered Mode  
Self Powered Mode with  
Regulator enabled  
18  
28  
mA  
1
(USB Active Mode)  
Self Powered Mode with  
Regulator disabled  
Digital Supply Current  
(USB Suspend Mode)  
Bus Powered Mode  
Self Powered Mode with  
Regulator enabled  
—
—
750  
940  
1.2  
µA  
1
Self Powered Mode with  
Regulator disabled  
0.99  
mA  
2
Supply Current - USB Pull-up  
—
200  
—
228  
+85  
µA  
°C  
Specified Operating Temperature  
Range  
–40  
Notes:  
1. If the device is connected to the USB bus, the USB Pull-up Current should be added to the supply current for total  
supply current.  
2. The USB Pull-up supply current values are calculated values based on USB specifications.  
Rev. 1.1  
5
CP2114  
Table 2. I2S, I2C, UART and Suspend I/O DC Electrical Characteristics  
VDD = 3.0 to 3.6 V, VIO = 1.8 V to VDD, –40 to +85 °C unless otherwise specified.  
Parameters  
Test Condition  
Min  
Typ  
Max  
Unit  
Output High Voltage (V  
)
I
I
= –10 µA  
= –3 mA  
= –10 mA  
V
V
– 0.1  
– 0.2  
—
—
—
– 0.4  
IO  
—
—
—
OH  
OH  
IO  
IO  
V
OH  
I
V
OH  
Output Low Voltage (V  
)
I
= 10 µA  
= 8.5 mA  
= 25 mA  
—
—
—
—
—
0.6  
0.1  
0.4  
—
OL  
OL  
I
V
OL  
I
OL  
Input High Voltage (V )  
0.7 x V  
—
—
—
—
V
V
IH  
IO  
Input Low Voltage (V )  
0.6  
IL  
Input Leakage Current  
Weak Pull-Up Off  
—
—
—
25  
1
50  
µA  
Weak Pull-Up On, V = 0 V  
IO  
Maximum Input Voltage  
Open drain, logic high (1)  
—
—
5.8  
V
Table 3. Reset Electrical Characteristics  
–40 to +85 °C unless otherwise specified.  
Parameter  
Test Condition  
Min  
Typ  
Max  
Units  
RST Input High Voltage  
0.75 x V  
—
—
—
0.6  
—
V
IO  
RST Input Low Voltage  
—
—
V
Minimum RST Low Time to  
Generate a System Reset  
15  
µs  
V
Ramp Time for  
—
—
1
ms  
DD  
Power On  
Table 4. Voltage Regulator Electrical Specifications  
–40 to +85 °C unless otherwise specified.  
Parameter  
Input Voltage Range  
Test Condition  
Min  
3.0  
3.3  
2.5  
—
Typ  
Max  
Unit  
V
—
5.25  
3.6  
—
Output Voltage  
Output Current = 1 to 100 mA*  
3.45  
—
V
VBUS Detection Input Threshold  
Bias Current  
V
—
120  
µA  
*Note: The maximum regulator supply current is 100 mA. This includes the supply current of the CP2114.  
6
Rev. 1.1  
CP2114  
Table 5. GPIO Output Specifications  
–40 to +85 °C unless otherwise specified.  
Parameter  
Test Condition  
Min  
Typ  
Max  
Unit  
GPIO.9 Clock Output  
f
x
f
f
x
Hz  
OUT  
OUT  
OUT  
0.985  
1.015  
TX Toggle Rate  
RX Toggle Rate  
—
20  
20  
—
Hz  
Hz  
—
—
Table 6. One Time Programming Specifications  
VDD = 3.3 to 3.6 V, –40 to +85 °C unless otherwise specified.  
Parameter  
Test Condition  
Min  
Typ  
Max  
Unit  
Digital Port I/O Supply Voltage  
3.3  
V
V
DD  
(V ) during programming  
IO  
Voltage on V with respect to  
GND during a programming  
operation  
V
> 3.3 V  
5.75  
—
—
V + 3.6  
IO  
V
PP  
IO  
Capacitor on V for programming  
4.7  
—
µF  
PP  
Table 7. System Clock Specifications  
VDD = 3.3 to 3.6 V, –40 to +85 °C unless otherwise specified.  
Parameter  
Internal Oscillator  
Test Condition  
Min  
Typ  
Max  
Unit  
SF = 0 (Register: System_Props, bit: 1)  
SF = 1 (Register: System_Props, bit: 1)  
—
—
48  
49.152  
—
—
MHz  
MHz  
External CMOS clock input  
frequency  
SF = 0 (Register: System_Props, bit: 1) 47.880  
SF = 1 (Register: System_Props, bit: 1)  
48  
49.152  
48.120  
—
MHz  
MHz  
—
1. Depending on the requirements of the external DAC, the system clock frequency will be either 48.0 or 49.152 MHz. See  
Section 5.6 for more information.  
2. The USB specification requires a clock accuracy of ±0.25%.  
Rev. 1.1  
7
CP2114  
Table 8. I2S Digital Audio Interface Specifications  
VDD = 3.3 to 3.6 V, –40 to +85 °C unless otherwise specified.  
Parameter  
Test Condition  
Min  
Typ  
Max  
Unit  
Resolution (analog output)  
—
16  
—
bits  
Resolution (analog input)  
MCLK frequency  
—
—
—
—
—
—
—
15  
12  
—
—
—
—
—
—
—
bits  
MHz  
(SYSCLK = 48 MHz)  
(SYSCLK = 49.152 MHz)  
12.288  
48  
MHz  
LRCK frequency  
SCK frequency  
kHz  
(SYSCLK = 48 MHz)  
3.429  
3.511  
20  
MHz  
(SYSCLK = 49.152 MHz)  
MHz  
MCLK/LRCK jitter  
SCS = 0 (external Si500S clock)  
(Register: System_Props, bit: 2)  
ps RMS*  
SCS = 1 (internal oscillator)  
—
140  
—
ps RMS*  
(Register: System_Props, bit: 2)  
*Note: Measurement bandwidth: 100 Hz –40 kHz.  
Table 9. I2C Specifications  
VDD = 3.3 to 3.6 V, –40 to +85 °C unless otherwise specified.  
Parameter  
SCL frequency  
Test Condition  
Min  
Typ  
Max  
Unit  
I2C_CK = 0 (Register: Audio_Props, bit: 5)  
I2C_CK = 1 (Register: Audio_Props, bit: 5)  
—
—
400  
100  
—
—
kHz  
8
Rev. 1.1  
CP2114  
Table 10. Analog Output/Input Characteristics (CS42L55 daughtercard)  
2
25 °C, bus-powered, USB synchronization mode: asynchronous, digital audio interface mode: I S, DAC/ADC gains set to 0 dB,  
test signal for analog output: uncompressed WAV file, full-scale sine wave at 997 Hz, measurement bandwidth 20 Hz to 20 kHz  
Additional parameters that apply to this table are as follows:  
VA = VCP = VLDO = 2.5 V  
Internal oscillator mode  
Parameter  
Test Condition  
Min  
Typ  
Max  
Unit  
Analog Output (Line Output)  
THD + Noise  
0 dB input  
–20 dB input  
–60 dB input  
—
—
—
–80  
–91  
–91  
—
—
—
dB  
dB  
dB  
Dynamic Range  
Noise Level  
A-weighted  
Output muted  
20 Hz – 20 kHz  
—
—
—
92  
—
—
—
dB  
dB  
dB  
–112  
Frequency response  
+0.03,  
–0.07  
Analog Input  
THD + Noise  
–1 dB input  
–20 dB input  
–60 dB input  
—
—
—
–85  
–87  
–87  
—
—
—
dB  
dB  
dB  
Dynamic Range  
Noise Level  
A-weighted  
—
—
90  
0*  
—
—
dB  
dB  
Analog input locally muted  
*Note: When analog input is locally muted, the CP2114 transmits sample values of 0 to the host.  
Table 11. Analog Output Characteristics (WM8523 daughtercard)  
2
25 °C, bus-powered, USB synchronization mode: asynchronous, digital audio interface mode: I S, DAC/ADC gains set to 0 dB,  
test signal for analog output: uncompressed WAV file, full-scale sine wave at 997 Hz, measurement bandwidth 20 Hz to 20 kHz  
Additional parameters that apply to this table are as follows:  
LINEVDD = AVDD = 3.3 V  
Internal oscillator mode  
External headphone amplifier disconnected, no lowpass filter on LINEVOUTL/LINEVOUTR  
Parameter  
Test Condition  
Min  
Typ  
Max  
Unit  
THD + Noise  
0 dB FS input  
–20 dB FS input  
–60 dB FS input  
—
—
—
–83  
–91  
–91  
—
—
—
dB  
dB  
dB  
Dynamic Range  
Noise Level  
A-weighted  
Output muted  
20 Hz – 20 kHz  
—
—
—
94  
—
—
—
dB  
dB  
dB  
–99  
Frequency response  
+0.04,  
–0.05  
Rev. 1.1  
9
CP2114  
Figure 2. WM8523 Frequency Response (0 dB FS)  
Figure 3. WM8523 THD+N vs. Frequency (0 dB FS)  
10  
Rev. 1.1  
CP2114  
Figure 4. WM8523 THD+N vs. Amplitude (997 Hz)  
Table 12. Analog Output/Input Characteristics (PCM1774 Daughtercard)  
2
25 °C, bus-powered, USB synchronization mode: asynchronous, digital audio interface mode: I S, DAC/ADC gains set to 0 dB,  
test signal for analog output: uncompressed WAV file, full-scale sine wave at 997 Hz, measurement bandwidth 20 Hz to 20 kHz  
Additional parameters that apply to this table are as follows:  
VIO = VDD = VCC = VPA = 3.3 V.  
AOUT_L and AOUT_R outputs have 4.7 series resistors.  
Internal oscillator mode.  
Parameter  
Test Condition  
Min  
Typ  
Max  
Unit  
THD + Noise  
0 dB FS input  
–20 dB FS input  
–60 dB FS input  
—
—
—
–82  
–89  
–89  
—
—
—
dB  
dB  
dB  
Dynamic Range  
Noise Level  
A-weighted  
Output muted  
20 Hz – 20 kHz  
—
—
—
89  
—
—
—
dB  
dB  
dB  
–103  
Frequency response  
+0.04,  
–0.11  
Rev. 1.1  
11  
CP2114  
Table 13. Absolute Maximum Ratings  
Parameter  
Ambient Temperature Under Bias  
Storage Temperature  
Test Condition  
Min  
–55  
–65  
Typ  
—
Max  
125  
150  
5.8  
Unit  
°C  
°C  
V
—
2
2
Voltage on RST, GPIO, I S, I C, or UART Pins with  
respect to GND  
V
V
> 2.2 V  
< 2.2 V  
–0.3  
–0.3  
—
—
IO  
IO  
V
+
IO  
3.6  
Voltage on VBUS with respect to GND  
V
> 3.0 V  
not powered  
–0.3  
–0.3  
—
—
5.8  
V
DD  
V
V
+
DD  
DD  
3.6  
Voltage on V or V with respect to GND  
–0.3  
—
—
—
—
4.2  
V
DD  
IO  
Maximum Total Current through V , V , and GND  
500  
100  
mA  
mA  
DD  
IO  
Maximum Output Current Sunk by RST or any I/O pin  
—
Note: Stresses above those listed may cause permanent damage to the device. This is a stress rating only, and functional  
operation of the devices at or exceeding the conditions in the operation listings of this specification is not implied.  
Exposure to maximum rating conditions for extended periods may affect device reliability.  
12  
Rev. 1.1  
CP2114  
3. Pinout and Package Definitions  
Table 14. CP2114 Pin Definitions  
Name  
Pin #  
Type  
Power In Power Supply Voltage Input.  
Description  
VDD  
7
Power Out Voltage Regulator Output. See Section 10.  
Power In I/O Supply Voltage Input.  
VIO  
GND  
RST  
6
3
Ground. Must be tied to ground.  
10  
D I/O  
Device Reset. Open-drain output of internal POR or V monitor. An external  
DD  
source can initiate a system reset by driving this pin low for the time specified  
in Table 3.  
REGIN  
VBUS  
8
9
Power In 5 V Regulator Input. This pin is the input to the on-chip voltage regulator.  
D In  
VBUS Sense Input. This pin should be connected to the VBUS signal of a  
USB network.  
D+  
D–  
4
5
D I/O  
D I/O  
USB D+  
USB D–  
VPP  
21*  
Special Connect a 4.7 µF capacitor between this pin and ground to support one-time  
programming via the USB interface.  
SUSPEND  
SUSPEND  
17*  
18*  
D Out  
This pin indicates whether the device is in the USB Suspend or not (active-  
low).  
D Out  
This pin indicates whether the device is in the USB Suspend or not (active-  
high).  
2
SCK  
SDIN  
2
1
D Out  
D In  
Serial clock output signal for the I S interface.  
2
Serial data input signal for the I S interface.  
2
SDOUT  
MCLK  
LRCK  
32  
25  
23  
31*  
D Out  
D Out  
D Out  
D In  
Serial data output signal for the I S interface.  
2
Master clock output signal for the I S interface.  
2
Left-right clock output for the I S interface.  
EXTCLK  
External clock input of CP2114 (optional). An external clock is needed if the  
codec/DAC does not support a 12.000 MHz master clock (MCLK).  
2
SDA  
SCL  
27  
26  
D I/O  
D I/O  
D I/O  
Serial data signal for the I C interface.  
2
Serial clock signal for the I C interface.  
GPIO.0  
30*  
User-configurable input or output.  
RMUTE  
D In  
Record Mute: Toggles record between mute and un-mute each time this pin is  
driven low.  
GPIO.1  
PMUTE  
29*  
D I/O  
D In  
User-configurable input or output.  
Playback Mute: Toggles playback between mute and un-mute each time this  
pin is driven low.  
*Note: Pins can be left unconnected when not used.  
Rev. 1.1  
13  
CP2114  
Table 14. CP2114 Pin Definitions (Continued)  
Name  
Pin #  
Type  
Description  
User-configurable input or output.  
GPIO.2  
14*  
D I/O  
VOL-  
D In  
Decreases volume each time this pin is driven low.  
User-configurable input or output.  
GPIO.3  
13*  
12*  
28*  
D I/O  
VOL+  
D In  
Increases volume each time this pin is driven low.  
User-configurable input or output.  
GPIO.4  
D I/O  
RMUTELED  
GPIO.5  
D Out  
D I/O  
Record Mute LED: This pin is driven low while recording is muted.  
User-configurable input or output.  
TXT  
D Out  
This pin toggles while the UART is transmitting data and is logic high when  
the UART is not transmitting data.  
Selects one of the predefined DACs. See Section 8.2 for more information.  
User-configurable input or output.  
DACSEL0  
GPIO.6  
D In  
11*  
D I/O  
RXT  
Out  
This pin toggles while the UART is receiving data and is logic high when the  
UART is not receiving data.  
Selects one of the predefined DACs. See Section 8.2 for more information.  
User-configurable input or output.  
DACSEL1  
GPIO.7  
D In  
19*  
20*  
D I/O  
RTS  
D Out  
Ready to Send control output (active low) for the UART Interface.  
DACSEL2  
GPIO.8  
D In  
Selects one of the predefined DACs. See Section 8.2 for more information.  
User-configurable input or output.  
D I/O  
CTS  
D In  
Clear To Send control input (active low) for the UART Interface.  
DACSEL3  
GPIO.9  
D In  
Selects one of the predefined DACs. See Section 8.2 for more information.  
User-configurable input or output.  
22*  
16*  
15*  
24*  
D I/O  
CLKOUT  
GPIO.10  
D Out  
D I/O  
Outputs a configurable frequency clock signal.  
User-configurable input or output.  
TX  
D Out  
D I/O  
Asynchronous data output (UART Transmit) for the UART Interface.  
User-configurable input or output.  
GPIO.11  
RX  
NC  
D In  
Asynchronous data input (UART Receive) for the UART Interface.  
This pin should be left unconnected or tied to V  
IO.  
*Note: Pins can be left unconnected when not used.  
14  
Rev. 1.1  
CP2114  
SDIN  
SCK  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
NC  
LRCK  
GND  
GPIO.9_CLKOUT  
VPP  
D+  
D-  
CP2114-GM  
Top View  
GPIO.8_CTS_DACSEL3  
GPIO.7_RTS_DACSEL2  
SUSPEND  
VIO  
VDD  
REGIN  
GND (optional)  
SUSPEND  
Figure 5. QFN-32 Pinout Diagram (Top View)  
Rev. 1.1  
15  
CP2114  
4. QFN-32 Package Specifications  
Figure 6. QFN-32 Package Drawing  
Table 15. QFN-32 Package Dimensions  
Dimension  
Min  
Typ  
Max  
Dimension  
Min  
Typ  
Max  
A
A1  
b
D
D2  
0.80  
0.00  
0.18  
0.90  
0.02  
0.25  
1.00  
0.05  
0.30  
E2  
L
L1  
aaa  
bbb  
ddd  
eee  
3.20  
0.30  
0.00  
—
—
—
3.30  
0.40  
—
—
—
3.40  
0.50  
0.15  
0.15  
0.10  
0.05  
0.08  
5.00 BSC.  
3.30  
0.50 BSC.  
5.00 BSC.  
3.20  
3.40  
e
E
—
—
—
Notes:  
1. All dimensions shown are in millimeters (mm) unless otherwise noted.  
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.  
3. This drawing conforms to the JEDEC Solid State Outline MO-220, variation VHHD except for  
custom features D2, E2, and L which are toleranced per supplier designation.  
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body  
Components.  
16  
Rev. 1.1  
CP2114  
Figure 7. QFN-32 Recommended PCB Land Pattern  
Table 16. QFN-32 PCB Land Pattern Dimensions  
Dimension  
Min  
Max  
Dimension  
Min  
Max  
C1  
C2  
E
4.80  
4.80  
4.90  
4.90  
X2  
Y1  
Y2  
3.20  
0.75  
3.20  
3.40  
0.85  
3.40  
0.50 BSC  
X1  
0.20  
0.30  
Notes:  
General  
1. All dimensions shown are in millimeters (mm) unless otherwise noted.  
2. This Land Pattern Design is based on the IPC-7351 guidelines.  
Solder Mask Design  
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder  
mask and the metal pad is to be 60 m minimum, all the way around the pad.  
Stencil Design  
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used  
to assure good solder paste release.  
5. The stencil thickness should be 0.125 mm (5 mils).  
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.  
7. A 3x3 array of 1.0 mm square openings on 1.2 mm pitch should be used for the center ground  
pad.  
Card Assembly  
8. A No-Clean, Type-3 solder paste is recommended.  
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small  
Body Components.  
Rev. 1.1  
17  
CP2114  
5. Audio (I2S and I2C) Interfaces  
2
2
The I C interface configures the DAC to output sound and the I S interface provides the digital audio stream to the  
DAC. In addition to full-featured off the shelf functionality, the CP2114 can be customized in two ways; via one-time  
programmable ROM configuration and a real-time API.  
5.1. One-Time Programmable ROM Configuration Programming  
The CP2114 has 5.5kB of on board one-time programmable ROM available to store up to 29 different custom  
configurations. Three of the 32 slots are preprogrammed configurations. The configurations can be selected as  
2
boot configurations and will automatically configure the CP2114 and the I C connected DAC when the CP2114 is  
powered on. Alternatively the custom configurations can be assigned to a DAC select pin selection. The boot  
configuration is then selected by pin-strapping the DAC select pins. Silicon Labs provides a PC GUI application to  
program the configuration to the CP2114 one-time programmable ROM. The CP2114 can be programmed on a  
production line or a configuration file can be provided to Silicon Labs and pre-programmed parts can be supplied  
directly by Silicon Labs.  
5.2. Real-Time Programming  
The CP2114 presents the host with a USB HID interface which can be used to send messages directly to the  
2
CP2114 for internal configuration or directly to the DAC over the I C interface. This provides real-time configuration  
changes to the CP2114 and DAC via host program control. In addition, the USB HID pipe can be used to write and  
read to the CP2114 GPIO pins as desired.  
2
5.3. CP2114 I S and Left-Justified Digital Audio  
2
The CP2114 supports “I S” and “Left-Justified” digital audio formats. Note that the difference in the two modes is  
2
that for the I S format, the MSB of the data streams (SDOUT and SDIN) are delayed by one clock (SCK) cycle after  
the channel clock (LRCK) transitions as compared to the Left Justified format. The digital audio format can be  
2
configured in the CP2114 one-time programmable ROM. Figure 8 shows the signals in I S format, and Figure 9  
shows the signals in Left-Justified format.  
MCLK  
Left Channel  
LRCK  
SCK  
Right Channel  
MSB  
MSB  
-1  
-1  
-2  
-2  
+2  
+2  
+1  
+1  
LSB  
LSB  
MSB  
MSB  
-1  
-1  
-2  
-2  
+2  
+2  
+1  
+1  
LSB  
LSB  
SDOUT  
SDIN  
Figure 8. I2S Format  
18  
Rev. 1.1  
CP2114  
MCLK  
LRCK  
Left Channel  
Right Channel  
SCK  
MSB  
MSB  
-1  
-1  
-2  
-2  
-3  
-3  
+2  
+2  
+1  
+1  
LSB  
LSB  
MSB  
MSB  
-1  
-1  
-2  
-2  
-3  
-3  
+2  
+2  
+1  
+1  
LSB  
SDOUT  
SDIN  
LSB  
Figure 9. Left-Justified Format  
MCLK: Master Clock. This is a high frequency clock to the connected audio device (e.g. CODEC or DAC) used for  
the Digital to Analog conversion process within the connected audio device. This clock will be a multiple of the  
LRCK going to the connected audio device. Typically MCLK = 250*LRCK or MCLK=256*LRCK.  
LRCK: Left-Right Clock. This is used to synchronize the connected audio device audio data word timing with the  
CP2114 audio data word timing (i.e., edges are used to synchronize the beginning of the left and right audio  
samples).  
SCK: Bit Synchronization Clock (also called BCLK). This provides a timing signal used by the connected audio  
device to latch the audio output data bits on SDOUT and assert the audio input data bits on SDIN.  
SDOUT: Audio-out data stream going to the connected audio device (e.g. CODEC).  
SDIN: Audio-in data stream coming from the connected audio device (e.g. CODEC).  
Note: MCLK, LRCK, SCK and SDOUT are driven by the CP2114. SDIN is driven by the connected audio device.  
The CP2114 supports only 48 kHz, 16 bit digital audio. This is typically not an issue for source USB audio as the  
device capabilities are reported to the host and any sample rate conversion (for say 44.1 kHz audio) is done  
2
automatically by the host. However, some audio devices may require 24-bit digital audio data on the I S data  
stream. In this case, the CP2114 will send the useful 16-bit audio to the connected audio device on SDOUT in the  
most significant 16 bits and pad the remaining 8 bits of data with 0s. Likewise the CP2114 will read the MSB 16 bits  
of data on DIN and throw out the LSB 8 bits from SDIN. The CP2114 can be configured in 16 bit or 24 bit mode via  
a configuration option in the CP2114 one-time programmable ROM.  
5.4. USB and Digital Audio Clock Requirements  
The CP2114 supports a number of clock configurations allowing support for a variety of audio devices and  
associated clocking options to optimize cost and quality. The two clocks of consideration are:  
USB Clock: Full speed USB requires devices have a 12 MHz clock with tolerance of ±0.25%. This means the USB  
device (CP2114) must maintain its USB clock in the range of 11.97 MHz < USB Clock < 12.03 MHz. This range is  
supported by the CP2114 which also has built-in USB clock recovery. However, it does have implications on the  
audio device.  
Digital Audio Clock (MCLK): Audio devices typically require that MCLK must be a multiple of LRCK, and this  
multiple is typically required to be 250 or 256 (or some sub or super multiple of these values). Given an audio  
sample rate of LRCK = 48 kHz, the resulting MCLK requirement is shown in Equation 1 or Equation 2.  
MCLK = 250 48 kHz = 12.000 MHz  
Equation 1. Digital Audio Clock (MCLK) Frequency for a Multiple of 250  
MCLK = 256 48 kHz = 12.288 MHz  
Equation 2. Digital Audio Clock (MCLK) Frequency for a Multiple of 256  
Rev. 1.1  
19  
CP2114  
An audio device accepting a multiple of 250 is thus compatible with USB clock requirements, whereas an audio  
device requiring a 256 multiple is fundamentally incompatible with USB clock requirements. In this case, generally  
one clock is needed for USB and another clock is needed for audio. The CP2114 supports a variety of  
configurations to address this issue and is covered in Section 5.6.  
5.5. USB Audio Synchronization Modes  
The USB standard defines synchronization relative to source and sinks. For audio-out, the host is the source and  
the device is the sink. For audio-in, the device is the source and the host is the sink. USB defines modes which  
govern the operation of sources and sinks according to the following table. The CP2114 supports asynchronous  
and synchronous modes.  
Table 17. USB Audio Synchronization Modes  
Mode  
Source  
Sink  
Asynchronous  
Free running clock  
Free running clock  
Provides implicit feedforward to the sink  
Provides explicit feedback to the source  
Synchronous  
Adaptive  
Clock locked to USB SOF  
Uses implicit feedback  
Clock locked to the USB SOF  
Uses implicit feedback  
Clock locked to sink  
Uses explicit feedback  
Clock locked to the data flow  
Uses implicit feedback  
Notes:  
1. Implicit feedforward means the recipient determines the next data input size according to the current input  
size (i.e. if 48 samples were sent in the current frame then expect the same number in the next frame).  
2. Explicit feedback means the recipient of the feedback will receive an explicit request for the number of  
samples to send in the next frame.  
20  
Rev. 1.1  
CP2114  
5.6. CP2114 Clock Configuration  
The CP2114 always reports its capabilities to the USB host at a sample rate of 48 kHz and sample size of 16 bits.  
For source audio files differing from this format the USB host will automatically perform sample rate conversion.  
The CP2114 has the following configuration options:  
Table 18. Clock Configuration Options  
Configuration Parameter  
Stream Type  
Options  
Asynchronous  
Internal  
Internal  
48 MHz  
250  
Synchronous  
External  
USB Clock Source  
System Clock Source  
System Clock Frequency  
MCLK/LRCK Ratio  
External  
49.152 MHz  
256  
Table 19 shows all possible clock configuration settings for the CP2114. The CP2114 divides the USB source clock  
by 4 so a clock of 48 MHz provides the 12 MHz clock needed for USB. The CP2114 divides the system clock by 4  
to derive MCLK. So a 48 MHz system clock will generate MCLK = 12 MHz. If the CP2114 is configured to operate  
in Asynchronous mode, it will automatically use explicit feedback to the host. If it is configured for Synchronous  
mode, then the sample synchronization method is noted in the table. There are a number of invalid clocking  
configurations that result from either the USB clock not resulting in 12 MHz or the MCLK/LRCK not being an  
integer divisor. Operating in asynchronous mode is recommended because it best accommodates any mismatch in  
host/CP2114 clocks. Operating in synchronous mode requires the CP2114 to adjust its internal oscillator to match  
the host sample rate, or to periodically drop or repeat an audio sample if SYSCLK is driven by an External Clock.  
Table 19. Valid Clock Configuration Modes  
Mode  
USB  
System  
Clock  
Int Freq  
(MHz)  
MCLK/  
LRCK  
Ext Osc  
Freq  
(MHz)  
Notes  
Clock  
Ratio  
(USBCLK) (SYSCLK)  
Source  
Source  
Lowest cost - no external clock required  
Audio device must support 12.0 MHz MCLK  
1
Int  
Int  
48  
48  
250  
NA  
Sync mode: IntOsc adjusted to  
accommodate clock mismatch  
Async mode: best audio quality  
2
3
Int  
Ext  
Int  
256  
49.152  
48  
Sync mode: must drop/repeat samples to  
accommodate clock mismatch  
IntOsc frequency dictated by audio device  
Ext  
48  
49.152  
250  
256  
MCLK/LRCK ratio  
Sync mode: IntOsc adjusted to  
accommodate clock mismatch  
Audio device must support 12.0 MHz MCLK  
Async mode: best audio quality  
4
Ext  
Ext  
48  
250  
48  
Sync mode: must drop/repeat samples to  
accommodate clock mismatch  
Rev. 1.1  
21  
CP2114  
Figure 10 shows the clocking scheme, with the configurable options shown in darker boxes.  
The USB clock frequency must always be 12 MHz whether using the internal or an external oscillator.  
MCLK is SYSCLK/4 and so will be 12 MHz or 12.288 MHz (as determined by the audio device clock  
requirement).  
LRCK is MCLK divided by 250 or 256 in order to get the correct 48 kHz sample rate conversion.  
For MCLK = 12.288 MHz, the LRCK divisor must be 256.  
For MCLK = 12.000 MHz, the LRCK divisor must be 250.  
LRCK gates SCK and SCK is driven at SYSCLK / 14.  
SCK is the clock for SDOUT and SDIN.  
CMOS Oscillator  
48MHz/  
49.152MHz  
SYSCLK  
MCLK  
4
250/256  
14  
MCLK  
LRCK  
SCK  
4
Internal  
Oscillator  
48MHz/49.152  
LRCK  
SCK  
USB  
Block  
USB  
Audio Out Buffer  
SDOUT  
SDIN  
MSB  
MSB  
-1  
-1  
SDOUT  
SDIN  
Audio In Buffer  
Figure 10. Clock Configuration Block Diagram  
The particular setting for configuration 1 (USB and SYSCLK = internal frequency of 48 MHz, MCLK/LRCK  
divisor = 250) is shown in Figure 11.  
NC  
SYSCLK  
MCLK  
4
MCLK  
LRCK  
SCK  
4
Internal  
Oscillator  
48MHz  
LRCK  
SCK  
250  
14  
USB  
Block  
USB  
Audio Out Buffer  
SDOUT  
SDIN  
MSB  
MSB  
-1  
-1  
SDOUT  
SDIN  
Audio In Buffer  
Figure 11. Configuration 1 Example  
22  
Rev. 1.1  
CP2114  
6. USB Function Controller and Transceiver  
The Universal Serial Bus (USB) function controller in the CP2114 is a USB 2.0 compliant full-speed device with  
integrated transceiver and on-chip matching and pullup resistors. The USB function controller manages all control,  
audio, and UART transfers between the USB and the CP2114. The USB Suspend and Resume modes are  
supported for power management of both the CP2114 device as well as external circuitry. The CP2114 will enter  
Suspend mode when Suspend signaling is detected on the bus. On entering Suspend mode, the Suspend signals  
are asserted. The Suspend signals are also asserted after a CP2114 reset until device configuration during USB  
enumeration is complete. The SUSPEND pin is logic high when the device is in the Suspend state, and logic low  
when the device is in the normal mode. The SUSPEND pin has the opposite logic value of the SUSPEND pin.  
The CP2114 exits Suspend mode when any of the following occur: Resume signaling is detected or generated, a  
USB Reset signal is detected, or a device reset occurs. SUSPEND and SUSPEND are weakly pulled to VIO in a  
high impedance state during a CP2114 reset. If this behavior is undesirable, a strong pulldown (10 k) can be used  
to ensure SUSPEND remains low during reset.  
The logic level and output mode (push-pull or open-drain) of various pins during USB Suspend is configurable in  
the PROM. See Section 9 for more information.  
7. Asynchronous Serial Data Bus (UART) Interfaces  
The UART interface consists of the TX (transmit) and RX (receive) data signals as well as RTS (ready to send) and  
CTS (clear to send) flow control signals. The UART is programmable to support a variety of data formats and baud  
rates. The data formats and baud rates available are listed in Table 20.  
Table 20. Data Formats and Baud Rates  
5, 6, 7, and 8  
Data Bits  
Stop Bits  
1
1, 1.5 , and 2  
Parity Type  
Baud Rate  
None, Even, Odd, Mark, Space  
2, 3, 4, 5  
300 bps to 1 Mbps  
Notes:  
1. 1.5 stop bits only available when using 5 data bits.  
2. Baud rates above 500,000 baud are not supported with 5 or 6  
data bits  
3. Max of 500 kBaud with flow control, audio playback only  
4. Max of 230 kBaud with flow control, audio playback and listening  
5. With flow control, audio can support higher baud rates, but  
throughput is greatly reduced.  
The baud rate generator for the UART interface is very flexible, allowing the user to request any baud rate in the  
range from 300 bps to 1 Mbps. If the baud rate cannot be directly generated from the 48 MHz oscillator, the device  
will choose the closest possible option. The actual baud rate is dictated by Equation 3 and Equation 4.  
Prescale = 4 if Requested Baud Rate 300 bps  
Prescale = 1 if Requested Baud Rate 300 bps  
48 MHz  
----------------------------------------------------------------------------------------------------  
Clock Divider =  
2 Prescale Requested Baud Rate  
Equation 3. Clock Divider Calculation  
Prescale = 4 if Requested Baud Rate 300 bps  
Prescale = 1 if Requested Baud Rate 300 bps  
48 MHz  
2 Prescale Clock Divider  
----------------------------------------------------------------------------  
Actual Baud Rate =  
Equation 4. Baud Rate Calculation  
Most baud rates can be generated with an error of less than 1.0%. A general rule of thumb for the majority of UART  
applications is to limit the baud rate error on both the transmitter and the receiver to no more than ±2%. The clock  
Rev. 1.1  
23  
CP2114  
divider value obtained in Equation 3 is rounded to the nearest integer, which may produce an error source. Another  
error source will be the 48 MHz oscillator, which is accurate to ±0.25%. Knowing the actual and requested baud  
rates, the total baud rate error can be found using Equation 5.  
Actual Baud Rate  
Requested Baud Rate  
----------------------------------------------------------  
Baud Rate Error (%) = 100 1 –  
0.25%  
Equation 5. Baud Rate Error Calculation  
The UART also supports the transmission of a line break. The length of time for a line break is programmable from  
1 to 125 ms, or it can be set to transmit indefinitely until a stop command is sent from the application.  
8. GPIO Pins  
The CP2114 supports twelve user-configurable GPIO pins. Each of these GPIO pins are usable as inputs, open-  
drain outputs, or push-pull outputs. All of the pins have alternate functions which are listed in Table 21. To use the  
pin as a GPIO, the pin must first be configured for that mode. More information regarding the configuration and  
usage of these pins is available in “AN721: CP210x/CP21xx Device Customization Guide” available on the Silicon  
Labs website. The configuration of the pins is one-time programmable for each device. See Section 9 for more  
information about programming the GPIO pin functionality.  
Table 21. GPIO Alternate Functions  
Pin  
Default Function  
Alternate Function 1  
(GPIO Function)  
Alternate Function 2  
GPIO.0_RMUTE  
GPIO.1_PMUTE  
Record Mute  
Playback Mute  
Volume Down  
Volume Up  
GPIO.0  
GPIO.1  
GPIO.2  
GPIO.3  
GPIO.4  
GPIO.5  
GPIO.6  
GPIO.7  
GPIO.8  
GPIO.9  
GPIO.10  
GPIO.11  
GPIO.2_VOL-  
GPIO.3_VOL+  
GPIO.4_RMUTELED  
GPIO.5_TXT_DACSEL0  
GPIO.6_RXT_DACSEL1  
GPIO.7_RTS_DACSEL2  
GPIO.8_CTS_DACSEL3  
GPIO.9_CLKOUT  
GPIO.10_TX  
Record Mute LED  
DAC Selector 0  
DAC Selector 1  
DAC Selector 2  
DAC Selector 3  
Clock Output  
UART TX  
TX Toggle  
RX Toggle  
UART RTS  
UART CTS  
GPIO.11_RX  
UART RX  
The difference between an open-drain output and a push-pull output is when the GPIO output is driven to logic  
high. A logic high, open-drain output pulls the pin to the VIO rail through an internal, pull-up resistor. A logic high,  
push-pull output directly connects the pin to the VIO voltage. Open-drain outputs are typically used when  
interfacing to logic at a higher voltage than the VIO pin. These pins can be safely pulled to the higher, external  
voltage through an external pull-up resistor. The maximum external pull-up voltage is 5 V.  
The speed of reading and writing the GPIO pins is subject to the timing of the USB bus. GPIO pins configured as  
inputs or outputs are not recommended for real-time signaling.  
24  
Rev. 1.1  
CP2114  
8.1. GPIO.0-4—Audio Playback and Record  
The CP2114 includes several audio playback and record signals, such as volume increase, volume decrease,  
playback mute, and record mute. When connected over USB, the CP2114 can control the host volume settings  
with these pins via the standard USB HID Consumer Control Interface. On the CP2114 evaluation board, these  
pins are all connected to buttons. Single-pressing the volume increase (GPIO.3_VOL+) and volume decrease  
(GPIO.2_VOL-) buttons will increase or decrease the volume; holding the button will continue increasing or  
decreasing the volume. If playback is muted, changing the volume with either of these buttons will unmute  
playback. In addition, there are two mute functions implemented as well. Single-pressing the record mute  
(GPIO.0_RMUTE) and the playback mute (GPIO.1_PMUTE) buttons will toggle between mute and unmute states.  
When record is muted, the signal GPIO.4_RMUTELED will be driven low (and illuminate an LED on the evaluation  
board).  
8.2. GPIO.5-8—DAC Selection  
The state of GPIO.5 through GPIO.8 specify which DAC configuration will be loaded after reset. By default,  
GPIO.5, GPIO.6, GPIO.7, and GPIO.8 are all configured for the DAC selection function (Alternate Function 1). If  
the four GPIO.5 through GPIO.8 pins are all configured as DAC Select inputs (their default configuration), the state  
of these pins specifies which DAC configuration will be loaded after reset (see Table 22). The boot DAC  
configuration specified by the one-time programmable ROM will be used if the state of these DAC Select pins is  
1110b (Index 14), or if any of the four GPIO.5-8 pins have been configured to something other than DAC Select.  
The No DAC configuration option (1111b, i.e., Index 15) should be used when bringing up a new DAC. Using this  
configuration, DAC configuration text files can be written to RAM and tested until the DAC configuration string is  
finalized. At that point, the configuration string can be programmed into the one-time programmable ROM. DAC  
selection pin mapping is shown in Table 22.  
Table 22. DAC Selection Pin Mapping  
Index  
GPIO.8  
GPIO.7  
GPIO.6  
GPIO.5  
Boot DAC configuration  
DACSEL3 DACSEL2 DACSEL1 DACSEL0  
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Config[0]: CS42L55  
Config[1]: WM8523  
Config[2]: PCM1774  
2
3
4
5
6
7
8
9
User-programmed DAC configurations  
10  
11  
12  
13  
14  
Boot DAC configuration is specified by the one-  
time programmable ROM  
15  
1
1
1
1
No DAC configuration  
Rev. 1.1  
25  
CP2114  
8.3. GPIO.5-6—UART Transmit and Receive Toggle  
GPIO.5 and GPIO.6 are configurable as UART Transmit Toggle and Receive Toggle pins. These pins are logic high  
when a device is not transmitting or receiving data, and they toggle at a fixed rate as specified in Table 5 when  
UART data transfer is in progress. Typically, these pins are connected to two LEDs to indicate data transfer.  
VIO  
CP2114  
GPIO.5 – TX Toggle  
GPIO.6 – RX Toggle  
Figure 12. Transmit and Receive Toggle Typical Connection Diagram  
26  
Rev. 1.1  
CP2114  
8.4. GPIO.7-8—Hardware Flow Control (RTS and CTS)  
To utilize the functionality of the RTS and CTS pins of the CP2114, the device must be configured to use hardware  
flow control.  
RTS, or Ready To Send, is an active-low output from the CP2114 and indicates to the external UART device that  
the CP2114’s UART RX FIFO has not reached the watermark level and is ready to accept more data. When the  
CP2114 is processing audio, the watermark level is 2 bytes. When the CP2114 is not processing audio, the  
watermark is 226 bytes. When the amount of data in the RX FIFO reaches the watermark, the CP2114 pulls RTS  
high to indicate to the external UART device to stop sending data.  
CTS, or Clear To Send, is an active-low input to the CP2114 and is used by the external UART device to indicate to  
the CP2114 when the external UART device’s RX FIFO is getting full. The CP2114 will not send more than two  
bytes of data once CTS is pulled high.  
CP2114  
RS-232  
DTE  
TX  
RX  
TX  
RX  
GPIO.7 – RTS  
GPIO.8 – CTS  
RTS  
CTS  
Figure 13. Hardware Flow Control Typical Connection Diagram  
8.5. GPIO.9—Clock Output  
GPIO.9 is configurable to output a configurable CMOS clock output. The clock output appears at the pin at the  
same time the device completes enumeration and exits USB Suspend mode. The clock output is removed from the  
pin when the device enters USB Suspend mode. The output frequency is configurable through the use of a divider  
and the accuracy is specified in Table 6. The output frequency is 24 MHz when the divider is set to 0 and the  
system clock is 48 MHz. The output frequency is 24.576 MHz when the divider is set to 0 and the system clock is  
49.152 MHz. For divider values between 1 and 255, the output frequency is determined by the formula:  
SYSCLK  
2 ClockDivider  
----------------------------------------------  
GPIO.9 Clock Frequency =  
Equation 6. GPIO.9 Clock Output Frequency  
Rev. 1.1  
27  
CP2114  
9. One-Time Programmable ROM  
The CP2114 has an internal 5.5 kB configuration one-time programmable ROM. There are two configuration areas  
in the one-time programmable ROM:  
1. Global configuration area. This area stores the USB string descriptors and GPIO pin configuration. The  
CP2114 ships with default global configuration settings that allow the CP2114 to be used as-is for customer  
production. There is also a Customer Global Configuration area that provides customization of the device if  
desired.  
2. Audio specific configuration area. This area stores up to 32 different audio configurations. The  
configurations set behavior of the CP2114 audio functions as well as configuration data for DACs.  
The one-time programmable ROM is shown in Figure 14. Note that the CP2114 standard device ships pre-  
programmed for three different DACs, with the desired DAC being selected via the DAC Select pins (DACSEL0,  
DACSEL1, DACSEL2, DACSEL3). Additional DAC support can be added, and configuration of that DAC controlled  
by an one-time programmable ROM setting or by the DAC select pins. If the programmable ROM has not been  
programmed, the device uses the default configuration data shown in Table 26 and Table 27.  
The configuration data ROM can be programmed by Silicon Labs prior to shipment with the desired configuration  
information. It can also be programmed in-system over the USB interface by adding a capacitor to the PCB. If the  
configuration ROM is to be programmed in-system, a 4.7 µF capacitor must be present between the VPP pin and  
ground. No other circuitry should be connected to VPP during a programming operation, and VIO must remain at  
3.3 V or higher to successfully write to the configuration ROM.  
Digital Audio Signal  
CP2114  
I2S  
Audio  
DAC  
USB  
Host  
USB  
I2C  
Controller  
4
RAM  
Config  
DAC  
Select  
DAC Configuration  
& Control  
Pins[0:3]  
EPROM  
Empty0  
Empty1  
Empty2  
Empty3  
Empty4  
CS42L55  
WM8523  
Default  
Global  
Config  
PCM1774  
Audio Config  
Empty  
Customized  
Global  
Config  
Empty31  
Global  
Config  
Area  
Boot  
Index  
Area  
Audio  
Config  
Area  
Figure 14. One-Time Programmable ROM Configuration Block Diagram  
28  
Rev. 1.1  
CP2114  
9.1. Audio Interface Configuration  
The Audio configuration area is used to configure the boot index as well as the audio configuration strings. The  
boot index determines which of the programmed audio configuration strings will be used after reset. The following  
sections describe the audio interface in more detail.  
9.1.1. Audio Interface Boot Configuration Process  
The global configurations are automatically loaded when the CP2114 powers up. The audio boot configuration  
depends on the GPIO DAC select pin settings according to flow chart shown in Figure 15. The audio configuration  
can be set by a one-time programmable ROM boot index or by reading the boot index from the DAC Select pins.  
Setting the DAC_Select pins to 0x0F will not boot any DAC configuration. This is needed for adding support for a  
new DAC. In this case, the Silicon Labs GUI can be used to write the DAC settings. After experimentation and  
testing, the configuration can be written to the one-time programmable ROM. The one-time programmable ROM  
can be programmed in-system or Silicon Labs can provide preprogrammed parts with a customer configuration.  
Boot  
Read EPROM  
Global Config  
Yes  
Use DAC  
Select Pins?  
Boot Index =  
DAC Select Pins  
No  
Boot Index =  
EPROM Boot  
Index  
Yes  
No  
Boot Index  
= 0x0E?  
No  
Load CP2114  
Config from  
EPROM  
Boot Index  
= 0x0F?  
Yes  
Program DAC  
config over I2C  
Do not load any  
audio config  
Enumerate USB  
Low Power  
Suspend waiting  
for USB traffic  
Figure 15. Boot Configuration Flowchart  
Rev. 1.1  
29  
CP2114  
9.1.2. Audio Configuration String Format  
There are two components to the audio configuration of the CP2114:  
1. Programmability of the CP2114 itself.  
2. Programmability of the DAC.  
To simplify the configuration of the CP2114 and the attached DAC, a unified configuration string is employed. The  
first 30 bytes of this configuration string are for the CP2114 audio and control properties. All data after byte 30 is for  
configuration of the DAC. Table 23 shows the format of the configuration string for the CP2114 and attached DAC.  
Note also that in the DAC configuration part there may be “in-band” commands. These are special characters that  
are used to specify delays and are documented in the following sections.  
In the one-time programmable ROM, the audio configuration string is preceded by a two-byte length field  
specifying the total size of the configuration in bytes including the two-byte length field itself. The least significant  
byte (LSB) of the length field goes first. For example, the audio configuration for the CS42L55 DAC consists of 98-  
byte configuration. The length field itself is 2-byte long, which makes the total size 100-byte. The audio  
configuration starts with 0x64, 0x00 followed by the configuration string. The CP2114 configuration program only  
requires the configuration string. The program will parse the string, calculate the total length, and insert the length  
field before sending the request to the device.  
Table 23. Audio Configuration String  
Byte  
Name  
Description  
0
1
2
DAC_Version Identifies revision of DAC  
User_Defined User can store any info desired here  
2
I2C_Address Specify the DAC I C address  
30  
Rev. 1.1  
CP2114  
Table 23. Audio Configuration String  
Description  
Byte  
Name  
3
Audio_Props Controls audio properties  
Bit Position  
Bit Name  
MB  
7
6
5
4
3
2
1
0
MB  
ST  
I2C_CK I2C_PR  
DRS  
DVC  
LJMS  
AF  
Mute Bit.  
0: No affect  
1: CP2114 will handle mute via mute bits at bytes 12,13,14,15 and 17  
ST  
Synchronization Type  
0: Asynchronous. Will send feedback to USB host.  
1: Synchronous. No feedback to USB host. Audio is synchronized via continuous  
clock adjustment of sample insert/drop, depending on clock configuration.  
2
I2C_CK  
I2C_PR  
DRS  
Maximum I C clock rate supported by the DAC.  
0: 400 kHz  
1: 100 kHz  
2
I C Protocol for read operations.  
0: Stop  
1: Repeated Start  
DAC Register Size  
0: 8 bit  
1: 16 bit  
DVC  
DAC Volume Control.  
0: No volume control supported by DAC  
1: Volume control supported by DAC  
If set, the CP2114 populates volume control in the feature unit USB descriptor. If  
clear, 0 is specified in volume control to prevent the host from sending SET_CUR  
requests.  
2
LJMS  
AF  
I S Mode. Only applies if using Left Justified format.  
0: 16bit Left Justified Mode.  
1: 24bit Left Justified Mode  
Audio Format  
0: I S format  
2
1: Left Justified format  
4
5
6
Min_Volume Minimum Volume in dB, 8-bit signed. This corresponds to the volume control attri-  
bute MIN in USB Audio spec.  
Max_Volume Maximum Volume in dB, 8-bit signed. This corresponds to the volume control attri-  
bute MAX in USB Audio spec.  
Vol_Step  
Volume Step Counts per dB. For instance, if volume resolution is 0.25 dB, 4 shall be  
written. A computed RES is returned in response to volume control attribute query  
of RES from the host.  
Rev. 1.1  
31  
CP2114  
Table 23. Audio Configuration String  
Description  
Byte  
Name  
7
System_Props System Properties  
Bit Position  
Bit Names  
DMMF  
7
6
5
4
3
2
1
0
DMMF  
ARE  
SVRP  
VUR  
UCS  
SCS  
SF  
ACR  
DAC Min/Max register Format.  
0: Unsigned  
1: Signed  
ARE  
Analog Record Enabled  
0: Disable  
1: Enable  
SVRP  
Secondary Volume Registers Polarity.  
0: Secondary volume registers have same polarity as primary registers  
1: Secondary volume registers have opposite polarity as primary registers.  
If only line out is present on the DAC, primary shall be line out; if only headphone is  
present, primary shall be headphone. If both line out and headphone are present on  
the DAC, either can be designated as primary.  
CP2114 updates either or both registers when the host changes volume.  
Some DACs may require a separate bit as a “take into effect immediately” bit.  
VUR  
Volume Update Registers. Some DACs require a specific register is written for vol-  
ume updates to take effect.  
0: DAC has no volume update registers.  
1: DAC has volume update registers.  
UCS  
SCS  
SF  
USB Clock Source  
0: USB clock uses internal oscillator  
1: USB clock uses external oscillator  
System Clock Source. NOTE: Audio clocks will be driven from this source.  
0: Audio uses internal oscillator  
1: Audio uses external oscillator  
System Frequency  
0: 48 MHz  
1: 49.152 MHz  
ACR  
Audio Clock Ratio. This is the MCLK/LRCK ratio.  
0: 250  
1: 256  
8
DPVCL  
DPVCR  
DAC Primary Volume Control Left channel register address.  
9
DAC Primary Volume Control Right channel register address.  
DAC Secondary Volume Control Left channel register address.  
DAC Secondary Volume Control Right channel register address.  
DAC Primary Mute Bit Left Channel register address. Ignored if MB=0.  
DAC Primary Mute Bit Right Channel register address. Ignored if MB=0.  
DAC Secondary Mute Bit Left Channel register address. Ignored if MB=0.  
DAC Secondary Mute Bit Right Channel register address. Ignored if MB=0.  
10  
11  
12  
13  
14  
15  
DSVCL  
DSVCR  
DPMBLC  
DPMBRC  
DSMBLC  
DSMBRC  
32  
Rev. 1.1  
CP2114  
Table 23. Audio Configuration String  
Byte  
Name  
Description  
16  
DVCB  
DAC Volume Control Bits start position and bits count.  
Some DAC volume registers have limited significant bits. This field lets the signifi-  
cant bits be specified. For example if the volume registers use only bit [6:0] you  
would set Volume_Bit_Count=7 and Volume_Bit_Start=0.  
Bit position  
Bit name  
VBC  
7
6
5
4
3
2
1
0
VBC  
VBS  
Volume Bit Count. Specifies number of significant bits for the volume registers  
Volume Bits Start. Specifies the start position of the volume significant bits.  
DAC Mute Bit Positions.  
VBS  
17  
DMBP  
Bit Position  
Bit Name  
DMBPL  
DMBPR  
DVMV  
7
6
5
4
3
2
1
0
DMBPL  
DMBPR  
DAC Mute Bit Position Left channel. Ignored if MB=0.  
DAC Mute Bit Position Right channel. Ignored if MB=0.  
18  
19  
20  
DAC Value Minimum Volume. Specifies the value needed for minimum volume from  
the DAC  
DVXV  
DAC Value Maximum Volume. Specifies the value needed for maximum volume  
from the DAC  
DVUBP  
Bit position  
Bit name  
DVUBPL  
RCUBP  
DAC Volume Update Bit Position. Ignored VUR=0.  
7
6
5
4
3
2
1
0
DVUBPL  
DAC Volume Update Bit Position Left channel  
DAC Volume Update Bit Position Right channel  
RCUBP  
21  
22  
23  
24  
DPVURL  
DAC Primary Volume Update Register Left channel register address. Ignored f  
VUR=0.  
DPVURR  
DSVURL  
DSVURR  
DAC Primary Volume Update Register Right channel register address. Ignored f  
VUR=0.  
DAC Secondary Volume Update Register Left channel register address. Ignored f  
VUR=0.  
DAC Secondary Volume Update Register Right channel register address. Ignored f  
VUR=0.  
Rev. 1.1  
33  
CP2114  
Table 23. Audio Configuration String  
Description  
Byte  
Name  
25  
DMP1  
DAC Mute Property 1  
Bit Position  
Bit Name  
GPION  
7
6
5
4
3
x
2
x
1
0
GPION  
SWM  
MBG  
GPIO Number (0..11) used for DAC mute. Ignored of MBG=0.  
SWM  
GPIO State When Muted. Ignored of MBG=0.  
0: Muted when GPIO is low  
1: Muted when GPIO is high.  
MBG  
Mute By GPIO.  
0: Do not use GPIO for mute.  
1: Use GPIO for Mute.  
26  
DMP2  
DAC Mute Property 2  
Bit Position  
7
6
5
x
4
x
3
x
2
x
1
0
Bit Name  
MBZ  
x
x
MBZ  
MBVR  
Mute By Zeros.  
0: Do not mute by sending 00’s to the DAC  
1: Mute by sending 00’s to the DAC.  
This is useful for a DAC that does not support hardware mute or volume functions.  
Not supported when playback and record are both active.  
MBVR  
DVMV  
Mute By Volume Register.  
0: Do not mute via the volume register.  
1: Mute via the volume register.  
Some DACs mute by sending a specific value to the volume register.  
27  
DAC Volume Mute Value. Mute by sending this value to the volume registers.  
Ignored if MBVR=0.  
28  
29  
Reserved  
Reserved  
Reserved  
Reserved  
30-xx  
DAC Config Start of DAC configuration string and “in-band” commands  
34  
Rev. 1.1  
CP2114  
9.1.3. DAC Configuration String  
2
Starting at byte 30, a DAC configuration string is used to communicate with the DAC over the I C interface. If the  
DAC register size bit is 0 (indicating 8-bit mode), the DAC register/value pairs should be written in the format of:  
Byte[30] = <DAC_Register_Address>  
Byte[31] = <DAC_Register_Value>  
Byte[32] = <DAC_Register_Address>  
Byte[33] = <DAC_Register_Value>  
...  
If the DAC register size bit is 1 (indicating 16-bit mode), the DAC register/value pairs should be written in the format  
of:  
Byte[30] = <DAC_Register_Address>  
Byte[31] = <DAC_Register_Value_MSB>  
Byte[32] = <DAC_Register_Value_LSB>  
Byte[33] = <DAC_Register_Address>  
Byte[34] = <DAC_Register_Value_MSB>  
Byte[35] = <DAC_Register_Value_LSB>  
...  
9.1.4. DAC Configuration In-Band Commands  
To support special functions such as GPIO outputs, arbitrary delay in between DAC register access, DAC power off  
sequence in suspend and power on sequence in active mode, the CP2114 supports special in-band commands  
starting from byte 30. These commands are identified by command codes 0xFA to 0xFF. When parsing DAC  
register/value pairs, if CP2114 firmware encounters 0xFA to 0xFF in the <DAC_Register_Address> field, the  
CP2114 performs the task associated with the command instead of sending it to the DAC.  
SUSPEND_SEQUENCE specifies a sequence of DAC register/value pairs/triplets to power down certain  
blocks on the DAC in suspend mode to minimize power consumption.  
ACTIVE_SEQUENCE specifies a sequence of DAC register/value pairs/triplets to power up certain blocks  
on the DAC in active mode.  
The DELAY_MICROSECONDS, SET_GPIO and DELAY_MILLISECONDS in-band commands can be  
embedded in SUSPEND_SEQUENCE and ACTIVE_SEQUENCE if needed.  
SET_GPIO sets a specified GPIO to high or low.  
DELAY_MICROSECONDS instructs the firmware to introduce a coarse delay of n microseconds as  
specified in the parameter list. Similarly, DELAY_MILLISECONDS instructs the firmware to introduce a  
course delay in milliseconds.  
The format of most In-band commands except for SUSPEND_SEQUENCE and ACTIVE_SEQUENCE is  
analogous to DAC register/value pairs/triplets.  
Rev. 1.1  
35  
CP2114  
Table 24. DAC Configuration In-Band Commands  
Name  
Identifier  
In-Band Parameter List  
In-Band Parameter List  
DAC register size = 0 (8bit)  
DAC register size = 1(16bit)  
SUSPEND_  
SEQUENCE  
0xFA  
<Length in bytes of register/value pairs or  
other in-band commands>  
<reg or other in-band commands>  
<value or in-band command parameter>…  
<Reserved>  
<Length in bytes of register/value triplet  
pairs or other in-band commands>  
<reg or other in-band command ID>  
<Value_Hi or high byte of in-band  
command parameter>  
<Value_Lo or low byte of inband command  
parameter>  
ACTIVE_  
SEQUENCE  
0xFB  
<Length in bytes of register/value pairs or  
other in-band commands>  
<reg or other in-band commands>  
<value or in-band command parameter>…  
<Reserved>  
<Length in bytes of register/value triplet  
pairs or other in-band commands>  
<reg or other in-band command ID>  
<Value_Hi or high byte of in-band  
command parameter>  
<Value_Lo or low byte of inband command  
parameter>  
REENUMER-  
ATE  
0xFC  
0xFD  
<Reserved>  
<Delay>  
<Reserved><Reserved>  
DELAY_  
MICROSEC-  
ONDS  
<Reserved> <Delay>  
SET_GPIO  
0xFE  
0xFF  
(<GPIO_State> << 7 | <GPIO_Number> & <Reserved> (<GPIO_State> << 7 | <GPI-  
0x0F)  
O_Number> & 0x0F)  
DELAY_MIL-  
LISECONDS  
<Delay>  
<Reserved> <Delay>  
The combination of SET_GPIO in-band commands and DELAY commands can be used to send pulses or toggle  
output GPIOs (assuming that these GPIOs have been configured as output pins). Some DACs may require DAC  
reset via a GPIO pin, this can be accomplished with in-band commands as well.  
9.1.5. DAC Initialization  
The DAC configuration string should configure the DAC to initialize with muted playback. DAC volume registers  
should be set to minimum. This allows CP2114 to synchronize with the host at startup.  
36  
Rev. 1.1  
CP2114  
9.1.6. Example CP2114 Configuration String  
As can be seen in the Audio Configuration String Format, a number of fields are dedicated to defining how the DAC  
volume and mute function are implemented in the DAC. This is needed for the CP2114 to properly scale the  
volume from dB to DAC register values using a linear equation and send volume and mute messages from the host  
to the DAC. As an example of CP2114 configuration string, Table 25 shows the configuration string in one-time  
programmable ROM as shipped for the CS42L55 codec.  
Table 25. CS42L55 Configuration String  
Byte  
Value  
01  
Description  
0
DAC Version = 01. This can simply be an identifier for the configuration  
User byte – any purpose  
1
2
3
00  
94  
A6  
2
I C Address of this DAC is 0x94  
MB = 1 Mute is handled with this DAC.  
ST = 0. Use Asynchronous mode—provide feedback to the host.  
2
I2C_CK = 1. Use 100 kHz I C clock.  
2
I2C_PR = 0. I C uses stop bit.  
DRS = 0. DAC has 8-bit registers.  
DVC = 1. DAC volume control is supported  
LJMS = 1. 24bit Left Justified mode is used.  
AF = 0. Left Justified format is used.  
4
5
6
7
C4  
0C  
01  
Minimum volume value for the DAC is 0xC4 = –60 dB.  
Maximum volume for the DAC is 0x0C = 12 dB  
Volume step per dB is 1.  
E0  
DMMF = 1. DAC min/max registers are signed.  
ARE = 1. Analog Record is enabled.  
SVRP = 1. Secondary volume registers have opposite polarity as primary registers.  
VUR = 0. DAC does not have volume update (take effect) registers.  
UCS = 0. USB clock uses internal oscillator.  
SCS = 0. System clock uses internal oscillator.  
SF = 0. System frequency is 48 MHz.  
ACR = 0. Audio Clock Ration (MCLK/LRCK) is 250.  
8
1C  
1D  
1A  
1B  
1C  
1D  
1A  
1B  
70  
DPVL = 0x1C. DAC Primary Volume Control Left channel register address is 0x1C  
DPVR = 0x1D. DAC Primary Volume Control Right channel register address is 0x1D  
DSVL = 0x1A. DAC Secondary Volume Control Left channel register address is 0x1A  
DSVR = 0x1B. DAC Secondary Volume Control Right channel register address is 0x1B  
DPMBLC = 0x1C. DAC Primary Mute Bit Left channel register address is 0x1C  
DPMBRC = 0x1D DAC Primary Mute Bit Right channel register address is 0x1D  
DSMBLC = 0x1A. DAC Secondary Mute Bit Left channel register address is 0x1A  
DSMBRC = 0x1B. DAC Secondary Mute Bit Right channel register address is 0x1B  
9
10  
11  
12  
13  
14  
15  
16  
DVCB = 0x70.  
VBC = 7. Volume register has 7 significant bits.  
VBS = 0. Volume control starts at bit 0.  
17  
77  
DMBP = 0x77.  
DMBPL = 7. DAC Mute Bit Position Left channel is bit 7  
DMBPR = 7. DAC Mute Bit Position Right channel is bit 7  
Rev. 1.1  
37  
CP2114  
Table 25. CS42L55 Configuration String  
Description  
Byte  
18  
Value  
44  
0C  
00  
00  
00  
00  
00  
00  
00  
DVMV = 0x44. DAC value for minimum volume is 0x44.  
DVXV = 0x0C. DAC value for maximum volume is 0x0C.  
NA - No volume update register.  
19  
20  
21  
22  
23  
24  
25  
26  
NA - No volume update register.  
NA - No volume update register.  
NA - No volume update register.  
NA - No volume update register.  
NA. MBG = 0. No Mute by GPIO.  
MBZ = 0. Do not mute by sending 00’s.  
MBVR = 0. Do not mute but volume register.  
27  
28  
29  
00  
00  
00  
DVMV = 0. Do not mute by sending value to register.  
Reserved  
Reserved  
38  
Rev. 1.1  
CP2114  
9.2. USB and GPIO Configuration  
The global configuration area is used to store USB descriptors and GPIO configuration. If the programmable ROM  
has not been programmed, the default configuration data shown in Table 26, Table 27, and Table 28 is used. In  
addition, each field in Table 26, Table 27, and Table 28 may only be customized once.  
Table 26. Default USB Configuration Data  
Name  
Value  
Vendor ID  
Product ID  
10C4h  
EAB0h  
Power Descriptor (Attributes)  
80h (Bus-powered)  
Power Descriptor (Max. Power) 32h (100 mA)  
Release Number  
0100h (Release Version 01.00)  
Manufacturer String  
Product Description String  
Serial String  
“Silicon Laboratories” (62 ASCII characters maximum)  
“CP2114 USB-Audio Bridge” (62 characters maximum)  
Unique 8 character ASCII string (30 characters maximum)  
Table 27. Default GPIO Data  
Pin Name  
GPIO.0_RMUTE  
Default Function  
Record Mute  
Playback Mute  
Volume Down  
Volume Up  
GPIO.1_PMUTE  
GPIO.2_VOL-  
GPIO.3_VOL+  
GPIO.4_RMUTELED  
GPIO.5_TXT_DACSEL0  
GPIO.6_RXT_DACSEL1  
GPIO.7_RTS_DACSEL2  
GPIO.8_CTS_DACSEL3  
GPIO.9_CLKOUT  
GPIO.10_TX  
Record Mute LED  
DAC Selector 0  
DAC Selector 1  
DAC Selector 2  
DAC Selector 3  
Clock Output  
UART TX  
GPIO.11_RX  
UART RX  
Table 28. Default UART and Suspend Data  
Name  
Default Function  
Flush TX and RX FIFO on open  
Output—Push Pull  
Flush Buffers  
SUSPEND  
Output—Push Pull  
SUSPEND  
Suspend Latch  
Suspend Mode  
Clock Divider  
0x0000  
0x0000  
Divide by 1  
While customization of the USB configuration data is optional, customizing the VID/PID combination is strongly  
recommended. A unique VID/PID will prevent the device from being recognized by any other manufacturer’s  
software application. A vendor ID can be obtained from www.usb.org or Silicon Labs can provide a free PID for the  
OEM product that can be used with the Silicon Labs VID. All CP2114 devices are pre-programmed with a unique  
serial number. It is important to have a unique serial if it is possible for multiple CP2114-based devices to be  
connected to the same PC.  
Rev. 1.1  
39  
CP2114  
10. Voltage Regulator  
The CP2114 includes an on-chip voltage regulator with a 3.45 V output. This allows the CP2114 to be configured  
as either a USB bus-powered device or a USB self-powered device. A typical connection diagram of the device in  
a bus-powered application using the regulator is shown in Figure 16. When enabled, the voltage regulator output  
appears on the VDD pin and can be used to power external devices. See Table 4 for the voltage regulator electrical  
characteristics.  
If it is desired to use the regulator to provide VDD in a self-powered application, the same connections from  
Figure 16 can be used, but connect REGIN to an on-board 5 V supply, and disconnect it from the VBUS pin. In  
addition, if REGIN may be unpowered while VBUS is 5 V, a resistor divider (or functionally equivalent circuit)  
shown in Note 5 of Figure 17 is required to meet the absolute maximum voltage on VBUS specification in Table 13.  
Note 3  
VIO  
4.7 k  
CP2114  
RST  
Suspend  
Signals  
SUSPEND  
SUSPEND  
Note 4  
VPP  
VIO  
Note 2  
4.7 F  
3.45 V Power  
VDD  
SDA  
SCL  
1-5 F  
0.1 F  
MCLK  
SCK  
I2S and  
I2C  
Signals to  
DAC  
REGIN  
GND  
LRCK  
SDIN  
1 F  
SDOUT  
Clock  
Input  
(optional)  
EXTCLK  
USB  
Connector  
GPIO.0_RMUTE  
GPIO.1_PMUTE  
GPIO.2_VOL-  
Volume/  
Mute  
Controls  
VBUS  
D+  
VBUS  
D+  
GPIO.3_VOL+  
D-  
D-  
GPIO.4_RMUTELED  
GPIO.5_TXT_DACSEL0  
GND  
GPIO.6_RXT_DACSEL1  
GPIO.7_RTS_DACSEL2  
GPIO.8_CTS_DACSEL3  
DAC  
Selector  
Note 1  
Clock  
Output  
GPIO.9_CLKOUT  
(optional)  
GPIO.10_TX  
GPIO.11_RX  
UART  
Note 1 : Avalanche transient voltage suppression diodes compatible with Full-speed USB should be  
added at the connector for ESD protection. Use Littelfuse p/n SP0503BAHT or equivalent.  
Note 2 : VIO can be connected directly to VDD or to a supply as low as 1.8 V to set the I/O interface  
voltage.  
Note 3 : An external pull-up is not required, but can be added for noise immunity.  
Note 4 : If configuration ROM is to be programmed via USB, a 4.7 F capacitor must be added  
between VPP and ground. During a programming operation, the pin should  
not be connected to other circuitry, and VIO must be at least 3.3 V.  
Figure 16. Typical Bus-Powered Connection Diagram  
40  
Rev. 1.1  
CP2114  
Alternatively, if 3.0 to 3.6 V power source is supplied to the VDD pin, the CP2114 can function as a USB self-  
powered device with the voltage regulator bypassed. For this configuration, the REGIN input should be tied to VDD  
to bypass the voltage regulator. A typical connection diagram showing the device in a self-powered application with  
the regulator bypassed is shown in Figure 17.  
The USB max power and power attributes descriptor must match the device power usage and configuration. See  
application note “AN721: CP210x/CP21xx Device Customization Guide” for information on how to customize USB  
descriptors for the CP2114.  
Note 3  
VIO  
4.7 k  
CP2114  
RST  
Suspend  
Signals  
SUSPEND  
SUSPEND  
Note 4  
VPP  
VIO  
Note 2  
4.7 F  
VDD  
3.3 V  
Power  
REGIN  
SDA  
SCL  
MCLK  
SCK  
I2S and  
I2C  
Signals to  
DAC  
1-5 F  
0.1 F  
LRCK  
SDIN  
GND  
SDOUT  
Clock  
Input  
EXTCLK  
(optional)  
GPIO.0_RMUTE  
GPIO.1_PMUTE  
GPIO.2_VOL-  
Note 5  
(Optional)  
Volume/  
Mute  
Controls  
24 k  
47 k  
VBUS  
USB  
Connector  
GPIO.3_VOL+  
GPIO.4_RMUTELED  
VBUS  
D+  
GPIO.5_TXT_DACSEL0  
D+  
D-  
GPIO.6_RXT_DACSEL1  
GPIO.7_RTS_DACSEL2  
GPIO.8_CTS_DACSEL3  
DAC  
Selector  
D-  
GND  
Clock  
Output  
GPIO.9_CLKOUT  
(optional)  
Note 1  
GPIO.10_TX  
GPIO.11_RX  
UART  
Note 1 : Avalanche transient voltage suppression diodes compatible with Full-speed USB should be  
added at the connector for ESD protection. Use Littelfuse p/n SP0503BAHT or equivalent.  
Note 2 : VIO can be connected directly to VDD or to a supply as low as 1.8 V to set the I/O interface  
voltage.  
Note 3 : An external pull-up is not required, but can be added for noise immunity.  
Note 4 : If configuration ROM is to be programmed via USB, a 4.7 F capacitor must be added  
between VPP and ground. During a programming operation, the pin should  
not be connected to other circuitry, and VIO must be at least 3.3 V.  
Note 5 : For self-powered systems where VDD and VIO may be unpowered when VBUS is connected  
to 5 V, a resistor divider (or functionally-equivalent circuit) on VBUS is required to meet the  
absolute maximum voltage on VBUS specification in the Electrical Characteristics section.  
Figure 17. Typical Self-Powered Connection Diagram (Regulator Bypass)  
Rev. 1.1  
41  
CP2114  
11. CP2114 Interface Specification and Windows Interface DLL  
The CP2114 is a USB Human Interface Device (HID), and as most operating systems include native HID drivers,  
custom drivers do not need to be installed. The CP2114 does not fit one of the standard HID device types, such as  
a keyboard or mouse, and any CP2114 PC application needs to use the CP2114’s HID specification to  
communicate with the device. The low-level HID specification for the CP2114 is provided in “AN433: CP2110/  
CP2114 HID Interface Specification.” This document describes all of the basic functions for opening, reading from,  
writing to, and closing the device, as well as the ROM programming functions.  
A Windows DLL that encapsulates the CP2114 HID interface and also adds higher level features such as read/  
write time-outs is provided by Silicon Labs. This DLL is the recommended interface for the CP2114. The Windows  
DLL is documented in CP2114 Windows DLL Specification.  
Both of these documents and the DLL are available online at http://www.silabs.com/.  
12. Relevant Application Notes  
The following Application Notes are applicable to the CP2114. The latest versions of these application notes and  
their accompanying software are available at http://www.silabs.com/appnotes.  
AN721: CP210x/CP21xx Device Customization Guide. This application note describes how to use the  
AN721 software CP21xxSetIDs to configure the USB parameters on the CP21xx devices.  
AN433: CP2110/CP2114 HID to UART API Specification. This application note describes how to  
interface to the CP2114 using the Windows Interface DLL and the Max OS-X dylib.  
42  
Rev. 1.1  
CP2114  
DOCUMENT CHANGE LIST  
Revision 1.0 to Revision 1.1  
Updated text describing MCLK as an input. MCLK is an output from the CP2114.  
Referenced the SDIN signal to a generic audio device, rather than a DAC, since a DAC would not have an input  
signal.  
Added a row for VBUS in Table 13, “Absolute Maximum Ratings,” on page 12.  
Added V Ramp Time for Power On specification to Table 3, “Reset Electrical Characteristics,” on page 6.  
DD  
Added V Voltage specification to Table 6, “One Time Programming Specifications,” on page 7.  
PP  
Updated "10. Voltage Regulator" on page 40 to add absolute maximum voltage on VBUS requirements in self-  
powered systems.  
Rev. 1.1  
43  
CP2114  
CONTACT INFORMATION  
Silicon Laboratories Inc.  
400 West Cesar Chavez  
Austin, TX 78701  
Tel: 1+(512) 416-8500  
Fax: 1+(512) 416-9669  
Toll Free: 1+(877) 444-3032  
Please visit the Silicon Labs Technical Support web page:  
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx  
and register to submit a technical support request.  
Patent Notice  
Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analog-  
intensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team.  
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.  
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from  
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed fea-  
tures or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty,  
representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any  
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation  
consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intend-  
ed to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where  
personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized  
application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.  
Silicon Laboratories, Silicon Labs, and USBXpress are trademarks of Silicon Laboratories Inc.  
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders  
44  
Rev. 1.1  

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