CP2120-GM_技术文档

CP2120

SPI TO I²C BRIDGE AND GPIO PORT EXPANDER

2

Input and Output Port Pins

Single Chip SPI to I C Transfer

8 Pins Configurable as Push-Pull or Open-Drain

1 Pin Configurable as an edge-triggered interrupt

source

Integrated clock; no external clock required

On-Chip Voltage Monitor

Slave Serial Peripheral Interface (SPI)

All pins 5 V Tolerant

Up to 1.0 Mbit/s Transfers

Configurable to Least Significant Bit or Most Significant

Bit first byte transfers

INT active low interrupt pin

Supply Voltage of 2.7 V to 3.6 V

Typical operating current: 6.4 mA

2

I C Master Interface

Package

Operates at configurable rates up to 400 kHz

255 RX and TX Data Buffers

Pb-free 20-pin QFN

Internal

Oscillator

Voltage

Monitor

MISO

MOSI

SCK

CS

I²C

Interface

SDA

SCL

SPI

Interface

Controller

Internal Registers

Port Controller

Edge-Triggered

Interrupt Source

Eight I/O Pins

Figure 1. Block Diagram

Rev. 0.4 4/09

CP2120

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

CP2120

2

Rev. 0.4

CP2120

TABLE OF CONTENTS

Section

Page

1. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

3. Global DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

4. Pinout And Package Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

4.1. Pin Out Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

4.2. QFN-20 Pinout Diagram (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

4.3. QFN-20 Pinout Diagram (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

4.4. QFN-20 Solder Paste Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

5. SPI Slave Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

5.1. Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

5.2. Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

5.3. SPI Byte Orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

5.4. SPI Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

2

5.5. I C Activity During SPI Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

6. I C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

2

6.1. Determining Pull-Up Register Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

2

6.2. I C Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

2

6.3. I C Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

2

6.4. I C Receive Buffer Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

2

6.5. I C Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

7. Port I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

8. CP2120 Revision Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Rev. 0.4

3

CP2120

1. System Overview

2

The CP2120 is a highly-integrated SPI-to-I C Bridge Controller with an SPI interface that provides a simple and

2

reliable method for communicating with I C devices. The CP2120 includes a 4-wire serial peripheral interface

2

(SPI), a serial I C interface, 256 byte data buffers, an internal oscillator, eight input/output port pins, and one pin

configurable as an edge-triggered interrupt source in a compact 4x4 package. No external components other than

2

pull-up resisters on the I C pins are required. The SPI Master controls the CP2120 across the SPI interface using

a command set that governs all CP2120 configuration and operation.

2. Absolute Maximum Ratings

Table 1. Absolute Maximum Ratings

Parameter

Ambient temperature under bias

Storage Temperature

Conditions

Min

–55

–65

–0.3

Typ

—

Max

125

150

5.8

Units

°C

—

°C

Voltage on any Port I/O Pin or RST with respect

to GND

—

V

Voltage on V with respect to GND

–0.3

—

4.2

500

100

V

DD

Maximum Total current through V or GND

mA

DD

Maximum output current sunk by RST or any

Port pin

—

Note: Stresses above the absolute maximum ratings may cause permanent device damage. This is a stress rating only, and

functional operation of the devices at any conditions equal to or greater than those indicated in the operational listings

of this specification are not implied. Exposure to maximum rating conditions for extended periods may affect device

reliability.

3. Global DC Electrical Characteristics

Table 2. Global Electrical Characteristics

–40 to +85 °C, 25 MHz system clock unless otherwise specified.

Parameter

Digital Supply Voltage

Conditions

Min

Typ

Max

Units

V

3.0

3.6

V

RST

Digital Supply Current

—

3.8

—

4.1

mA

°C

V

=3.0 V

DD

Specified Operating

Temperature Range

–40

+85

4

Rev. 0.4

CP2120

4. Pinout And Package Definition

4.1. Pin Out Chart

Name

Pin #

Type

Description

V

3

2

4

Power Supply Pin

Ground

DD

GND

RST

Digital I/O

Device Reset. Open-drain output of internal POR or VDD monitor. An

external source can initiate a system reset by driving this pin low for at

least 15 µs.

SCLK

MISO

MOSI

CS

1

Digital In

SPI Clock Input

SPI Slave Output

SPI Slave Input

SPI Slave Select

20

19

18

17

16

5

Digital Out

Digital In

2

SDA

Digital I/O

Digital Out

I C Data Input/Output

2

SCL

I C Clock Input/Output

GPIO 0

GPIO 1

GPIO 2

GPIO 3

GPIO 4

GPIO 5

GPIO 6

GPIO 7

EINT

General Purpose Configurable Digital Input/Output

Edge-Triggered Interrupt Source

12

11

10

9

8

7

6

13

14

15

INT

CP2120 Interrupt Indicator

NC

Not connected, leave floating

Rev. 0.4

5

CP2120

4.2. QFN-20 Pinout Diagram (Top View)

SCLK

GND

1

2

3

4

5

15

14

13

12

11

NC

INT

VDD

EINT

GPIO 1

GPIO 2

CP2120

RST

GND

GPIO 0

6

Rev. 0.4

CP2120

4.3. QFN-20 Pinout Diagram (Bottom View)

Table 4.1. QFN-20

Package Dimensions

MM

MIN

0.80

0

—

0.18

—

2.00

—

2.00

—

TYP

0.90

0.02

0.65

0.25

0.23

4.00

2.15

4.00

2.15

0.5

MAX

1.00

0.05

1.00

—

0.30

—

2.25

—

A

A1

A2

A3

b

D

D2

E

E2

e

2.25

—

L

N

0.45

—

0.55

20

0.65

—

ND

NE

R

AA

BB

CC

DD

—

0.09

—

5

—

0.435

0.18

—

Rev. 0.4

7

CP2120

4.4. QFN-20 Solder Paste Recommendations

8

Rev. 0.4

CP2120

5. SPI Slave Bus

The CP2120 provides a four-wire slave SPI interface. The CP2120's SPI Bus activates whenever the SPI Master

pulls the NSS pin low. The master can then clock data into the CP2120 through the Master-Out-Slave-In (MOSI)

pin and receive data from the CP2120 through the Master-In-Slave-Out (MISO) pin. The SPI Master provides the

SPI with a clock source. Figure 2 shows typical connections for an SPI bus.

SPI Master

MISO

MOSI

SCLK

CS

CP2120

SPICLK

CS

Figure 2. SPI Bus Typical Connections

SCLK should be held high when idle. Figure 3 shows a CP2120 data transfer on the SPI Bus. If the CP2120 is the

only slave device on the SPI bus, the NSS pin can be tied low.

SCK

Bit 5

Bit 4

Bit 1

MOSI

MISO

NSS

Bit 6

Bit 3

Bit 2

Bit 0

MSB

Figure 3. Slave Mode Data/Clock Timing

Rev. 0.4

9

CP2120

5.1. Command Set

2

An SPI Master controls the CP2120 by sending commands across the SPI bus. Some commands initiate I C

transactions, while other commands modify or monitor CP2120 operation and events.

5.2. Internal Registers

2

The CP2120 maintains a set of internal registers that can be modified to configure general purpose port I/O and I C

operation and can be read to obtain device status. Commands reading to and writing from the internal registers can

2

be issued at any time, even while an I C transaction is in progress, as they do not initiate any I C bus transactions.

Table 3 shows a list of all internal registers.

Table 3. Internal Register Addresses

Internal Register

IOCONFIG

IOSTATE

I2CCLOCK

I2CTO

Address

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

Section

7.

6.1

6.2

6.1

6.3

7.

I2CSTAT

I2CADR

RXBUFF

IOCONFIG2

EDGEINT

I2CTO2

7.

6.1

5.2.1. Write to Internal Register

0x20

COMMAND

REGISTER

X

SPI Master

DATA BYTE

A Write to Internal Register command updates the value of one of the CP2120's Internal Registers. A Write to

Internal Register command begins with the command byte, 0x20, followed by the internal register address,

followed by the new value of the internal register. Only one register can be accessed per Write to Internal Register

command.

10

Rev. 0.4

CP2120

5.2.2. Read From Internal Register

REGISTER

Address

COMMAND

0x21

SPI Master

CP2120

Don’t Care

REGISTER

DATA

A Read from Internal Register command retrieves the current value of one of the CP2120's internal registers. The

command begins with the command byte, 0x21, followed by the internal register address. This byte is followed by

the transmission of a "don't care" byte, which can be of any value and is ignored by the CP2120. After the "don't

care" byte, the internal register value is transmitted across the MISO line.

5.3. SPI Byte Orientation

The SPI Configuration command configures the bit orientation of transfers across the SPI bus to one of two states.

If SPI transmits most-significant-bit first, bit 7 is transmitted first. If SPI transmits least-significant-bit first, bit 0 is

transmitted first.

5.3.1. SPI Configuration

SPI

COMMAND

0x18

SPI Master

CONFIGURATION

The command begins with the command byte (0x18), followed by SPI Configuration byte, which should equal one

of the values shown in the following table. Any values other than those listed in the table are ignored.

Byte Value

0x81

Configuration

Most Significant Bit First

Least Significant Bit First

0x42

5.4. SPI Timing Diagrams

NSS

T_SE

T_CKL

T_SD

SCK*

T_CKH

T_SIS

T_SIH

MOSI

T_SOH

T_SDZ

T_SLH

T_SEZ

MISO

Figure 4. SPI Slave Timing

Rev. 0.4

11

CP2120

Table 4. SPI Slave Timing Parameters

*

Slave Mode Timing (See Figure 4)

T

2 x T

—

ns

NSS Falling to First SCLK Edge

Last SCLK Edge to NSS Rising

NSS Falling to MISO Valid

NSS Rising to MISO High-Z

SCLK High Time

SE

SYSCLK

SD

SYSCLK

—

4 x T

SEZ

SDZ

CKH

CKL

SIS

SYSCLK

—

SYSCLK

5 x T

2 x T

—

SYSCLK

—

SCLK Low Time

MOSI Valid to SCLK Sample Edge

SCLK Sample Edge to MOSI Change

SCLK Shift Edge to MISO Change

SIH

SOH

SYSCLK

—

4 x T

8 x T

SYSCLK

Last SCLK Edge to MISO Change

(CKPHA = 1 ONLY)

6 x T

SYSCLK

T

SLH

*Note: T_SYSCLKequals 24.5 MHz.

2

5.5. I C Activity During SPI Transactions

2

If the SPI Master attempts to transmit a command to the CP2120 while the I C bus is inactive, the CP2120 will

2

disable its slave response. If an I C Master device on the bus attempts to address the CP2120 during this time, the

CP2120 will not ACK the address defined in the I2CADR Internal Register.

If the SPI Master attempts to transmit a command to the CP2120 while the CP2120 is acting as the Master on the

2

I C bus, the CP2120 will suspend I C bus activity until the SPI Master has completed transmission of the

command. For instance, if the SPI Master calls the Read Internal Register command while the CP2120 is in the

2

middle of an I C transaction, that I C transaction will stall until the CP2120 completely processes the Read Internal

Register command.

12

Rev. 0.4

CP2120

6. I²C Serial Interface

2

The CP2120 provides an I C interface able to transfer data at frequencies up to 400 kHz. During a transaction, the

2

CP2120, operating as the I C master, sources a data clock on the SCL pin as data travels across the bidirectional

2

SDA pin to and from an I C slave device. The I C interface lines each require a pull-up resistor. Figure 5 shows a

typical I C bus.

2

V_DD

R

pU

R

pU

SDA

SCL

I²C-bus

I²C-BUS Device

I²C-BUS DEVICE

CP2120

2

Figure 5. Typical I C Bus*

*Note: VDD is defined in Table 1, “Absolute Maximum Ratings,” on page 4. For Rpu values, please see “6.1.

Determining Pull-Up Register Values” .

6.1. Determining Pull-Up Register Values

Logic low to logic high transitions on the SCL and SDA pins, which are configured to open-drain output with

external pull-ups to VDD, take the form of an exponential curve with an RC time constant, where C equals the

2

capacitance of the bus and R equals the pull-up resistor value. I C specification defines rise time as the time

required for a signal level to change from Vmin +0.15 V to Vmax-0.15 V. By solving the exponential equation using

a Vmin of 0 V and a Vmax of 3.3 V, the following equation can be used to find values for pull-up resistors:

Rise time = 3.04448 RC

Bus capacitance is governed by a number of factors, including signal trace length and capacitance introduced by

devices on the bus. 8 mm PCB signal traces on a two-layer board generally add 1 pF of capacitance per

2

centimeter of trace length. To determine the amount of capacitance introduced to the bus by I C devices, consult

2

those devices’ datasheets. The maximum capacitance allowed before the bus violates I C specification is 400 pF.

2

Rise time requirements vary depending on each connected I C device’s timing requirements and the SCL clock

2

frequency. The maximum rise time allowed by the I C specification is 1000 ns.

2

6.2. I C Internal Registers

2

Features of the I C interface are configured through the CP2120's Internal Registers. SCL clock frequency is set

2

by writing to the I2CCLK Internal Register. The frequency can be determined using the equation below. The I C

2

frequency configured by the I2CCLOCK register is only an approximate frequency. Actual I C frequencies can vary

due to conditions on the bus, such as a slave device extending the SCL low time.

2

2000

I²CCLK

I C Clock Frequency (kHz) = ---------------------

2

Equation 1. I C Clock Frequency

Rev. 0.4

13

CP2120

2

Internal Register Definition 1. I2CCLOCK: I C Clock Frequency Configuration

R/W

I2CCK7

Bit 7

R/W

I2CCK6

Bit 6

R/W

I2CCK5

Bit 5

R/W

I2CCK4

Bit 4

R/W

I2CCK3

Bit3

R/W

I2CCK2

Bit 2

R/W

I2CCK1

Bit 1

R/W

I2CCK0

Bit 0

Internal Register Address: 0x02

Reset Value: 0xA0

2

Bit 7-0: I2CCK7-0: I C Clock Frequency Configuration value (minimum register value = 5,

maximum register value = 255)

2

The transaction time-out counter, which terminates an I C transaction after a set period of time has passed, can be

configured through the I2CTO Internal Register. If the time-out counter is not enabled, the CP2120 will make only

2

one attempt at executing an I C transaction and abort if that transaction attempt fails.

TO

128

---------

Time-out Frequency =

Hz

Equation 2. CTO Time-Out Frequency

2

Internal Register Definition 2. I2CTO: I C Time Out

R/W

TO6

Bit 7

R/W

TO5

Bit 6

R/W

TO4

Bit 5

R/W

TO3

Bit 4

R/W

TO2

Bit3

R/W

TO1

Bit 2

R/W

TO0

Bit 1

R/W

TEN

Bit 0

Internal Register Address: 0x03

Reset Value: 0x00

Bit 7-1: TO6-0: Time Out Value

Bit 0: TEN:Time Out Enable Bit.

0: Disable Timer.

1: Enable Timer.

2

The SPI Master can assign an I C address to the CP2120 by writing to the I2CADR Internal Register. Setting this

2

address is not necessary for device operation. If set, the CP2120 will ACK this address when another I C Master

on the bus attempts to communicate with it. The CP2120 will NACK all attempts at data transfer when responding

2

as an I C slave.

2

Internal Register Definition 3. I2CADR: I C Address

R/W

I2CAD7

Bit 7

R/W

I2CAD6

Bit 6

R/W

I2CAD5

Bit 5

R/W

I2CAD4

Bit 4

R/W

I2CAD3

Bit3

R/W

I2CAD2

Bit 2

R/W

I2CAD1

Bit 1

R/W

I2CAD0

Bit 0

Internal Register Address: 0x05

Reset Value: 0x00

2

Bit 7-Bit 0: I2CAD7-0: I C Address

Sets I2C bus address.

14

Rev. 0.4

CP2120

2

The SPI2I2C provides additional SMBus-related timers to enable I C protocol compatibility. Setting the I C Bus

Free Detect enables the device to poll the SMBus lines and determine when a transfer can begin. Setting the SCL

Low Time Out detect will cause an SMBus transaction to abort if the SCL line has been held low by a device for a

period of approximately 25 ms.

2

Internal Register Definition 4. I2CTO2: Additional I C Time Outs

R/W

FREN

Bit 1

R/W

LWEN

Bit 0

Reserved Reserved Reserved Reserved Reserved Reserved

Bit 7

Bit 6

Bit 5

Bit 4

Bit3

Bit 2

Internal Register Address: 0x09

Reset Value: 0x00

2

Bit 1: I C Bus Free Detect

0: Bus Free Detect Disabled

1: Bus Free Detect Enabled

2

Bit 0:

I C SCL Low Time Out Detect

0: SCL Low Time Out Detect disable

1: SCL Low Time Out Detect enable

2

6.3. I C Status

2

The CP2120 maintains an Internal Register, I2CSTAT, which describes the current status of the I C Interface. The

2

I2CSTAT register can be read at any time. The CP2120 updates I2CSTAT when an I C transaction begins, when

2

an I C transaction completes (successfully or unsuccessfully), and when a received SPI command contains errors.

2

It is not recommended that an SPI master poll the CP2120's I2CSTAT Internal Register to determine when an I C

transaction has completed. The SPI master should instead watch for the INT pin to drop low, and then read the

2

I2CSTAT register to determine the I C transaction results.

Rev. 0.4

15

CP2120

2

Internal Register Definition 5. I2CSTAT: I C Status Register

R

I2ST7

Bit 7

I2ST6

Bit 6

I2ST5

Bit 5

I2ST4

Bit 4

I2ST3

Bit3

I2ST2

Bit 2

I2ST1

Bit 1

I2ST0

Bit 0

Internal Register Address: 0x04

Reset Value: 0x00

2

Bit 7–0

I2ST: I C Status

2

Status Description

I C Status Value

2

0xF0

0xF1

0xF2

0xF3

0xF8

0xF9

I C transaction completed successfully.

Slave address NACKed.

Slave data NACKed.

2

I C transaction in progress.

2

I C transaction timed out due to timer configured in I2CTO.

Command’s Bytes to Transmit Byte and Data Buffer Size do not match, or Read

Buffer read number of bytes greater than buffer count.

2

0xFA

0xFB

I C SCL Low time-out, using timer configured in I2CTO2.

2

I C bus free detect has been disabled, and the bus is not free.

16

Rev. 0.4

CP2120

2

6.4. I C Receive Buffer Size

2

Bytes received from I C transactions are stored in the 255-byte data buffer. The number of bytes currently stored

inside this buffer is saved in the RXBUFF Internal Register.

Internal Register Definition 6. RXBUFF: Receive Buffer Size Register

R

RXB7

Bit 7

RXB6

Bit 6

RXB5

Bit 5

RXB4

Bit 4

RXB3

Bit3

RXB2

Bit 2

RXB1

Bit 1

RXB0

Bit 0

Internal Register Address: 0x06

Reset Value: 0x00

Bit 7-0: RXB7-0: Receive Buffer Size

2

Indicates the number of bytes received during the last I C read transaction.

2

6.5. I C Commands

2

SPI commands initiate all I C transactions. The CP2120 executes I C transactions only after every byte of the

command has been successfully received across the SPI bus. Once the CP2120 has completed the I C

2

transaction prompted by the command, the INT pin will be pulled low to indicate that command execution has

2

completed. If an I C command is issued while an I C command is in progress, the second I C command will be

ignored.

2

6.5.1. Write Bytes to I C

NUMBER

OF BYTES

SLAVE

ADDRESS +W

DATA

BYTE N

DATA

BYTE1

COMMAND

0x00

SPI Master

...

2

This command transmits data to an I C slave device. The command begins with the command byte (0x00),

2

followed by the number of bytes to be transmitted across I C, which can range from 1 to 255, and the address of

2

the I C Slave. The SPI master then sends the data to be transmitted across I C. Sending more or fewer bytes than

was indicated by the second byte of the command will result in an error condition, and the I2C transaction will not

be initiated.

2

Once the I C transaction completes, the CP2120 pulls the INT pin low and sets the internal register according to

the results of the transaction.

2

6.5.2. Read Bytes from I C

COMMAND

0x01

NUMBER

OF BYTES

SLAVE ADDRESS

+R

SPI Master

2

This command attempts to retrieve bytes from an I C Slave device. The command begins with the command byte,

2

0x01, followed by the number of bytes to read (1 to 255) and the address of the I C slave device.

2

Once the I C transaction completes, the CP2120 pulls the INT pin low and sets I2CSTAT according to the results of

the transaction. The CP2120 saves the number of bytes stored in the buffer in the internal register named

RXBUFF. A Read Buffer command can be issued to retrieve the bytes from the buffer.

2

Note that if the SPI Master issues a second Read Bytes from I C command before issuing a Read Buffer

command, the bytes stored in the CP2120's buffer will be overwritten.

Rev. 0.4

17

CP2120

6.5.3. Read Buffer

COMMAND

0x06

SPI Master

CP2120

Don’t Care

...

Data Byte N

Data Byte 0

The Read Buffer command retrieves bytes from the CP2120's data buffer. The command begins with the command

byte, 0x06. After the command byte, the SPI Master must transmit a single byte of data, which is ignored by the

CP2120. After receiving the ignored byte of data, the CP2120 transmits data bytes across the MISO pin.

It is recommended that the SPI Master read the RXBUFF Internal Register to determine how many bytes are

stored in the CP2120's buffer before issuing a Read Buffer command. If the SPI Master attempts to retrieve more

bytes than the buffer contains, the CP2120 will signal the error in I2CSTAT. If an SPI Master attempts to retrieve

fewer bytes than are stored in the data buffer, all bytes left in the buffer will be deleted when the Read Buffer

command terminates.

6.5.4. Read After Write

0x02

COMMAND

SLAVE

ADDRESS+R

SLAVE

ADDRESS+W

NUMBER OF

WRITE BYTES

NUMBER OF

READ BYTES

DATA WRITE

BYTE N

DATA WRITE

BYTE 0

...

SPI Master

2

The Read After Write command writes bytes to one I C slave and then reads bytes from another I C slave. The

SPI Master calls this command by first sending the command byte, 0x02, then the number of bytes to write (1 to

2

255) and bytes to read (1 to 255). These bytes are followed by the address of the I C slave to which the CP2120

2

will attempt to write bytes, followed by the data bytes to write. The last byte of the command is the I C slave from

which the CP2120 will attempt to read bytes.

6.5.5. Write After Write

0x03

COMMAND

NUMBER OF

BYTES 1

NUMBER OF

BYTES 2

SLAVE 1

ADDRESS +W

SLAVE 2

ADDRESS +W

...

SPI Master

DATA BYTE N

DATA BYTE 1

DATA BYTE N

DATA BYTE 1

2

The Write After Write command writes to an I C slave device and then issues another write to a second I C slave

device. The command begins with the command byte, 0x08, followed by the number of bytes to write to the first I C

device and the bytes to write to the second I C device. The SPI master sends the slave address of the first I C

device and the data bytes to write to the first I C slave. The SPI Master then sends the slave address of the second

2

I C slave device followed by the data bytes to transmit to that slave device.

6.5.6. Write To Multiple Slaves

0x 09

COMMAND

...

SPI Master

Slave N

Data Byte0

Data Byte N

Num Bytes

Num Slaves

Slave0

2

The Write to Multiple Slaves command allows an SPI Master to write the same data buffer to multiple I C slaves.

The command begins with the command byte, 0x09, followed by the size of the data buffer (0 to 255), followed by

the number of slaves (0 to 254). Next, the list of slave addresses is transmitted. Following that, the data buffer to

write to each slave is transmitted. The combined size of the slave address list and the data buffer should not

2

exceed 255 bytes. The I2CSTAT Internal Register shows the results from the last I C transaction of the command.

18

Rev. 0.4

CP2120

7. Port I/O

The CP2120 offers eight general-purpose port pins that can be configured as output, input, or quasi-bidirectional

output by writing to the internal registers, IOCONFIG and IOCONFIG2. Pin state can be updated by writing to the

internal register, IOSTATE. Reading the IOSTATE Internal Register will return the current values of each port pin.

The port pin, EINT, can be configured as an edge-triggered interrupt source by writing to the EDGEINT Internal

Register. The EIT bit sets the interrupt to trigger upon a 0 to 1 or a 1 to 0 logic change on the pin. The bit, EIE,

enables the pin as an interrupt source.

Once the interrupt has been configured and enabled, the CP2120 will pull the INT pin low when the port pin's logic

value switches to “1'” or “0”, depending on the interrupt configuration specified in the EIT bit. When an interrupt is

triggered, EIF in the EDGEINT Internal Register is set. Reading from EDGEINT will clear the EIF bit.

Internal Register Definition 7. IOCONFIG: Port I/O Configuration

R/W

PCIO3.1

Bit 7

R/W

PCIO3.0

Bit 6

R/W

PCIO2.1

Bit 5

R/W

PCIO2.0

Bit 4

R/W

PCIO1.1

Bit3

R/W

PCIO1.0

Bit 2

R/W

PCIO0.1

Bit 1

R/W

PCIO0.0

Bit 0

Internal Register Address: 0x00

Reset Value: 0x00

Bit 7-6: PCIO3.1-PCIO3.0: Port Configuration for GPIO Pin 3

Bit 5-4: PCIO2.1-PCIO2.0: Port Configuration for GPIO Pin 2

Bit 3-2: PCIO1.1-PCIO1.0: Port Configuration for GPIO Pin 1

Bit 1-0: PCIO0.1-PCIO0.0: Port Configuration for GPIO Pin 0

These bits select the port state for GPIO pins 3 through 0.

PCIOx.1

PCIOx.0

GPIO Pin x Mode

Open Drain Output

Input Only

0

1

0

1

0

1

Push-Pull Output

Input Only

Rev. 0.4

19

CP2120

Internal Register Definition 8. IOCONFIG2: Port I/O Configuration 2

R/W

PCIO7.1

Bit 7

R/W

PCIO7.0

Bit 6

R/W

PCIO6.1

Bit 5

R/W

PCIO6.0

Bit 4

R/W

PCIO5.1

Bit3

R/W

PCIO5.0

Bit 2

R/W

PCIO4.1

Bit 1

R/W

PCIO4.0

Bit 0

Internal Register Address: 0x07

Reset Value: 0x00

Bit 7-6: PCIO7.1-PCIO7.0: Port Configuration for GPIO Pin 7

Bit 5-4: PCIO6.1-PCIO6.0: Port Configuration for GPIO Pin 6

Bit 3-2: PCIO5.1-PCIO5.0: Port Configuration for GPIO Pin 5

Bit 1-0: PCIO4.1-PCIO4.0: Port Configuration for GPIO Pin 4

These bits select the port state for GPIO pins 7 through 4.

PCIOx.1

PCIOx.0

GPIO Pin x Mode

Open Drain Output

Input Only

0

1

0

1

0

1

Push-Pull Output

Input Only

Internal Register Definition 9. IOSTATE: Port I/O State

R/W

GPIO7

Bit 7

R/W

GPIO6

Bit 6

R/W

GPIO5

Bit 5

R/W

GPIO4

Bit 4

R/W

GPIO3

Bit3

R/W

GPIO2

Bit 2

R/W

GPIO1

Bit 1

R/W

GPIO0

Bit 0

Internal Register Address: 0x01

Reset Value: 0x00

Bit 7-0: GPIO7-0: General Purpose Input/Output State

Write - Output appears on output pins.

0: GPIOx set to logic low output.

1: GPIO set to logic high output.

Read - Reads port state.

0: GPIOx is logic low.

1: GPIOx is logic high.

20

Rev. 0.4

CP2120

Internal Register Definition 10. EDGEINT: Edge Triggered Interrupt Enable

R/W

EIF

Bit 7

R/W

EIE

Bit 6

R/W

EIT

Bit 5

R/W

Rsvd

Bit 4

R/W

Rsvd

Bit3

R/W

Rsvd

Bit 2

R/W

Rsvd

Bit 1

R/W

Rsvd

Bit 0

Internal Register Address: 0x08

Reset Value: 0x00

Bit 7: EIF: Edge Triggered Interrupt Flag

0: No edge triggered event has occurred on the EI_INT pin.

1: Edge-triggered event has occurred on the EI_INT pin.

Bit 6: EIE: Edge Triggered Interrupt Enable

0: Edge Triggered interrupts disabled.

1: Edge Triggered interrupts enabled.

Bit 5: EIT: Edge Triggered Interrupt Trigger

0: Interrupt triggered on negative-to-positive digital transition on the EI_INT port

pin.

1: Interrupt triggered on positive-to-negative digital transition on the EI_INT port

pin.

Bit 4–Bit 0: Not used.

Rev. 0.4

21

CP2120

8. CP2120 Revision Number

The CP2120 revision number can be retrieved by first sending the Revision Number command byte of 0x40 and

then transmitting one “don’t care” transitional byte. The CP2120 then transmits the two-byte revision number, most

significant byte first, in BCD format. For example, a transmitted byte sequence of “0x01 0x44” would indicate that

the CP2120’s revision number is equal to 1.44.

0x40

SPI Master

Don’t Care

COMMAND

Rev Num

Byte 1

Rev Num

Byte 2

CP2120

22

Rev. 0.4

CP2120

DOCUMENT CHANGE LIST

Revision 0.1 to Revision 0.2

 Various small text changes.

 Updated 4.1 Pin Out Chart.

 Updated 4.2 Pin Out Diagram.

 Updated Figure 2. SPI Bus Typical Connections.

 Added Table 3. Internal Register Addresses.

 Updated all CP2120 command drawings.

 Added section 6.1 Determining Pull-Up Register

Values.

 Changed appearance of all Internal Register

Definition charts.

 Changed contents of Section 8. CP2120 Revision

Number.

Revision 0.2 to Revision 0.3

 Removed references to power down mode.

 Corrected Equation 1, “I2C Clock Frequency,” on

page 13.

2

 In Internal Register 4, “I2CTO2: Additional I C Time

Outs,” on page 15, changed Internal Register

Address to “0x09”.

2

 In Internal Register 5, “I2CSTAT: I C Status

Register,” on page 16, changed all bits to “R” instead

of “R/W”

 In Internal Register 6, “RXBUFF: Receive Buffer

Size Register,” on page 17, changed all bits to “R”

instead of “R/W”.

Revision 0.3 to Revision 0.4

 Updated Figure 1.

 Updated Digital Supply Voltage in Table 2.

 Updated Figure 3.

Rev. 0.4

23

CP2120

CONTACT INFORMATION

Silicon Laboratories Inc.

400 West Cesar Chavez

Austin, TX 78701

Please visit the Silicon Labs Technical Support web page:

https://www.silabs.com/support/pages/contacttechnicalsupport.aspx

and register to submit a technical support request.

The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.

Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from

the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed fea-

tures or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no war-

ranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume

any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without

limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in appli-

cations intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create

a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended

or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.

Silicon Laboratories, Silicon Labs, and USBXpress are trademarks of Silicon Laboratories Inc.

Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders

24

Rev. 0.4


型号：	CP2120-GM
厂家：	SILICON
描述：	暂无描述总线控制器微控制器和处理器外围集成电路监控时钟
文件：	总24页 (文件大小：189K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CP2120-GM [SILICON]

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