CY28548ZXC [SILICON]
Clock Generator for Intel®Crestline Chipset;
| 型号： | CY28548ZXC |
| 厂家： | 
SILICON |
| 描述： | Clock Generator for Intel®Crestline Chipset |
| 文件： | 总31页 (文件大小：1245K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY28548
Clock Generator for Intel®Crestline Chipset
• 33 MHz PCI clock
Features
• 27 MHz Video clocks
• Compliant to Intel® CK505
• Buffered Reference Clock 14.318 MHz
• Low power push-pull type differential output buffers
• Integrated voltage regulator
• Low-voltage frequency select input
• I2C support with readback capabilities
• Integrated resistors on differential clocks
• Scalable low voltage VDD_IO (3.3V to 1.25V)
• Differential CPU clocks with selectable frequency
• 100 MHz Differential SRC clocks
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V Power supply
• 64-pin QFN/TSSOP packages
• 100 MHz Differential LCD clock
CPU SRC PCI REF DOT96 USB_48 LCD 27M
• 96 MHz Differential DOT clock
x2 / x3 x7/11 x6
x 1
x 1
x 1
x1
x2
• 48 MHz USB clocks
Block Diagram
........................Document #: 001-08400 Rev ** Page 1 of 30
400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500 1+(512) 416-9669
www.silabs.com
CY28548
Pin Configuration
64-Pin TSSOP
64-Pin QFN
1
2
3
4
5
6
7
8
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PCI0/CR#_A
VDD_PCI
PCI1/CR#_B
PCI2/TME
SCLK
SDATA
REF0/FSC/TEST_SEL
VDD_REF
XIN
XOUT
VSS_REF
FSB/TEST_MODE
CKPWRGD/PWRDWN#
VDD_CPU
CPUT0
CPUC0
VSS_CPU
CPUT1
CPUC1
VDD_CPU_IO
NC
SRCT8/CPU2_ITPT
SRCC8/CPU2_ITPC
VDD_SRC_IO
SRCT7/CR#_F
SRCC7/CR#_E
VSS_SRC
PCI3
PCI4/GCLK_SEL
PCIF0/ITP_EN
VSS_PCI
VDD_48
USB_48/FSA
VSS_48
VDD_IO
SRCT0/DOT96T
SRCC0/DOT96C
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VSS_IO
VDD_PLL3
SRCT1/LCDT_100/27M_NSS
SRCC1/LCDC_100/27M_SS
VSS_PLL3
VDD_PLL3_IO
SRCT2/SATAT
SRCC2/SATAC
VSS_SRC
SRCT3/CR#_C
SRCT6
SRCC6
VDD_SRC
PCI_STOP#
CPU_STOP#
VDD_SRC_IO
SRCC10
SRCC3/CR#_D
VDD_SRC
SRCT4
SRCC4
VSS_SRC_IO
SRCT9
SRCT10
SRCT11/CR#_H
SRCC9
SRCC11/CR#_G
QFN Pin Definitions
Pin No.
Name
VSS_REF
Type
Description
1
2
3
4
GND Ground for outputs.
Xout
O, SE 14.318 MHz Crystal output.
Xin
I
14.318 MHz Crystal input.
VDD_REF
PWR 3.3V Power supply for outputs and maintains SMBUS registers during power
down.
5
REF0 / FSC / TEST_SEL
I/O
Fixed 14.318 clock output/3.3V-tolerant input for CPU frequency selection/
Selects test mode if pulled to VIHFS_C when CK_PWRGD is asserted HIGH.
Refer to DC Electrical Specifications table for VILFS_C, VIMFS_C, VIHFS_C specifica-
tions.
6
7
SDATA
SCLK
I/O
I
SMBus compatible SDATA.
SMBus compatible SCLOCK.
........................Document #: 001-08400 Rev ** Page 2 of 30
CY28548
QFN Pin Definitions (continued)
Pin No.
Name
PCI0 / CR#_A
Type
Description
8
I/O, SE 33 MHz Clock/3.3V Clock Request # Input
Mappable via I2C to control either SRC 0 or SRC 2. Default PCI0.
To configure this pin to serve as a Clock Request pin for either SRC pair 2 or pair
0 using the CR#_A_EN bit located in byte 5 bit 7, first disable PCI output (Hi-z) in
byte 2, bit 1.
0 = PCI0 enabled (default)
1= CR#_A enabled.
Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair
Byte 5, bit 6:
0 = CR#_A controls SRC0 pair (default)
1= CR#_A controls SRC2 pair
9
VDD_PCI
PWR 3.3V power supply for PCI PLL
10
PCI1 / CR#_B
I/O, SE 33 MHz Clock/3.3V Clock Request # Input
Mappable via I2C to control either SRC 1 or SRC 4. Default PCI1.
To configure this pin to serve as a Clock Request pin for either SRC pair 1 or pair
4 using the CR#_B_EN bit located in byte 5, bit 5, first disable PCI output (Hi-z) in
byte 2, bit 1.
0 = PCI1 enabled (default)
1= CR#_B enabled.
Byte 5, bit 4 controls whether CR#_B controls SRC1 or SRC4 pair
Byte 5, bit 4:
0 = CR#_B controls SRC1 pair (default)
1= CR#_B controls SRC4 pair
11
PCI2 / TME
I/O, SE 33 MHz Clock output/3.3V-tolerance input for enabling Trusted Mode
Sampled at CKPWRGD assertion:
0 = Normal mode, 1 = Trusted mode (no overclocking)
12
13
PCI3
O, SE 33 MHz Clock output
PCI4 / GCLK_SEL
I/O, SE 33 MHz Clock output/3.3V-tolerant input for selecting graphic clock source
on pin 20, 21, 24 and 25
Sampled on CKPWRGD assertion;
GCLK_SEL Pin 20
Pin 21
DOT96T DOT96C SRC1T/LCD_100T SRC1C/LCD_100C
SRCT0 SRCC0 27M_NSS 27M_SS
Pin 24
Pin 25
0
1
14
PCIF0 / ITP_EN
I/O, SE 33 MHz free running clock output/3.3V LVTTL input to enable SRC8 or
CPU2_ITP (sampled on the CKPWRGD assertion)
1 = CPU2_ITP, 0 = SRC8
15
16
17
VSS_PCI
GND Ground for outputs.
VDD_48
PWR 3.3V power supply for outputs and PLL.
USB_48 / FSA
I/O
Fixed 48 MHz clock output/3.3V-tolerant input for CPU frequency selection
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
18
19
20
VSS_48
GND Ground for outputs.
VDD_IO
PWR 3.3V-1.25V power supply for outputs
SRCT0 / DOT96T
O, DIF True 100 MHz Differential serial reference clocks/Fixed True 96 MHz clock
output. Selected via GCLK_SEL at CKPWRGD assertion
21
SRCC0 / DOT96C
O, DIF Complementary 100 MHz Differential serial reference clocks/Fixed
complement 96 MHz clock output.
Selected via GCLK_SEL at CKPWRGD assertion
22
23
24
VSS_IO
GND Ground for outputs.
VDD_PLL3
PWR 3.3V Power supply for PLL3.
SRCT1 /
LCDT_100/27M_NSS
O, DIF, True 100 MHz differential serial reference clock output/True 100 MHz LCD
SE
video clock output / Non spread 27-MHz video clock output.
Selected via GCLK_SEL at CKPWRGD assertion.
........................Document #: 001-08400 Rev ** Page 3 of 30
CY28548
QFN Pin Definitions (continued)
Pin No.
Name
Type
Description
25
SRCC1 /
LCDC_100/27M_SS
O, DIF, Complementary 100 MHz differential serial reference clock output/Comple-
SE
mentary 100 MHz LCD video clock output /Spread 27 MHz video clock output.
Selected via GCLK_SEL at CKPWRGD assertion.
26
27
28
29
30
31
VSS_PLL3
GND Ground for PLL3.
VDD_PLL3_IO
SRCT2 / SATAT
SRCC2 / SATAC
VSS_SRC
PWR 3.3V-1.25V power supply for outputs.
O, DIF True 100 MHz differential serial reference clock output.
O, DIF Complementary 100 MHz differential serial reference clock output.
GND Ground for outputs.
SRCT3 / CR#_C
I/O, True 100 MHz differential serial reference clock output /3.3V Clock Request
DIF #_C/D input
Selected via CR#_C_EN/CR#_D_EN bit located in byte 5 bit 3and 1.
The CR#_C_SEL and CR#_D_SEL bits in byte 5 bit 2 and 0 will select which SRC
to stop when asserted
32
SRCC3 / CR#_D
I/O, Complementary 100 MHz differential serial reference clock output/3.3V Clock
DIF Request #_C/D input
Selected via CR#_C_EN/CR#_D_EN bit located in byte 5 bit 3and 1.
The CR#_C_SEL and CR#_D_SEL bits in byte 5 bit 2 and 0 will select which SRC
to stop when asserted
33
34
35
36
37
38
39
VDD_SRC_IO
SRCT4
PWR 3.3V-1.25V Power supply for outputs.
O, DIF True 100 MHz differential serial reference clocks.
O, DIF Complementary 100 MHz differential serial reference clocks.
GND Ground for outputs.
SRCC4
VSS_SRC
SRCT9
O, DIF True 100 MHz differential serial reference clocks.
O, DIF Complementary 100 MHz differential serial reference clocks.
SRCC9
SRCC11/ CR#_G
I/O, True 100 MHz differential serial reference clocks/3.3V CR#_G Input.
DIF Selected via CR#_G_EN/CR#_H_EN bit located in byte 6 bit 5 and 4.
When selected, CR#_G controls SRC9, CR#_H controls SRC10
40
SRCT11/ CR#_H
I/O, Complementary 100 MHz Differential serial reference clocks/3.3V CR#_H
DIF Input.
Selected via CR#_G_EN/CR#_H_EN bit located in byte 6 bit 5 and 4.
When selected, CR#_G controls SRC9, CR#_H controls SRC10
41
42
43
44
SRCT10
O, DIF True 100 MHz Differential serial reference clocks.
O, DIF Complementary 100 MHz Differential serial reference clocks.
PWR 3.3V-1.25V power supply for outputs.
SRCC10
VDD_SRC_IO
CPU_STOP#
I
3.3V-tolerant input for stopping CPU outputs
During direct clock off to M1 mode transition, a serial load of BSEL data is driven
on CPU_STOP# and sampled on the rising edge of PCI_STOP#. See Figure 13
for more information.
45
PCI_STOP#
I
3.3V-tolerant input for stopping PCI and SRC outputs
During direct clock off to M1 mode transition, a serial load of BSEL data is driven
on CPU_STOP# and sampled on the rising edge of PCI_STOP#. See Figure 13
for more information.
46
47
48
49
50
VDD_SRC
SRCC6
PWR 3.3V power supply for SRC PLL.
O, DIF Complementary 100 MHz Differential serial reference clocks.
O, DIF True 100 MHz Differential serial reference clocks.
GND Ground for outputs.
SRCT6
VSS_SRC
SRCC7/ CR#_E
I/O, Complementary 100 MHz differential serial reference clocks/3.3V CR#_E
DIF Input.
Selected via CR#_E_EN/CR#_F_EN bit located in byte 6 bit 7 and 6.
When selected, CR#_E controls SRC6, CR#_F controls SRC8
........................Document #: 001-08400 Rev ** Page 4 of 30
CY28548
QFN Pin Definitions (continued)
Pin No.
Name
Type
Description
51
SRCT7/ CR#_F
I/O, True 100 MHz differential serial reference clocks/3.3V CR#_F Input.
DIF Selected via CR#_E_EN/CR#_F_EN bit located in byte 6 bit 7 and 6.
When selected, CR#_E controls SRC6, CR#_F controls SRC8
52
53
VDD_SRC_IO
PWR 3.3V-1.25V Power supply for outputs.
SRCC8 / CPUC2_ITP
O, DIF Selectable complementary differential CPU or SRC clock output.
ITP_EN = 0 @ CK_PWRGD assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
54
SRCT8 / CPUT2_ITP,
O, DIF Selectable True differential CPU or SRC clock output.
ITP_EN = 0 @ CK_PWRGD assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
55
56
57
NC
NC
No connect.
VDD_CPU_IO
CPUC1
PWR 3.3V-1.25V Power supply for outputs.
O, DIF Complementary differential CPU clock outputs.
Note that CPU1 is the iAMT clock and is on in that mode.
58
CPUT1
O, DIF True differential CPU clock outputs.
Note that CPU1 is the iAMT clock and is on in that mode.
59
60
61
62
63
VSS_CPU
GND Ground for outputs.
CPUC0
O, DIF Complement differential CPU clock outputs.
O, DIF True differential CPU clock outputs.
PWR 3.3V Power supply for CPU PLL.
CPUT0
VDD_CPU
CKPWRGD / PWRDWN#
I
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A,
FS_B, FS_C, GLCK_SEL and ITP_EN.
After CKPWRGD (active HIGH) assertion, this pin becomes a real-time input for
asserting power down (active LOW).
64
FSB / TEST_MODE
I
3.3V-tolerant input for CPU frequency selection / Selects Ref/N or Tri-state
when in test mode.
0 = Tri-state, 1 = Ref/N
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
TSSOP Pin Definitions
Pin No.
Name
PCI0 / CR#_A
Type
Description
1
I/O, SE 33 MHz clock/3.3V Clock Request # Input.
Selected via CR#_A_EN bit located in byte 5 bit 7.
The CR#_A_SEL bit in byte 5 bit 6 will select to control SRC0 or SRC2 when
asserted.
2
3
VDD_PCI
PWR 3.3V Power supply for PCI PLL.
PCI1 / CR#_B
I/O, SE 33 MHz Clock/3.3V Clock Request # Input.Selected via CR#_B_EN bit located
in byte 5 bit 5.
The CR#_B_SEL bit in byte 5 bit 4 will select to control SRC1 or SRC4 when
asserted.
4
5
PCI2 / TME
PCI3
I/O, SE 33 MHz clock output / 3.3V-tolerance input for enabling trusted mode
Sampled at CKPWRGD assertion:
0 = Normal mode, 1 = Trusted mode (no overclocking)
O, SE 33 MHz clock output
........................Document #: 001-08400 Rev ** Page 5 of 30
CY28548
TSSOP Pin Definitions (continued)
Pin No.
Name
Type
Description
6
PCI4 / GCLK_SEL
I/O, SE 33 MHz clock output/3.3V-tolerant input for selecting graphic clock source
on pin 13, 14, 17and 18
Sampled on CKPWRGD assertion
GCLK_SEL
Pin13
DOT96T DOT96C SRC1T/LCD_100T SRC1C/LCD_100C
SRCT0 SRCC0 27M_NSS 27M_SS
Pin14
Pin17
Pin 18
0
1
7
PCIF0 / ITP_EN
I/O, SE 33 MHz free running clock output / 3.3V LVTTL input to enable SRC8 or
CPU2_ITP (sampled on the CKPWRGD assertion)
1 = CPU2_ITP, 0 = SRC8
8
VSS_PCI
GND Ground for outputs.
9
VDD_48
PWR 3.3V power supply for outputs and PLL.
10
USB_48 / FSA
I/O
Fixed 48 MHz clock output / 3.3V-tolerant input for CPU frequency selection
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
11
12
13
VSS_48
GND Ground for outputs.
VDD_IO
PWR 3.3V-1.25V power supply for outputs
SRCT0 / DOT96T
O, DIF True 100 MHz differential serial reference clocks / Fixed True 96 MHz clock
output. Selected via GCLK_SEL at CKPWRGD assertion
14
SRCC0 / DOT96C
O, DIF Complementary 100 MHz differential serial reference clocks / Fixed Comple-
mentary 96 MHz clock output. Selected via GCLK_SEL at CKPWRGD assertion
15
16
17
VSS_IO
GND Ground for outputs
VDD_PLL3
PWR 3.3V Power supply for PLL3
SRCT1 /
LCDT_100/27M_NSS
O, DIF, True 100 MHz differential serial reference clock output / True 100 MHz LCD
SE
video clock output / Non spread 27 MHz video clock output.
Selected via GCLK_SEL at CKPWRGD assertion
18
SRCC1 /
LCDC_100/27M_SS
O, DIF, Complementary100 MHz differential serial reference clock output / Comple-
SE
mentary 100 MHz LCD video clock output / Spread 27 MHz video clock output.
Selected via GCLK_SEL at CKPWRGD assertion
19
20
21
22
23
24
VSS_PLL3
GND Ground for PLL3.
VDD_PLL3_IO
SRCT2 / SATAT
SRCC2 / SATAC
VSS_SRC
PWR 3.3V-1.25V power supply for outputs.
O, DIF True 100 MHz differential serial reference clock output.
O, DIF Complementary 100 MHz differential serial reference clock output.
GND Ground for outputs.
SRCT3 / CR#_C
I/O, True 100 MHz differential serial reference clock output / 3.3V CR #_C/D input
DIF Selected via CR#_C_EN/CR#_D_EN bit located in byte 5 bit 3and 1.
The CR#_C_SEL and CR#_D_SEL bits in byte 5 bit 2 and 0 will select which SRC
to stop when asserted
25
SRCC3 / CR#_D
I/O, Complementary 100 MHz differential serial reference clock output / 3.3V CR
DIF #_C/D input
Selected via CR#_C_EN/CR#_D_EN bit located in byte 5 bit 3and 1.
The CR#_C_SEL and CR#_D_SEL bits in byte 5 bit 2 and 0 will select which SRC
to stop when asserted
26
27
28
29
30
31
VDD_SRC_IO
SRCT4
PWR 3.3V-1.25V power supply for outputs.
O, DIF True 100 MHz differential serial reference clocks.
O, DIF Complementary 100 MHz differential serial reference clocks.
GND Ground for outputs.
SRCC4
VSS_SRC
SRCT9
O, DIF True 100 MHz differential serial reference clocks.
O, DIF Complementary 100 MHz differential serial reference clocks.
SRCC9
........................Document #: 001-08400 Rev ** Page 6 of 30
CY28548
TSSOP Pin Definitions (continued)
Pin No.
Name
Type
Description
32
SRCC11/ CR#_G
I/O, Complementary 100 MHz differential serial reference clocks/3.3V CR#_G
DIF Input Selected via CR#_G_EN/CR#_H_EN bit located in byte 6 bit 5 and 4.
When selected, CR#_G controls SRC9, CR#_H controls SRC10
33
SRCT11/ CR#_H
I/O, True 100 MHz differential serial reference clocks/3.3V CR#_H Input Selected
DIF via CR#_G_EN/CR#_H_EN bit located in byte 6 bit 5 and 4.
When selected, CR#_G controls SRC9, CR#_H controls SRC10
34
35
36
37
SRCT10
O, DIF True 100 MHz differential serial reference clocks.
O, DIF Complementary 100 MHz differential serial reference clocks.
PWR 3.3V-1.25V Power supply for outputs.
SRCC10
VDD_SRC_IO
CPU_STOP#
I
3.3V-tolerant input for stopping CPU outputs
During direct clock off to M1 mode transition, a serial load of BSEL data is driven
on CPU_STOP# and sampled on the rising edge of PCI_STOP#. See Figure 13
for more information.
38
PCI_STOP#
I
3.3V-tolerant input for stopping PCI and SRC outputs
During direct clock off to M1 mode transition, a serial load of BSEL data is driven
on CPU_STOP# and sampled on the rising edge of PCI_STOP#. See Figure 13
for more information.
39
40
41
42
43
VDD_SRC
SRCC6
PWR 3.3V Power supply for SRC PLL.
O, DIF Complementary 100 MHz differential serial reference clocks.
O, DIF True 100 MHz differential serial reference clocks.
GND Ground for outputs.
SRCT6
VSS_SRC
SRCC7/ CR#_E
I/O, Complementary 100 MHz differential serial reference clocks/3.3V CR#_E
DIF Input. Selected via CR#_E_EN/CR#_F_EN bit located in byte 6 bit 7 and 6.
When selected, CR#_E controls SRC6, CR#_F controls SRC8
44
SRCT7/ CR#_F
I/O, True 100 MHz differential serial reference clocks/3.3V CR#_FInput.
DIF Selected via CR#_E_EN/CR#_F_EN bit located in byte 6 bit 7 and 6.
When selected, CR#_E controls SRC6, CR#_F controls SRC8
45
46
VDD_SRC_IO
PWR 3.3V-1.25V power supply for outputs.
SRCC8 / CPUC2_ITP
O, DIF Selectable Complementary differential CPU or SRC clock output.
ITP_EN = 0 @ CK_PWRGD assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
47
SRCC8 / CPUC2_ITP
O, DIF Selectable True differential CPU or SRC clock output.
ITP_EN = 0 @ CK_PWRGD assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
48
49
50
NC
NC No connect.
VDD_CPU_IO
CPUC1
PWR 3.3V-1.25V Power supply for outputs.
O, DIF Complementary differential CPU clock outputs.
Note that CPU1 is the iAMT clock and is on in that mode.
51
CPUT1
O, DIF True differential CPU clock outputs.
Note that CPU1 is the iAMT clock and is on in that mode.
52
53
54
55
56
VSS_CPU
GND Ground for outputs.
CPUC0
O, DIF Complementary differential CPU clock outputs.
O, DIF True differential CPU clock outputs.
PWR 3.3V Power supply for CPU PLL.
CPUT0
VDD_CPU
CKPWRGD / PWRDWN#
I
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A,
FS_B, FS_C, GLCK_SEL and ITP_EN.
After CKPWRGD (active HIGH) assertion, this pin becomes a real-time input for
asserting power down (active LOW).
........................Document #: 001-08400 Rev ** Page 7 of 30
CY28548
TSSOP Pin Definitions (continued)
PinNo.
Name
Type
Description
57
FSB / TEST_MODE
I
3.3V-tolerant input for CPU frequency selection / Selects Ref/N or Tri-state
when in test mode:
0 = Tri-state, 1 = Ref/N
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
58
59
60
61
VSS_REF
Xout
GND Ground for outputs.
O, SE 14.318 MHz Crystal output.
Xin
I
14.318 MHz Crystal input.
VDD_REF
PWR 3.3V Power supply for outputs and also maintains SMBUS registers during
power down.
62
REF0 / FSC / TEST_SEL
I/O
Fixed 14.318 clock output / 3.3V-tolerant input for CPU frequency selection /
Selects test mode if pulled to VIHFS_C when CK_PWRGD is asserted HIGH.
Refer to DC Electrical Specifications table for VILFS_C, VIMFS_C, VIHFS_C specifica-
tions.
63
64
SDATA
SCLK
I/O
I
SMBus-compatible SDATA.
SMBus-compatible SCLOCK.
Table 1. Frequency Select Pin (FSA, FSB and FSC)
FSC
0
FSB
0
FSA
0
CPU
SRC
PCIF/PCI
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
27MHz
27 MHz
27 MHz
27 MHz
27 MHz
27 MHz
27 MHz
27 MHz
REF
DOT96
96 MHz
96 MHz
96 MHz
96 MHz
96 MHz
96 MHz
96 MHz
USB
266 MHz
133 MHz
200 MHz
166 MHz
333 MHz
100 MHz
400 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
Reserved
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Reserved Reserved Reserved Reserved
Reserved Reserved
optional. Clock device register changes are normally made at
system initialization, if any are required. The interface cannot
be used during system operation for power management
functions.
Frequency Select Pin (FSA, FSB and FSC)
Apply the appropriate logic levels to FSA, FSB, and FSC
inputs before CK-PWRGD assertion to achieve host clock
frequency selection. When the clock chip sampled HIGH on
CK-PWRGD and indicates that VTT voltage is stable then
FSA, FSB, and FSC input values are sampled. This process
employs a one-shot functionality and once the CK-PWRGD
sampled a valid HIGH, all other FSA, FSB, FSC, and
CK-PWRGD transitions are ignored except in test mode
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, Access the bytes in sequential
order from lowest to highest (most significant bit first) with the
ability to stop after any complete byte is transferred. For byte
write and byte read operations, the system controller can
access individually indexed bytes. The offset of the indexed
byte is encoded in the command code described in Table 2.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers are individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
The block write and block read protocol is outlined in Table 3
while Table 4 outlines byte write and byte read protocol. The
slave receiver address is 11010010 (D2h)
their default setting at power-up. The use of this interface is
.
Table 2. Command Code Definition
Bit
Description
7
0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
........................Document #: 001-08400 Rev ** Page 8 of 30
CY28548
Table 3. Block Read and Block Write Protocol
Block Write Protocol
Block Read Protocol
Description
Bit
1
Description
Bit
1
Start
Start
8:2
9
Slave address–7 bits
Write
8:2
9
Slave address–7 bits
Write
10
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
10
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Repeat start
18:11
19
18:11
19
27:20
Byte Count–8 bits
20
(Skip this step if I2C_EN bit set)
28
36:29
37
Acknowledge from slave
Data byte 1–8 bits
27:21
28
Slave address–7 bits
Read = 1
Acknowledge from slave
Data byte 2–8 bits
29
Acknowledge from slave
Byte Count from slave–8 bits
Acknowledge
45:38
46
37:30
38
Acknowledge from slave
Data Byte /Slave Acknowledges
Data Byte N–8 bits
....
46:39
47
Data byte 1 from slave–8 bits
Acknowledge
....
....
Acknowledge from slave
Stop
55:48
56
Data byte 2 from slave–8 bits
Acknowledge
....
....
Data bytes from slave / Acknowledge
Data Byte N from slave–8 bits
NOT Acknowledge
....
....
....
Stop
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Byte Read Protocol
Description
Bit
1
Description
Bit
1
Start
Start
8:2
9
Slave address–7 bits
Write
8:2
9
Slave address–7 bits
Write
10
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Data byte–8 bits
10
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Repeated start
18:11
19
18:11
19
27:20
28
20
Acknowledge from slave
Stop
27:21
28
Slave address–7 bits
Read
29
29
Acknowledge from slave
Data from slave–8 bits
NOT Acknowledge
Stop
37:30
38
39
........................Document #: 001-08400 Rev ** Page 9 of 30
CY28548
Control Registers
Byte 0: Control Register 0
Bit
7
@Pup
HW
HW
HW
0
Name
FS_C
Description
CPU Frequency Select Bit, set by HW
6
FS_B
CPU Frequency Select Bit, set by HW
CPU Frequency Select Bit, set by HW
5
FS_A
4
iAMT_EN
Set via SMBus or by combination of PWRDWN, CPU_STP, and PCI_STP
0 = Legacy Mode, 1 = iAMT Enabled
3
2
0
0
Reserved
Reserved
SRC_Main_SEL
Select source for SRC clock
0 = SRC_MAIN = PLL1, PLL3_CFG Table applies
1 = SRC_MAIN = PLL3, PLL3_CFG Table does not apply
1
0
0
1
SATA_SEL
Select source of SATA clock
0 = SATA = SRC_MAIN, 1= SATA = PLL2
PD_Restore
Save Config. In powerdown
0 = Config. Cleared, 1 = Config. Saved
Byte 1: Control Register 1
Bit
@Pup
Name
Description
7
0
SRC0_SEL
Select for SRC0 or DOT96
0 = SRC0, 1 = DOT96
When GCLK_SEL=0, this bit is 1. When GCLK_SEL=1, this bit is 0
6
5
0
0
PLL1_SS_DC
PLL3_SS_DC
Select for down or center SS
0 = Down spread, 1 = Center spread
Select for down or center SS
0 = Down spread, 1 = Center spread
4
3
2
1
0
0
0
0
1
1
PLL3_CFB3
PLL3_CFB2
PLL3_CFB1
PLL3_CFB0
Reserved
Bit 4:1 only applies when SRC_Main_SEL = 0
SeeTable 8: PLL3 / SE configuration table
Reserved
Byte 2: Control Register 2
Bit
@Pup
Name
Description
7
1
REF
Output enable for REF
0 = Output Disabled, 1 = Output Enabled
6
5
4
3
2
1
0
1
1
1
1
1
1
1
USB
PCIF0
PCI4
PCI3
PCI2
PCI1
PCI0
Output enable for USB
0 = Output Disabled, 1 = Output Enabled
Output enable for PCIF0
0 = Output Disabled, 1 = Output Enabled
Output enable for PCI4
0 = Output Disabled, 1 = Output Enabled
Output enable for PCI3
0 = Output Disabled, 1 = Output Enabled
Output enable for PCI2
0 = Output Disabled, 1 = Output Enabled
Output enable for PCI1
0 = Output Disabled, 1 = Output Enabled
Output enable for PCI0
0 = Output Disabled, 1 = Output Enabled
......................Document #: 001-08400 Rev ** Page 10 of 30
CY28548
Byte 3: Control Register 3
Bit
@Pup
Name
Description
7
1
SRC[T/C]11
Output enable for SRC11
0 = Output Disabled, 1 = Output Enabled
6
5
4
3
2
1
1
1
1
1
SRC[T/C]10
SRC[T/C]9
Output enable for SRC10
0 = Output Disabled, 1 = Output Enabled
Output enable for SRC9
0 = Output Disabled, 1 = Output Enabled
SRC[T/C]8/CPU2_ITP
SRC[T/C]7
Output enable for SRC8 or CPU2_ITP
0 = Output Disabled, 1 = Output Enabled
Output enable for SRC7
0 = Output Disabled, 1 = Output Enabled
SRC[T/C]6
Output enable for SRC6
0 = Output Disabled, 1 = Output Enabled
1
0
1
1
Reserved
Reserved
SRC[T/C]4
Output enable for SRC4
0 = Output Disabled, 1 = Output Enabled
Byte 4: Control Register 4
Bit
@Pup
Name
Description
7
1
SRC[T/C]3
Output enable for SRC3
0 = Output Disabled, 1 = Output Enabled
6
5
4
3
2
1
0
1
1
1
1
1
1
1
SRC[T/C]2/SATA
Output enable for SRC2/SATA
0 = Output Disabled, 1 = Output Enabled
SRC[T/C]1/LCD_100M[T/C] Output enable for SRC1/LCD_100M
0 = Output Disabled, 1 = Output Enabled
SRC[T/C]0/DOT96[T/C]
Output enable for SRC0/DOT96
0 = Output Disabled, 1 = Output Enabled
CPU[T/C]1
Output enable for CPU1
0 = Output Disabled, 1 = Output Enabled
CPU[T/C]0
Output enable for CPU0
0 = Output Disabled, 1 = Output Enabled
PLL1_SS_EN
PLL3_SS_EN
Enable PLL1s spread modulation,
0 = Spread Disabled, 1 = Spread Enabled
Enable PLL3s spread modulation
0 = Spread Disabled, 1 = Spread Enabled
Byte 5: Control Register 5
Bit
@Pup
Name
Description
7
0
CR#_A_EN
Enable CR#_A (clk req)
0 = Disabled, 1 = Enabled,
6
5
4
3
2
0
0
0
0
0
CR#_A_SEL
CR#_B_EN
CR#_B_SEL
CR#_C_EN
CR#_C_SEL
Set CR#_A SRC0 or SRC2
0 = CR#_ASRC0, 1 = CR#_ASRC2
Enable CR#_B(clk req)
0 = Disabled, 1 = Enabled,
Set CR#_B SRC1 or SRC4
0 = CR#_BSRC1, 1 = CR#_BSRC4
Enable CR#_C (clk req)
0 = Disabled, 1 = Enabled
Set CR#_C SRC0 or SRC2
0 = CR#_CSRC0, 1 = CR#_CSRC2
......................Document #: 001-08400 Rev ** Page 11 of 30
CY28548
Byte 5: Control Register 5 (continued)
Bit
@Pup
Name
Description
1
0
CR#_D_EN
Enable CR#_D (clk req)
0 = Disabled, 1 = Enabled
0
0
CR#_D_SEL
Set CR#_D SRC1 or SRC4
0 = CR#_DSRC1, 1 = CR#_DSRC4
Byte 6: Control Register 6
Bit
@Pup
Name
Description
7
0
CR#_E_EN
Enable CR#_E (clk req) SRC6
0 = Disabled, 1 = Enabled
6
5
4
0
0
0
CR#_F_EN
CR#_G_EN
CR#_H_EN
Enable CR#_F (clk req) SRC8
0 = Disabled, 1 = Enabled
Enable CR#_G (clk req) SRC9
0 = Disabled, 1 = Enabled
Enable CR#_H (clk req) SRC10
0 = Disabled, 1 = Enabled
3
2
1
0
0
0
Reserved
Reserved
Reserved
Reserved
LCD_100_STP_CTRL
If set, LCD_100 stop with PCI_STOP#
0 = Free running, 1 = PCI_STOP# stoppable
0
0
SRC_STP_CTRL
If set, SRCs stop with PCI_STOP#
0 = Free running, 1 = PCI_STOP# stoppable
Byte 7: Vendor ID
Bit
7
@Pup
Name
Description
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
0
1
1
0
1
0
0
0
Rev Code Bit 3
Rev Code Bit 2
Rev Code Bit 1
Rev Code Bit 0
Vendor ID bit 3
Vendor ID bit 2
Vendor ID bit 1
Vendor ID bit 0
6
5
4
3
2
Vendor ID Bit 2
1
Vendor ID Bit 1
0
Vendor ID Bit 0
......................Document #: 001-08400 Rev ** Page 12 of 30
CY28548
Byte 8: Control Register 8
Bit
7
@Pup
Name
Description
1
0
0
1
Device_ID3
Device_ID2
Device_ID1
Device_ID0
0000 = CK505 Yellow Cover Device, 56-pin TSSOP
0001 = CK505 Yellow Cover Device, 64-pin TSSOP
6
0010 = CK505 Yellow Cover Device, 48-pin QFN (Reserved)
0011 = CK505 Yellow Cover Device, 56-pin QFN (Reserved)
0100 = CK505 Yellow Cover Device, 64-pin QFN
0101 = CK505 Yellow Cover Device, 72-pin QFN (Reserved)
0110 = CK505 Yellow Cover Device, 48-pin SSOP (Reserved)
0111 = CK505 Yellow Cover Device, 48-pin SSOP (Reserved)
1000 = Reserved
5
4
1001 = CY28548
1010 = Reserved
1011 = Reserved
1100 = Reserved
1101 = Reserved
1110 = Reserved
1111 = Reserved
3
2
1
0
0
1
Reserved
Reserved
Reserved
Reserved
27M_NSS_OE
Output enable for 27M_NSS
0 = Output Disabled, 1 = Output Enabled
0
1
27M_SS_OE
Output enable for 27M_SS
0 = Output Disabled, 1 = Output Enabled
Byte 9: Control Register 9
Bit
@Pup
Name
Description
7
0
PCIF_0_with PCI_STOP# Allows control of PCIF_0 with assertion of PCI_STOP#
0 = Free running PCIF, 1 = Stopped with PCI_STOP#
6
5
4
3
HW
1
TME_STRAP
REF drive strength
TEST_MODE_SEL
TEST_MODE_ENTRY
Trusted mode enable strap status
0 = Normal, 1 = No overclocking
REF drive strength
0 = Low 1x, 1 = High 2x
0
Mode select either REF/N or tri-state
0 = All output tri-state, 1 = All output REF/N
0
Allow entry into test mode
0 = Normal operation, 1 = Enter test mode
2
1
0
1
0
1
12C_VOUT<2>
12C_VOUT<1>
12C_VOUT<0>
I2C_VOUT[2,1,0]
000 = 0.63V
001 = 0.71V
010 = 0.77V
011 = 082V
100 = 0.86V
101 = 0.90V (default)
110 = 0.93V
111 = unused
Byte 10: Control Register 10
Bit
@Pup
Name
Description
7
HW
GCLK_SEL latch
Readback of GCLK_SEL latch
0 = DOT96/LCD_100, 1 = SRC0/27 MHz
6
1
PLL3_EN
PLL3 power down
0 = Power down, 1 = Power up
......................Document #: 001-08400 Rev ** Page 13 of 30
CY28548
Byte 10: Control Register 10 (continued)
Bit
@Pup
Name
Description
5
1
PLL2_EN
PLL2 power down
0 = Power down, 1 = Power up
4
3
2
1
0
1
1
1
1
1
SRC_DIV_EN
PCI_DIV_EN
SRC divider disable
0 = Disabled, 1 = Enabled
PCI divider disable
0 = Disabled, 1 = Enabled
CPU_DIV_EN
CPU divider disable
0 = Disabled, 1 = Enabled
CPU1 Stop Enable
CPU0 Stop Enable
Enable CPU_STOP# control of CPU1
0 = Free running, 1= Stoppable
Enable CPU_STOP# control of CPU0
0 = Free running, 1= Stoppable
Byte 11: Control Register 11
Bit
7
@Pup
Name
Description
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
6
5
4
3
2
1
0
Byte 12: Byte Count
Bit
7
@Pup
Name
Reserved
Reserved
BC5
Description
0
0
0
0
1
1
0
1
Reserved
Reserved
Byte count
Byte count
Byte count
Byte count
Byte count
Byte count
6
5
4
BC4
3
BC3
2
BC2
1
BC1
0
BC0
Byte 13: Control Register 13
Bit
@Pup
Name
Description
7
1
USB drive strength
USB drive strength
0 = Low, 1= High
6
5
4
3
1
0
1
1
PCI/ PCIF drive strength PCI drive strength
0 = Low, 1 = High
PLL1_Spread
SATA_SS_EN
CPU[T/C]2
Select percentage of spread for PLL1
0 = 0.5%, 1=1%
Enable SATA spread modulation,
0 = Spread Disabled, 1 = Spread Enabled
Allow control of CPU2 with assertion of CPU_STOP#
0 = Free running, 1 = Stopped with CPU_STOP#
......................Document #: 001-08400 Rev ** Page 14 of 30
CY28548
Byte 13: Control Register 13 (continued)
Bit
@Pup
Name
Description
2
1
SE1/SE2 drive strength SE1 and SE2 Drive Strength Setting 1 of 2 (See Byte
1 of 2
0 = Low, 1= High
Reserved
1
0
0
1
Reserved
SW_PCI
SW PCI_STP# Function
0 = SW PCI_STP assert, 1 = SW PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs are
stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs are
resumed in a synchronous manner with no short pulses.
Byte 14: Control Register 14
Bit
7
@Pup
Name
Description
0
0
0
0
0
0
0
0
CPU_DAF_N7
CPU_DAF_N6
CPU_DAF_N5
CPU_DAF_N4
CPU_DAF_N3
CPU_DAF_N2
CPU_DAF_N1
CPU_DAF_N0
If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and
CPU_DAF_M[6:0] are used to determine the CPU output frequency.
6
5
4
3
2
1
0
Byte 15: Control Register 15
Bit
7
@Pup
Name
Description
0
0
0
0
0
0
0
0
CPU_DAF_N8
CPU_DAF_M6
CPU_DAF_M5
CPU_DAF_M4
CPU_DAF_M3
CPU_DAF_M2
CPU_DAF_M1
CPU_DAF_M0
See Byte 14 for description
6
If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and
CPU_DAF_M[6:0] are used to determine the CPU output frequency.
5
4
3
2
1
0
Byte 16: Control Register 16
Bit
7
@Pup
Name
Description
PCI-E Dial-A-Frequency® Bit N7
PCI-E Dial-A-Frequency Bit N6
PCI-E Dial-A-Frequency Bit N5
PCI-E Dial-A-Frequency Bit N4
PCI-E Dial-A-Frequency Bit N3
PCI-E Dial-A-Frequency Bit N2
PCI-E Dial-A-Frequency Bit N1
PCI-E Dial-A-Frequency Bit N0
0
0
0
0
0
0
0
0
PCI-E_N7
PCI-E_N6
PCI-E_N5
PCI-E_N4
PCI-E_N3
PCI-E_N2
PCI-E_N1
PCI-E_N0
6
5
4
3
2
1
0
Byte 17: Control Register 17
Bit @Pup
Name
Description
......................Document #: 001-08400 Rev ** Page 15 of 30
CY28548
Byte 17: Control Register 17 (continued)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
SMSW_EN
Enable Smooth Switching
0 = Disabled, 1= Enabled
SMSW_SEL
Smooth switch select
0 = CPU_PLL, 1 = SRC_PLL
SE1/SE2 drive strength SE1 and SE2 drive strength Setting 2 of 2
2 of 2
Prog_PCI-E_EN
Programmable PCI-E frequency enable
0 = Disabled, 1= Enabled
Prog_CPU_EN
Programmable CPU frequency enable
0 = Disabled, 1= Enabled
REF drive strength
2 of 2
REFdrive strength strength Setting 2 of 2
USB drive strength
2 of 2
USB drive strength strength Setting 2 of 2
PCI/ PCIF drive strength PCI drive strength strength Setting 2 of 2
2of 2
Table 5. Crystal Recommendations
Frequency
Drive
(max.)
Shunt Cap Motional
Tolerance
(max.)
Stability
(max.)
Aging
(max.)
(Fund)
Cut
Loading Load Cap
(max.)
(max.)
14.31818 MHz
AT
Parallel 20 pF
0.1 mW
5 pF
0.016 pF
35 ppm
30 ppm
5 ppm
The CY28548 requires a Parallel Resonance Crystal. Substi-
tuting a series resonance crystal causes the CY28548 to
operate at the wrong frequency and violates the ppm specifi-
cation. For most applications there is a 300-ppm frequency
shift between series and parallel crystals due to incorrect
loading
crystal loading correctly. Again, the capacitance on each side
is in series with the crystal. The total capacitance on both side
is twice the specified crystal load capacitance (CL). Trim
capacitors are calculated to provide equal capacitive loading
on both sides.
Crystal Loading
C lo ck C h ip
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, use the total capac-
itance the crystal sees to calculate the appropriate capacitive
loading (CL).
C i2
C i1
P in
3 to 6 p
Figure 1 shows a typical crystal configuration using the two
trim capacitors. It is important that the trim capacitors are in
series with the crystal. It is not true that load capacitors are in
parallel with the crystal and are approximately equal to the
load capacitance of the crystal.
X 2
X 1
C s2
C s1
T ra ce
2 .8 p F
X T A L
C e 1
C e 2
T rim
3 3 p F
Figure 2. Crystal Loading Example
,
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
Load Capacitance (each side)
Ce = 2 * CL – (Cs + Ci)
Figure 1. Crystal Capacitive Clarification
Total Capacitance (as seen by the crystal)
Calculating Load Capacitors
1
CLe
=
1
1
(
)
In addition to the standard external trim capacitors, consider
the trace capacitance and pin capacitance to calculate the
+
Ce2 + Cs2 + Ci2
Ce1 + Cs1 + Ci1
......................Document #: 001-08400 Rev ** Page 16 of 30
CY28548
CL ...................................................Crystal load capacitance
CLe .........................................Actual loading seen by crystal
using standard value trim capacitors
Smooth Switching
The device contains one smooth switch circuit that is shared
by the CPU PLL and SRC PLL. The smooth switch circuit
ensures that when the output frequency changes by
overclocking, the transition from the old frequency to the new
frequency is a slow, smooth transition containing no glitches.
The rate of change of output frequency when using the smooth
switch circuit is less than 1 MHz/0.667 s. The frequency
overshoot and undershoot is less than 2%.
Ce .....................................................External trim capacitors
Cs.............................................. Stray capacitance (terraced)
Ci ...........................................................Internal capacitance
(lead frame, bond wires, etc.)
Dial-A-Frequency® (CPU and PCIEX)
The Smooth Switch circuit assigns auto or manual. In Auto
mode, clock generator assigns smooth switch automatically
when the PLL does overclocking. For manual mode, assign
the smooth switch circuit to PLL via Smbus. By default the
smooth switch circuit is set to auto mode. PLL can be
over-clocked when it does not have control of the smooth
switch circuit but it is not guaranteed to transition to the new
frequency without large frequency glitches.
This feature allows the user to over-clock their system by
slowly stepping up the CPU or SRC frequency. When the
programmable output frequency feature is enabled, the CPU
and SRC frequencies are determined by the following
equation:
Fcpu = G * N/M or Fcpu=G2 * N, where G2 = G / M.
Do not enable over-clocking and change the N values of both
PLLs in the same SMBUS block write and use smooth switch
mechanism on spread spectrum on/off.
• “N” and “M” are the values programmed in Programmable
Frequency Select N-Value Register and M-Value Register,
respectively.
• “G” stands for the PLL Gear Constant, which is determined
by the programmed value of FS[E:A]. See Table 1,
Frequency Select Table for the Gear Constant for each
Frequency selection. The PCI Express only allows user
control of the N register, the M value is fixed and
documented in Table 1, Frequency Select Table.
PD_RESTORE
If a ‘0’ is set for Byte 0 bit 0 then, upon assertion of PWRDWN#
LOW, the CY28548 initiates a full reset. The result of this is
that the clock chip emulates a cold power on start and goes to
the “Latches Open” state. If the PD_RESTORE bit is set to a
‘1’ then the configuration is stored upon PWRDWN# asserted
LOW. Note that if the iAMT bit, Byte 0 bit 3, is set to a ‘1’ then
the PD_RESTORE bit must be ignored. In other words, in Intel
iAMT mode, PWRDWN# reset is not allowed.
In this mode, the user writes the desired N and M values into
the DAF I2C registers. The user cannot change only the M
value and must change both the M and the N values at the
same time, if they require a change to the M value. The user
may change only the N value.
PWRDWN# (Power down) Clarification
The CKPWRGD/PWRDWN# pin is a dual-function pin. During
initial power up, the pin functions as CKPWRGD. Once
CKPWRGD has been sampled HIGH by the clock chip, the pin
assumes PD# functionality. The PD# pin is an asynchronous
active LOW input used to shut off all clocks cleanly before
shutting off power to the device. This signal is synchronized
internally to the device before powering down the clock
synthesizer. PD# is also an asynchronous input for powering
up the system. When PD# is asserted LOW, clocks are driven
to a LOW value and held before turning off the VCOs and the
crystal oscillator.
Associated Register Bits
• CPU_DAF Enable – This bit enables CPU DAF mode. By
default, it is not set. When set, the operating frequency is
determined by the values entered into the CPU_DAF_N
register. Note that the CPU_DAF_N and M register must
contain valid values before CPU_DAF is set. Default = 0,
(No DAF).
• CPU_DAF_N – There are nine bits (for 512 values) to
linearly change the CPU frequency (limited by VCO range).
Default = 0, (0000). The allowable values for N are detailed
in Table 1, Frequency Select Table.
PWRDWN# (Power down) Assertion
• CPU DAF M – There are 7 bits (for 128 values) to linearly
change the CPU frequency (limited by VCO range). Default
= 0, the allowable values for M are detailed in Table 1,
Frequency Select Table
When PD is sampled HIGH by two consecutive rising edges
of CPUC, all single-ended outputs will be held LOW on their
next HIGH-to-LOW transition and differential clocks must held
LOW. When PD mode is desired as the initial power on state,
PD must be asserted HIGH in less than 10 s after asserting
CKPWRGD.
• SRC_DAF Enable – This bit enables SRC DAF mode. By
default, it is not set. When set, the operating frequency is
determined by the values entered into the SRC_DAF_N
register. Note that the SRC_DAF_N register must contain
valid values before SRC_DAF is set. Default = 0, (No DAF).
PWRDWN# Deassertion
The power up latency is less than 1.8 ms. This is the time from
the deassertion of the PD# pin or the ramping of the power
supply until the time that stable clocks are generated from the
clock chip. All differential outputs stopped in a three-state
condition, resulting from power down are driven high in less
than 300 s of PD# deassertion to a voltage greater than
200 mV. After the clock chip’s internal PLL is powered up and
locked, all outputs are enabled within a few clock cycles of
• SRC_DAF_N – There are nine bits (for 512 values) to
linearly change the CPU frequency (limited by VCO range).
Default = 0, (0000). The allowable values for N are detailed
in Table 1, Frequency Select Table.
......................Document #: 001-08400 Rev ** Page 17 of 30
CY28548
each clock. Figure 4 is an example showing the relationship of
clocks coming up.
PD#
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
USB, 48MHz
DOT96T
DOT96C
PCI, 33 MHz
REF
Figure 3. Power down Assertion Timing Waveform
Ts table
<1.8 ms
PD#
CP UT , 133MHz
CP UC, 133MHz
S RCT 100MHz
S RCC 100MHz
US B , 48MHz
DOT 96T
DOT 96C
P CI, 33MHz
REF
Tdriv e_PW R D N #
<300 s , >200m V
Figure 4. Power down Deassertion Timing Waveform
FS_A, FS_B,FS_C,FS_D
CK_PWRGD
PWRGD_VRM
0.2-0.3 ms
Delay
Wait for
VTT_PWRGD#
Device is not affected,
VTT_PWRGD# is ignored
Sample Sels
State 2
VDD Clock Gen
Clock State
State 0
Off
State 1
State 3
On
Clock Outputs
Clock VCO
On
Off
Figure 5. CK_PWRGD Timing Diagram
......................Document #: 001-08400 Rev ** Page 18 of 30
CY28548
CPU_STP# Assertion
CPU_STP# Deassertion
The CPU_STP# signal is an active LOW input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
When the CPU_STP# pin is asserted, all CPU outputs that are
set with the SMBus configuration to be stoppable are stopped
within two to six CPU clock periods after sampled by two rising
edges of the internal CPUC clock. The final states of the
stopped CPU signals are CPUT = HIGH and CPUC = LOW.
The deassertion of the CPU_STP# signal causes all stopped
CPU outputs to resume normal operation in a synchronous
manner. No short or stretched clock pulses are produced when
the clock resumes. The maximum latency from the
deassertion to active outputs is no more than two CPU clock
cycles.
CPU_STP#
CPUT
CPUC
Figure 6. CPU_STP# Assertion Waveform
CPU_STP#
CPUT
CPUC
CPUT Internal
CPUC Internal
Tdrive_CPU_STP#,10 ns>200 mV
Figure 7. CPU_STP# Deassertion Waveform
1.8 ms
CPU_STOP#
PD#
CPUT(Free Running
CPUC(Free Running
CPUT(Stoppable)
CPUC(Stoppable)
DOT96T
DOT96C
Figure 8. CPU_STP# = Driven, CPU_PD = Driven, DOT_PD = Driven
......................Document #: 001-08400 Rev ** Page 19 of 30
CY28548
1.8 ms
CPU_STOP#
PD#
CPUT(Free Running)
CPUC(Free Running)
CPUT(Stoppable)
CPUC(Stoppable)
DOT96T
DOT96C
Figure 9. CPU_STP# = Tri-state, CPU_PD = Tri-state, DOT_PD = Tri-state
.
PCI_STP# Assertion
The PCI_STP# signal is an active LOW input used for
synchronously stopping and starting the PCI outputs while the
rest of the clock generator continues to function. The set-up
time for capturing PCI_STP# going LOW is 10 ns (tSU). (See
Figure 10.) The PCIF clocks are affected by this pin if their
corresponding control bit in the SMBus register is set to allow
them to be free running.
Tsu
PCI_STP#
PCI_F
PCI
SRC 100MHz
Figure 10. PCI_STP# Assertion Waveform
PCI_STP# Deassertion
.
The deassertion of the PCI_STP# signal causes all PCI and
stoppable PCIF clocks to resume running in a synchronous
manner within two PCI clock periods, after PCI_STP# transi-
tions to a HIGH level.
Tdrive_SRC
Tsu
PCI_STP#
PCI_F
PCI
SRC 100MHz
Figure 11. PCI_STP# Deassertion Waveform
......................Document #: 001-08400 Rev ** Page 20 of 30
CY28548
.
Table 6. Output Driver Status during PCI-STOP# and CPU-STOP#
PCI_STOP# Asserted
CPU_STOP# Asserted
Running
SMBus OE Disabled
Single-ended Clocks Stoppable
Non stoppable
Stoppable
Driven low
Driven low
Running
Running
Differential Clocks
Clock driven high
Clock# driven low
Running
Clock driven high
Clock# driven low
Running
Clock driven Low or 20K
pulldown
Non stoppable
Table 7. Output Driver Status
All Differential Clocks except
CPU1
All Single-ended Clocks
w/o Strap w/ Strap
Low Hi-z
CPU1
Clock
Clock#
Clock
Low or 20K pulldown Low
Low or 20K pulldown Low
Running Running
Clock#
Latches Open State
Powerdown
M1
Low or 20K pulldown Low
Low or 20K pulldown Low
Low or 20K pulldown Low
Low
Low
Hi-z
Hi-z
.
Table 8. PLL3/SE Configuration Table
GCLK_SEL
B1b4
0
B1b3
0
B1b2
0
B1b1
0
Pin 27 (17) MHz Pin 25 (18) MHz Spread (%)
Comment
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
PLL3 Disabled
0
0
0
1
100
100
100
100
0.5
0.5
1
SRC1 from SRC_Main
0
0
1
0
LCD_100 from PLL3
0
0
1
1
100
100
LCD_100 from PLL3
0
1
0
0
100
100
1.5
2
LCD_100 from PLL3
0
1
0
1
100
100
LCD_100 from PLL3
0
1
1
0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
none
N/A
N/A
N/A
N/A
0.5
0.5
1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0
1
1
1
N/A
N/A
1
0
0
0
N/A
N/A
1
0
0
1
N/A
N/A
1
0
1
0
N/A
N/A
1
0
1
1
N/A
N/A
1
1
0
0
N/A
N/A
1
1
0
1
N/A
N/A
1
1
1
0
N/A
N/A
1
1
1
1
N/A
N/A
0
0
0
0
N/A
N/A
0
0
0
1
27M_NSS
27M_NSS
27M_NSS
27M_NSS
27M_NSS
N/A
27M_NSS
27M_NSS
27M_NSS
27M_NSS
27M_NSS
N/A
27M_NSS from PLL3
27M_NSS from PLL3
27M_NSS from PLL3
27M_NSS from PLL3
27M_NSS from PLL3
0
0
1
0
0
0
1
1
0
1
0
0
1.5
2
0
1
0
1
0
1
1
0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0
1
1
1
N/A
N/A
1
0
0
0
N/A
N/A
1
0
0
1
N/A
N/A
1
0
1
0
N/A
N/A
1
0
1
1
N/A
N/A
1
1
0
0
N/A
N/A
......................Document #: 001-08400 Rev ** Page 21 of 30
CY28548
Table 8. PLL3/SE Configuration Table (continued)
GCLK_SEL
B1b4
B1b3
B1b2
B1b1
Pin 27 (17) MHz Pin 25 (18) MHz Spread (%)
N/A N/A N/A
Comment
1
1
1
0
1
Figure 12. Clock Generator Power up/Run State Diagram
C l o c k O f f t o M1
3.3V
Vcc
2.0V
T_delay t
FSC
FSB
FSA
CPU_STOP#
PCI_STOP#
CKPWRGD/PWRDWN
CK505 SMBUS
CK505 State
Off
Latches Open
Off
Off
M1
BSEL[0..2]
CK505 Core Logic
PLL1
Locked
CPU1
PLL2 & PLL3
All Other Clocks
REF Oscillator
T_delay2
T_delay3
Figure 13. BSEL Serial Latching
......................Document #: 001-08400 Rev ** Page 22 of 30
CY28548
Absolute Maximum Conditions
Parameter
VDD
Description
Core Supply Voltage
Analog Supply Voltage
IO Supply Voltage
Input Voltage
Condition
Min.
Max.
4.6
4.6
1.5
4.6
150
85
Unit
V
–
–
VDD_A
VDD_IO
VIN
V
V
Relative to VSS
Non-functional
Functional
–0.5
–65
0
VDC
°C
°C
TS
Temperature, Storage
TA
Temperature, Operating
Ambient
TJ
Temperature, Junction
Functional
–
–
150
20
°C
ØJC
Dissipation, Junction to Case Mil-STD-883E Method 1012.1
°C/
W
ØJA
Dissipation, Junction to Ambient JEDEC (JESD 51)
–
60
–
°C/
W
ESDHBM
ESD Protection (Human Body MIL-STD-883, Method 3015
Model)
2000
V
UL-94
MSL
Flammability Rating
At 1/8 in.
V–0
1
Moisture Sensitivity Level
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications
Parameter
VDD core
Description
Condition
Min.
Max.
3.465
VDD + 0.3
0.8
Unit
V
3.3V Operating Voltage
3.3V Input High Voltage (SE)
3.3V Input Low Voltage (SE)
Input High Voltage
3.3 ± 5%
3.135
VIH
2.0
V
VIL
VSS – 0.3
V
VIHI2C
VILI2C
VIH_FS
VIL_FS
VIHFS_C_TEST
SDATA, SCLK
SDATA, SCLK
2.2
–
V
Input Low Voltage
–
1.0
V
FS_[A,B] Input High Voltage
FS_[A,B] Input Low Voltage
FS_C Input High Voltage
0.7
1.5
V
VSS – 0.3
0.35
VDD + 0.3
1.5
V
2
0.7
V
VIMFS_C_NORMAL FS_C Input Middle Voltage
VILFS_C_NORMAL FS_C Input Low Voltage
V
VSS – 0.3
–
0.35
5
V
IIH
Input High Leakage Current
Input Low Leakage Current
Except internal pull-down resistors, 0 < VIN < VDD
Except internal pull-up resistors, 0 < VIN < VDD
A
A
V
IIL
–5
–
VOH
VOL
VDD IO
VOH
VOL
IOZ
3.3V Output High Voltage (SE) IOH = –1 mA
3.3V Output Low Voltage (SE) IOL = 1 mA
Low Voltage IO Supply Voltage
2.4
–
–
0.4
V
0.72
0.70
0.88
0.90
0.40
10
3.3V Input High Voltage (DIFF)
V
V
3.3V Input Low Voltage (DIFF)
High-impedance Output
Current
–10
1.5
A
CIN
Input Pin Capacitance
Output Pin Capacitance
Pin Inductance
5
6
pF
pF
nH
V
COUT
LIN
–
7
VXIH
VXIL
IDD3.3V
Xin High Voltage
0.7VDD
VDD
0.3VDD
250
Xin Low Voltage
0
–
V
Dynamic Supply Current
mA
......................Document #: 001-08400 Rev ** Page 23 of 30
CY28548
AC Electrical Specifications
Parameter
Crystal
TDC
Description
Condition
Min.
Max.
Unit
XIN Duty Cycle
XIN Period
The device operates reliably with input
duty cycles up to 30/70 but the REFclock
duty cycle will not be within specification
47.5
52.5
%
TPERIOD
When XIN is driven from an external
clock source
69.841
71.0
ns
TR/TF
XIN Rise and Fall Times
XIN Cycle to Cycle Jitter
Long-term Accuracy
Measured between 0.3VDD and 0.7VDD
–
–
–
10.0
500
300
ns
ps
TCCJ
As an average over 1-s duration
LACC
ppm
CPU at 0.7V
TDC
45
55
CPUT and CPUC Duty Cycle
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9.99900
7.49925
5.99940
4.99950
3.74963
2.99970
2.49975
10.0100
7.50075
6.00060
5.00050
3.75038
3.00030
2.50025
TPERIOD
TPERIOD
TPERIOD
TPERIOD
TPERIOD
TPERIOD
TPERIOD
TPERIODSS
TPERIODSS
TPERIODSS
TPERIODSS
TPERIODSS
TPERIODSS
TPERIODSS
TPERIODAbs
100 MHz CPUT and CPUC Period
133 MHz CPUT and CPUC Period
166 MHz CPUT and CPUC Period
200 MHz CPUT and CPUC Period
266 MHz CPUT and CPUC Period
333 MHz CPUT and CPUC Period
400 MHz CPUT and CPUC Period
10.02406 10.02607
100 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s
133 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s
166 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s
200 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s
266 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s
333 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s
400 MHz CPUT and CPUC Period, SSC Measured at 0V differential at 0.1s
7.51804
6.01444
5.01203
3.75902
3.00722
2.50601
9.91400
7.51955
6.01564
5.01303
3.75978
3.00782
2.50652
10.0860
100 MHz CPUT and CPUC Absolute
period
Measured at 0V differential at 1 clock
Measured at 0V differential at 1 clock
Measured at 0V differential @ 1 clock
Measured at 0V differential @ 1 clock
Measured at 0V differential @ 1 clock
Measured at 0V differential @ 1 clock
Measured at 0V differential @ 1 clock
Measured at 0V differential @ 1 clock
Measured at 0V differential @ 1 clock
Measured at 0V differential @ 1 clock
Measured at 0V differential @ 1 clock
7.41425
5.91440
4.91450
3.66463
2.91470
2.41475
9.91406
7.41430
5.91444
4.91453
7.58575
6.08560
5.08550
3.83538
3.08530
2.58525
10.1362
7.62340
6.11572
5.11060
TPERIODAbs
TPERIODAbs
TPERIODAbs
TPERIODAbs
TPERIODAbs
TPERIODAbs
133 MHz CPUT and CPUC Absolute
period
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
166 MHz CPUT and CPUC Absolute
period
200 MHz CPUT and CPUC Absolute
period
266 MHz CPUT and CPUC Absolute
period
333 MHz CPUT and CPUC Absolute
period
400 MHz CPUT and CPUC Absolute
period
TPERIODSSAbs 100 MHz CPUT and CPUC Absolute
period, SSC
TPERIODSSAbs 133 MHz CPUT and CPUC Absolute
period, SSC
TPERIODSSAbs 166 MHz CPUT and CPUC Absolute
period, SSC
TPERIODSSAbs 200 MHz CPUT and CPUC Absolute
period, SSC
......................Document #: 001-08400 Rev ** Page 24 of 30
CY28548
AC Electrical Specifications (continued)
Parameter
Description
Condition
Min.
Max.
Unit
3.66465
3.85420
TPERIODSSAbs 266 MHz CPUT and CPUC Absolute
period, SSC
Measured at 0V differential @ 1 clock
ns
2.91472
2.41477
3.10036
2.59780
TPERIODSSAbs 333 MHz CPUT and CPUC Absolute
period, SSC
Measured at 0V differential @ 1 clock
Measured at 0V differential @ 1 clock
ns
ns
TPERIODSSAbs 400 MHz CPUT and CPUC Absolute
period, SSC
TCCJ
CPU Cycle to Cycle Jitter
CPU2_ITP Cycle to Cycle Jitter
Long-term Accuracy
Measured at 0V differential
–
–
85
125
100
100
150
8
ps
ps
TCCJ2
Measured at 0V differential
LACC
Measured at 0V differential
–
ppm
ps
TSKEW
TSKEW2
TR / TF
TRFM
CPU0 to CPU1 Clock Skew
CPU2_ITP to CPU0 Clock Skew
CPU Rising/Falling Slew rate
Rise/Fall Matching
Measured at 0V differential
–
Measured at 0V differential
–
ps
Measured differentially from ±150 mV
Measured single-endedly from ±75 mV
2.5
–
V/ns
%
20
VHIGH
Voltage High
1.15
–
V
VLOW
Voltage Low
–0.3
300
V
VOX
Crossing Point Voltage at 0.7V Swing
550
mV
SRC at 0.7V
TDC
SRC Duty Cycle
Measured at 0V differential
45
55
%
ns
ns
ns
ns
ns
9.99900
10.0010
TPERIOD
TPERIODSS
TPERIODAbs
100 MHz SRC Period
Measured at 0V differential @ 0.1s
Measured at 0V differential @ 0.1s
Measured at 0V differential @ 1 clock
Measured at 0V differential @ 1 clock
10.02406 10.02607
100 MHz SRC Period, SSC
100 MHz SRC Absolute Period
9.87400
9.87406
–
10.1260
10.1762
3.0
TPERIODSSAbs 100 MHz SRC Absolute Period, SSC
TSKEW(window) Any SRC Clock Skew from the earliest Measured at 0V differential
bank to the latest bank
TCCJ
SRC Cycle to Cycle Jitter
SRC Long Term Accuracy
SRC Rising/Falling Slew Rate
Rise/Fall Matching
Measured at 0V differential
–
–
125
100
8
ps
ppm
V/ns
%
LACC
Measured at 0V differential
TR / TF
TRFM
Measured differentially from ±150 mV
Measured single-endedly from ±75 mV
2.5
–
20
VHIGH
VLOW
Voltage High
1.15
–
V
Voltage Low
–0.3
300
V
VOX
Crossing Point Voltage at 0.7V Swing
550
mV
DOT96 at 0.7V
TDC
DOT96 Duty Cycle
Measured at 0V differential
45
55
10.4177
10.6677
250
100
8
%
ns
10.4156
TPERIOD
TPERIODAbs
TCCJ
DOT96 Period
Measured at 0V differential at 0.1s
Measured at 0V differential at 0.1s
Measured at 0V differential at 1 clock
Measured at 0V differential at 1 clock
Measured differentially from ±150 mV
Measured single-endedly from ±75 mV
10.1656
DOT96 Absolute Period
DOT96 Cycle to Cycle Jitter
DOT96 Long Term Accuracy
DOT96 Rising/Falling Slew Rate
Rise/Fall Matching
ns
–
–
ps
LACC
ppm
V/ns
%
TR / TF
TRFM
2.5
–
20
VHIGH
VLOW
Voltage High
1.15
–
V
Voltage Low
–0.3
300
V
VOX
Crossing Point Voltage at 0.7V Swing
550
mV
LCD_100_SSC at 0.7V
TDC
LCD_100 Duty Cycle
100 MHz LCD_100 Period
Measured at 0V differential
45
55
%
TPERIOD
Measured at 0V differential at 0.1s
9.99900
10.0010
ns
......................Document #: 001-08400 Rev ** Page 25 of 30
CY28548
AC Electrical Specifications (continued)
Parameter
TPERIODSS
TPERIODAbs
Description
Condition
Min.
Max.
Unit
100 MHz LCD_100 Period, SSC -0.5% Measured at 0V differential at 0.1s
10.02406 10.02607 ns
9.74900 10.25100 ns
100 MHz LCD_100 Absolute Period
Measured at 0V differential at 1 clock
Measured at 0V differential @ 1 clock
TPERIODSSAbs 100 MHz LCD_100 Absolute Period,
SSC
9.74906
10.3012
ns
TCCJ
LCD_100 Cycle to Cycle Jitter
LCD_100 Long Term Accuracy
LCD_100 Rising/Falling Slew Rate
Rise/Fall Matching
Measured at 0V differential
–
–
250
100
8
ps
ppm
V/ns
%
LACC
TR / TF
TRFM
VHIGH
VLOW
VOX
Measured at 0V differential
Measured differentially from ±150 mV
Measured single-endedly from ±75 mV
2.5
–
20
Voltage High
1.15
–
V
Voltage Low
–0.3
300
V
Crossing Point Voltage at 0.7V Swing
550
mV
PCI/PCIF at 3.3V
TDC
PCI Duty Cycle
Measurement at 1.5V
Measurement at 1.5V
Measurement at 1.5V
Measurement at 1.5V
Measurement at 1.5V
45
55
%
ns
ns
ns
ns
29.99700 30.00300
30.08421 30.23459
29.49700 30.50300
29.56617 30.58421
TPERIOD
TPERIODSS
TPERIODAbs
Spread Disabled PCIF/PCI Period
Spread Enabled PCIF/PCI Period
Spread Disabled PCIF/PCI Period
TPERIODSSAbs Spread Enabled PCIF/PCI Period
THIGH
TLOW
THIGH
Spread Enabled PCIF and PCI high time Measurement at 2V
Spread Enabled PCIF and PCI low time Measurement at 0.8V
12.27095 16.27995 ns
11.87095 16.07995 ns
12.27365 16.27665 ns
Spread Disabled PCIF and PCI high
time
Measurement at 2.V
TLOW
Spread Disabled PCIF and PCI low time Measurement at 0.8V
11.87365 16.07665 ns
TR / TF
TSKEW
TCCJ
PCIF/PCI Rising/Falling Slew Rate
Measured between 0.8V and 2.0V
1.0
–
4.0
1000
500
100
V/ns
ps
Any PCI clock to Any PCI clock Skew Measurement at 1.5V
PCIF and PCI Cycle to Cycle Jitter
PCIF/PCI Long Term Accuracy
Measurement at 1.5V
Measurement at 1.5V
–
ps
LACC
–
ppm
48_M at 3.3V
TDC
Duty Cycle
Measurement at 1.5V
Measurement at 1.5V
Measurement at 1.5V
Measurement at 2V
45
55
%
ns
20.83125 20.83542
20.48125 21.18542
8.216563 11.15198
7.816563 10.95198
TPERIOD
TPERIODAbs
THIGH
Period
Absolute Period
48_M High time
ns
ns
TLOW
48_M Low time
Measurement at 0.8V
Measured between 0.8V and 2.0V
Measurement at 1.5V
Measurement at 1.5V
ns
TR / TF
TCCJ
Rising and Falling Edge Rate
Cycle to Cycle Jitter
48M Long Term Accuracy
1.0
–
2.0
350
100
V/ns
ps
LACC
–
ppm
27M_NSS/27M_SS at 3.3V
TDC
Duty Cycle
Measurement at 1.5V
45
55
%
TPERIOD
Spread Disabled 27M Period
Spread Enabled 27M Period
Rising and Falling Edge Rate
Cycle to Cycle Jitter
Measurement at 1.5V
37.03594 37.03813 ns
37.03594 37.03813 ns
Measurement at 1.5V
TR / TF
TCCJ
LACC
REF
Measured between 0.4V and 2.0V
Measurement at 1.5V
1.0
–
4.0
200
50
V/ns
ps
27_M Long Term Accuracy
Measured at crossing point VOX
–
ppm
TDC
REF Duty Cycle
Measurement at 1.5V
45
55
%
......................Document #: 001-08400 Rev ** Page 26 of 30
CY28548
AC Electrical Specifications (continued)
Parameter
TPERIOD
TPERIODAbs
THIGH
Description
Condition
Measurement at 1.5V
Min.
Max.
Unit
ns
69.82033 69.86224
68.83429 70.84826
29.97543 38.46654
29.57543 38.26654
REF Period
Measurement at 1.5V
ns
REF Absolute Period
REF High time
Measurement at 2V
ns
Measurement at 0.8V
ns
TLOW
REF Low time
TR / TF
TSKEW
REF Rising and Falling Edge Rate
REF Clock to REF Clock
REF Cycle to Cycle Jitter
Long Term Accuracy
Measured between 0.8V and 2.0V
Measurement at 1.5V
Measurement at 1.5V
Measurement at 1.5V
1.0
–
4.0
500
V/ns
ps
TCCJ
–
1000
100
ps
LACC
–
ppm
ENABLE/DISABLE and SET-UP
TSTABLE Clock Stabilization from Power-up
TSS Stopclock Set-up Time
–
1.8
–
ms
ns
10.0
Test and Measurement Set-up
For PCI Single-ended Signals and Reference
The following diagram shows the test load configurations for
the single-ended PCI, USB, and REF output signals.
Measurement
Point
22
L1
L2
50
4 pF
4 pF
L1 = 0.5", L2 = 8"
22
PCI/USB
Measurement
Point
50
L2
L1
Figure 14. Single-ended PCI and USB Double Load Configuration
Measurement
15
L2
L1
Point
50
4 pF
Measurement
Point
4 pF
15
15
L1
L1
L2
REF
50
Measurement
Point
4 pF
L2
50
Figure 15. Single-ended REF Triple Load Configuration
......................Document #: 001-08400 Rev ** Page 27 of 30
CY28548
Figure 16. Single-ended Output Signals (for AC Parameters Measurement)
For CPU, SRC, and DOT96 Signals and Reference
This diagram shows the test load configuration for the differential CPU and SRC outputs
M e asu rem e nt P oin t
L
O U T +
5 0 O h m
2p F
L= 8"
M e asure m e nt P o int
L
O U T -
5 0 O h m
2 p F
Figure 17. 0.7V Differential Load Configuration
Clock Period (Differential)
Positive Duty Cycle (Differential)
Negative Duty Cycle (Differential)
0.0V
0.0V
Clck-Clck#
Rise
Edge
Rate
Fall
Edge
Rate
VIH = +150V
VIH = +150V
0.0V
0.0V
VIL = -150V
VIL = -150V
Clock-Clock#
Figure 18. Differential Measurement for Differential Output Signals (for AC Parameters Measurement)
......................Document #: 001-08400 Rev ** Page 28 of 30
CY28548
VMAX = 1.15V
VMAX = 1.15V
CLK#
VcrossMAX = 550mV
VcrossMIN = 300mV
VcrossMAX = 550mV
VcrossMIN = 300mV
CLK
VMIN = 0.30V
VMIN = 0.30V
CLK#
Vcross delta = 140mV
Vcross delta = 140mV
CLK#
CLK#
Vcross median +75mV
Vcross median
Vcross median
Vcross median -75mV
CLK
CLK
Figure 19. Single-ended Measurement for Differential Output Signals (for AC Parameters Measurement)
Ordering Information
Part Number
Package Type
Product Flow
Lead-free
CY28548ZXC
CY28548ZXCT
CY28548LFXC
CY28548LFXCT
64-pin TSSOP
Commercial, 0 to 85C
Commercial, 0 to 85C
Commercial, 0 to 85C
Commercial, 0 to 85C
64-pin TSSOP–Tape and Reel
64-pin QFN
64-pin QFN–Tape and Reel
......................Document #: 001-08400 Rev ** Page 29 of 30
CY28548
Package Diagrams
64-Lead Thin Shrunk Small Outline Package (6 mm x 17 mm) Z64
32
1
DIMENSIONS IN MM MIN.
MAX.
REFERENCE JEDEC MO-153
PART #
8.00[0.315]
8.20[0.322]
Z6424
STANDARD PKG.
6.00[0.236]
6.20[0.244]
ZZ6424
LEAD FREE PKG.
33
64
16.90[0.665]
17.10[0.673]
1.10[0.043]
MAX.
GAUGE PLANE
0.25[0.010]
0.20[0.008]
0.50[0.020]
0.75[0.027]
0.50[0.020]
BSC
0.85[0.033]
0.95[0.037]
0.10[0.004]
0.20[0.008]
0.05[0.002]
0.15[0.006]
0°-8°
0.17[0.006]
0.27[0.010]
SEATING
PLANE
64-Lead QFN 9 x 9 mm (Punch Version) LF64A
REFERENCE JEDEC MO-220
WEIGHT: 0.2 GRAMS
0.08[0.003]
C
8.90[0.350]
9.10[0.358]
A
1.00[0.039] MAX.
0.80[0.031] MAX.
0.05[0.002] MAX.
0.18[0.007]
0.28[0.011]
8.70[0.342]
8.80[0.346]
PIN1 ID
0.20[0.008] R.
0.20[0.008] REF.
N
N
1
2
1
2
3
0.45[0.018]
0.80 DIA.
0.30[0.012]
0.50[0.020]
0.24[0.009]
0.60[0.024]
(4X)
0°-12°
0.50[0.020]
TOP VIEW
7.45[0.293]
7.55[0.297]
C
SEATING
PLANE
BOTTOM VIEW
SIDE VIEW
......................Document #: 001-08400 Rev ** Page 30 of 30
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