EFM32GG900F1024G-E-D1I [SILICON]
Memory Protection Unit;
| 型号： | EFM32GG900F1024G-E-D1I |
| 厂家： | 
SILICON |
| 描述： | Memory Protection Unit |
| 文件： | 总27页 (文件大小：485K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EFM32GG900 DATASHEET
F1024/F512
• ARM Cortex-M3 CPU platform
• High Performance 32-bit processor @ up to 48 MHz
• Memory Protection Unit
• External Bus Interface for up to 4x256 MB of external
memory mapped space
• TFT Controller with Direct Drive
• Communication interfaces
• 3× Universal Synchronous/Asynchronous Receiv-
er/Transmitter
• UART/SPI/SmartCard (ISO 7816)/IrDA/I2S
• 2× Universal Asynchronous Receiver/Transmitter
• 2× Low Energy UART
• Flexible Energy Management System
• 20 nA @ 3 V Shutoff Mode
• 0.4 µA @ 3 V Shutoff Mode with RTC
• 0.8 µA @ 3 V Stop Mode, including Power-on Reset, Brown-out
Detector, RAM and CPU retention
• 1.1 µA @ 3 V Deep Sleep Mode, including RTC with 32.768 kHz
oscillator, Power-on Reset, Brown-out Detector, RAM and CPU
retention
• Autonomous operation with DMA in Deep Sleep
Mode
• 80 µA/MHz @ 3 V Sleep Mode
• 219 µA/MHz @ 3 V Run Mode, with code executed from flash
• 1024/512 KB Flash
• 2× I2C Interface with SMBus support
• Address recognition in Stop Mode
• Universal Serial Bus (USB) with Host & OTG support
• Fully USB 2.0 compliant
• Read-while-write support
• 128 KB RAM
• 93 General Purpose I/O pins
• On-chip PHY and embedded 5V to 3.3V regulator
• Ultra low power precision analog peripherals
• 12-bit 1 Msamples/s Analog to Digital Converter
• 8 single ended channels/4 differential channels
• On-chip temperature sensor
• 12-bit 500 ksamples/s Digital to Analog Converter
• 2 single ended channels/1 differential channel
• 2× Analog Comparator
• Configurable push-pull, open-drain, pull-up/down, input filter, drive
strength
• Configurable peripheral I/O locations
• 16 asynchronous external interrupts
• Output state retention and wake-up from Shutoff Mode
• 12 Channel DMA Controller
• 12 Channel Peripheral Reflex System (PRS) for autonomous in-
ter-peripheral signaling
• Capacitive sensing with up to 16 inputs
• 3× Operational Amplifier
• Hardware AES with 128/256-bit keys in 54/75 cycles
• Timers/Counters
• 6.1 MHz GBW, Rail-to-rail, Programmable Gain
• Supply Voltage Comparator
• 4× 16-bit Timer/Counter
• 4×3 Compare/Capture/PWM channels
• Dead-Time Insertion on TIMER0
• Low Energy Sensor Interface (LESENSE)
• Autonomous sensor monitoring in Deep Sleep Mode
• Wide range of sensors supported, including LC sen-
sors and capacitive buttons
• 16-bit Low Energy Timer
• 1× 24-bit Real-Time Counter and 1× 32-bit Real-Time Counter
• 3× 16/8-bit Pulse Counter with asynchronous operation
• Watchdog Timer with dedicated RC oscillator @ 50 nA
• Integrated LCD Controller for up to 8×36 segments
• Voltage boost, adjustable contrast and autonomous animation
• Backup Power Domain
• RTC and retention registers in a separate power domain, avail-
able in all energy modes
• Operation from backup battery when main power drains out
• Ultra efficient Power-on Reset and Brown-Out Detec-
tor
• Debug Interface
• 2-pin Serial Wire Debug interface
• 1-pin Serial Wire Viewer
• Embedded Trace Module v3.5 (ETM)
• Pre-Programmed USB/UART Bootloader
• Temperature range -40 to 85 ºC
• Single power supply 1.98 to 3.8 V
• Delivered as full wafer
32-bit ARM Cortex-M0+, Cortex-M3 and Cortex-M4 microcontrollers for:
• Energy, gas, water and smart metering
• Health and fitness applications
• Smart accessories
• Alarm and security systems
• Industrial and home automation
...the world's most energy friendly microcontrollers
1 Ordering Information
Table 1.1 (p. 2) shows the available EFM32GG900 devices.
Table 1.1. Ordering Information
Ordering Code
Flash (kB) RAM (kB)
Max
Speed
(MHz)
Supply
Voltage
(V)
Temperature
(ºC)
Package
EFM32GG900F512G-E-D1I
EFM32GG900F1024G-E-D1I
512
128
128
48
48
1.98 - 3.8
1.98 - 3.8
-40 - 85
-40 - 85
Wafer
Wafer
1024
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2 System Summary
The EFM32GG900 products are delivered in wafer form, but are otherwise identical to the EFM32GG995
packaged parts. Please refer to the EFM32GG995 datasheet for additional information.
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3 Pinout and Package
Note
Please refer to the application note "AN0002 EFM32 Hardware Design Considerations" for
guidelines on designing Printed Circuit Boards (PCB's) for the EFM32GG900.
3.1 Padout
The EFM32GG900 padout is shown in Figure 3.1 (p. 4) and Table 3.1 (p. 5). Alternate locations
are denoted by "#" followed by the location number (Multiple locations on the same pad are split with "/").
Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module
in question.
Figure 3.1. EFM32GG900 Padout (top view, not to scale)
(X,Y): (- 3090, 2615)
(X,Y): (3090, 2615)
97
96
PF11
PC15
PA0
PA1
PA2
PA3
PA4
PA5
PA6
1
2
3
4
5
6
7
95 PF10
94 PC14
93 usb_vrego_1
92 usb_vrego_0
91 usb_vregi_1
90
89
88
usb_vregi_0
PC13
PC12
iovdd_0
iovss_0
PD14
8
9
87
86
PC11
PC10
10
85 PC9
84 PC8
NC
NC
11
12
13
83 PE7
82 PE6
PD15
81 PE5
PB0
PB1
PB2
14
15
16
80
79
78
77
76
PE4
PE3
PE2
PE1
PE0
(X,Y): (0, 0)
NC
17
18
PB3
75 NC
74
iovss_4
PB4
PB5
PB6
19
20
21
iovss_1
iovdd_1
PC0
22
23
24
25
26
27
28
29
30
31
73 dec_2
72 dec_1
71 dec_0
PC1
PC2
70
69
68
iovdd_4
vdd_dreg
vss_dreg
PC3
PC4
67
66
PC7
PC6
PC5
65 PD8
64 PD7
63 PD6
62 PD5
PB7
PB8
(X,Y): (- 3090, - 2615)
(X,Y): (3090, - 2615)
The pad coordinates represent the center of the pad opening relative to the die center.
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Table 3.1. Device Padout
Wafer Pads and Coordinates
Pad Alternate Functionality / Description
Commu-
X
Y
Pad Name
Analog
EBI
Timers
Other
[µm] [µm]
nication
I2C0_SDA #0
LEU0_RX #4
PRS_CH0 #0
GPIO_EM4WU0
1
2
3
4
5
6
7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
-3040.0 2309.4
-3040.0 2149.3
-3040.0 1989.2
-3040.0 1829.1
-3040.0 1669.0
-3040.0 1508.9
-3040.0 1348.8
LCD_SEG13
LCD_SEG14
LCD_SEG15
LCD_SEG16
LCD_SEG17
LCD_SEG18
LCD_SEG19
EBI_AD09 #0/1/2
EBI_AD10 #0/1/2
EBI_AD11 #0/1/2
EBI_AD12 #0/1/2
EBI_AD13 #0/1/2
EBI_AD14 #0/1/2
EBI_AD15 #0/1/2
TIM0_CC0 #0/1/4
TIM0_CC1 #0/1
TIM0_CC2 #0/1
TIM0_CDTI0 #0
TIM0_CDTI1 #0
TIM0_CDTI2 #0
CMU_CLK1 #0
PRS_CH1 #0
I2C0_SCL #0
CMU_CLK0 #0
ETM_TD0 #3
LES_ALTEX2 #0
ETM_TD1 #3
U0_TX #2
U0_RX #2
LES_ALTEX3 #0
ETM_TD2 #3
LES_ALTEX4 #0
ETM_TD3 #3
LEU1_TX #1
LEU1_RX #1
ETM_TCLK #3
GPIO_EM4WU1
8
IOVDD_0
IOVSS_0
PD14
NC
-3040.0 1188.7 Digital IO power supply 0.
-3040.0 1045.4 Digital IO ground 0.
9
10
11
12
13
14
15
16
17
-3040.0
-3040.0
-3040.0
-3040.0
-3040.0
-3040.0
-3040.0
-3040.0
902.1
I2C0_SDA #3
I2C0_SCL #3
740.0 Do not connect.
598.7 Do not connect.
455.4
NC
PD15
PB0
295.3
135.2
-24.9
LCD_SEG32
LCD_SEG33
LCD_SEG34
EBI_A16 #0/1/2
EBI_A17 #0/1/2
EBI_A18 #0/1/2
TIM1_CC0 #2
TIM1_CC1 #2
TIM1_CC2 #2
PB1
PB2
NC
-185.0 Do not connect.
LCD_SEG20/
-328.3
18
19
20
21
PB3
PB4
PB5
PB6
-3040.0
-3040.0
-3040.0
EBI_A19 #0/1/2
EBI_A20 #0/1/2
EBI_A21 #0/1/2
EBI_A22 #0/1/2
PCNT1_S0IN #1
PCNT1_S1IN #1
US2_TX #1
US2_RX #1
US2_CLK #1
US2_CS #1
LCD_COM4
LCD_SEG21/
-488.4
LCD_COM5
LCD_SEG22/
-648.5
LCD_COM6
LCD_SEG23/
-808.6
-3040.0
-3040.0
LCD_COM7
22
23
IOVSS_1
IOVDD_1
-968.7 Digital IO ground 1.
-3040.0 -1112.0 Digital IO power supply 1.
ACMP0_CH0
-3040.0 -1255.3 DAC0_OUT0ALT #0/
OPAMP_OUT0ALT
US0_TX #5
US1_TX #0
I2C0_SDA #4
TIM0_CC1 #4
PCNT0_S0IN #2
LES_CH0 #0
PRS_CH2 #0
24
25
26
27
28
PC0
PC1
PC2
PC3
PC4
EBI_A23 #0/1/2
EBI_A24 #0/1/2
EBI_A25 #0/1/2
ACMP0_CH1
-3040.0 -1404.9 DAC0_OUT0ALT #1/
OPAMP_OUT0ALT
US0_RX #5
US1_RX #0
I2C0_SCL #4
TIM0_CC2 #4
PCNT0_S1IN #2
LES_CH1 #0
PRS_CH3 #0
ACMP0_CH2
-3040.0 -1554.6 DAC0_OUT0ALT #2/
OPAMP_OUT0ALT
TIM0_CDTI0 #4
TIM0_CDTI1 #4
US2_TX #0
US2_RX #0
LES_CH2 #0
LES_CH3 #0
LES_CH4 #0
ACMP0_CH3
-3040.0 -1704.3 DAC0_OUT0ALT #3/
OPAMP_OUT0ALT
EBI_NANDREn
#0/1/2
TIM0_CDTI2 #4
LETIM0_OUT0 #3
PCNT1_S0IN #0
ACMP0_CH4
-3040.0 -1854.0
US2_CLK #0
I2C1_SDA #0
EBI_A26 #0/1/2
OPAMP_P0
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Wafer Pads and Coordinates
Pad Alternate Functionality / Description
X
Y
Commu-
nication
Pad Name
Analog
EBI
Timers
Other
[µm] [µm]
ACMP0_CH5
OPAMP_N0
EBI_NANDWEn
#0/1/2
LETIM0_OUT1 #3
PCNT1_S1IN #0
US2_CS #0
I2C1_SCL #0
29
30
31
PC5
PB7
PB8
-3040.0 -2003.6
-3040.0 -2153.3
-3040.0 -2303.0
LES_CH5 #0
US0_TX #4
US1_CLK #0
LFXTAL_P
LFXTAL_N
TIM1_CC0 #3
TIM1_CC1 #3
US0_RX #4
US1_CS #0
32
33
34
35
36
37
38
39
40
41
PA7
PA8
-2790.0 -2565.0
-2618.1 -2565.0
-2453.1 -2565.0
-2277.7 -2565.0
-2095.2 -2565.0
LCD_SEG35
LCD_SEG36
LCD_SEG37
LCD_SEG38
LCD_SEG39
EBI_CSTFT #0/1/2
EBI_DCLK #0/1/2
EBI_DTEN #0/1/2
EBI_VSNC #0/1/2
EBI_HSNC #0/1/2
TIM2_CC0 #0
TIM2_CC1 #0
TIM2_CC2 #0
PA9
PA10
PA11
IOVDD_2
IOVSS_2
PA12
-1909.3 -2565.0 Digital IO power supply 2.
-1764.7 -2565.0 Digital IO ground 2.
-1613.0 -2565.0
-1455.0 -2565.0
-1296.9 -2565.0
LCD_BCAP_P
LCD_BCAP_N
EBI_A00 #0/1/2
EBI_A01 #0/1/2
EBI_A02 #0/1/2
TIM2_CC0 #1
TIM2_CC1 #1
TIM2_CC2 #1
PA13
PA14
LCD_BEXT
Reset input, active low.
42
RESETn
-1159.8 -2565.0 To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the inter-
nal pull-up ensure that reset is released.
43
44
PB9
-987.8
-819.3
-2565.0
-2565.0
EBI_A03 #0/1/2
EBI_A04 #0/1/2
U1_TX #2
U1_RX #2
PB10
DAC0_OUT0 /
OPAMP_OUT0
LETIM0_OUT0 #1
TIM1_CC2 #3
45
46
PB11
PB12
228.1
357.3
-2565.0
-2565.0
I2C1_SDA #1
I2C1_SCL #1
DAC0_OUT1 /
OPAMP_OUT1
LETIM0_OUT1 #1
47
48
49
50
AVSS_2
AVDD_2
AVDD_1
AVSS_1
493.4
579.7
666.3
-2565.0 Analog ground 2.
-2565.0 Analog power supply 2.
-2565.0 Analog power supply 1.
1727.9 -2565.0 Analog ground 1.
US0_CLK #4/5
LEU0_TX #1
51
52
PB13
PB14
1808.3 -2565.0
1894.5 -2565.0
HFXTAL_P
HFXTAL_N
US0_CS #4/5
LEU0_RX #1
53
54
55
56
IOVSS_3
IOVDD_3
AVSS_0
AVDD_0
2030.5 -2565.0 Digital IO ground 3.
2129.1 -2565.0 Digital IO power supply 3.
2227.6 -2565.0 Analog ground 0.
2317.6 -2565.0 Analog power supply 0.
ADC0_CH0
DAC0_OUT0ALT #4/
OPAMP_OUT0ALT
OPAMP_OUT2 #1
57
58
PD0
PD1
2413.0 -2565.0
PCNT2_S0IN #0
US1_TX #1
US1_RX #1
ADC0_CH1
2529.8 -2565.0 DAC0_OUT1ALT #4/
OPAMP_OUT1ALT
TIM0_CC0 #3
PCNT2_S1IN #0
DBG_SWO #2
USB_DMPU #0
US1_CLK #1
59
60
PD2
PD3
2617.5 -2565.0
2722.4 -2565.0
ADC0_CH2
EBI_A27 #0/1/2
TIM0_CC1 #3
TIM0_CC2 #3
DBG_SWO #3
ETM_TD1 #0/2
ADC0_CH3
OPAMP_N2
US1_CS #1
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Wafer Pads and Coordinates
Pad Alternate Functionality / Description
X
Y
Commu-
nication
Pad Name
Analog
EBI
Timers
Other
[µm] [µm]
ADC0_CH4
OPAMP_P2
61
62
PD4
PD5
2825.3 -2565.0
3040.0 -2373.0
LEU0_TX #0
LEU0_RX #0
ETM_TD2 #0/2
ETM_TD3 #0/2
ADC0_CH5
OPAMP_OUT2 #0
LETIM0_OUT0 #0
TIM1_CC0 #4
PCNT0_S0IN #3
LES_ALTEX0 #0
ACMP0_O #2
ETM_TD0 #0
ADC0_CH6
OPAMP_P1
US1_RX #2
I2C0_SDA #1
63
64
PD6
PD7
3040.0 -2272.2
3040.0 -2171.0
CMU_CLK0 #2
LES_ALTEX1 #0
ACMP1_O #2
LETIM0_OUT1 #0
TIM1_CC1 #4
PCNT0_S1IN #3
ADC0_CH7
OPAMP_N1
US1_TX #2
I2C0_SCL #1
ETM_TCLK #0
65
66
PD8
PC6
3040.0 -2066.7
3040.0 -1980.9
BU_VIN
CMU_CLK1 #1
I2C0_SDA #2
LEU1_TX #0
LES_CH6 #0
ETM_TCLK #2
ACMP0_CH6
EBI_A05 #0/1/2
EBI_A06 #0/1/2
I2C0_SCL #2
LEU1_RX #0
LES_CH7 #0
ETM_TD0 #2
67
PC7
3040.0 -1894.5
ACMP0_CH7
68
69
70
71
72
73
74
75
VSS_DREG
VDD_DREG
IOVDD_4
DEC_0
3040.0 -1797.5 Ground for on-chip voltage regulator.
3040.0 -1717.5 Power supply for on-chip voltage regulator.
3040.0 -1637.8 Digital IO power supply 4.
3040.0 -1340.2 Decouple output for on-chip voltage regulator.
3040.0 -1256.5 Decouple output for on-chip voltage regulator.
3040.0 -1178.8 Decouple output for on-chip voltage regulator.
DEC_1
DEC_2
IOVSS_4
NC
3040.0
3040.0
-442.1 Digital IO ground 4.
-342.0 Do not connect.
TIM3_CC0 #1
PCNT0_S0IN #1
U0_TX #1
I2C1_SDA #2
76
77
PE0
PE1
3040.0
3040.0
-239.4
-134.1
EBI_A07 #0/1/2
EBI_A08 #0/1/2
TIM3_CC1 #1
PCNT0_S1IN #1
U0_RX #1
I2C1_SCL #2
78
79
80
81
82
83
84
PE2
PE3
PE4
PE5
PE6
PE7
PC8
3040.0
3040.0
3040.0
3040.0
3040.0
3040.0
3040.0
-30.9
65.8
BU_VOUT
BU_STAT
EBI_A09 #0
EBI_A10 #0
TIM3_CC2 #1
U1_TX #3
U1_RX #3
ACMP0_O #1
ACMP1_O #1
160.3
329.8
461.6
578.7
689.3
LCD_COM0
LCD_COM1
LCD_COM2
LCD_COM3
ACMP1_CH0
EBI_A11 #0/1/2
EBI_A12 #0/1/2
EBI_A13 #0/1/2
EBI_A14 #0/1/2
EBI_A15 #0/1/2
US0_CS #1
US0_CLK #1
US0_RX #1
US0_TX #1
US0_CS #2
TIM2_CC0 #2
TIM2_CC1 #2
TIM2_CC2 #2
LES_CH8 #0
LES_CH9 #0
GPIO_EM4WU2
85
PC9
3040.0
778.3
ACMP1_CH1
EBI_A09 #1/2
US0_CLK #2
86
87
PC10
PC11
3040.0
3040.0
880.2
970.9
ACMP1_CH2
ACMP1_CH3
ACMP1_CH4
EBI_A10 #1/2
EBI_ALE #1/2
US0_RX #2
US0_TX #2
LES_CH10 #0
LES_CH11 #0
CMU_CLK0 #1
LES_CH12 #0
88
89
PC12
PC13
3040.0
3040.0
1520.0 DAC0_OUT1ALT #0/
OPAMP_OUT1ALT
U1_TX #0
U1_RX #0
TIM0_CDTI0 #1/3
TIM1_CC0 #0
TIM1_CC2 #4
ACMP1_CH5
1623.9 DAC0_OUT1ALT #1/
OPAMP_OUT1ALT
LES_CH13 #0
PCNT0_S0IN #0
90 USB_VREGI_0 3040.0
91 USB_VREGI_1 3040.0
1729.8 USB input to internal 3.3 V regulator.
1809.0 USB input to internal 3.3 V regulator.
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Wafer Pads and Coordinates
Pad Alternate Functionality / Description
X
Y
Commu-
nication
Pad Name
Analog
EBI
Timers
Other
[µm] [µm]
92 USB_VREGO_0 3040.0
93 USB_VREGO_1 3040.0
1888.3 USB decoupling for internal 3.3 V USB regulator and regulator output.
1967.7 USB decoupling for internal 3.3 V USB regulator and regulator output.
ACMP1_CH6
2066.3 DAC0_OUT1ALT #2/
OPAMP_OUT1ALT
TIM0_CDTI1 #1/3
TIM1_CC1 #0
PCNT0_S1IN #0
US0_CS #3
U0_TX #3
94
95
96
PC14
PF10
PC15
3040.0
3040.0
3040.0
LES_CH14 #0
U1_TX #1
USB_DM
2171.6
ACMP1_CH7
2255.8 DAC0_OUT1ALT #3/
OPAMP_OUT1ALT
TIM0_CDTI2 #1/3
TIM1_CC2 #0
US0_CLK #3
U0_RX #3
LES_CH15 #0
DBG_SWO #1
U1_RX #1
USB_DP
97
98
PF11
3040.0
2761.9
2366.2
IOVSS_7
2565.0 Digital IO ground 7.
US1_CLK #2
I2C0_SDA #5
LEU0_TX #3
TIM0_CC0 #5
LETIM0_OUT0 #2
DBG_SWCLK
#0/1/2/3
99
PF0
PF1
2596.1
2495.1
2565.0
2565.0
US1_CS #2
I2C0_SCL #5
LEU0_RX #3
DBG_SWDIO
#0/1/2/3
GPIO_EM4WU3
TIM0_CC1 #5
LETIM0_OUT1 #2
100
ACMP1_O #0
DBG_SWO #0
GPIO_EM4WU4
101
102
PF2
PF3
2368.6
2242.0
2565.0
2565.0
LCD_SEG0
LCD_SEG1
EBI_ARDY #0/1/2
EBI_ALE #0
TIM0_CC2 #5
LEU0_TX #4
PRS_CH0 #1
ETM_TD3 #1
TIM0_CDTI0 #2/5
103 USB_VBUS
2056.1
1928.9
1802.4
1675.9
1532.8
1415.0
1300.0
499.5
2565.0 USB 5.0 V VBUS input.
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
PF4
PF12
PF5
2565.0
2565.0
2565.0
LCD_SEG2
EBI_WEn #0/2
EBI_REn #0/2
TIM0_CDTI1 #2/5
TIM0_CDTI2 #2/5
PRS_CH1 #1
PRS_CH2 #1
USB_ID
LCD_SEG3
USB_VBUSEN #0
IOVSS_5
IOVDD_5
PF6
2565.0 Digital IO ground 5.
2565.0 Digital IO power supply 5.
2565.0
2565.0
2565.0
2565.0
2565.0
2565.0
2565.0
2565.0
2565.0
2565.0
2565.0
LCD_SEG24
LCD_SEG25
LCD_SEG26
LCD_SEG27
LCD_SEG28
LCD_SEG29
LCD_SEG30
LCD_SEG31
EBI_BL0 #0/1/2
EBI_BL1 #0/1/2
EBI_WEn #1
TIM0_CC0 #2
TIM0_CC1 #2
TIM0_CC2 #2
U0_TX #0
U0_RX #0
PF7
PF8
377.6
ETM_TCLK #1
ETM_TD0 #1
PF9
244.1
EBI_REn #1
PD9
118.3
EBI_CS0 #0/1/2
EBI_CS1 #0/1/2
EBI_CS2 #0/1/2
EBI_CS3 #0/1/2
PD10
PD11
PD12
PD13
PB15
PE8
-15.1
-148.6
-276.3
-608.6
-780.8
-952.9
ETM_TD1 #1
ETM_TD2 #1
PRS_CH3 #1
LCD_SEG4
LCD_SEG5
LCD_SEG6
EBI_AD00 #0/1/2
EBI_AD01 #0/1/2
EBI_AD02 #0/1/2
PCNT2_S0IN #1
PCNT2_S1IN #1
TIM1_CC0 #1
PE9
-1135.5 2565.0
-1318.1 2565.0
PE10
US0_TX #0
US0_RX #0
BOOT_TX
LES_ALTEX5 #0
BOOT_RX
122
PE11
-1500.7 2565.0
LCD_SEG7
EBI_AD03 #0/1/2
TIM1_CC1 #1
123
124
IOVDD_6
IOVSS_6
-1683.2 2565.0 Digital IO power supply 6.
-1849.0 2565.0 Digital IO ground 6.
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Wafer Pads and Coordinates
Pad Alternate Functionality / Description
X
Y
Commu-
nication
Pad Name
Analog
EBI
Timers
Other
[µm] [µm]
US0_RX #3
US0_CLK #0
I2C0_SDA #6
CMU_CLK1 #2
LES_ALTEX6 #0
125
126
PE12
PE13
-2014.8 2565.0
-2197.4 2565.0
LCD_SEG8
LCD_SEG9
EBI_AD04 #0/1/2
EBI_AD05 #0/1/2
TIM1_CC2 #1
US0_TX #3
US0_CS #0
I2C0_SCL #6
LES_ALTEX7 #0
ACMP0_O #0
GPIO_EM4WU5
127
128
129
PE14
PE15
PA15
-2379.9 2565.0
-2562.5 2565.0
-2745.1 2565.0
LCD_SEG10
LCD_SEG11
LCD_SEG12
EBI_AD06 #0/1/2
EBI_AD07 #0/1/2
EBI_AD08 #0/1/2
TIM3_CC0 #0
TIM3_CC1 #0
TIM3_CC2 #0
LEU0_TX #2
LEU0_RX #2
3.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in
Table 3.2 (p. 9). The table shows the name of the alternate functionality in the first column, followed
by columns showing the possible LOCATION bitfield settings.
Note
Some functionality, such as analog interfaces, do not have alternate settings or a LOCA-
TION bitfield. In these cases, the pinout is shown in the column corresponding to LOCA-
TION 0.
Table 3.2. Alternate functionality overview
Alternate
LOCATION
Functionality
ACMP0_CH0
ACMP0_CH1
ACMP0_CH2
ACMP0_CH3
ACMP0_CH4
ACMP0_CH5
ACMP0_CH6
ACMP0_CH7
ACMP0_O
0
1
2
PD6
PD7
3
4
5
6
Description
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PE13
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
PF2
Analog comparator ACMP0, channel 0.
Analog comparator ACMP0, channel 1.
Analog comparator ACMP0, channel 2.
Analog comparator ACMP0, channel 3.
Analog comparator ACMP0, channel 4.
Analog comparator ACMP0, channel 5.
Analog comparator ACMP0, channel 6.
Analog comparator ACMP0, channel 7.
Analog comparator ACMP0, digital output.
Analog comparator ACMP1, channel 0.
Analog comparator ACMP1, channel 1.
Analog comparator ACMP1, channel 2.
Analog comparator ACMP1, channel 3.
Analog comparator ACMP1, channel 4.
Analog comparator ACMP1, channel 5.
Analog comparator ACMP1, channel 6.
Analog comparator ACMP1, channel 7.
Analog comparator ACMP1, digital output.
Analog to digital converter ADC0, input channel number 0.
Analog to digital converter ADC0, input channel number 1.
PE2
ACMP1_CH0
ACMP1_CH1
ACMP1_CH2
ACMP1_CH3
ACMP1_CH4
ACMP1_CH5
ACMP1_CH6
ACMP1_CH7
ACMP1_O
PE3
ADC0_CH0
PD0
PD1
ADC0_CH1
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Alternate
LOCATION
Functionality
ADC0_CH2
ADC0_CH3
ADC0_CH4
ADC0_CH5
ADC0_CH6
ADC0_CH7
BOOT_RX
0
1
2
3
4
5
6
Description
PD2
PD3
PD4
PD5
PD6
PD7
PE11
PE10
Analog to digital converter ADC0, input channel number 2.
Analog to digital converter ADC0, input channel number 3.
Analog to digital converter ADC0, input channel number 4.
Analog to digital converter ADC0, input channel number 5.
Analog to digital converter ADC0, input channel number 6.
Analog to digital converter ADC0, input channel number 7.
Bootloader RX.
BOOT_TX
Bootloader TX.
Backup Power Domain status, whether or not the system
is in backup mode
BU_STAT
PE3
BU_VIN
PD8
PE2
PA2
PA1
PC5
PD7
PD3
Battery input for Backup Power Domain
BU_VOUT
CMU_CLK0
CMU_CLK1
OPAMP_N0
OPAMP_N1
OPAMP_N2
Power output for Backup Power Domain
PC12
PD8
PD7
Clock Management Unit, clock output number 0.
Clock Management Unit, clock output number 1.
Operational Amplifier 0 external negative input.
Operational Amplifier 1 external negative input.
Operational Amplifier 2 external negative input.
PE12
DAC0_OUT0 /
OPAMP_OUT0
Digital to Analog Converter DAC0_OUT0 /
OPAMP output channel number 0.
PB11
PC0
DAC0_OUT0ALT /
OPAMP_OUT0ALT
Digital to Analog Converter DAC0_OUT0ALT /
OPAMP alternative output for channel 0.
PC1
PC2
PC3
PD0
DAC0_OUT1 /
OPAMP_OUT1
Digital to Analog Converter DAC0_OUT1 /
OPAMP output channel number 1.
PB12
PC12
DAC0_OUT1ALT /
OPAMP_OUT1ALT
Digital to Analog Converter DAC0_OUT1ALT /
OPAMP alternative output for channel 1.
PC13
PD0
PC14
PC15
PD1
OPAMP_OUT2
OPAMP_P0
OPAMP_P1
OPAMP_P2
PD5
PC4
PD6
PD4
Operational Amplifier 2 output.
Operational Amplifier 0 external positive input.
Operational Amplifier 1 external positive input.
Operational Amplifier 2 external positive input.
Debug-interface Serial Wire clock input.
DBG_SWCLK
DBG_SWDIO
DBG_SWO
PF0
PF1
PF2
PF0
PF0
PF1
PD1
PF0
PF1
PD2
Note that this function is enabled to pin out of reset, and
has a built-in pull down.
Debug-interface Serial Wire data input / output.
PF1
Note that this function is enabled to pin out of reset, and
has a built-in pull up.
Debug-interface Serial Wire viewer Output.
PC15
Note that this function is not enabled after reset, and must
be enabled by software to be used.
EBI_A00
EBI_A01
EBI_A02
EBI_A03
EBI_A04
EBI_A05
EBI_A06
EBI_A07
PA12
PA13
PA14
PB9
PA12
PA13
PA14
PB9
PA12
PA13
PA14
PB9
External Bus Interface (EBI) address output pin 00.
External Bus Interface (EBI) address output pin 01.
External Bus Interface (EBI) address output pin 02.
External Bus Interface (EBI) address output pin 03.
External Bus Interface (EBI) address output pin 04.
External Bus Interface (EBI) address output pin 05.
External Bus Interface (EBI) address output pin 06.
External Bus Interface (EBI) address output pin 07.
PB10
PC6
PB10
PC6
PB10
PC6
PC7
PC7
PC7
PE0
PE0
PE0
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Alternate
LOCATION
Functionality
EBI_A08
EBI_A09
EBI_A10
EBI_A11
EBI_A12
EBI_A13
EBI_A14
EBI_A15
EBI_A16
EBI_A17
EBI_A18
EBI_A19
EBI_A20
EBI_A21
EBI_A22
EBI_A23
EBI_A24
EBI_A25
EBI_A26
EBI_A27
0
1
2
PE1
PC9
PC10
PE4
PE5
PE6
PE7
PC8
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PC0
PC1
PC2
PC4
PD2
3
4
5
6
Description
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PC8
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PC0
PC1
PC2
PC4
PD2
PE1
External Bus Interface (EBI) address output pin 08.
External Bus Interface (EBI) address output pin 09.
External Bus Interface (EBI) address output pin 10.
External Bus Interface (EBI) address output pin 11.
External Bus Interface (EBI) address output pin 12.
External Bus Interface (EBI) address output pin 13.
External Bus Interface (EBI) address output pin 14.
External Bus Interface (EBI) address output pin 15.
External Bus Interface (EBI) address output pin 16.
External Bus Interface (EBI) address output pin 17.
External Bus Interface (EBI) address output pin 18.
External Bus Interface (EBI) address output pin 19.
External Bus Interface (EBI) address output pin 20.
External Bus Interface (EBI) address output pin 21.
External Bus Interface (EBI) address output pin 22.
External Bus Interface (EBI) address output pin 23.
External Bus Interface (EBI) address output pin 24.
External Bus Interface (EBI) address output pin 25.
External Bus Interface (EBI) address output pin 26.
External Bus Interface (EBI) address output pin 27.
PC9
PC10
PE4
PE5
PE6
PE7
PC8
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PC0
PC1
PC2
PC4
PD2
External Bus Interface (EBI) address and data input / out-
put pin 00.
EBI_AD00
EBI_AD01
EBI_AD02
EBI_AD03
EBI_AD04
EBI_AD05
EBI_AD06
EBI_AD07
EBI_AD08
EBI_AD09
EBI_AD10
EBI_AD11
EBI_AD12
EBI_AD13
PE8
PE8
PE8
External Bus Interface (EBI) address and data input / out-
put pin 01.
PE9
PE9
PE9
External Bus Interface (EBI) address and data input / out-
put pin 02.
PE10
PE11
PE12
PE13
PE14
PE15
PA15
PA0
PE10
PE11
PE12
PE13
PE14
PE15
PA15
PA0
PE10
PE11
PE12
PE13
PE14
PE15
PA15
PA0
External Bus Interface (EBI) address and data input / out-
put pin 03.
External Bus Interface (EBI) address and data input / out-
put pin 04.
External Bus Interface (EBI) address and data input / out-
put pin 05.
External Bus Interface (EBI) address and data input / out-
put pin 06.
External Bus Interface (EBI) address and data input / out-
put pin 07.
External Bus Interface (EBI) address and data input / out-
put pin 08.
External Bus Interface (EBI) address and data input / out-
put pin 09.
External Bus Interface (EBI) address and data input / out-
put pin 10.
PA1
PA1
PA1
External Bus Interface (EBI) address and data input / out-
put pin 11.
PA2
PA2
PA2
External Bus Interface (EBI) address and data input / out-
put pin 12.
PA3
PA3
PA3
External Bus Interface (EBI) address and data input / out-
put pin 13.
PA4
PA4
PA4
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Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
External Bus Interface (EBI) address and data input / out-
put pin 14.
EBI_AD14
PA5
PA5
PA5
External Bus Interface (EBI) address and data input / out-
put pin 15.
EBI_AD15
EBI_ALE
PA6
PF3
PF2
PA6
PC11
PF2
PA6
PC11
PF2
External Bus Interface (EBI) Address Latch Enable output.
External Bus Interface (EBI) Hardware Ready Control in-
put.
EBI_ARDY
EBI_BL0
PF6
PF6
PF6
External Bus Interface (EBI) Byte Lane/Enable pin 0.
External Bus Interface (EBI) Byte Lane/Enable pin 1.
External Bus Interface (EBI) Chip Select output 0.
External Bus Interface (EBI) Chip Select output 1.
External Bus Interface (EBI) Chip Select output 2.
External Bus Interface (EBI) Chip Select output 3.
External Bus Interface (EBI) Chip Select output TFT.
External Bus Interface (EBI) TFT Dot Clock pin.
External Bus Interface (EBI) TFT Data Enable pin.
EBI_BL1
PF7
PF7
PF7
EBI_CS0
EBI_CS1
EBI_CS2
EBI_CS3
EBI_CSTFT
EBI_DCLK
EBI_DTEN
PD9
PD10
PD11
PD12
PA7
PD9
PD10
PD11
PD12
PA7
PD9
PD10
PD11
PD12
PA7
PA8
PA8
PA8
PA9
PA9
PA9
External Bus Interface (EBI) TFT Horizontal Synchroniza-
tion pin.
EBI_HSNC
PA11
PA11
PA11
EBI_NANDREn
EBI_NANDWEn
EBI_REn
PC3
PC5
PF5
PC3
PC5
PF9
PC3
PC5
PF5
External Bus Interface (EBI) NAND Read Enable output.
External Bus Interface (EBI) NAND Write Enable output.
External Bus Interface (EBI) Read Enable output.
External Bus Interface (EBI) TFT Vertical Synchronization
pin.
EBI_VSNC
PA10
PA10
PA10
EBI_WEn
PF4
PD7
PD6
PD3
PD4
PD5
PA0
PA6
PC9
PF1
PF2
PE13
PF8
PF4
PC6
PC7
PD3
PD4
PD5
External Bus Interface (EBI) Write Enable output.
Embedded Trace Module ETM clock .
ETM_TCLK
PF8
PA6
PA2
PA3
PA4
PA5
ETM_TD0
PF9
Embedded Trace Module ETM data 0.
ETM_TD1
PD13
PB15
PF3
Embedded Trace Module ETM data 1.
ETM_TD2
Embedded Trace Module ETM data 2.
ETM_TD3
Embedded Trace Module ETM data 3.
GPIO_EM4WU0
GPIO_EM4WU1
GPIO_EM4WU2
GPIO_EM4WU3
GPIO_EM4WU4
GPIO_EM4WU5
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
High Frequency Crystal negative pin. Also used as exter-
nal optional clock input pin.
HFXTAL_N
PB14
HFXTAL_P
I2C0_SCL
I2C0_SDA
I2C1_SCL
I2C1_SDA
PB13
PA1
PA0
PC5
PC4
High Frequency Crystal positive pin.
I2C0 Serial Clock Line input / output.
I2C0 Serial Data input / output.
PD7
PC7
PC6
PE1
PE0
PD15
PD14
PC1
PC0
PF1
PF0
PE13
PE12
PD6
PB12
PB11
I2C1 Serial Clock Line input / output.
I2C1 Serial Data input / output.
LCD voltage booster (optional), boost capacitor, negative
pin. If using the LCD voltage booster, connect a 22 nF ca-
pacitor between LCD_BCAP_N and LCD_BCAP_P.
LCD_BCAP_N
PA13
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Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
LCD voltage booster (optional), boost capacitor, positive
pin. If using the LCD voltage booster, connect a 22 nF ca-
pacitor between LCD_BCAP_N and LCD_BCAP_P.
LCD_BCAP_P
PA12
PA14
LCD voltage booster (optional), boost output. If using the
LCD voltage booster, connect a 1 uF capacitor between
this pin and VSS.
LCD_BEXT
An external LCD voltage may also be applied to this pin if
the booster is not enabled.
If AVDD is used directly as the LCD supply voltage, this
pin may be left unconnected or used as a GPIO.
LCD_COM0
LCD_COM1
LCD_COM2
LCD_COM3
PE4
PE5
PE6
PE7
LCD driver common line number 0.
LCD driver common line number 1.
LCD driver common line number 2.
LCD driver common line number 3.
LCD segment line 0. Segments 0, 1, 2 and 3 are con-
trolled by SEGEN0.
LCD_SEG0
LCD_SEG1
LCD_SEG2
LCD_SEG3
LCD_SEG4
LCD_SEG5
LCD_SEG6
LCD_SEG7
LCD_SEG8
LCD_SEG9
LCD_SEG10
LCD_SEG11
LCD_SEG12
LCD_SEG13
LCD_SEG14
LCD_SEG15
LCD_SEG16
LCD_SEG17
LCD_SEG18
LCD_SEG19
PF2
LCD segment line 1. Segments 0, 1, 2 and 3 are con-
trolled by SEGEN0.
PF3
LCD segment line 2. Segments 0, 1, 2 and 3 are con-
trolled by SEGEN0.
PF4
LCD segment line 3. Segments 0, 1, 2 and 3 are con-
trolled by SEGEN0.
PF5
LCD segment line 4. Segments 4, 5, 6 and 7 are con-
trolled by SEGEN1.
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PA15
PA0
PA1
PA2
PA3
PA4
PA5
PA6
LCD segment line 5. Segments 4, 5, 6 and 7 are con-
trolled by SEGEN1.
LCD segment line 6. Segments 4, 5, 6 and 7 are con-
trolled by SEGEN1.
LCD segment line 7. Segments 4, 5, 6 and 7 are con-
trolled by SEGEN1.
LCD segment line 8. Segments 8, 9, 10 and 11 are con-
trolled by SEGEN2.
LCD segment line 9. Segments 8, 9, 10 and 11 are con-
trolled by SEGEN2.
LCD segment line 10. Segments 8, 9, 10 and 11 are con-
trolled by SEGEN2.
LCD segment line 11. Segments 8, 9, 10 and 11 are con-
trolled by SEGEN2.
LCD segment line 12. Segments 12, 13, 14 and 15 are
controlled by SEGEN3.
LCD segment line 13. Segments 12, 13, 14 and 15 are
controlled by SEGEN3.
LCD segment line 14. Segments 12, 13, 14 and 15 are
controlled by SEGEN3.
LCD segment line 15. Segments 12, 13, 14 and 15 are
controlled by SEGEN3.
LCD segment line 16. Segments 16, 17, 18 and 19 are
controlled by SEGEN4.
LCD segment line 17. Segments 16, 17, 18 and 19 are
controlled by SEGEN4.
LCD segment line 18. Segments 16, 17, 18 and 19 are
controlled by SEGEN4.
LCD segment line 19. Segments 16, 17, 18 and 19 are
controlled by SEGEN4.
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Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
LCD segment line 20. Segments 20, 21, 22 and 23 are
controlled by SEGEN5. This pin may also be used as LCD
COM line 4
LCD_SEG20/
LCD_COM4
PB3
PB4
PB5
PB6
LCD segment line 21. Segments 20, 21, 22 and 23 are
controlled by SEGEN5. This pin may also be used as LCD
COM line 5
LCD_SEG21/
LCD_COM5
LCD segment line 22. Segments 20, 21, 22 and 23 are
controlled by SEGEN5. This pin may also be used as LCD
COM line 6
LCD_SEG22/
LCD_COM6
LCD segment line 23. Segments 20, 21, 22 and 23 are
controlled by SEGEN5. This pin may also be used as LCD
COM line 7
LCD_SEG23/
LCD_COM7
LCD segment line 24. Segments 24, 25, 26 and 27 are
controlled by SEGEN6.
LCD_SEG24
LCD_SEG25
LCD_SEG26
LCD_SEG27
LCD_SEG28
LCD_SEG29
LCD_SEG30
LCD_SEG31
LCD_SEG32
LCD_SEG33
LCD_SEG34
LCD_SEG35
LCD_SEG36
LCD_SEG37
LCD_SEG38
LCD_SEG39
PF6
LCD segment line 25. Segments 24, 25, 26 and 27 are
controlled by SEGEN6.
PF7
LCD segment line 26. Segments 24, 25, 26 and 27 are
controlled by SEGEN6.
PF8
LCD segment line 27. Segments 24, 25, 26 and 27 are
controlled by SEGEN6.
PF9
LCD segment line 28. Segments 28, 29, 30 and 31 are
controlled by SEGEN7.
PD9
PD10
PD11
PD12
PB0
PB1
PB2
PA7
PA8
PA9
PA10
PA11
LCD segment line 29. Segments 28, 29, 30 and 31 are
controlled by SEGEN7.
LCD segment line 30. Segments 28, 29, 30 and 31 are
controlled by SEGEN7.
LCD segment line 31. Segments 28, 29, 30 and 31 are
controlled by SEGEN7.
LCD segment line 32. Segments 32, 33, 34 and 35 are
controlled by SEGEN8.
LCD segment line 33. Segments 32, 33, 34 and 35 are
controlled by SEGEN8.
LCD segment line 34. Segments 32, 33, 34 and 35 are
controlled by SEGEN8.
LCD segment line 35. Segments 32, 33, 34 and 35 are
controlled by SEGEN8.
LCD segment line 36. Segments 36, 37, 38 and 39 are
controlled by SEGEN9.
LCD segment line 37. Segments 36, 37, 38 and 39 are
controlled by SEGEN9.
LCD segment line 38. Segments 36, 37, 38 and 39 are
controlled by SEGEN9.
LCD segment line 39. Segments 36, 37, 38 and 39 are
controlled by SEGEN9.
LES_ALTEX0
LES_ALTEX1
LES_ALTEX2
LES_ALTEX3
LES_ALTEX4
LES_ALTEX5
LES_ALTEX6
LES_ALTEX7
LES_CH0
PD6
PD7
PA3
LESENSE alternate exite output 0.
LESENSE alternate exite output 1.
LESENSE alternate exite output 2.
LESENSE alternate exite output 3.
LESENSE alternate exite output 4.
LESENSE alternate exite output 5.
LESENSE alternate exite output 6.
LESENSE alternate exite output 7.
LESENSE channel 0.
PA4
PA5
PE11
PE12
PE13
PC0
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Alternate
LOCATION
Functionality
LES_CH1
0
1
2
3
4
5
6
Description
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
PD6
PD7
PD5
LESENSE channel 1.
LESENSE channel 2.
LESENSE channel 3.
LESENSE channel 4.
LESENSE channel 5.
LESENSE channel 6.
LESENSE channel 7.
LESENSE channel 8.
LESENSE channel 9.
LES_CH2
LES_CH3
LES_CH4
LES_CH5
LES_CH6
LES_CH7
LES_CH8
LES_CH9
LES_CH10
LES_CH11
LES_CH12
LES_CH13
LES_CH14
LES_CH15
LETIM0_OUT0
LETIM0_OUT1
LEU0_RX
LESENSE channel 10.
LESENSE channel 11.
LESENSE channel 12.
LESENSE channel 13.
LESENSE channel 14.
LESENSE channel 15.
PB11
PB12
PB14
PF0
PC4
PC5
PF1
Low Energy Timer LETIM0, output channel 0.
Low Energy Timer LETIM0, output channel 1.
LEUART0 Receive input.
PF1
PE15
PA0
LEUART0 Transmit output. Also used as receive input in
half duplex communication.
LEU0_TX
LEU1_RX
LEU1_TX
PD4
PC7
PC6
PB13
PA6
PA5
PE14
PF0
PF2
LEUART1 Receive input.
LEUART1 Transmit output. Also used as receive input in
half duplex communication.
Low Frequency Crystal (typically 32.768 kHz) negative
pin. Also used as an optional external clock input pin.
LFXTAL_N
PB8
LFXTAL_P
PCNT0_S0IN
PCNT0_S1IN
PCNT1_S0IN
PCNT1_S1IN
PCNT2_S0IN
PCNT2_S1IN
PRS_CH0
PB7
PC13
PC14
PC4
PC5
PD0
PD1
PA0
PA1
PC0
PC1
PA0
PA1
PA2
PA3
PA4
PA5
PC13
Low Frequency Crystal (typically 32.768 kHz) positive pin.
Pulse Counter PCNT0 input number 0.
PE0
PE1
PB3
PB4
PE8
PE9
PF3
PC0
PC1
PD6
PD7
Pulse Counter PCNT0 input number 1.
Pulse Counter PCNT1 input number 0.
Pulse Counter PCNT1 input number 1.
Pulse Counter PCNT2 input number 0.
Pulse Counter PCNT2 input number 1.
Peripheral Reflex System PRS, channel 0.
Peripheral Reflex System PRS, channel 1.
Peripheral Reflex System PRS, channel 2.
Peripheral Reflex System PRS, channel 3.
Timer 0 Capture Compare input / output channel 0.
Timer 0 Capture Compare input / output channel 1.
Timer 0 Capture Compare input / output channel 2.
Timer 0 Complimentary Deat Time Insertion channel 0.
Timer 0 Complimentary Deat Time Insertion channel 1.
Timer 0 Complimentary Deat Time Insertion channel 2.
Timer 1 Capture Compare input / output channel 0.
PRS_CH1
PF4
PRS_CH2
PF5
PRS_CH3
PE8
PA0
PA1
PA2
PC13
PC14
PC15
PE10
TIM0_CC0
PF6
PF7
PF8
PF3
PF4
PF5
PB0
PD1
PA0
PC0
PC1
PC2
PC3
PC4
PD6
PF0
PF1
PF2
PF3
PF4
PF5
TIM0_CC1
PD2
TIM0_CC2
PD3
TIM0_CDTI0
TIM0_CDTI1
TIM0_CDTI2
TIM1_CC0
PC13
PC14
PC15
PB7
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Alternate
LOCATION
Functionality
TIM1_CC1
TIM1_CC2
TIM2_CC0
TIM2_CC1
TIM2_CC2
TIM3_CC0
TIM3_CC1
TIM3_CC2
U0_RX
0
1
PE11
PE12
PA12
PA13
PA14
PE0
2
PB1
PB2
PC8
PC9
PC10
3
PB8
PB11
4
5
6
Description
PC14
PC15
PA8
PD7
Timer 1 Capture Compare input / output channel 1.
Timer 1 Capture Compare input / output channel 2.
Timer 2 Capture Compare input / output channel 0.
Timer 2 Capture Compare input / output channel 1.
Timer 2 Capture Compare input / output channel 2.
Timer 3 Capture Compare input / output channel 0.
Timer 3 Capture Compare input / output channel 1.
Timer 3 Capture Compare input / output channel 2.
UART0 Receive input.
PC13
PA9
PA10
PE14
PE15
PA15
PF7
PE1
PE2
PE1
PA4
PA3
PB10
PB9
PC15
PC14
PE3
UART0 Transmit output. Also used as receive input in half
duplex communication.
U0_TX
U1_RX
U1_TX
PF6
PE0
PC13
PC12
PF11
PF10
UART1 Receive input.
UART1 Transmit output. Also used as receive input in half
duplex communication.
PE2
US0_CLK
US0_CS
PE12
PE13
PE5
PE4
PC9
PC8
PC15
PC14
PB13
PB14
PB13
PB14
USART0 clock input / output.
USART0 chip select input / output.
USART0 Asynchronous Receive.
US0_RX
US0_TX
PE11
PE10
PE6
PE7
PC10
PC11
PE12
PE13
PB8
PB7
PC1
PC0
USART0 Synchronous mode Master Input / Slave Output
(MISO).
USART0 Asynchronous Transmit.Also used as receive in-
put in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input
(MOSI).
US1_CLK
US1_CS
PB7
PB8
PD2
PD3
PF0
PF1
USART1 clock input / output.
USART1 chip select input / output.
USART1 Asynchronous Receive.
US1_RX
US1_TX
PC1
PC0
PD1
PD0
PD6
PD7
USART1 Synchronous mode Master Input / Slave Output
(MISO).
USART1 Asynchronous Transmit.Also used as receive in-
put in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input
(MOSI).
US2_CLK
US2_CS
PC4
PC5
PB5
PB6
USART2 clock input / output.
USART2 chip select input / output.
USART2 Asynchronous Receive.
US2_RX
US2_TX
PC3
PC2
PB4
PB3
USART2 Synchronous mode Master Input / Slave Output
(MISO).
USART2 Asynchronous Transmit.Also used as receive in-
put in half duplex communication.
USART2 Synchronous mode Master Output / Slave Input
(MOSI).
USB_DM
PF10
PD2
USB D- pin.
USB_DMPU
USB_DP
USB D- Pullup control.
USB D+ pin.
PF11
PF12
USB_ID
USB ID pin. Used in OTG mode.
USB 5 V VBUS input.
USB 5 V VBUS enable.
USB_VBUS
USB_VBUSEN
USB_VBUS
PF5
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Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
USB_VREGI
USB_VREGI
USB Input to internal 3.3 V regulator
USB Decoupling for internal 3.3 V USB regulator and reg-
ulator output
USB_VREGO
USB_VREGO
3.3 GPIO Pinout Overview
The specific GPIO pins available in EFM32GG900 is shown in Table 3.3 (p. 17). Each GPIO port is
organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated
by a number from 15 down to 0.
Table 3.3. GPIO Pinout
Port
Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin
Pin
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Port A
Port B
Port C
Port D
Port E
Port F
PA15 PA14 PA13 PA12 PA11 PA10
PB15 PB14 PB13 PB12 PB11 PB10
PC15 PC14 PC13 PC12 PC11 PC10
PD15 PD14 PD13 PD12 PD11 PD10
PE15 PE14 PE13 PE12 PE11 PE10
PA9
PB9
PC9
PD9
PE9
PF9
PA8
PB8
PC8
PD8
PE8
PF8
PA7
PB7
PC7
PD7
PE7
PF7
PA6
PB6
PC6
PD6
PE6
PF6
PA5
PB5
PC5
PD5
PE5
PF5
PA4
PB4
PC4
PD4
PE4
PF4
PA3
PB3
PC3
PD3
PE3
PF3
PA2
PB2
PC2
PD2
PE2
PF2
PA1
PB1
PC1
PD1
PE1
PF1
PA0
PB0
PC0
PD0
PE0
PF0
-
-
-
PF12
PF11
PF10
3.4 Bonding Instructions
All pads should be bonded out, with the exception of the pads labeled “NC” and listed as “Do not connect”
in Table 3.1 (p. 5) . Gold bond wires are recommended for these devices.
All three voltage regulator output decouple pads (DEC_0, DEC_1, DEC_2) must be bonded out and
electrically connected on the PCB. In the packaged devices, these three pads are all bonded to a single
DECOUPLE pin.
If the USB feature of EFM32GG900 will be used, all of the USB pads must be bonded out, and
• both USB_VREGO_0 and USB_VREGO_1 must be bonded out and electrically connected on the
PCB. In the packaged devices, these two pads are both bonded to a single USB_VREGO pin.
• both USB_VREGI_0 and USB_VREGI_1 must be bonded out and electrically connected on the PCB.
In the packaged devices, these two pads are both bonded to a single USB_VREGI pin.
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3.5 Wafer Description
Table 3.4. Wafer and Die Information
Parameter
Value
EFM32GG (Giant Gecko)
8 in
Device Family
Wafer Diameter
Die Dimensions (Outer edge of seal ring)
Wafer Thickness (No backgrind)
6180 µm × 5230 µm
725 µm ±15 µm
(28.54 mil ±1 mil)
Wafer Identification
Notch
Scribe Street Width
80 µm × 160 µm
Die Per Wafer 1
Contact sales for information
Passivation
Standard
Wafer Packaging Detail
Bond Pad Dimensions
Bond Pad Pitch Minimum
Maximum Processing Temperature
Electronic Die Map Format
Wafer Jar
65 µm (parallel to die edge) × 66 µm
78 µm
250°C
.txt
1Note: This is the Expected Known Good Die yielded per wafer and represents the batch order quantity (one wafer).
3.5.1 Environmental
Bare silicon die are susceptible to mechanical damage and may be sensitive to light. When bare die
must be used in an environment exposed to light, it may be necessary to cover the top and sides with
an opaque material.
For additional Quality and Environmental information, please see:
http://www.silabs.com/support/quality/pages/default.aspx.
3.6 Wafer Storage Guidelines
It is necessary to conform to appropriate wafer storage practices to avoid product degradation or con-
tamination.
• Wafers may be stored for up to 18 months in the original packaging supplied by Silicon Labs.
• Wafers must be stored at a temperature of 18 - 24 °C.
• Wafers must be stored in a humidity-controlled environment with a relative humidity of <30%
• Wafers should be stored in a clean, dry, inert atmosphere (e.g. nitrogen or clean, dry air).
3.7 Failure Analysis (FA) Guidelines
Certain conditions must be met for Silicon Laboratories to perform Failure Analysis on devices sold in
wafer form.
• In order to conduct failure analysis on a device in a customer-provided package, Silicon Laboratories
must be provided with die assembled in an industry standard package that is pin compatible with
existing packages Silicon Laboratories offers for the device. Initial response time for FA requests that
meet these requirements will follow the standard FA guidelines for packaged parts.
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• If retest of the entire wafer is requested, Silicon Laboratories must be provided with the whole wafer.
Silicon Laboratories cannot retest any wafers that have been sawed, diced, backgrind or are on tape.
Initial response time for FA requests that meet these requirements will be 3 weeks.
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4 Chip Marking, Revision and Errata
4.1 Errata
Please see the errata document for EFM32GG900 for description and resolution of device erratas. This
document is available in Simplicity Studio and online at:
http://www.silabs.com/support/pages/document-library.aspx?p=MCUs--32-bit
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5 Revision History
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A Disclaimer and Trademarks
A.1 Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation
of all peripherals and modules available for system and software implementers using or intending to use
the Silicon Laboratories products. Characterization data, available modules and peripherals, memory
sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and
do vary in different applications. Application examples described herein are for illustrative purposes only.
Silicon Laboratories reserves the right to make changes without further notice and limitation to product
information, specifications, and descriptions herein, and does not give warranties as to the accuracy
or completeness of the included information. Silicon Laboratories shall have no liability for the conse-
quences of use of the information supplied herein. This document does not imply or express copyright
licenses granted hereunder to design or fabricate any integrated circuits. The products must not be
used within any Life Support System without the specific written consent of Silicon Laboratories. A "Life
Support System" is any product or system intended to support or sustain life and/or health, which, if it
fails, can be reasonably expected to result in significant personal injury or death. Silicon Laboratories
products are generally not intended for military applications. Silicon Laboratories products shall under no
circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological
or chemical weapons, or missiles capable of delivering such weapons.
A.2 Trademark Information
Silicon Laboratories Inc., Silicon Laboratories, Silicon Labs, SiLabs and the Silicon Labs logo, CMEMS®,
EFM, EFM32, EFR, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most ener-
gy friendly microcontrollers", Ember®, EZLink®, EZMac®, EZRadio®, EZRadioPRO®, DSPLL®, ISO-
modem®, Precision32®, ProSLIC®, SiPHY®, USBXpress® and others are trademarks or registered
trademarks of Silicon Laboratories Inc. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or reg-
istered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited. All other products
or brand names mentioned herein are trademarks of their respective holders.
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B Contact Information
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Please visit the Silicon Labs Technical Support web page:
http://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
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Table of Contents
1. Ordering Information .................................................................................................................................. 2
2. System Summary ...................................................................................................................................... 3
3. Pinout and Package .................................................................................................................................. 4
3.1. Padout .......................................................................................................................................... 4
3.2. Alternate Functionality Pinout ............................................................................................................ 9
3.3. GPIO Pinout Overview ................................................................................................................... 17
3.4. Bonding Instructions ...................................................................................................................... 17
3.5. Wafer Description .......................................................................................................................... 18
3.6. Wafer Storage Guidelines ............................................................................................................... 18
3.7. Failure Analysis (FA) Guidelines ...................................................................................................... 18
4. Chip Marking, Revision and Errata .............................................................................................................. 20
4.1. Errata ......................................................................................................................................... 20
5. Revision History ...................................................................................................................................... 21
A. Disclaimer and Trademarks ....................................................................................................................... 22
A.1. Disclaimer ................................................................................................................................... 22
A.2. Trademark Information ................................................................................................................... 22
B. Contact Information ................................................................................................................................. 23
B.1. ................................................................................................................................................. 23
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List of Figures
3.1. EFM32GG900 Padout (top view, not to scale) .............................................................................................. 4
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List of Tables
1.1. Ordering Information ................................................................................................................................ 2
3.1. Device Padout ....................................................................................................................................... 5
3.2. Alternate functionality overview .................................................................................................................. 9
3.3. GPIO Pinout ........................................................................................................................................ 17
3.4. Wafer and Die Information ...................................................................................................................... 18
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Simplicity Studio
One-click access to MCU and
wireless tools, documentation,
software, source code libraries &
more. Available for Windows,
Mac and Linux!
IoT Portfolio
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www.silabs.com/simplicity
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www.silabs.com/quality
Support and Community
community.silabs.com
Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using
or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and
"Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories reserves the right to
make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the
included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses
granted hereunder to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any Life Support System without the specific written consent
of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant
personal injury or death. Silicon Laboratories products are not designed or authorized for military applications. Silicon Laboratories products shall under no circumstances be used in
weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.
Trademark Information
Silicon Laboratories Inc.® , Silicon Laboratories®, Silicon Labs®, SiLabs® and the Silicon Labs logo®, Bluegiga®, Bluegiga Logo®, Clockbuilder®, CMEMS®, DSPLL®, EFM®, EFM32®,
EFR, Ember®, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZRadio®, EZRadioPRO®, Gecko®,
ISOmodem®, Precision32®, ProSLIC®, Simplicity Studio®, SiPHY®, Telegesis, the Telegesis Logo®, USBXpress® and others are trademarks or registered trademarks of Silicon Laborato-
ries Inc. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited. All other products or brand
names mentioned herein are trademarks of their respective holders.
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
USA
http://www.silabs.com
相关型号：
EFM32GG900F512G-D-D1I
This change is considered a minor change which does not affect form, fit, function, quality, or reliability.
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