EFM32HG321F32G-A-QFP48 [SILICON]
Output state retention and wake-up from Shutoff Mode;
| 型号： | EFM32HG321F32G-A-QFP48 |
| 厂家： | 
SILICON |
| 描述： | Output state retention and wake-up from Shutoff Mode |
| 文件： | 总70页 (文件大小：1850K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EFM32HG321 DATASHEET
F64/F32
Preliminary
• ARM Cortex-M0+ CPU platform
• High Performance 32-bit processor @ up to 25 MHz
• Wake-up Interrupt Controller
• Communication interfaces
• 2× Universal Synchronous/Asynchronous Receiv-
er/Transmitter
• UART/SPI/SmartCard (ISO 7816)/IrDA/I2S
• Triple buffered full/half-duplex operation
• Low Energy UART
• Flexible Energy Management System
• 20 nA @ 3 V Shutoff Mode
• 0.6 µA @ 3 V Stop Mode, including Power-on Reset, Brown-out
Detector, RAM and CPU retention
• 0.9 µA @ 3 V Deep Sleep Mode, including RTC with 32.768 kHz
oscillator, Power-on Reset, Brown-out Detector, RAM and CPU
retention
• 53 µA/MHz @ 3 V Sleep Mode
• 132 µA/MHz @ 3 V Run Mode, with code executed from flash
• 64/32 KB Flash
• Autonomous operation with DMA in Deep Sleep
Mode
• I2C Interface with SMBus support
• Address recognition in Stop Mode
• Low Energy Universal Serial Bus (USB) Device
• Fully USB 2.0 compliant
• On-chip PHY and embedded 5V to 3.3V regulator
• Crystal-free operation
• 8/8 KB RAM
• 35 General Purpose I/O pins
• Configurable push-pull, open-drain, pull-up/down, input filter, drive
strength
• Configurable peripheral I/O locations
• 16 asynchronous external interrupts
• Output state retention and wake-up from Shutoff Mode
• 6 Channel DMA Controller
• Ultra low power precision analog peripherals
• 12-bit 1 Msamples/s Analog to Digital Converter
• 4 single ended channels/2 differential channels
• On-chip temperature sensor
• Current Digital to Analog Converter
• Selectable current range between 0.05 and 64 uA
• 1× Analog Comparator
• 6 Channel Peripheral Reflex System (PRS) for autonomous in-
ter-peripheral signaling
• Timers/Counters
• Capacitive sensing with up to 5 inputs
• Supply Voltage Comparator
• Ultra efficient Power-on Reset and Brown-Out Detec-
tor
• 3× 16-bit Timer/Counter
• 3×3 Compare/Capture/PWM channels
• Dead-Time Insertion on TIMER0
• 1× 24-bit Real-Time Counter
• Debug Interface
• 2-pin Serial Wire Debug interface
• Micro Trace Buffer (MTB)
• 1× 16-bit Pulse Counter
• Watchdog Timer with dedicated RC oscillator @ 50 nA
• Pre-Programmed USB/UART Bootloader
• Temperature range -40 to 85 ºC
• Single power supply 1.98 to 3.8 V
• TQFP48 package
• Preliminary - This datasheet revision applies to a product
under development
32-bit ARM Cortex-M0+, Cortex-M3 and Cortex-M4 microcontrollers for:
• Energy, gas, water and smart metering
• Health and fitness applications
• Smart accessories
• Alarm and security systems
• Industrial and home automation
Preliminary
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1 Ordering Information
Table 1.1 (p. 2) shows the available EFM32HG321 devices.
Table 1.1. Ordering Information
Ordering Code
Flash (kB) RAM (kB)
Max
Speed
(MHz)
Supply
Voltage
(V)
Temperature
(ºC)
Package
EFM32HG321F32G-A-QFP48
EFM32HG321F64G-A-QFP48
32
64
8
8
25
25
1.98 - 3.8
1.98 - 3.8
-40 - 85
-40 - 85
TQFP48
TQFP48
Adding the suffix 'R' to the part number (e.g. EFM32HG321F32G-A-QFP48R) denotes tape and reel.
Visit www.silabs.com for information on global distributors and representatives.
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2 System Summary
2.1 System Introduction
The EFM32 MCUs are the world’s most energy friendly microcontrollers. With a unique combination
of the powerful 32-bit ARM Cortex-M0+, innovative low energy techniques, short wake-up time from
energy saving modes, and a wide selection of peripherals, the EFM32HG microcontroller is well suited
for any battery operated application as well as other systems requiring high performance and low-energy
consumption. This section gives a short introduction to each of the modules in general terms and also
shows a summary of the configuration for the EFM32HG321 devices. For a complete feature set and
in-depth information on the modules, the reader is referred to the EFM32HG Reference Manual.
A block diagram of the EFM32HG321 is shown in Figure 2.1 (p. 3) .
Figure 2.1. Block Diagram
HG321F64/ F32
Energy Management
Core and Memory
Clock Management
High Freq
RC
48/ 24 MHz
Comm. RC
Oscillator
Voltage
Voltage
Oscillator
Regulator
Comparator
ARM Cortex™M0+ processor
Aux High
Freq RC
High Freq
Crystal
Power- on
Reset
Oscillator
Oscillator
Brown- out
Detector
Low Freq
RC
Low Freq
Crystal
Flash
Program
Memory
Debug
Interface
w/ MTB
Oscillator
Oscillator
RAM
Memory
DMA
Controller
Ultra Low Freq
RC
Oscillator
32- bit bus
Peripheral Reflex System
Serial Interfaces
I/ O Ports
Timers and Triggers
Analog Interfaces
Security
General
External
Analog
Comparator
USART
I2C
Purpose
ADC
Timer/
Counter
Real Time
Counter
Interrupts
I/ O
Low
Energy
USB
Low
Energy
UART™
Pin
Pin
Pulse
Counter
Watchdog
Timer
Current
DAC
Reset
Wakeup
2.1.1 ARM Cortex-M0+ Core
The ARM Cortex-M0+ includes a 32-bit RISC processor which can achieve as much as 0.9 Dhrystone
MIPS/MHz. A Wake-up Interrupt Controller handling interrupts triggered while the CPU is asleep is in-
cluded as well. The EFM32 implementation of the Cortex-M0+ is described in detail in ARM Cortex-M0+
Devices Generic User Guide.
2.1.2 Debug Interface (DBG)
This device includes hardware debug support through a 2-pin serial-wire debug interface and a Micro
Trace Buffer (MTB) for data/instruction tracing.
2.1.3 Memory System Controller (MSC)
The Memory System Controller (MSC) is the program memory unit of the EFM32HG microcontroller.
The flash memory is readable and writable from both the Cortex-M0+ and DMA. The flash memory is
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divided into two blocks; the main block and the information block. Program code is normally written to
the main block. Additionally, the information block is available for special user data and flash lock bits.
There is also a read-only page in the information block containing system and device calibration data.
Read and write operations are supported in the energy modes EM0 and EM1.
2.1.4 Direct Memory Access Controller (DMA)
The Direct Memory Access (DMA) controller performs memory operations independently of the CPU.
This has the benefit of reducing the energy consumption and the workload of the CPU, and enables
the system to stay in low energy modes when moving for instance data from the USART to RAM or
from the External Bus Interface to a PWM-generating timer. The DMA controller uses the PL230 µDMA
controller licensed from ARM.
2.1.5 Reset Management Unit (RMU)
The RMU is responsible for handling the reset functionality of the EFM32HG.
2.1.6 Energy Management Unit (EMU)
The Energy Management Unit (EMU) manage all the low energy modes (EM) in EFM32HG microcon-
trollers. Each energy mode manages if the CPU and the various peripherals are available. The EMU
can also be used to turn off the power to unused SRAM blocks.
2.1.7 Clock Management Unit (CMU)
The Clock Management Unit (CMU) is responsible for controlling the oscillators and clocks on-board the
EFM32HG. The CMU provides the capability to turn on and off the clock on an individual basis to all
peripheral modules in addition to enable/disable and configure the available oscillators. The high degree
of flexibility enables software to minimize energy consumption in any specific application by not wasting
power on peripherals and oscillators that are inactive.
2.1.8 Watchdog (WDOG)
The purpose of the watchdog timer is to generate a reset in case of a system failure, to increase appli-
cation reliability. The failure may e.g. be caused by an external event, such as an ESD pulse, or by a
software failure.
2.1.9 Peripheral Reflex System (PRS)
The Peripheral Reflex System (PRS) system is a network which lets the different peripheral module
communicate directly with each other without involving the CPU. Peripheral modules which send out
Reflex signals are called producers. The PRS routes these reflex signals to consumer peripherals which
apply actions depending on the data received. The format for the Reflex signals is not given, but edge
triggers and other functionality can be applied by the PRS.
2.1.10 Low Energy USB
The unique Low Energy USB peripheral provides a full-speed USB 2.0 compliant device controller and
PHY with ultra-low current consumption. The device supports both full-speed (12MBit/s) and low speed
(1.5MBit/s) operation, and includes a dedicated USB oscillator with clock recovery mechanism for crys-
tal-free operation. No external components are required. The Low Energy Mode ensures the current
consumption is optimized and enables USB communication on a strict power budget. The USB device
includes an internal dedicated descriptor-based Scatter/Gather DMA and supports up to 3 OUT end-
points and 3 IN endpoints, in addition to endpoint 0. The on-chip PHY includes software controllable
pull-up and pull-down resistors.
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2.1.11 Inter-Integrated Circuit Interface (I2C)
The I2C module provides an interface between the MCU and a serial I2C-bus. It is capable of acting as
both a master and a slave, and supports multi-master buses. Both standard-mode, fast-mode and fast-
mode plus speeds are supported, allowing transmission rates all the way from 10 kbit/s up to 1 Mbit/s.
Slave arbitration and timeouts are also provided to allow implementation of an SMBus compliant system.
The interface provided to software by the I2C module, allows both fine-grained control of the transmission
process and close to automatic transfers. Automatic recognition of slave addresses is provided in all
energy modes.
2.1.12 Universal Synchronous/Asynchronous Receiver/Transmitter (US-
ART)
The Universal Synchronous Asynchronous serial Receiver and Transmitter (USART) is a very flexible
serial I/O module. It supports full duplex asynchronous UART communication as well as RS-485, SPI,
MicroWire and 3-wire. It can also interface with ISO7816 SmartCards, IrDA and I2S devices.
2.1.13 Pre-Programmed USB/UART Bootloader
The bootloader presented in application note AN0042 is pre-programmed in the device at factory. The
bootloader enables users to program the EFM32 through a UART or a USB CDC class virtual UART
without the need for a debugger. The autobaud feature, interface and commands are described further
in the application note.
2.1.14 Low Energy Universal Asynchronous Receiver/Transmitter
(LEUART)
The unique LEUARTTM, the Low Energy UART, is a UART that allows two-way UART communication on
a strict power budget. Only a 32.768 kHz clock is needed to allow UART communication up to 9600 baud/
s. The LEUART includes all necessary hardware support to make asynchronous serial communication
possible with minimum of software intervention and energy consumption.
2.1.15 Timer/Counter (TIMER)
The 16-bit general purpose Timer has 3 compare/capture channels for input capture and compare/Pulse-
Width Modulation (PWM) output. TIMER0 also includes a Dead-Time Insertion module suitable for motor
control applications.
2.1.16 Real Time Counter (RTC)
The Real Time Counter (RTC) contains a 24-bit counter and is clocked either by a 32.768 kHz crystal
oscillator, or a 32.768 kHz RC oscillator. In addition to energy modes EM0 and EM1, the RTC is also
available in EM2. This makes it ideal for keeping track of time since the RTC is enabled in EM2 where
most of the device is powered down.
2.1.17 Pulse Counter (PCNT)
The Pulse Counter (PCNT) can be used for counting pulses on a single input or to decode quadrature
encoded inputs. It runs off either the internal LFACLK or the PCNTn_S0IN pin as external clock source.
The module may operate in energy mode EM0 - EM3.
2.1.18 Analog Comparator (ACMP)
The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indi-
cating which input voltage is higher. Inputs can either be one of the selectable internal references or from
external pins. Response time and thereby also the current consumption can be configured by altering
the current supply to the comparator.
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2.1.19 Voltage Comparator (VCMP)
The Voltage Supply Comparator is used to monitor the supply voltage from software. An interrupt can
be generated when the supply falls below or rises above a programmable threshold. Response time and
thereby also the current consumption can be configured by altering the current supply to the comparator.
2.1.20 Analog to Digital Converter (ADC)
The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits
at up to one million samples per second. The integrated input mux can select inputs from 4 external
pins and 6 internal signals.
2.1.21 Current Digital to Analog Converter (IDAC)
The current digital to analog converter can source or sink a configurable constant current, which can
be output on, or sinked from pin or ADC. The current is configurable with several ranges of various
step sizes.
2.1.22 General Purpose Input/Output (GPIO)
In the EFM32HG321, there are 35 General Purpose Input/Output (GPIO) pins, which are divided into
ports with up to 16 pins each. These pins can individually be configured as either an output or input. More
advanced configurations like open-drain, filtering and drive strength can also be configured individually
for the pins. The GPIO pins can also be overridden by peripheral pin connections, like Timer PWM
outputs or USART communication, which can be routed to several locations on the device. The GPIO
supports up to 16 asynchronous external pin interrupts, which enables interrupts from any pin on the
device. Also, the input value of a pin can be routed through the Peripheral Reflex System to other
peripherals.
2.2 Configuration Summary
The features of the EFM32HG321 is a subset of the feature set described in the EFM32HG Reference
Manual. Table 2.1 (p. 6) describes device specific implementation of the features.
Table 2.1. Configuration Summary
Module
Cortex-M0+
DBG
Configuration
Pin Connections
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
NA
DBG_SWCLK, DBG_SWDIO,
MSC
NA
DMA
NA
RMU
NA
EMU
NA
CMU
CMU_OUT0, CMU_OUT1
WDOG
PRS
NA
NA
USB
USB_VREGI, USB_VREGO, USB_DM,
USB_DMPU, USB_DP
I2C0
Full configuration
I2C0_SDA, I2C0_SCL
USART0
USART1
Full configuration with IrDA and I2S
Full configuration with I2S and IrDA
US0_TX, US0_RX. US0_CLK, US0_CS
US1_TX, US1_RX, US1_CLK, US1_CS
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Module
LEUART0
TIMER0
TIMER1
TIMER2
RTC
Configuration
Pin Connections
Full configuration
LEU0_TX, LEU0_RX
TIM0_CC[2:0], TIM0_CDTI[2:0]
TIM1_CC[2:0]
Full configuration with DTI
Full configuration
Full configuration
TIM2_CC[2:0]
Full configuration
NA
PCNT0
ACMP0
VCMP
Full configuration, 16-bit count register PCNT0_S[1:0]
Full configuration
Full configuration
Full configuration
Full configuration
35 pins
ACMP0_CH[4:0], ACMP0_O
NA
ADC0
ADC0_CH[7:4]
IDAC0_OUT
IDAC0
GPIO
Available pins are shown in
Table 4.3 (p. 57)
2.3 Memory Map
The EFM32HG321 memory map is shown in Figure 2.2 (p. 7), with RAM and Flash sizes for the
largest memory configuration.
Figure 2.2. EFM32HG321 Memory Map with largest RAM and Flash sizes
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3 Electrical Characteristics
3.1 Test Conditions
3.1.1 Typical Values
The typical data are based on TAMB=25°C and VDD=3.0 V, as defined in Table 3.2 (p. 8), by simu-
lation and/or technology characterisation unless otherwise specified.
3.1.2 Minimum and Maximum Values
The minimum and maximum values represent the worst conditions of ambient temperature, supply volt-
age and frequencies, as defined in Table 3.2 (p. 8), by simulation and/or technology characterisa-
tion unless otherwise specified.
3.2 Absolute Maximum Ratings
The absolute maximum ratings are stress ratings, and functional operation under such conditions are
not guaranteed. Stress beyond the limits specified in Table 3.1 (p. 8) may affect the device reliability
or cause permanent damage to the device. Functional operating conditions are given in Table 3.2 (p.
8) .
Table 3.1. Absolute Maximum Ratings
Symbol
Parameter
Condition
Min
Typ
Max
Unit
1501 °C
TSTG
Storage tempera-
ture range
-40
TS
Maximum soldering Latest IPC/JEDEC J-STD-020
260 °C
temperature
Standard
VDDMAX
External main sup-
ply voltage
0
3.8
V
V
VIOPIN
Voltage on any I/O
pin
-0.3
VDD+0.3
1Based on programmed devices tested for 10000 hours at 150ºC. Storage temperature affects retention of preprogrammed cal-
ibration values stored in flash. Please refer to the Flash section in the Electrical Characteristics for information on flash data re-
tention for different temperatures.
3.3 General Operating Conditions
3.3.1 General Operating Conditions
Table 3.2. General Operating Conditions
Symbol
TAMB
VDDOP
fAPB
Parameter
Min
Typ
Max
Unit
85 °C
3.8
Ambient temperature range
Operating supply voltage
Internal APB clock frequency
Internal AHB clock frequency
-40
1.98
V
25 MHz
25 MHz
fAHB
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3.4 Current Consumption
Table 3.3. Current Consumption
Symbol
Parameter
Condition
Min
Typ
Max
Unit
24 MHz HFXO, all peripheral
clocks disabled, VDD= 3.0 V,
TAMB=25°C
148
153
132
134
134
137
136
139
142
146
184
194
64
158 µA/
MHz
24 MHz HFXO, all peripheral
clocks disabled, VDD= 3.0 V,
TAMB=85°C
163 µA/
MHz
21 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=25°C
140 µA/
MHz
21 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=85°C
143 µA/
MHz
14 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=25°C
143 µA/
MHz
14 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=85°C
145 µA/
MHz
EM0 current. No
prescaling. Running
prime number cal-
culation code from
Flash.
IEM0
11 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=25°C
144 µA/
MHz
11 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=85°C
148 µA/
MHz
6.6 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=25°C
150 µA/
MHz
6.6 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=85°C
154 µA/
MHz
1.2 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=25°C
196 µA/
MHz
1.2 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=85°C
208 µA/
MHz
24 MHz HFXO, all peripheral
clocks disabled, VDD= 3.0 V,
TAMB=25°C
68 µA/
MHz
24 MHz HFXO, all peripheral
clocks disabled, VDD= 3.0 V,
TAMB=85°C
67
71 µA/
MHz
IEM1
EM1 current
21 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=25°C
53
57 µA/
MHz
21 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=85°C
54
58 µA/
MHz
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Symbol
Parameter
Condition
Min
Typ
Max
Unit
14 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=25°C
56
57
59 µA/
MHz
14 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=85°C
61 µA/
MHz
11 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=25°C
58
61 µA/
MHz
11 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=85°C
59
63 µA/
MHz
6.6 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=25°C
64
68 µA/
MHz
6.6 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=85°C
67
71 µA/
MHz
1.2 MHz HFRCO. all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=25°C
106
114
0.9
114 µA/
MHz
1.2 MHz HFRCO. all peripher-
al clocks disabled, VDD= 3.0 V,
TAMB=85°C
126 µA/
MHz
EM2 current with RTC
prescaled to 1 Hz, 32.768
kHz LFRCO, VDD= 3.0 V,
TAMB=25°C
1.35 µA
IEM2
EM2 current
EM2 current with RTC
prescaled to 1 Hz, 32.768
kHz LFRCO, VDD= 3.0 V,
TAMB=85°C
1.6
3.50 µA
EM3 current (ULFRCO en-
abled, LFRCO/LFXO disabled),
VDD= 3.0 V, TAMB=25°C
0.6
1.2
0.90 µA
2.65 µA
IEM3
EM3 current
EM4 current
EM3 current (ULFRCO en-
abled, LFRCO/LFXO disabled),
VDD= 3.0 V, TAMB=85°C
VDD= 3.0 V, TAMB=25°C
VDD= 3.0 V, TAMB=85°C
0.02
0.18
0.035 µA
0.480 µA
IEM4
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3.4.1 EM0 Current Consumption
Figure 3.1. EM0 Current consumption while executing prime number calculation code from flash
with HFRCO running at 24 MHz
2.84
2.82
2.80
2.78
2.76
2.74
2.72
2.70
2.68
2.84
2.82
2.80
2.78
2.76
2.74
2.72
2.70
2.68
- 40.0°C
- 15.0°C
5.0°C
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
25.0°C
45.0°C
65.0°C
85.0°C
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
Figure 3.2. EM0 Current consumption while executing prime number calculation code from flash
with HFRCO running at 21 MHz
2.45
2.40
2.35
2.30
2.45
2.40
2.35
2.30
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
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Figure 3.3. EM0 Current consumption while executing prime number calculation code from flash
with HFRCO running at 14 MHz
1.68
1.66
1.64
1.62
1.60
1.58
1.56
1.54
1.68
1.66
1.64
1.62
1.60
1.58
1.56
1.54
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
Figure 3.4. EM0 Current consumption while executing prime number calculation code from flash
with HFRCO running at 11 MHz
1.34
1.32
1.30
1.28
1.26
1.24
1.22
1.34
1.32
1.30
1.28
1.26
1.24
1.22
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
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Figure 3.5. EM0 Current consumption while executing prime number calculation code from flash
with HFRCO running at 6.6 MHz
0.84
0.83
0.82
0.81
0.80
0.79
0.78
0.77
0.84
0.83
0.82
0.81
0.80
0.79
0.78
0.77
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
3.4.2 EM1 Current Consumption
Figure 3.6. EM1 Current consumption with all peripheral clocks disabled and HFRCO running
at 24 MHz
1.20
1.18
1.16
1.14
1.12
1.10
1.20
1.18
1.16
1.14
1.12
1.10
- 40.0°C
- 15.0°C
5.0°C
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
25.0°C
45.0°C
65.0°C
85.0°C
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
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Figure 3.7. EM1 Current consumption with all peripheral clocks disabled and HFRCO running
at 21 MHz
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.97
0.96
0.95
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.97
0.96
0.95
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
Figure 3.8. EM1 Current consumption with all peripheral clocks disabled and HFRCO running
at 14 MHz
0.73
0.72
0.71
0.70
0.69
0.68
0.67
0.66
0.73
0.72
0.71
0.70
0.69
0.68
0.67
0.66
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
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Figure 3.9. EM1 Current consumption with all peripheral clocks disabled and HFRCO running
at 11 MHz
0.59
0.58
0.57
0.56
0.55
0.54
0.53
0.59
0.58
0.57
0.56
0.55
0.54
0.53
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
Figure 3.10. EM1 Current consumption with all peripheral clocks disabled and HFRCO running
at 6.6 MHz
0.395
0.390
0.385
0.380
0.375
0.370
0.365
0.360
0.355
0.350
0.395
0.390
0.385
0.380
0.375
0.370
0.365
0.360
0.355
0.350
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
- 40.0°C
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
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3.4.3 EM2 Current Consumption
Figure 3.11. EM2 current consumption. RTC prescaled to 1kHz, 32.768 kHz LFRCO.
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
- 40.0°C
- 15.0°C
5.0°C
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
25.0°C
45.0°C
65.0°C
85.0°C
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
3.4.4 EM3 Current Consumption
Figure 3.12. EM3 current consumption.
1.6
1.6
1.4
1.2
1.0
0.8
0.6
0.4
- 40.0°C
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
- 15.0°C
5.0°C
1.4
1.2
1.0
0.8
0.6
0.4
25.0°C
45.0°C
65.0°C
85.0°C
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
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3.4.5 EM4 Current Consumption
Figure 3.13. EM4 current consumption.
0.5
0.5
- 40.0°C
Vdd= 2.0V
- 15.0°C
Vdd= 2.2V
5.0°C
Vdd= 2.4V
0.4
0.4
25.0°C
45.0°C
65.0°C
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
0.3
0.3
85.0°C
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
0.2
0.1
0.2
0.1
Vdd= 3.8V
0.0
0.0
–0.1
–0.1
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
3.5 Transition between Energy Modes
The transition times are measured from the trigger to the first clock edge in the CPU.
Table 3.4. Energy Modes Transitions
Symbol
Parameter
Min
Typ
Max
Unit
tEM10
Transition time from EM1 to EM0
0
HF-
CORE-
CLK
cycles
tEM20
tEM30
tEM40
Transition time from EM2 to EM0
Transition time from EM3 to EM0
Transition time from EM4 to EM0
2
2
µs
µs
µs
163
3.6 Power Management
The EFM32HG requires the AVDD_x, VDD_DREG and IOVDD_x pins to be connected together (with
optional filter) at the PCB level. For practical schematic recommendations, please see the application
note, "AN0002 EFM32 Hardware Design Considerations".
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Table 3.5. Power Management
Symbol
Parameter
Condition
Min
Typ
Max
Unit
VBODextthr-
BOD threshold on
falling external sup-
ply voltage
1.74
1.96
V
VBODextthr+
BOD threshold on
rising external sup-
ply voltage
1.89
163
V
tRESET
Delay from reset
is released until
program execution
starts
Applies to Power-on Reset,
Brown-out Reset and pin reset.
µs
CDECOUPLE
CUSB_VREGO
CUSB_VREGI
Voltage regulator
decoupling capaci-
tor.
X5R capacitor recommended.
Apply between DECOUPLE pin
and GROUND
1
1
µF
µF
µF
USB voltage regu-
lator out decoupling Apply between USB_VREGO
capacitor. pin and GROUND
X5R capacitor recommended.
USB voltage regula- X5R capacitor recommended.
tor in decoupling ca- Apply between USB_VREGI
4.7
pacitor.
pin and GROUND
3.7 Flash
Table 3.6. Flash
Symbol
Parameter
Condition
Min
Typ
Max
Unit
ECFLASH
Flash erase cycles
before failure
20000
cycles
TAMB<150°C
10000
10
h
RETFLASH
Flash data retention TAMB<85°C
TAMB<70°C
years
years
µs
20
tW_PROG
Word (32-bit) pro-
gramming time
20
tP_ERASE
tD_ERASE
IERASE
Page erase time
Device erase time
Erase current
20
40
20.4
40.8
20.8 ms
41.6 ms
71 mA
IWRITE
Write current
71 mA
VFLASH
Supply voltage dur-
ing flash erase and
write
1.98
3.8
V
1Measured at 25°C
3.8 General Purpose Input Output
Table 3.7. GPIO
Symbol
VIOIL
Parameter
Condition
Min
Typ
Max
0.30VDD
Unit
V
Input low voltage
Input high voltage
VIOIH
0.70VDD
V
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Symbol
Parameter
Condition
Min
Typ
Max
Unit
Sourcing 0.1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= LOWEST
0.80VDD
0.90VDD
0.85VDD
0.90VDD
V
Sourcing 0.1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= LOWEST
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Sourcing 1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= LOW
Sourcing 1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= LOW
Output high volt-
age (Production test
condition = 3.0V,
DRIVEMODE =
STANDARD)
VIOOH
Sourcing 6 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= STANDARD
0.75VDD
Sourcing 6 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= STANDARD
0.85VDD
0.60VDD
0.80VDD
Sourcing 20 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= HIGH
Sourcing 20 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= HIGH
Sinking 0.1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= LOWEST
0.20VDD
0.10VDD
0.10VDD
0.05VDD
Sinking 0.1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= LOWEST
Sinking 1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= LOW
Sinking 1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= LOW
Output low voltage
(Production test
condition = 3.0V,
DRIVEMODE =
STANDARD)
VIOOL
Sinking 6 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= STANDARD
0.30VDD
Sinking 6 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= STANDARD
0.20VDD
0.35VDD
0.25VDD
Sinking 20 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= HIGH
Sinking 20 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= HIGH
IIOLEAK
Input leakage cur-
rent
High Impedance IO connected
to GROUND or Vdd
±0.1
40
±40 nA
RPU
I/O pin pull-up resis-
tor
kOhm
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Preliminary
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Symbol
Parameter
Condition
Min
Typ
Max
Unit
RPD
I/O pin pull-down re-
sistor
40
kOhm
RIOESD
Internal ESD series
resistor
200
Ohm
tIOGLITCH
Pulse width of puls-
es to be removed
by the glitch sup-
pression filter
10
50 ns
GPIO_Px_CTRL DRIVEMODE
= LOWEST and load capaci-
tance CL=12.5-25pF.
20+0.1CL
20+0.1CL
0.1VDD
250 ns
250 ns
V
tIOOF
Output fall time
GPIO_Px_CTRL DRIVEMODE
= LOW and load capacitance
CL=350-600pF
VIOHYST
I/O pin hysteresis
VDD = 1.98 - 3.8 V
(VIOTHR+ - VIOTHR-
)
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Preliminary
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Figure 3.14. Typical Low-Level Output Current, 2V Supply Voltage
0.20
0.15
0.10
0.05
0.00
5
4
3
2
1
- 40°C
25°C
85°C
- 40°C
25°C
85°C
0
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
Low- Level Output Voltage [V]
Low- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = LOWEST
GPIO_Px_CTRL DRIVEMODE = LOW
20
45
40
35
30
25
20
15
10
5
15
10
5
- 40°C
25°C
- 40°C
25°C
85°C
85°C
0
0.0
0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
Low- Level Output Voltage [V]
Low- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
GPIO_Px_CTRL DRIVEMODE = HIGH
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Preliminary
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Figure 3.15. Typical High-Level Output Current, 2V Supply Voltage
0.00
–0.05
–0.10
–0.15
–0.20
0.0
–0.5
–1.0
–1.5
–2.0
–2.5
- 40°C
25°C
85°C
- 40°C
25°C
85°C
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
High- Level Output Voltage [V]
High- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = LOWEST
GPIO_Px_CTRL DRIVEMODE = LOW
0
0
- 40°C
- 40°C
25°C
85°C
25°C
85°C
–10
–20
–30
–40
–50
–5
–10
–15
–20
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
High- Level Output Voltage [V]
High- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
GPIO_Px_CTRL DRIVEMODE = HIGH
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Figure 3.16. Typical Low-Level Output Current, 3V Supply Voltage
0.5
0.4
0.3
0.2
0.1
0.0
10
8
6
4
2
- 40°C
25°C
85°C
- 40°C
25°C
85°C
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Low- Level Output Voltage [V]
Low- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = LOWEST
GPIO_Px_CTRL DRIVEMODE = LOW
40
35
30
25
20
15
10
50
40
30
20
10
0
5
- 40°C
- 40°C
25°C
85°C
25°C
85°C
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Low- Level Output Voltage [V]
Low- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
GPIO_Px_CTRL DRIVEMODE = HIGH
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Preliminary
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Figure 3.17. Typical High-Level Output Current, 3V Supply Voltage
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
0
- 40°C
25°C
85°C
- 40°C
25°C
85°C
–1
–2
–3
–4
–5
–6
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
High- Level Output Voltage [V]
High- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = LOWEST
GPIO_Px_CTRL DRIVEMODE = LOW
0
0
- 40°C
- 40°C
25°C
85°C
25°C
85°C
–10
–20
–30
–40
–50
–10
–20
–30
–40
–50
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
High- Level Output Voltage [V]
High- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
GPIO_Px_CTRL DRIVEMODE = HIGH
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Preliminary
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Figure 3.18. Typical Low-Level Output Current, 3.8V Supply Voltage
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
14
12
10
8
6
4
2
- 40°C
25°C
85°C
- 40°C
25°C
85°C
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Low- Level Output Voltage [V]
Low- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = LOWEST
GPIO_Px_CTRL DRIVEMODE = LOW
50
40
30
20
10
50
40
30
20
10
0
- 40°C
25°C
- 40°C
25°C
85°C
85°C
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Low- Level Output Voltage [V]
Low- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
GPIO_Px_CTRL DRIVEMODE = HIGH
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Preliminary
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Figure 3.19. Typical High-Level Output Current, 3.8V Supply Voltage
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
0
- 40°C
25°C
85°C
- 40°C
25°C
85°C
–1
–2
–3
–4
–5
–6
–7
–8
–9
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
High- Level Output Voltage [V]
High- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = LOWEST
GPIO_Px_CTRL DRIVEMODE = LOW
0
0
- 40°C
- 40°C
25°C
85°C
25°C
85°C
–10
–20
–30
–40
–50
–10
–20
–30
–40
–50
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
High- Level Output Voltage [V]
High- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
GPIO_Px_CTRL DRIVEMODE = HIGH
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3.9 Oscillators
3.9.1 LFXO
Table 3.8. LFXO
Symbol
Parameter
Condition
Min
Typ
Max
Unit
fLFXO
Supported nominal
crystal frequency
32.768
30
kHz
ESRLFXO
Supported crystal
equivalent series re-
sistance (ESR)
120 kOhm
CLFXOL
Supported crystal
external load range
5
25 pF
nA
ILFXO
Current consump-
tion for core and
buffer after startup.
ESR=30 kOhm, CL=10 pF,
LFXOBOOST in CMU_CTRL is
1
190
tLFXO
Start- up time.
ESR=30 kOhm, CL=10 pF,
40% - 60% duty cycle has
been reached, LFXOBOOST in
CMU_CTRL is 1
1100
ms
For safe startup of a given crystal, the energyAware Designer in Simplicity Studio contains a tool to help
users configure both load capacitance and software settings for using the LFXO. For details regarding
the crystal configuration, the reader is referred to application note "AN0016 EFM32 Oscillator Design
Consideration".
3.9.2 HFXO
Table 3.9. HFXO
Symbol
Parameter
Condition
Min
Typ
Max
Unit
fHFXO
Supported nominal
crystal Frequency
4
25 MHz
Supported crystal
equivalent series re-
sistance (ESR)
Crystal frequency 25 MHz
Crystal frequency 4 MHz
30
100 Ohm
ESRHFXO
400
1500 Ohm
gmHFXO
The transconduc-
tance of the HFXO
input transistor at
crystal startup
HFXOBOOST in CMU_CTRL
equals 0b11
20
5
mS
CHFXOL
Supported crystal
external load range
25 pF
µA
4 MHz: ESR=400 Ohm,
CL=20 pF, HFXOBOOST in
CMU_CTRL equals 0b11
85
165
785
Current consump-
tion for HFXO after
startup
IHFXO
25 MHz: ESR=30 Ohm,
CL=10 pF, HFXOBOOST in
CMU_CTRL equals 0b11
µA
µs
tHFXO
Startup time
25 MHz: ESR=30 Ohm,
CL=10 pF, HFXOBOOST in
CMU_CTRL equals 0b11
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3.9.3 LFRCO
Table 3.10. LFRCO
Symbol
Parameter
Condition
Min
Typ
Max
Unit
fLFRCO
Oscillation frequen-
cy , VDD= 3.0 V,
TAMB=25°C
31.3
32.768
150
34.3 kHz
tLFRCO
Startup time not in-
cluding software
calibration
µs
ILFRCO
Current consump-
tion
361
1.5
nA
%
TUNESTEPL- Frequency step
for LSB change in
FRCO
TUNING value
Figure 3.20. Calibrated LFRCO Frequency vs Temperature and Supply Voltage
42
40
38
36
34
32
30
42
40
38
36
34
32
30
- 40°C
25°C
85°C
2.0 V
3.0 V
3.8 V
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
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3.9.4 HFRCO
Table 3.11. HFRCO
Symbol
Parameter
Condition
Min
Typ
Max
Unit
24.72 MHz
21.63 MHz
14.42 MHz
11.33 MHz
6.80 MHz
1.25 MHz
24 MHz frequency band
21 MHz frequency band
14 MHz frequency band
11 MHz frequency band
7 MHz frequency band
1 MHz frequency band
fHFRCO = 14 MHz
23.28
20.37
13.58
10.67
6.40
24.0
21.0
14.0
11.0
6.60
1.20
0.6
Oscillation frequen-
cy, VDD= 3.0 V,
TAMB=25°C
fHFRCO
1.15
tHFRCO_settling Settling time after
start-up
Cycles
fHFRCO = 24 MHz
fHFRCO = 21 MHz
fHFRCO = 14 MHz
fHFRCO = 11 MHz
fHFRCO = 6.6 MHz
fHFRCO = 1.2 MHz
158
143
113
101
84
184 µA
175 µA
140 µA
125 µA
105 µA
40 µA
%
Current consump-
tion
IHFRCO
27
TUNESTEPH- Frequency step
0.31
for LSB change in
FRCO
TUNING value
1The TUNING field in the CMU_HFRCOCTRL register may be used to adjust the HFRCO frequency. There is enough adjustment
range to ensure that the frequency bands above 7 MHz will always have some overlap across supply voltage and temperature. By
using a stable frequency reference such as the LFXO or HFXO, a firmware calibration routine can vary the TUNING bits and the
frequency band to maintain the HFRCO frequency at any arbitrary value between 7 MHz and 21 MHz across operating conditions.
Figure 3.21. Calibrated HFRCO 1 MHz Band Frequency vs Supply Voltage and Temperature
1.45
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
1.45
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
- 40°C
25°C
85°C
2.0 V
3.0 V
3.8 V
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
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Figure 3.22. Calibrated HFRCO 7 MHz Band Frequency vs Supply Voltage and Temperature
6.70
6.65
6.60
6.55
6.50
6.45
6.40
6.35
6.30
6.70
6.65
6.60
6.55
6.50
6.45
6.40
6.35
6.30
- 40°C
25°C
85°C
2.0 V
3.0 V
3.8 V
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
Figure 3.23. Calibrated HFRCO 11 MHz Band Frequency vs Supply Voltage and Temperature
11.2
11.1
11.0
10.9
10.8
10.7
10.6
11.2
11.1
11.0
10.9
10.8
10.7
10.6
- 40°C
25°C
85°C
2.0 V
3.0 V
3.8 V
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
Figure 3.24. Calibrated HFRCO 14 MHz Band Frequency vs Supply Voltage and Temperature
14.2
14.1
14.0
13.9
13.8
13.7
13.6
13.5
13.4
14.2
14.1
14.0
13.9
13.8
13.7
13.6
13.5
13.4
- 40°C
25°C
85°C
2.0 V
3.0 V
3.8 V
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
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Figure 3.25. Calibrated HFRCO 21 MHz Band Frequency vs Supply Voltage and Temperature
21.2
21.0
20.8
20.6
20.4
20.2
21.2
21.0
20.8
20.6
20.4
20.2
- 40°C
25°C
85°C
2.0 V
3.0 V
3.8 V
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
3.9.5 AUXHFRCO
Table 3.12. AUXHFRCO
Symbol
Parameter
Condition
Min
Typ
Max
Unit
21 MHz frequency band
14 MHz frequency band
11 MHz frequency band
7 MHz frequency band
1 MHz frequency band
fAUXHFRCO = 14 MHz
20.37
13.58
10.67
6.40
21.0
14.0
11.0
6.60
1.20
0.6
21.63 MHz
14.42 MHz
11.33 MHz
6.80 MHz
1.25 MHz
Oscillation frequen-
cy, VDD= 3.0 V,
TAMB=25°C
fAUXHFRCO
1.15
tAUXHFRCO_settlingSettling time after
start-up
Cycles
TUNESTEPAUX-Frequency step
0.3
%
for LSB change in
HFRCO
TUNING value
3.9.6 USHFRCO
Table 3.13. USHFRCO
Symbol
Parameter
Condition
Min
Typ
Max
Unit
No Clock Recovery, Full Tem-
perature and Supply Range
47.10
48.00
48.90 MHz
Oscillation frequen- No Clock Recovery, 25°C, 3.3V
47.50
47.88
48.00
48.00
48.50 MHz
48.12 MHz
fUSHFRCO
cy
USB Active with Clock Recov-
ery, Full Temperature and Sup-
ply Range
TCUSHFRCO
Temperature coeffi- 3.3V
cient
0.0175
0.0045
%/°C
%/V
VCUSHFRCO
Supply voltage co-
efficient
25°C
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3.9.7 ULFRCO
Table 3.14. ULFRCO
Symbol
Parameter
Condition
Min
Typ
Max
Unit
fULFRCO
Oscillation frequen- 25°C, 3V
cy
0.70
1.75 kHz
TCULFRCO
Temperature coeffi-
cient
0.05
%/°C
%/V
VCULFRCO
Supply voltage co-
efficient
-18.2
3.10 Analog Digital Converter (ADC)
Table 3.15. ADC
Symbol
VADCIN
Parameter
Condition
Single ended
Differential
Min
Typ
Max
Unit
0
-VREF/2
1.25
VREF
VREF/2
VDD
V
V
V
Input voltage range
VADCREFIN
Input range of exter-
nal reference volt-
age, single ended
and differential
VADCREFIN_CH7 Input range of ex-
ternal negative ref-
erence voltage on
See VADCREFIN
0
0.625
0
VDD - 1.1
V
V
V
channel 7
VADCREFIN_CH6 Input range of ex-
ternal positive ref-
See VADCREFIN
VDD
erence voltage on
channel 6
VADCCMIN
Common mode in-
put range
VDD
IADCIN
Input current
2pF sampling capacitors
<100
65
nA
dB
CMRRADC
Analog input com-
mon mode rejection
ratio
1 MSamples/s, 12 bit, external
reference
392
67
510 µA
µA
10 kSamples/s 12 bit, internal
1.25 V reference, WARMUP-
MODE in ADCn_CTRL set to
0b00
10 kSamples/s 12 bit, internal
Average active cur- 1.25 V reference, WARMUP-
63
64
µA
µA
IADC
rent
MODE in ADCn_CTRL set to
0b01
10 kSamples/s 12 bit, internal
1.25 V reference, WARMUP-
MODE in ADCn_CTRL set to
0b10
10 kSamples/s 12 bit, internal
1.25 V reference, WARMUP-
244
µA
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Symbol
Parameter
Condition
Min
Typ
Max
Unit
MODE in ADCn_CTRL set to
0b11
IADCREF
Current consump-
tion of internal volt-
age reference
Internal voltage reference
65
2
µA
CADCIN
RADCIN
RADCFILT
Input capacitance
pF
Input ON resistance
1
MOhm
kOhm
Input RC filter resis-
tance
10
CADCFILT
Input RC filter/de-
coupling capaci-
tance
250
fF
fADCCLK
ADC Clock Fre-
quency
13 MHz
6 bit
7
11
13
1
ADC-
CLK
Cycles
8 bit
ADC-
CLK
Cycles
tADCCONV
Conversion time
Acquisition time
12 bit
ADC-
CLK
Cycles
tADCACQ
Programmable
256 ADC-
CLK
Cycles
tADCACQVDD3
Required acquisi-
tion time for VDD/3
reference
2
µs
Startup time of ref-
erence generator
and ADC core in
NORMAL mode
5
1
µs
tADCSTART
Startup time of ref-
erence generator
and ADC core in
KEEPADCWARM
mode
µs
1 MSamples/s, 12 bit, single
ended, internal 1.25V refer-
ence
59
dB
1 MSamples/s, 12 bit, single
ended, internal 2.5V reference
63
65
60
65
54
dB
dB
dB
dB
dB
1 MSamples/s, 12 bit, single
ended, VDD reference
Signal to Noise Ra-
tio (SNR)
SNRADC
1 MSamples/s, 12 bit, differen-
tial, internal 1.25V reference
1 MSamples/s, 12 bit, differen-
tial, internal 2.5V reference
1 MSamples/s, 12 bit, differen-
tial, 5V reference
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Symbol
Parameter
Condition
Min
Typ
Max
Unit
1 MSamples/s, 12 bit, differen-
tial, VDD reference
67
69
62
dB
1 MSamples/s, 12 bit, differen-
tial, 2xVDD reference
dB
dB
200 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V refer-
ence
200 kSamples/s, 12 bit, single
ended, internal 2.5V reference
63
67
63
66
66
66
70
58
dB
dB
dB
dB
dB
dB
dB
dB
200 kSamples/s, 12 bit, single
ended, VDD reference
200 kSamples/s, 12 bit, differ-
ential, internal 1.25V reference
200 kSamples/s, 12 bit, differ-
ential, internal 2.5V reference
200 kSamples/s, 12 bit, differ-
ential, 5V reference
200 kSamples/s, 12 bit, differ-
ential, VDD reference
200 kSamples/s, 12 bit, differ-
ential, 2xVDD reference
1 MSamples/s, 12 bit, single
ended, internal 1.25V refer-
ence
1 MSamples/s, 12 bit, single
ended, internal 2.5V reference
62
64
60
64
54
66
68
61
dB
dB
dB
dB
dB
dB
dB
dB
1 MSamples/s, 12 bit, single
ended, VDD reference
1 MSamples/s, 12 bit, differen-
tial, internal 1.25V reference
1 MSamples/s, 12 bit, differen-
tial, internal 2.5V reference
1 MSamples/s, 12 bit, differen-
tial, 5V reference
SIgnal-to-Noise
And Distortion-ratio
(SINAD)
1 MSamples/s, 12 bit, differen-
tial, VDD reference
SINADADC
1 MSamples/s, 12 bit, differen-
tial, 2xVDD reference
200 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V refer-
ence
200 kSamples/s, 12 bit, single
ended, internal 2.5V reference
65
66
63
66
dB
dB
dB
dB
200 kSamples/s, 12 bit, single
ended, VDD reference
200 kSamples/s, 12 bit, differ-
ential, internal 1.25V reference
200 kSamples/s, 12 bit, differ-
ential, internal 2.5V reference
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Symbol
Parameter
Condition
Min
Typ
Max
Unit
200 kSamples/s, 12 bit, differ-
ential, 5V reference
66
66
69
64
dB
200 kSamples/s, 12 bit, differ-
ential, VDD reference
dB
200 kSamples/s, 12 bit, differ-
ential, 2xVDD reference
dB
1 MSamples/s, 12 bit, single
ended, internal 1.25V refer-
ence
dBc
1 MSamples/s, 12 bit, single
ended, internal 2.5V reference
76
73
66
77
76
75
69
75
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
1 MSamples/s, 12 bit, single
ended, VDD reference
1 MSamples/s, 12 bit, differen-
tial, internal 1.25V reference
1 MSamples/s, 12 bit, differen-
tial, internal 2.5V reference
1 MSamples/s, 12 bit, differen-
tial, VDD reference
1 MSamples/s, 12 bit, differen-
tial, 2xVDD reference
1 MSamples/s, 12 bit, differen-
tial, 5V reference
Spurious-Free Dy-
namic Range (SF-
DR)
SFDRADC
200 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V refer-
ence
200 kSamples/s, 12 bit, single
ended, internal 2.5V reference
75
76
79
79
78
79
79
dBc
dBc
dBc
dBc
dBc
dBc
dBc
200 kSamples/s, 12 bit, single
ended, VDD reference
200 kSamples/s, 12 bit, differ-
ential, internal 1.25V reference
200 kSamples/s, 12 bit, differ-
ential, internal 2.5V reference
200 kSamples/s, 12 bit, differ-
ential, 5V reference
200 kSamples/s, 12 bit, differ-
ential, VDD reference
200 kSamples/s, 12 bit, differ-
ential, 2xVDD reference
After calibration, single ended
After calibration, differential
-4
0.3
0.3
4
mV
VADCOFFSET
Offset voltage
mV
-1.92
-6.3
mV/°C
Thermometer out-
put gradient
ADC
Codes/
°C
TGRADADCTH
DNLADC
Differential non-lin-
earity (DNL)
VDD= 3.0 V, external 2.5V ref-
erence
-1
±0.7
4
LSB
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Symbol
Parameter
Condition
Min
Typ
Max
Unit
INLADC
Integral non-linear-
ity (INL), End point
method
±1.2
LSB
MCADC
No missing codes
11.9991
12
bits
1On the average every ADC will have one missing code, most likely to appear around 2048 ± n*512 where n can be a value in
the set {-3, -2, -1, 1, 2, 3}. There will be no missing code around 2048, and in spite of the missing code the ADC will be monotonic
at all times so that a response to a slowly increasing input will always be a slowly increasing output. Around the one code that is
missing, the neighbour codes will look wider in the DNL plot. The spectra will show spurs on the level of -78dBc for a full scale
input for chips that have the missing code issue.
The integral non-linearity (INL) and differential non-linearity parameters are explained in Figure 3.26 (p.
36) and Figure 3.27 (p. 37) , respectively.
Figure 3.26. Integral Non-Linearity (INL)
Digital ouput code
INL= |[(VD- VSS)/ VLSBIDEAL] - D| where 0 < D < 2N - 1
4095
4094
Actual ADC
tranfer function
before offset and
4093
Actual ADC
gain correction
4092
tranfer function
after offset and
gain correction
INL Error
(End Point INL)
Ideal transfer
curve
3
2
1
0
VOFFSET
Analog Input
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Figure 3.27. Differential Non-Linearity (DNL)
Digital
ouput
DNL= |[(VD+ 1 - VD)/ VLSBIDEAL] - 1| where 0 < D < 2N - 2
code
4095
4094
4093
4092
Full Scale Range
Example: Adjacent
input value VD+ 1
corrresponds to digital
output code D+ 1
Actual transfer
function with one
missing code.
Example: Input value
VD corrresponds to
digital output code D
Code width = 2 LSB
DNL= 1 LSB
Ideal transfer
curve
0.5
LSB
Ideal spacing
between two
adjacent codes
VLSBIDEAL= 1 LSB
5
4
3
2
1
0
Ideal 50%
Transition Point
Ideal Code Center
Analog Input
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3.10.1 Typical performance
Figure 3.28. ADC Frequency Spectrum, Vdd = 3V, Temp = 25°C
1.25V Reference
2XVDDVSS Reference
VDD Reference
2.5V Reference
5VDIFF Reference
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Figure 3.29. ADC Integral Linearity Error vs Code, Vdd = 3V, Temp = 25°C
1.25V Reference
2XVDDVSS Reference
VDD Reference
2.5V Reference
5VDIFF Reference
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Figure 3.30. ADC Differential Linearity Error vs Code, Vdd = 3V, Temp = 25°C
1.25V Reference
2XVDDVSS Reference
VDD Reference
2.5V Reference
5VDIFF Reference
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Figure 3.31. ADC Absolute Offset, Common Mode = Vdd /2
5
4
3
2
1
0
2.0
1.5
Vref= 1V25
VRef= 1V25
Vref= 2V5
VRef= 2V5
Vref= 2XVDDVSS
Vref= 5VDIFF
Vref= VDD
VRef= 2XVDDVSS
VRef= 5VDIFF
VRef= VDD
1.0
0.5
–1
0.0
–2
–3
–4
–0.5
–1.0
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd (V)
Temp (C)
Offset vs Supply Voltage, Temp = 25°C
Offset vs Temperature, Vdd = 3V
Figure 3.32. ADC Dynamic Performance vs Temperature for all ADC References, Vdd = 3V
71
70
69
68
67
66
65
64
63
79.4
79.2
79.0
78.8
78.6
78.4
78.2
78.0
2XVDDV
Vdd
1V25
Vdd
2V5
5VDIFF
2V5
2XVDDV
5VDIFF
1V25
–40
–15
5
25
45
65
85
–40
–15
5
25
45
65
85
Temperature [°C]
Temperature [°C]
Signal to Noise Ratio (SNR)
Spurious-Free Dynamic Range (SFDR)
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Figure 3.33. ADC Temperature sensor readout
2800
Vdd = 2.0
Vdd = 3.0
Vdd = 3.8
2700
2600
2500
2400
2300
2200
2100
2000
1900
–40
–15
5
25
45
65
85
Temperature [°C]
3.11 Current Digital Analog Converter (IDAC)
Table 3.16. IDAC Range 0 Source
Symbol
IIDAC
Parameter
Condition
Min
Typ
Max
Unit
µA
EM0, default settings
Duty-cycled
13.0
10
Active current with
STEPSEL=0x10
nA
I0x10
Nominal IDAC out-
put current with
STEPSEL=0x10
0.85
µA
ISTEP
ID
Step size
0.05
0.79
µA
%
Current drop at high VIDAC_OUT = VDD - 100mV
impedance load
TCIDAC
VCIDAC
Temperature coeffi- VDD = 3.0V, STEPSEL=0x10
cient
0.3
nA/°C
nA/V
Voltage coefficient
T = 25 °C, STEPSEL=0x10
11.7
Table 3.17. IDAC Range 0 Sink
Symbol
Parameter
Condition
Min
Typ
Max
Unit
IIDAC
Active current with
STEPSEL=0x10
EM0, default settings
15.1
0.85
µA
I0x10
Nominal IDAC out-
put current with
STEPSEL=0x10
µA
ISTEP
ID
Step size
0.05
0.30
µA
%
Current drop at high VIDAC_OUT = 200 mV
impedance load
TCIDAC
VCIDAC
Temperature coeffi- VDD = 3.0 V, STEPSEL=0x10
cient
0.2
nA/°C
nA/V
Voltage coefficient
T = 25 °C, STEPSEL=0x10
12.5
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Table 3.18. IDAC Range 1 Source
Symbol
IIDAC
Parameter
Condition
Min
Typ
Max
Unit
µA
EM0, default settings
Duty-cycled
14.4
10
Active current with
STEPSEL=0x10
nA
I0x10
Nominal IDAC out-
put current with
STEPSEL=0x10
3.2
µA
ISTEP
ID
Step size
0.1
µA
%
Current drop at high VIDAC_OUT = VDD - 100mV
impedance load
0.75
TCIDAC
VCIDAC
Temperature coeffi- VDD = 3.0 V, STEPSEL=0x10
cient
0.7
nA/°C
nA/V
Voltage coefficient
T = 25 °C, STEPSEL=0x10
38.4
Table 3.19. IDAC Range 1 Sink
Symbol
Parameter
Condition
Min
Typ
Max
Unit
IIDAC
Active current with
STEPSEL=0x10
EM0, default settings
19.4
3.2
µA
I0x10
Nominal IDAC out-
put current with
STEPSEL=0x10
µA
ISTEP
ID
Step size
0.1
µA
%
Current drop at high VIDAC_OUT = 200 mV
impedance load
0.32
TCIDAC
VCIDAC
Temperature coeffi- VDD = 3.0 V, STEPSEL=0x10
cient
0.7
nA/°C
nA/V
Voltage coefficient
T = 25 °C, STEPSEL=0x10
40.9
Table 3.20. IDAC Range 2 Source
Symbol
IIDAC
Parameter
Condition
Min
Typ
Max
Unit
µA
EM0, default settings
Duty-cycled
17.3
10
Active current with
STEPSEL=0x10
nA
I0x10
Nominal IDAC out-
put current with
STEPSEL=0x10
8.5
µA
ISTEP
ID
Step size
0.5
µA
%
Current drop at high VIDAC_OUT = VDD - 100mV
impedance load
1.22
TCIDAC
VCIDAC
Temperature coeffi- VDD = 3.0 V, STEPSEL=0x10
cient
2.8
nA/°C
nA/V
Voltage coefficient
T = 25 °C, STEPSEL=0x10
96.6
Table 3.21. IDAC Range 2 Sink
Symbol
Parameter
Condition
Min
Typ
Max
Unit
IIDAC
Active current with
STEPSEL=0x10
EM0, default settings
29.3
µA
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Symbol
Parameter
Condition
Min
Typ
Max
Unit
I0x10
Nominal IDAC out-
put current with
STEPSEL=0x10
8.5
µA
ISTEP
ID
Step size
0.5
µA
%
Current drop at high VIDAC_OUT = 200 mV
impedance load
0.62
TCIDAC
VCIDAC
Temperature coeffi- VDD = 3.0 V, STEPSEL=0x10
cient
2.8
nA/°C
nA/V
Voltage coefficient
T = 25 °C, STEPSEL=0x10
94.4
Table 3.22. IDAC Range 3 Source
Symbol
IIDAC
Parameter
Condition
Min
Typ
Max
Unit
µA
EM0, default settings
Duty-cycled
18.7
10
Active current with
STEPSEL=0x10
nA
I0x10
Nominal IDAC out-
put current with
STEPSEL=0x10
33.9
µA
ISTEP
ID
Step size
2.0
µA
%
Current drop at high VIDAC_OUT = VDD - 100 mV
impedance load
3.54
TCIDAC
VCIDAC
Temperature coeffi- VDD = 3.0 V, STEPSEL=0x10
cient
10.9
nA/°C
nA/V
Voltage coefficient
T = 25 °C, STEPSEL=0x10
159.5
Table 3.23. IDAC Range 3 Sink
Symbol
Parameter
Condition
Min
Typ
Max
Unit
IIDAC
Active current with
STEPSEL=0x10
EM0, default settings
62.5
34.1
µA
I0x10
Nominal IDAC out-
put current with
STEPSEL=0x10
µA
ISTEP
ID
Step size
2.0
µA
%
Current drop at high VIDAC_OUT = 200 mV
impedance load
1.75
TCIDAC
VCIDAC
Temperature coeffi- VDD = 3.0 V, STEPSEL=0x10
cient
10.9
nA/°C
nA/V
Voltage coefficient
T = 25 °C, STEPSEL=0x10
148.6
Table 3.24. IDAC
Symbol
Parameter
Min
Typ
Max
Unit
tIDACSTART
Start-up time, from enabled to output settled
40
µs
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Figure 3.34. IDAC Source Current as a function of voltage on IDAC_OUT
101
100
99
98
97
96
95
94
93
92
91
90
101
100
99
98
97
96
95
94
93
92
91
90
- 40°C, 2.0V
25°C, 3.0V
85°C, 3.8V
- 40°C, 2.0V
25°C, 3.0V
85°C, 3.8V
–2.0
–1.5
–1.0
–0.5
0.0
–2.0
–1.5
–1.0
–0.5
0.0
V(IDAC_OUT) - Vdd [V]
V(IDAC_OUT) - Vdd [V]
Range 0
Range 1
101
100
99
98
97
96
95
94
93
92
91
90
101
100
99
98
97
96
95
94
93
92
91
90
- 40°C, 2.0V
25°C, 3.0V
85°C, 3.8V
- 40°C, 2.0V
25°C, 3.0V
85°C, 3.8V
–2.0
–1.5
–1.0
–0.5
0.0
–2.0
–1.5
–1.0
–0.5
0.0
V(IDAC_OUT) - Vdd [V]
V(IDAC_OUT) - Vdd [V]
Range 2
Range 3
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Figure 3.35. IDAC Sink Current as a function of voltage from IDAC_OUT
101
100
99
101
100
99
- 40°C, 2.0V
25°C, 3.0V
85°C, 3.8V
- 40°C, 2.0V
25°C, 3.0V
85°C, 3.8V
98
98
97
97
96
96
95
95
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
V(IDAC_OUT) [V]
V(IDAC_OUT) [V]
Range 0
Range 1
101
100
99
101
100
99
- 40°C, 2.0V
25°C, 3.0V
85°C, 3.8V
- 40°C, 2.0V
25°C, 3.0V
85°C, 3.8V
98
98
97
97
96
96
95
95
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
V(IDAC_OUT) [V]
V(IDAC_OUT) [V]
Range 2
Range 3
Figure 3.36. IDAC linearity
5
4
3
2
1
0
70
60
50
40
30
20
10
0
Range 0
Range 1
Range 2
Range 3
0
5
10
15
Step
20
25
30
0
5
10
15
Step
20
25
30
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3.12 Analog Comparator (ACMP)
Table 3.25. ACMP
Symbol
VACMPIN
VACMPCM
Parameter
Condition
Min
Typ
Max
Unit
V
Input voltage range
0
0
VDD
VDD
ACMP Common
V
Mode voltage range
BIASPROG=0b0000, FULL-
BIAS=0 and HALFBIAS=1 in
ACMPn_CTRL register
0.1
2.87
195
0
0.4 µA
15 µA
520 µA
µA
BIASPROG=0b1111, FULL-
BIAS=0 and HALFBIAS=0 in
ACMPn_CTRL register
IACMP
Active current
BIASPROG=0b1111, FULL-
BIAS=1 and HALFBIAS=0 in
ACMPn_CTRL register
Internal voltage reference off.
Using external voltage refer-
ence
Current consump-
tion of internal volt-
age reference
IACMPREF
Internal voltage reference
5
0
µA
VACMPOFFSET Offset voltage
BIASPROG= 0b1010, FULL-
BIAS=0 and HALFBIAS=0 in
ACMPn_CTRL register
-12
12 mV
VACMPHYST
ACMP hysteresis
Programmable
17
40
mV
CSRESSEL=0b00 in
ACMPn_INPUTSEL
kOhm
CSRESSEL=0b01 in
ACMPn_INPUTSEL
70
101
132
kOhm
kOhm
kOhm
Capacitive Sense
Internal Resistance
RCSRES
CSRESSEL=0b10 in
ACMPn_INPUTSEL
CSRESSEL=0b11 in
ACMPn_INPUTSEL
tACMPSTART
Startup time
10 µs
The total ACMP current is the sum of the contributions from the ACMP and its internal voltage reference
as given in Equation 3.1 (p. 47) . IACMPREF is zero if an external voltage reference is used.
Total ACMP Active Current
IACMPTOTAL = IACMP + IACMPREF
(3.1)
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Figure 3.37. ACMP Characteristics, Vdd = 3V, Temp = 25°C, FULLBIAS = 0, HALFBIAS = 1
2.5
2.0
1.5
1.0
0.5
0.0
20
15
10
5
HYSTSEL= 0
HYSTSEL= 2
HYSTSEL= 4
HYSTSEL= 6
0
0
4
8
12
0
2
4
6
8
10
12
14
ACMP_CTRL_BIASPROG
ACMP_CTRL_BIASPROG
Current consumption, HYSTSEL = 4
Response time , Vcm
=
1.25V, CP+ to CP- = 100mV
100
80
60
40
20
0
BIASPROG= 0.0
BIASPROG= 4.0
BIASPROG= 8.0
BIASPROG= 12.0
0
1
2
3
4
5
6
7
ACMP_CTRL_HYSTSEL
Hysteresis
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3.13 Voltage Comparator (VCMP)
Table 3.26. VCMP
Symbol
VVCMPIN
VVCMPCM
Parameter
Condition
Min
Typ
Max
Unit
V
Input voltage range
VDD
VDD
VCMP Common
V
Mode voltage range
BIASPROG=0b0000 and
HALFBIAS=1 in VCMPn_CTRL
register
0.2
22
10
µA
IVCMP
Active current
BIASPROG=0b1111 and
HALFBIAS=0 in VCMPn_CTRL
register. LPREF=0.
35 µA
tVCMPREF
Startup time refer-
ence generator
NORMAL
µs
Single ended
Differential
10
10
17
mV
mV
mV
VVCMPOFFSET Offset voltage
VVCMPHYST
tVCMPSTART
VCMP hysteresis
Startup time
10 µs
The VDD trigger level can be configured by setting the TRIGLEVEL field of the VCMP_CTRL register in
accordance with the following equation:
VCMP Trigger Level as a Function of Level Setting
VDD Trigger Level=1.667V+0.034 ×TRIGLEVEL
(3.2)
3.14 I2C
Table 3.27. I2C Standard-mode (Sm)
Symbol
fSCL
Parameter
Min
Typ
Max
Unit
SCL clock frequency
0
4.7
4.0
250
8
1001 kHz
tLOW
SCL clock low time
µs
tHIGH
SCL clock high time
µs
tSU,DAT
tHD,DAT
tSU,STA
tHD,STA
tSU,STO
tBUF
SDA set-up time
ns
SDA hold time
34502,3 ns
Repeated START condition set-up time
(Repeated) START condition hold time
STOP condition set-up time
Bus free time between a STOP and START condition
4.7
4.0
4.0
4.7
µs
µs
µs
µs
1For the minimum HFPERCLK frequency required in Standard-mode, see the I2C chapter in the EFM32HG Reference Manual.
2The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).
3When transmitting data, this number is guaranteed only when I2Cn_CLKDIV < ((3450*10-9 [s] * fHFPERCLK [Hz]) - 5).
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Table 3.28. I2C Fast-mode (Fm)
Symbol
fSCL
Parameter
Min
Typ
Max
Unit
SCL clock frequency
0
1.3
0.6
100
8
4001 kHz
tLOW
SCL clock low time
µs
tHIGH
SCL clock high time
µs
tSU,DAT
tHD,DAT
tSU,STA
tHD,STA
tSU,STO
tBUF
SDA set-up time
ns
SDA hold time
9002,3 ns
Repeated START condition set-up time
(Repeated) START condition hold time
STOP condition set-up time
Bus free time between a STOP and START condition
0.6
0.6
0.6
1.3
µs
µs
µs
µs
1For the minimum HFPERCLK frequency required in Fast-mode, see the I2C chapter in the EFM32HG Reference Manual.
2The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).
3When transmitting data, this number is guaranteed only when I2Cn_CLKDIV < ((900*10-9 [s] * fHFPERCLK [Hz]) - 5).
Table 3.29. I2C Fast-mode Plus (Fm+)
Symbol
fSCL
Parameter
Min
Typ
Max
Unit
SCL clock frequency
0
0.5
10001 kHz
tLOW
SCL clock low time
µs
µs
ns
ns
µs
µs
µs
µs
tHIGH
SCL clock high time
0.26
50
tSU,DAT
tHD,DAT
tSU,STA
tHD,STA
tSU,STO
tBUF
SDA set-up time
SDA hold time
8
Repeated START condition set-up time
(Repeated) START condition hold time
STOP condition set-up time
Bus free time between a STOP and START condition
0.26
0.26
0.26
0.5
1For the minimum HFPERCLK frequency required in Fast-mode Plus, see the I2C chapter in the EFM32HG Reference Manual.
3.15 USB
The USB hardware in the EFM32HG321 passes all tests for USB 2.0 Full Speed certification. The test
report will be distributed with application note "AN0046 - USB Hardware Design Guide" when ready.
3.16 Digital Peripherals
Table 3.30. Digital Peripherals
Symbol
Parameter
Condition
Min
Typ
Max
Unit
IUSART
USART current
USART idle current, clock en-
abled
7.5
150
µA/
MHz
ILEUART
LEUART current
I2C current
LEUART idle current, clock en-
abled
nA
II2C
I2C idle current, clock enabled
6.25
8.75
µA/
MHz
ITIMER
TIMER current
TIMER_0 idle current, clock
enabled
µA/
MHz
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Symbol
Parameter
Condition
Min
Typ
Max
Unit
IPCNT
PCNT current
PCNT idle current, clock en-
abled
100
nA
IRTC
RTC current
GPIO current
RTC idle current, clock enabled
100
nA
IGPIO
GPIO idle current, clock en-
abled
5.31
µA/
MHz
IPRS
PRS current
DMA current
PRS idle current
2.81
8.12
µA/
MHz
IDMA
Clock enable
µA/
MHz
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4 Pinout and Package
Note
Please refer to the application note "AN0002 EFM32 Hardware Design Considerations" for
guidelines on designing Printed Circuit Boards (PCB's) for the EFM32HG321.
4.1 Pinout
The EFM32HG321 pinout is shown in Figure 4.1 (p. 52) and Table 4.1 (p. 52). Alternate locations
are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/").
Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module
in question.
Figure 4.1. EFM32HG321 Pinout (top view, not to scale)
Table 4.1. Device Pinout
QFP48 Pin#
and Name
Pin Alternate Functionality / Description
Pin Name
Analog
Timers
Communication
Other
USB_DMPU #0
US1_RX #4
LEU0_RX #4
I2C0_SDA #0
TIM0_CC1 #6
TIM0_CC0 #0/1/4
PCNT0_S0IN #4
PRS_CH0 #0
PRS_CH3 #3
GPIO_EM4WU0
1
2
PA0
PA1
TIM0_CC0 #6
TIM0_CC1 #0/1
CMU_CLK1 #0
PRS_CH1 #0
I2C0_SCL #0
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QFP48 Pin#
and Name
Pin Alternate Functionality / Description
Pin Name
Analog
Timers
Communication
Other
3
4
5
PA2
IOVDD_0
VSS
TIM0_CC2 #0/1
CMU_CLK0 #0
Digital IO power supply 0.
Ground.
US0_TX #5/6
US1_TX #0
US1_CS #5
I2C0_SDA #4
TIM0_CC1 #4
PCNT0_S0IN #2
6
7
PC0
PC1
ACMP0_CH0
ACMP0_CH1
PRS_CH2 #0
PRS_CH3 #0
US0_RX #5/6
US1_TX #5
US1_RX #0
I2C0_SCL #4
TIM0_CC2 #4
PCNT0_S1IN #2
8
9
PC2
PC3
PC4
ACMP0_CH2
ACMP0_CH3
ACMP0_CH4
TIM0_CDTI0 #4
TIM0_CDTI1 #4
TIM0_CDTI2 #4
US1_RX #5
US1_CLK #5
10
GPIO_EM4WU6
US0_TX #4
US1_CLK #0
11
12
PB7
PB8
LFXTAL_P
LFXTAL_N
TIM1_CC0 #3
TIM1_CC1 #3
US0_RX #4
US1_CS #0
13
14
15
PA8
PA9
TIM2_CC0 #0
TIM2_CC1 #0
TIM2_CC2 #0
PA10
Reset input, active low.
16
17
RESETn
PB11
To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up
ensure that reset is released.
TIM1_CC2 #3
CMU_CLK1 #3
ACMP0_O #3
IDAC0_OUT
US1_CLK #4
PCNT0_S1IN #4
18
19
VSS
Ground.
AVDD_1
Analog power supply 1.
HFXTAL_P
US0_CLK #4/5
LEU0_TX #1
20
21
PB13
PB14
US0_CS #4/5
LEU0_RX #1
HFXTAL_N
22
23
24
25
IOVDD_3
AVDD_0
PD4
Digital IO power supply 3.
Analog power supply 0.
ADC0_CH4
LEU0_TX #0
LEU0_RX #0
PD5
ADC0_CH5
TIM1_CC0 #4
PCNT0_S0IN #3
US1_RX #2/3
I2C0_SDA #1
26
27
PD6
PD7
ADC0_CH6
ADC0_CH7
ACMP0_O #2
CMU_CLK0 #2
TIM1_CC1 #4
PCNT0_S1IN #3
US1_TX #2/3
I2C0_SCL #1
28
29
30
31
32
33
VDD_DREG
DECOUPLE
PC8
Power supply for on-chip voltage regulator.
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin.
TIM2_CC0 #2
TIM2_CC1 #2
TIM2_CC2 #2
US0_CS #2
US0_CLK #2
US0_RX #2
PC9
GPIO_EM4WU2
PC10
USB_VREGI
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QFP48 Pin#
and Name
Pin Alternate Functionality / Description
Pin Name
Analog
Timers
Communication
Other
34
35
USB_VREGO
PC14
US0_CS #3
US1_CS #3/4
LEU0_TX #5
USB_DM
TIM0_CDTI1 #1/6
TIM1_CC1 #0
PCNT0_S1IN #0
PRS_CH0 #2
PRS_CH1 #2
US0_CLK #3
US1_CLK #3
LEU0_RX #5
USB_DP
TIM0_CDTI2 #1/6
TIM1_CC2 #0
36
PC15
US1_CLK #2
LEU0_TX #3
I2C0_SDA #5
DBG_SWCLK #0
BOOT_TX
37
38
39
PF0
PF1
PF2
TIM0_CC0 #5
TIM0_CC1 #5
US1_CS #2
LEU0_RX #3
I2C0_SCL #5
DBG_SWDIO #0
GPIO_EM4WU3
BOOT_RX
CMU_CLK0 #3
PRS_CH0 #3
GPIO_EM4WU4
TIM0_CC2 #5/6
TIM2_CC0 #3
US1_TX #4
LEU0_TX #4
40
41
42
43
44
45
46
PF3
PF4
TIM0_CDTI0 #5
TIM0_CDTI1 #5
TIM0_CDTI2 #5
PRS_CH0 #1
PRS_CH1 #1
PRS_CH2 #1
PF5
IOVDD_5
VSS
Digital IO power supply 5.
Ground.
PE10
PE11
TIM1_CC0 #1
TIM1_CC1 #1
US0_TX #0
US0_RX #0
PRS_CH2 #2
PRS_CH3 #2
US0_RX #3
US0_CLK #0/6
I2C0_SDA #6
TIM1_CC2 #1
TIM2_CC1 #3
CMU_CLK1 #2
PRS_CH1 #3
47
48
PE12
PE13
ADC0_CH0
ADC0_CH1
US0_TX #3
US0_CS #0/6
I2C0_SCL #6
ACMP0_O #0
PRS_CH2 #3
GPIO_EM4WU5
TIM2_CC2 #3
4.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in
Table 4.2 (p. 54). The table shows the name of the alternate functionality in the first column, followed
by columns showing the possible LOCATION bitfield settings.
Note
Some functionality, such as analog interfaces, do not have alternate settings or a LOCA-
TION bitfield. In these cases, the pinout is shown in the column corresponding to LOCA-
TION 0.
Table 4.2. Alternate functionality overview
Alternate
LOCATION
Functionality
ACMP0_CH0
ACMP0_CH1
ACMP0_CH2
ACMP0_CH3
0
1
2
3
4
5
6
Description
Analog comparator ACMP0, channel 0.
Analog comparator ACMP0, channel 1.
Analog comparator ACMP0, channel 2.
Analog comparator ACMP0, channel 3.
PC0
PC1
PC2
PC3
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Alternate
LOCATION
Functionality
ACMP0_CH4
ACMP0_O
0
1
2
3
4
5
6
Description
PC4
PE13
PE12
PE13
PD4
PD5
PD6
PD7
PF1
Analog comparator ACMP0, channel 4.
PD6
PB11
Analog comparator ACMP0, digital output.
Analog to digital converter ADC0, input channel number 0.
Analog to digital converter ADC0, input channel number 1.
Analog to digital converter ADC0, input channel number 4.
Analog to digital converter ADC0, input channel number 5.
Analog to digital converter ADC0, input channel number 6.
Analog to digital converter ADC0, input channel number 7.
Bootloader RX.
ADC0_CH0
ADC0_CH1
ADC0_CH4
ADC0_CH5
ADC0_CH6
ADC0_CH7
BOOT_RX
BOOT_TX
PF0
Bootloader TX.
CMU_CLK0
CMU_CLK1
PA2
PA1
PD7
PF2
Clock Management Unit, clock output number 0.
Clock Management Unit, clock output number 1.
Debug-interface Serial Wire clock input.
PE12
PB11
DBG_SWCLK
DBG_SWDIO
PF0
PF1
Note that this function is enabled to pin out of reset, and
has a built-in pull down.
Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, and
has a built-in pull up.
GPIO_EM4WU0
GPIO_EM4WU2
GPIO_EM4WU3
GPIO_EM4WU4
GPIO_EM4WU5
GPIO_EM4WU6
PA0
PC9
PF1
PF2
PE13
PC4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
High Frequency Crystal negative pin. Also used as exter-
nal optional clock input pin.
HFXTAL_N
PB14
HFXTAL_P
I2C0_SCL
I2C0_SDA
IDAC0_OUT
LEU0_RX
PB13
PA1
High Frequency Crystal positive pin.
I2C0 Serial Clock Line input / output.
I2C0 Serial Data input / output.
IDAC0 output.
PD7
PC1
PF1
PF0
PE13
PE12
PA0
PD6
PC0
PB11
PD5
PB14
PB13
PF1
PF0
PA0
PF2
PC15
PC14
LEUART0 Receive input.
LEUART0 Transmit output. Also used as receive input in
half duplex communication.
LEU0_TX
PD4
Low Frequency Crystal (typically 32.768 kHz) negative
pin. Also used as an optional external clock input pin.
LFXTAL_N
PB8
PB7
LFXTAL_P
PCNT0_S0IN
PCNT0_S1IN
PRS_CH0
PRS_CH1
PRS_CH2
PRS_CH3
TIM0_CC0
TIM0_CC1
Low Frequency Crystal (typically 32.768 kHz) positive pin.
Pulse Counter PCNT0 input number 0.
PC0
PD6
PD7
PF2
PA0
PC14
PA0
PA1
PC0
PC1
PA0
PA1
PC1
PB11
Pulse Counter PCNT0 input number 1.
PF3
PF4
PF5
PC14
PC15
PE10
PE11
Peripheral Reflex System PRS, channel 0.
Peripheral Reflex System PRS, channel 1.
Peripheral Reflex System PRS, channel 2.
Peripheral Reflex System PRS, channel 3.
Timer 0 Capture Compare input / output channel 0.
Timer 0 Capture Compare input / output channel 1.
PE12
PE13
PA0
PA0
PA1
PA0
PC0
PF0
PF1
PA1
PA0
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Alternate
LOCATION
Functionality
TIM0_CC2
TIM0_CDTI0
TIM0_CDTI1
TIM0_CDTI2
TIM1_CC0
TIM1_CC1
TIM1_CC2
TIM2_CC0
TIM2_CC1
TIM2_CC2
US0_CLK
0
1
2
3
4
5
PF2
PF3
PF4
PF5
6
Description
PA2
PA2
PC1
PF2
Timer 0 Capture Compare input / output channel 2.
Timer 0 Complimentary Deat Time Insertion channel 0.
Timer 0 Complimentary Deat Time Insertion channel 1.
Timer 0 Complimentary Deat Time Insertion channel 2.
Timer 1 Capture Compare input / output channel 0.
Timer 1 Capture Compare input / output channel 1.
Timer 1 Capture Compare input / output channel 2.
Timer 2 Capture Compare input / output channel 0.
Timer 2 Capture Compare input / output channel 1.
Timer 2 Capture Compare input / output channel 2.
USART0 clock input / output.
PC2
PC3
PC4
PD6
PD7
PC14
PC15
PE10
PE11
PE12
PC14
PC15
PB7
PC14
PC15
PA8
PB8
PB11
PF2
PC8
PC9
PC10
PC9
PC8
PA9
PE12
PE13
PC15
PC14
PA10
PE12
PE13
PB13
PB14
PB13
PB14
PE12
PE13
US0_CS
USART0 chip select input / output.
USART0 Asynchronous Receive.
US0_RX
US0_TX
PE11
PE10
PC10
PE12
PE13
PB8
PB7
PC1
PC0
PC1
PC0
USART0 Synchronous mode Master Input / Slave Output
(MISO).
USART0 Asynchronous Transmit.Also used as receive in-
put in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input
(MOSI).
US1_CLK
US1_CS
PB7
PB8
PF0
PF1
PC15
PC14
PB11
PC14
PC3
PC0
USART1 clock input / output.
USART1 chip select input / output.
USART1 Asynchronous Receive.
US1_RX
US1_TX
PC1
PC0
PD6
PD7
PD6
PD7
PA0
PF2
PC2
PC1
USART1 Synchronous mode Master Input / Slave Output
(MISO).
USART1 Asynchronous Transmit.Also used as receive in-
put in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input
(MOSI).
USB_DM
PC14
PA0
USB D- pin.
USB_DMPU
USB_DP
USB D- Pullup control.
USB D+ pin.
PC15
USB_VREGI
USB_VREGI
USB_VREGO
USB Input to internal 3.3 V regulator
USB Decoupling for internal 3.3 V USB regulator and reg-
ulator output
USB_VREGO
4.3 GPIO Pinout Overview
The specific GPIO pins available in EFM32HG321 is shown in Table 4.3 (p. 57) . Each GPIO port is
organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated
by a number from 15 down to 0.
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Table 4.3. GPIO Pinout
Port
Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin
Pin
0
15
14
13
12
11
10
PA10
-
9
8
PA8
PB8
PC8
-
7
6
5
4
3
2
PA2
-
1
PA1
-
Port A
Port B
Port C
Port D
Port E
Port F
-
-
-
-
-
-
-
-
-
PA9
-
-
-
-
-
PA0
PB14 PB13
PB11
-
PB7
-
-
-
-
-
PC3
-
-
PC0
-
PC15 PC14
-
-
-
-
PC10
-
PC9
-
-
PC4
PD4
-
PC2
-
PC1
-
-
-
-
-
-
-
-
-
-
PD7
PD6
PD5
-
PE13 PE12 PE11 PE10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PF5
PF4
PF3
PF2
PF1
PF0
4.4 TQFP48 Package
Figure 4.2. TQFP48
Note:
1. Dimensions and tolerance per ASME Y14.5M-1994
2. Control dimension: Millimeter.
3. Datum plane AB is located at bottom of lead and is coincident with the lead where the lead exists
from the plastic body at the bottom of the parting line.
4. Datums T, U and Z to be determined at datum plane AB.
5. Dimensions S and V to be determined at seating plane AC.
6. Dimensions A and B do not include mold protrusion. Allowable protrusion is 0.250 per side. Dimen-
sions A and B do include mold mismatch and are determined at datum AB.
7. Dimension D does not include dambar protrusion. Dambar protrusion shall not cause the D dimension
to exceed 0.350.
8. Minimum solder plate thickness shall be 0.0076.
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9. Exact shape of each corner is optional.
Table 4.4. QFP48 (Dimensions in mm)
DIM
A
MIN
-
NOM
MAX
-
DIM
M
MIN
NOM
12DEG REF
-
MAX
7.000 BSC
-
-
A1
B
-
3.500 BSC
-
N
0.090
0.160
-
7.000 BSC
-
P
-
0.250 BSC
-
-
B1
C
-
3.500 BSC
-
R
0.150
0.250
1.000
0.170
0.950
0.170
-
-
1.200
0.270
1.050
0.230
-
S
-
-
-
-
-
-
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 BSC
1.000 BSC
-
-
-
-
-
-
D
-
S1
V
E
-
F
-
V1
W
AA
G
H
0.500 BSC
0.050
0.090
0.500
0DEG
-
-
-
-
0.150
0.200
0.700
7DEG
J
K
L
The TQFP48 Package is 7 by 7 mm in size and has a 0.5 mm pin pitch.
The TQFP48 package uses matte-Sn post plated leadframe.
All EFM32 packages are RoHS compliant and free of Bromine (Br) and Antimony (Sb).
For additional Quality and Environmental information, please see:
http://www.silabs.com/support/quality/pages/default.aspx
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5 PCB Layout and Soldering
5.1 Recommended PCB Layout
Figure 5.1. TQFP48 PCB Land Pattern
a
p8
p7
p6
p1
b
e
c
p2
p5
p3
p4
d
Table 5.1. QFP48 PCB Land Pattern Dimensions (Dimensions in mm)
Symbol
Dim. (mm)
1.60
Symbol
P1
Pin number
Symbol
Pin number
a
b
c
d
e
1
P6
P7
P8
-
36
37
48
-
0.30
P2
12
13
24
25
0.50
P3
8.50
P4
8.50
P5
-
-
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Figure 5.2. TQFP48 PCB Solder Mask
a
b
c
e
d
Table 5.2. QFP48 PCB Solder Mask Dimensions (Dimensions in mm)
Symbol
Dim. (mm)
a
b
c
d
e
1.72
0.42
0.50
8.50
8.50
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Figure 5.3. TQFP48 PCB Stencil Design
a
b
c
e
d
Table 5.3. QFP48 PCB Stencil Design Dimensions (Dimensions in mm)
Symbol
Dim. (mm)
a
b
c
d
e
1.50
0.20
0.50
8.50
8.50
1. The drawings are not to scale.
2. All dimensions are in millimeters.
3. All drawings are subject to change without notice.
4. The PCB Land Pattern drawing is in compliance with IPC-7351B.
5. Stencil thickness 0.125 mm.
6. For detailed pin-positioning, see Figure 4.2 (p. 57) .
5.2 Soldering Information
The latest IPC/JEDEC J-STD-020 recommendations for Pb-Free reflow soldering should be followed.
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6 Chip Marking, Revision and Errata
6.1 Chip Marking
In the illustration below package fields and position are shown.
Figure 6.1. Example Chip Marking (top view)
6.2 Revision
The revision of a chip can be determined from the "Revision" field in Figure 6.1 (p. 62) .
6.3 Errata
Please see the errata document for EFM32HG321 for description and resolution of device erratas. This
document is available in Simplicity Studio and online at:
http://www.silabs.com/support/pages/document-library.aspx?p=MCUs--32-bit
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7 Revision History
7.1 Revision 0.91
May 6th, 2015
Updated current consumption table for energy modes.
Updated GPIO max leakage current.
Updated startup time for HFXO and LFXO.
Updated current consumption for HFRCO and LFRCO.
Updated ADC current consumption.
Updated IDAC characteristics tables.
Updated ACMP internal resistance.
Updated VCMP current consumption.
7.2 Revision 0.90
March 16th, 2015
Note
This datasheet revision applies to a product under development. It’s characteristics and
specifications are subject to change without notice.
Corrected EM2 current consumption condition in Electrical Characteristics section.
Updated GPIO electrical characteristics.
Updated Max ESRHFXO value for Crystal Frequency of 25 MHz.
Updated LFRCO plots.
Updated HFRCO table and plots.
Updated ADC table and temp sensor plot.
Added DMA current in Digital Peripherals section.
Updated block diagram.
Corrected leadframe type to matte-Sn.
7.3 Revision 0.20
December 11th, 2014
Preliminary Release.
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A Disclaimer and Trademarks
A.1 Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation
of all peripherals and modules available for system and software implementers using or intending to use
the Silicon Laboratories products. Characterization data, available modules and peripherals, memory
sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and
do vary in different applications. Application examples described herein are for illustrative purposes only.
Silicon Laboratories reserves the right to make changes without further notice and limitation to product
information, specifications, and descriptions herein, and does not give warranties as to the accuracy
or completeness of the included information. Silicon Laboratories shall have no liability for the conse-
quences of use of the information supplied herein. This document does not imply or express copyright
licenses granted hereunder to design or fabricate any integrated circuits. The products must not be
used within any Life Support System without the specific written consent of Silicon Laboratories. A "Life
Support System" is any product or system intended to support or sustain life and/or health, which, if it
fails, can be reasonably expected to result in significant personal injury or death. Silicon Laboratories
products are generally not intended for military applications. Silicon Laboratories products shall under no
circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological
or chemical weapons, or missiles capable of delivering such weapons.
A.2 Trademark Information
Silicon Laboratories Inc., Silicon Laboratories, Silicon Labs, SiLabs and the Silicon Labs logo, CMEMS®,
EFM, EFM32, EFR, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most ener-
gy friendly microcontrollers", Ember®, EZLink®, EZMac®, EZRadio®, EZRadioPRO®, DSPLL®, ISO-
modem®, Precision32®, ProSLIC®, SiPHY®, USBXpress® and others are trademarks or registered
trademarks of Silicon Laboratories Inc. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or reg-
istered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited. All other products
or brand names mentioned herein are trademarks of their respective holders.
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B Contact Information
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Please visit the Silicon Labs Technical Support web page:
http://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
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Table of Contents
1. Ordering Information .................................................................................................................................. 2
2. System Summary ...................................................................................................................................... 3
2.1. System Introduction ......................................................................................................................... 3
2.2. Configuration Summary .................................................................................................................... 6
2.3. Memory Map ................................................................................................................................. 7
3. Electrical Characteristics ............................................................................................................................. 8
3.1. Test Conditions .............................................................................................................................. 8
3.2. Absolute Maximum Ratings .............................................................................................................. 8
3.3. General Operating Conditions ........................................................................................................... 8
3.4. Current Consumption ....................................................................................................................... 9
3.5. Transition between Energy Modes .................................................................................................... 17
3.6. Power Management ....................................................................................................................... 17
3.7. Flash .......................................................................................................................................... 18
3.8. General Purpose Input Output ......................................................................................................... 18
3.9. Oscillators .................................................................................................................................... 27
3.10. Analog Digital Converter (ADC) ...................................................................................................... 32
3.11. Current Digital Analog Converter (IDAC) .......................................................................................... 42
3.12. Analog Comparator (ACMP) .......................................................................................................... 47
3.13. Voltage Comparator (VCMP) ......................................................................................................... 49
3.14. I2C ........................................................................................................................................... 49
3.15. USB .......................................................................................................................................... 50
3.16. Digital Peripherals ....................................................................................................................... 50
4. Pinout and Package ................................................................................................................................. 52
4.1. Pinout ......................................................................................................................................... 52
4.2. Alternate Functionality Pinout .......................................................................................................... 54
4.3. GPIO Pinout Overview ................................................................................................................... 56
4.4. TQFP48 Package .......................................................................................................................... 57
5. PCB Layout and Soldering ........................................................................................................................ 59
5.1. Recommended PCB Layout ............................................................................................................ 59
5.2. Soldering Information ..................................................................................................................... 61
6. Chip Marking, Revision and Errata .............................................................................................................. 62
6.1. Chip Marking ................................................................................................................................ 62
6.2. Revision ...................................................................................................................................... 62
6.3. Errata ......................................................................................................................................... 62
7. Revision History ...................................................................................................................................... 63
7.1. Revision 0.91 ............................................................................................................................... 63
7.2. Revision 0.90 ............................................................................................................................... 63
7.3. Revision 0.20 ............................................................................................................................... 63
A. Disclaimer and Trademarks ....................................................................................................................... 64
A.1. Disclaimer ................................................................................................................................... 64
A.2. Trademark Information ................................................................................................................... 64
B. Contact Information ................................................................................................................................. 65
B.1. ................................................................................................................................................. 65
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List of Figures
2.1. Block Diagram ....................................................................................................................................... 3
2.2. EFM32HG321 Memory Map with largest RAM and Flash sizes ........................................................................ 7
3.1. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 24
MHz ........................................................................................................................................................ 11
3.2. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 21
MHz ........................................................................................................................................................ 11
3.3. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 14
MHz ........................................................................................................................................................ 12
3.4. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 11
MHz ........................................................................................................................................................ 12
3.5. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 6.6
MHz ........................................................................................................................................................ 13
3.6. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 24 MHz .............................. 13
3.7. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 21 MHz .............................. 14
3.8. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 14 MHz .............................. 14
3.9. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 11 MHz .............................. 15
3.10. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 6.6 MHz ........................... 15
3.11. EM2 current consumption. RTC prescaled to 1kHz, 32.768 kHz LFRCO. ....................................................... 16
3.12. EM3 current consumption. ................................................................................................................... 16
3.13. EM4 current consumption. ................................................................................................................... 17
3.14. Typical Low-Level Output Current, 2V Supply Voltage ................................................................................ 21
3.15. Typical High-Level Output Current, 2V Supply Voltage ................................................................................ 22
3.16. Typical Low-Level Output Current, 3V Supply Voltage ................................................................................ 23
3.17. Typical High-Level Output Current, 3V Supply Voltage ................................................................................ 24
3.18. Typical Low-Level Output Current, 3.8V Supply Voltage .............................................................................. 25
3.19. Typical High-Level Output Current, 3.8V Supply Voltage ............................................................................. 26
3.20. Calibrated LFRCO Frequency vs Temperature and Supply Voltage .............................................................. 28
3.21. Calibrated HFRCO 1 MHz Band Frequency vs Supply Voltage and Temperature ............................................ 29
3.22. Calibrated HFRCO 7 MHz Band Frequency vs Supply Voltage and Temperature ............................................ 30
3.23. Calibrated HFRCO 11 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 30
3.24. Calibrated HFRCO 14 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 30
3.25. Calibrated HFRCO 21 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 31
3.26. Integral Non-Linearity (INL) ................................................................................................................... 36
3.27. Differential Non-Linearity (DNL) .............................................................................................................. 37
3.28. ADC Frequency Spectrum, Vdd = 3V, Temp = 25°C ................................................................................. 38
3.29. ADC Integral Linearity Error vs Code, Vdd = 3V, Temp = 25°C ................................................................... 39
3.30. ADC Differential Linearity Error vs Code, Vdd = 3V, Temp = 25°C ............................................................... 40
3.31. ADC Absolute Offset, Common Mode = Vdd /2 ........................................................................................ 41
3.32. ADC Dynamic Performance vs Temperature for all ADC References, Vdd = 3V .............................................. 41
3.33. ADC Temperature sensor readout ......................................................................................................... 42
3.34. IDAC Source Current as a function of voltage on IDAC_OUT ....................................................................... 45
3.35. IDAC Sink Current as a function of voltage from IDAC_OUT ........................................................................ 46
3.36. IDAC linearity .................................................................................................................................... 46
3.37. ACMP Characteristics, Vdd = 3V, Temp = 25°C, FULLBIAS = 0, HALFBIAS = 1 ............................................. 48
4.1. EFM32HG321 Pinout (top view, not to scale) ............................................................................................. 52
4.2. TQFP48 .............................................................................................................................................. 57
5.1. TQFP48 PCB Land Pattern ..................................................................................................................... 59
5.2. TQFP48 PCB Solder Mask ..................................................................................................................... 60
5.3. TQFP48 PCB Stencil Design ................................................................................................................... 61
6.1. Example Chip Marking (top view) ............................................................................................................. 62
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2015-05-06 - EFM32HG321FXX - _Rev0.91
67
Preliminary
...the world's most energy friendly microcontrollers
List of Tables
1.1. Ordering Information ................................................................................................................................ 2
2.1. Configuration Summary ............................................................................................................................ 6
3.1. Absolute Maximum Ratings ...................................................................................................................... 8
3.2. General Operating Conditions ................................................................................................................... 8
3.3. Current Consumption ............................................................................................................................... 9
3.4. Energy Modes Transitions ...................................................................................................................... 17
3.5. Power Management ............................................................................................................................... 18
3.6. Flash .................................................................................................................................................. 18
3.7. GPIO .................................................................................................................................................. 18
3.8. LFXO .................................................................................................................................................. 27
3.9. HFXO ................................................................................................................................................. 27
3.10. LFRCO .............................................................................................................................................. 28
3.11. HFRCO ............................................................................................................................................. 29
3.12. AUXHFRCO ....................................................................................................................................... 31
3.13. USHFRCO ......................................................................................................................................... 31
3.14. ULFRCO ............................................................................................................................................ 32
3.15. ADC .................................................................................................................................................. 32
3.16. IDAC Range 0 Source ......................................................................................................................... 42
3.17. IDAC Range 0 Sink ............................................................................................................................. 42
3.18. IDAC Range 1 Source ......................................................................................................................... 43
3.19. IDAC Range 1 Sink ............................................................................................................................. 43
3.20. IDAC Range 2 Source ......................................................................................................................... 43
3.21. IDAC Range 2 Sink ............................................................................................................................. 43
3.22. IDAC Range 3 Source ......................................................................................................................... 44
3.23. IDAC Range 3 Sink ............................................................................................................................. 44
3.24. IDAC ................................................................................................................................................. 44
3.25. ACMP ............................................................................................................................................... 47
3.26. VCMP ............................................................................................................................................... 49
3.27. I2C Standard-mode (Sm) ...................................................................................................................... 49
3.28. I2C Fast-mode (Fm) ............................................................................................................................ 50
3.29. I2C Fast-mode Plus (Fm+) .................................................................................................................... 50
3.30. Digital Peripherals ............................................................................................................................... 50
4.1. Device Pinout ....................................................................................................................................... 52
4.2. Alternate functionality overview ................................................................................................................ 54
4.3. GPIO Pinout ........................................................................................................................................ 57
4.4. QFP48 (Dimensions in mm) .................................................................................................................... 58
5.1. QFP48 PCB Land Pattern Dimensions (Dimensions in mm) .......................................................................... 59
5.2. QFP48 PCB Solder Mask Dimensions (Dimensions in mm) ........................................................................... 60
5.3. QFP48 PCB Stencil Design Dimensions (Dimensions in mm) ........................................................................ 61
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2015-05-06 - EFM32HG321FXX - _Rev0.91
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Preliminary
...the world's most energy friendly microcontrollers
List of Equations
3.1. Total ACMP Active Current ..................................................................................................................... 47
3.2. VCMP Trigger Level as a Function of Level Setting ..................................................................................... 49
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2015-05-06 - EFM32HG321FXX - _Rev0.91
69
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