EFM32JG1 [SILICON]
The EFM32 Jade Gecko MCUs are the worldâs most energyfriendly microcontrollers;
| 型号： | EFM32JG1 |
| 厂家： | 
SILICON |
| 描述： | The EFM32 Jade Gecko MCUs are the worldâs most energyfriendly microcontrollers |
| 文件： | 总94页 (文件大小：952K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EFM32 Jade Gecko Family
EFM32JG1 Data Sheet
The EFM32 Jade Gecko MCUs are the world’s most energy-
friendly microcontrollers.
ENERGY FRIENDLY FEATURES
• ARM Cortex-M3 at 40 MHz
EFM32JG1 features a powerful 32-bit ARM® Cortex®-M3 and a wide selection of periph-
erals, including a unique cryptographic hardware engine supporting AES, ECC, and
SHA. These features, combined with ultra-low current active mode and short wake-up
time from energy-saving modes, make EFM32JG1 microcontrollers well suited for any
battery-powered application, as well as other systems requiring high performance and
low-energy consumption.
• Ultra low energy operation:
• 1.1 μA EM3 Stop current (CRYOTIMER
running with state/RAM retention)
• 1.4 μA EM2 DeepSleep current (RTCC
running with state and RAM retention)
• 60 μA/MHz in Energy Mode 0 (EM0)
• Hardware cryptographic engine supports
AES, ECC, and SHA
Example applications:
• Home automation and security
• IoT devices and sensors
• Integrated dc-dc converter
• CRYOTIMER operates down to EM4
• 5 V tolerant I/O
• Industrial and factory automation
• Health and fitness
• Smart accessories
Core / Memory
Clock Management
Energy Management
High Frequency
Crystal
Oscillator
High Frequency
RC Oscillator
Voltage
Regulator
Voltage Monitor
Power-On Reset
Memory
Protection Unit
ARM CortexTM M3 processor
Auxiliary High
Frequency RC
Oscillator
Low Frequency
RC Oscillator
DC-DC
Converter
Low Frequency
Crystal
Oscillator
Ultra Low
Frequency RC
Oscillator
Flash Program
RAM Memory
Memory
Brown-Out
Detector
Debug Interface
DMA Controller
32-bit bus
Peripheral Reflex System
Timers and Triggers
Serial Interfaces
USART
I/O Ports
Analog Interfaces
Other
CRYPTO
CRC
External Interrupts
Timer/Counter
Pulse Counter
Watchdog Timer
Low Energy Timer
ADC
Analog Comparator
IDAC
General Purpose I/O
Pin Reset
Real Time Counter
and Calendar
Low Energy UARTTM
I2C
CRYOTIMER
Pin Wakeup
Lowest power mode with peripheral operational:
EM0 - Active
EM2 – Deep Sleep
EM4 - Hibernate
EM1 - Sleep
EM3 - Stop
EM4 - Shutoff
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This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Preliminary Rev. 0.31
EFM32JG1 Data Sheet
Feature List
1. Feature List
The EFM32JG1 highlighted features are listed below.
• ARM Cortex-M3 CPU platform
• 8 Channel DMA Controller
• High Performance 32-bit processor @ up to 40 MHz
• Wake-up Interrupt Controller
• 12 Channel Peripheral Reflex System (PRS) for autono-
mous inter-peripheral signaling
• Communication Interfaces
• Flexible Energy Management System
• 60 μA/MHz in Energy Mode 0 (EM0)
• 2× Universal Synchronous/Asynchronous Receiver/ Trans-
mitter
• 1.4 μA EM2 DeepSleep current (RTCC running with state
and RAM retention)
• UART/SPI/SmartCard (ISO 7816)/IrDA/I2S/LIN
• Triple buffered full/half-duplex operation with flow control
• Low Energy UART
• 1.1 μA EM3 Stop current (CRYOTIMER running with
state/RAM retention)
• Up to 256 kB flash program memory
• 32 kB RAM data memory
• Autonomous operation with DMA in Deep Sleep Mode
I2C Interface with SMBus support
•
• Up to 32 General Purpose I/O Pins
• Address recognition in EM3 Stop Mode
• Configurable push-pull, open-drain, pull-up/down, input fil-
ter, drive strength
• Ultra Low-Power Precision Analog Peripherals
• 12-bit 1 Msamples/s Analog to Digital Converter
• 2× Analog Comparator
• Configurable peripheral I/O locations
• Asynchronous external interrupts
• Output state retention and wake-up from Shutoff Mode
• Hardware Cryptography
• Digital to Analog Current Converter
• Up to 24 pins connected to analog channels (APORT)
shared between Analog Comparators, ADC, and IDAC
• AES 128/256-bit keys
• Ultra efficient Power-on Reset and Brown-Out Detector
• Debug Interface
• ECC B/K163, B/K233, P192, P224, P256
• SHA-1 and SHA-2 (SHA-224 and SHA-256)
• Timers/Counters
• 2-pin Serial Wire Debug interface
• 1-pin Serial Wire Viewer
• 2× 16-bit Timer/Counter
• JTAG (programming only)
• 3 + 4 Compare/Capture/PWM channels
• 1× 32-bit Real Time Counter and Calendar
• Pre-Programmed UART Bootloader
• Wide Operating Range
• 1× 32-bit Ultra Low Energy CRYOTIMER for periodic wake-
up from any Energy Mode
• 1.85 V to 3.8 V single power supply
• Integrated dc-dc, down to 1.8 V output with up to 200 mA
load current for system
• 16-bit Low Energy Timer for waveform generation
• 16-bit Pulse Counter with asynchronous operation
• Watchdog Timer with dedicated RC oscillator @ 50 nA
• Temperature range -40 to 85 ºC
• Packages
• 7 mm × 7 mm QFN48
• 5 mm × 5 mm QFN32
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Preliminary Rev. 0.31 | 1
EFM32JG1 Data Sheet
Ordering Information
2. Ordering Information
Ordering Code
Flash (KB) RAM (KB)
DC-DC Converter
GPIO
Package
EFM32JG1B200F256GM48-B0*
EFM32JG1B200F128GM48-B0*
EFM32JG1B200F256GM32-B0*
EFM32JG1B200F128GM32-B0*
EFM32JG1B100F256GM32-B0*
256
128
256
128
256
128
32
32
32
32
32
32
Yes
32
32
20
20
24
24
QFN48
Yes
Yes
Yes
No
QFN48
QFN32
QFN32
QFN32
QFN32
EFM32JG1B100F128GM32-B0*
* Engineering Samples
No
EFM32 J G 1 B 200 F 256 G M 32 – B0 R
Tape and Reel (Optional)
Revision
Pin Count
Package – M (QFN)
Temperature Grade – G (-40 to +85 °C), I (-40 to +125 °C)
Flash Memory Size in kB
Memory Type (Flash)
Feature Set Code
Performance Grade – P (Performance), B (Basic), V (Value)
Generation
Gecko
Family – J (Jade), P (Pearl)
Energy Friendly Microcontroller 32-bit
Figure 2.1. OPN Decoder
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Preliminary Rev. 0.31 | 2
EFM32JG1 Data Sheet
System Overview
3. System Overview
3.1 Introduction
The EFM32JG1 product family is well suited for any battery operated application as well as other systems requiring high performance
and low energy consumption. This section gives a short introduction to the MCU system. The detailed functional description can be
found in the EFM32JG1 Reference Manual.
A block diagram of the EFM32JG1 family is shown in Figure 3.1 Detailed EFM32JG1 Block Diagram on page 3. The diagram shows
a superset of features available on the family, which vary by OPN. For more information about specific device features, consult Order-
ing Information.
Port I/O Configuration
ARM Cortex-M3 Core
Debug /
Programming
Hardware
Serial Wire
RESETn
Digital Peripherals
Up to 256 KB ISP Flash
Program Memory
LETIMER
IOVDD
PAn
TIMER
CRYOTIMER
PCNT
Reset
Up to 32 KB RAM
Memory Protection Unit
DMA Controller
Reset
Management
Unit
Port A
Drivers
Voltage
Monitor / Brown
Out Detector
RTC / RTCC
USART
Port
Mapper
Port B
Drivers
PBn
PCn
PDn
PFn
LEUART
I2C
DVDD
Power Net
bypass
Watchdog
Timer
VREGVDD
VREGSW
DC-DC
Converter
CRYPTO
CRC
Port C
Drivers
A
H
B
A
P
B
VREGVSS
VSS
Clock Configuration
Port D
Drivers
Analog Peripherals
Internal
Reference
ULFRCO
LFXO
IDAC
Port F
Drivers
LFXTAL_P
LFXTAL_N
VDD
VREF
HFXTAL_P
HFXTAL_N
VDD
HFXO
12-bit ADC
HFRCO
AUXHFRCO
LFRCO
Temp
Sensor
+
-
Analog Comparator
Figure 3.1. Detailed EFM32JG1 Block Diagram
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Preliminary Rev. 0.31 | 3
EFM32JG1 Data Sheet
System Overview
3.2 Power
The EFM32JG1 has an Energy Management Unit (EMU) and efficient integrated regulators to generate internal supply voltages. Only a
single external supply voltage is required, from which all internal voltages are created. An optional integrated dc-dc buck regulator can
be utilized to further reduce the current consumption. The dc-dc regulator requires one external inductor and one external capacitor.
AVDD and VREGVDD need to be 1.85 V or higher for the MCU to operate across all conditions; however the rest of the system will
operate down to 1.62 V, including the digital supply and I/O. This means that the device is fully compatible with 1.8 V components.
Running from a sufficiently high supply, the device can use the dc-dc to regulate voltage not only for itself, but also for other PCB com-
ponents, supplying up to a total of 200 mA.
3.2.1 Energy Management Unit (EMU)
The Energy Management Unit manages transitions of energy modes in the device. Each energy mode defines which peripherals and
features are available and the amount of current the device consumes. The EMU can also be used to turn off the power to unused RAM
blocks, and it contains control registers for the dc-dc regulator and the Voltage Monitor (VMON). The VMON is used to monitor multiple
supply voltages. It has multiple channels which can be programmed individually by the user to determine if a sensed supply has fallen
below a chosen threshold.
3.2.2 DC-DC Converter
The dc-dc buck converter covers a wide range of load currents and provides up to 90% efficiency in energy modes EM0, EM1, EM2
and EM3, and can supply up to 200 mA to the device and surrounding PCB components. Protection features include programmable
current limiting, short-circuit protection, and dead-time protection. The dc-dc converter may also enter bypass mode when the input volt-
age is too low for efficient operation. In bypass mode, the dc-dc input supply is internally connected directly to its output through a low
resistance switch. Bypass mode also supports in-rush current limiting to avoid dipping the input supply due to excessive current transi-
ents.
3.3 General Purpose Input/Output (GPIO)
EFM32JG1 has up to 32 General Purpose Input/Output pins. Each GPIO pin can be individually configured as either an output or input.
More advanced configurations including open-drain, open-source, and glitch-filtering can be configured for each individual GPIO pin.
The GPIO pins can be overridden by peripheral connections, like SPI communication. Each peripheral connection can be routed to sev-
eral GPIO pins on the device. The input value of a GPIO pin can be routed through the Peripheral Reflex System to other peripherals.
The GPIO subsystem supports asynchronous external pin interrupts.
3.4 Clocking
3.4.1 Clock Management Unit (CMU)
The Clock Management Unit controls oscillators and clocks in the EFM32JG1. Individual enabling and disabling of clocks to all periph-
eral modules is perfomed by the CMU. The CMU also controls enabling and configuration of the oscillators. A high degree of flexibility
allows software to optimize energy consumption in any specific application by minimizing power dissipation in unused peripherals and
oscillators.
3.4.2 Internal and External Oscillators
The EFM32JG1 supports two crystal oscillators and fully integrates four RC oscillators, listed below.
• A high frequency crystal oscillator (HFXO) with integrated load capacitors, tunable in small steps, provides a precise timing refer-
ence for the MCU. Crystal frequencies in the range from 38 to 40 MHz are supported. An external clock source such as a TCXO can
also be applied to the HFXO input for improved accuracy over temperature.
• A 32.768 kHz crystal oscillator (LFXO) provides an accurate timing reference for low energy modes.
• An integrated high frequency RC oscillator (HFRCO) is available for the MCU system, when crystal accuracy is not required. The
HFRCO employs fast startup at minimal energy consumption combined with a wide frequency range.
• An integrated auxilliary high frequency RC oscillator (AUXHFRCO) is available for timing the general-purpose ADC and the Serial
Wire debug port with a wide frequency range.
• An integrated low frequency 32.768 kHz RC oscillator (LFRCO) can be used as a timing reference in low energy modes, when crys-
tal accuracy is not required.
• An integrated ultra-low frequency 1 kHz RC oscillator (ULFRCO) is available to provide a timing reference at the lowest energy con-
sumption in low energy modes.
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EFM32JG1 Data Sheet
System Overview
3.5 Counters/Timers and PWM
3.5.1 Timer/Counter (TIMER)
TIMER peripherals keep track of timing, count events, generate PWM outputs and trigger timed actions in other peripherals through the
PRS system. The core of each TIMER is a 16-bit counter with up to 4 compare/capture channels. Each channel is configurable in one
of three modes. In capture mode, the counter state is stored in a buffer at a selected input event. In compare mode, the channel output
reflects the comparison of the counter to a programmed threshold value. In PWM mode, the TIMER supports generation of pulse-width
modulation (PWM) outputs of arbitrary waveforms defined by the sequence of values written to the compare registers, with optional
dead-time insertion available in timer unit TIMER_0 only.
3.5.2 Real Time Counter and Calendar (RTCC)
The Real Time Counter and Calendar (RTCC) is a 32-bit counter providing timekeeping in all energy modes. The RTCC includes a
Binary Coded Decimal (BCD) calendar mode for easy time and date keeping. The RTCC can be clocked by any of the on-board oscilla-
tors with the exception of the AUXHFRCO, and it is capable of providing system wake-up at user defined instances. When receiving
frames, the RTCC value can be used for timestamping. The RTCC includes 128 bytes of general purpose data retention, allowing easy
and convenient data storage in all energy modes.
3.5.3 Low Energy Timer (LETIMER)
The unique LETIMER is a 16-bit timer that is available in energy mode EM2 Deep Sleep in addition to EM1 Sleep and EM0 Active. This
allows it to be used for timing and output generation when most of the device is powered down, allowing simple tasks to be performed
while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of wave-
forms with minimal software intervention. The LETIMER is connected to the Real Time Counter and Calendar (RTCC), and can be con-
figured to start counting on compare matches from the RTCC.
3.5.4 Ultra Low Power Wake-up Timer (CRYOTIMER)
The CRYOTIMER is a 32-bit counter that is capable of running in all energy modes. It can be clocked by either the 32.768 kHz crystal
oscillator (LFXO), the 32.768 kHz RC oscillator (LFRCO), or the 1 kHz RC oscillator (ULFRCO). It can provide periodic Wakeup events
and PRS signals which can be used to wake up peripherals from any energy mode. The CRYOTIMER provides a wide range of inter-
rupt periods, facilitating flexible ultra-low energy operation.
3.5.5 Pulse Counter (PCNT)
The Pulse Counter (PCNT) peripheral can be used for counting pulses on a single input or to decode quadrature encoded inputs. The
clock for PCNT is selectable from either an external source on pin PCTNn_S0IN or from an internal timing reference, selectable from
among any of the internal oscillators, except the AUXHFRCO. The module may operate in energy mode EM0 Active, EM1 Sleep, EM2
Deep Sleep, and EM3 Stop.
3.5.6 Watchdog Timer (WDOG)
The watchdog timer can act both as an independent watchdog or as a watchdog synchronous with the CPU clock. It has windowed
monitoring capabilities, and can generate a reset or different interrupts depending on the failure mode of the system. The watchdog can
also monitor autonomous systems driven by PRS.
3.6 Communications and Other Digital Peripherals
3.6.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
The Universal Synchronous/Asynchronous Receiver/Transmitter is a flexible serial I/O module. It supports full duplex asynchronous
UART communication with hardware flow control as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with devices sup-
porting:
• ISO7816 SmartCards
• IrDA
I2S
•
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EFM32JG1 Data Sheet
System Overview
3.6.2 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART)
The unique LEUARTTM provides two-way UART communication on a strict power budget. Only a 32.768 kHz clock is needed to allow
UART communication up to 9600 baud. The LEUART includes all necessary hardware to make asynchronous serial communication
possible with a minimum of software intervention and energy consumption.
3.6.3 Inter-Integrated Circuit Interface (I2C)
The I2C module provides an interface between the MCU and a serial I2C bus. It is capable of acting as both a master and a slave and
supports multi-master buses. Standard-mode, fast-mode and fast-mode plus speeds are supported, allowing transmission rates from 10
kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also available, allowing implementation of an SMBus-compliant system. The
interface provided to software by the I2C module allows precise timing control of the transmission process and highly automated trans-
fers. Automatic recognition of slave addresses is provided in active and low energy modes.
3.6.4 Peripheral Reflex System (PRS)
The Peripheral Reflex System provides a communication network between different peripheral modules without software involvement.
Peripheral modules producing Reflex signals are called producers. The PRS routes Reflex signals from producers to consumer periph-
erals which in turn perform actions in response. Edge triggers and other functionality can be applied by the PRS. The PRS allows pe-
ripheral to act autonomously without waking the MCU core, saving power.
3.7 Security Features
3.7.1 GPCRC (General Purpose Cyclic Redundancy Check)
The GPCRC module implements a Cyclic Redundancy Check (CRC) function. It supports both 32-bit and 16-bit polynomials. The sup-
ported 32-bit polynomial is 0x04C11DB7 (IEEE 802.3), while the 16-bit polynomial can be programmed to any value, depending on the
needs of the application. Common 16-bit polynomials are 0x1021 (CCITT-16), and 0x8005 (802.15.4, and USB).
3.7.2 Crypto Accelerator (CRYPTO)
The Crypto Accelerator is a fast and energy-efficient autonomous hardware encryption and decryption accelerator. EFM32JG1 devices
support AES encryption and decryption with 128- or 256-bit keys, ECC over both GF(P) and GF(2m), and SHA-1 and SHA-2 (SHA-224
and SHA-256).
Supported modes of operation for AES include: ECB, CTR, CBC, PCBC, CFB, OFB, CBC-MAC, GMAC and CCM.
Supported ECC NIST recommended curves include P-192, P-224, P-256, K-163, K-233, B-163 and B-233.
The CRYPTO module allows fast processing of GCM (AES), ECC and SHA with little CPU intervention. CRYPTO also provides trigger
signals for DMA read and write operations.
3.8 Analog
3.8.1 Analog Port (APORT)
The Analog Port (APORT) is an analog interconnect matrix allowing access to analog modules ADC, ACMP, and IDAC on a flexible
selection of pins. Each APORT bus consists of analog switches connected to a common wire. Since many clients can operate differen-
tially, buses are grouped by X/Y pairs.
3.8.2 Analog Comparator (ACMP)
The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is high-
er. Inputs are selected from among internal references and external pins. The tradeoff between response time and current consumption
is configurable by software. Two 6-bit reference dividers allow for a wide range of internally-programmable reference sources. The
ACMP can also be used to monitor the supply voltage. An interrupt can be generated when the supply falls below or rises above the
programmable threshold.
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EFM32JG1 Data Sheet
System Overview
3.8.3 Analog to Digital Converter (ADC)
The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to 1 MSamples/s. The
output sample resolution is configurable and additional resolution is possible using integrated hardware for averaging over multiple
samples. The ADC includes integrated voltage references and an integrated temperature sensor. Inputs are selectable from a wide
range of sources, including pins configurable as either single-ended or differential.
3.8.4 Digital to Analog Current Converter (IDAC)
The Digital to Analog Current Converter can source or sink a configurable constant current. This current can be driven on an output pin
or routed to the selected ADC input pin for capacitive sensing. The current is programmable between 0.05 µA and 64 µA with several
ranges with various step sizes.
3.9 Reset Management Unit (RMU)
The RMU is responsible for handling reset of the EFM32JG1. A wide range of reset sources are available, including several power
supply monitors, pin reset, software controlled reset, core lockup reset and watchdog reset.
3.10 Core and Memory
3.10.1 Processor Core
The ARM Cortex-M processor includes a 32-bit RISC processor integrating the following features and tasks in the system:
• ARM Cortex-M3 RISC processor achieving 1.25 Dhrystone MIPS/MHz
• Memory Protection Unit (MPU) supporting up to 8 memory segments
• Up to 256 KB flash program memory
• Up to 32 KB RAM data memory
• Configuration and event handling of all modules
• 2-pin Serial-Wire debug interface
3.10.2 Memory System Controller (MSC)
The Memory System Controller (MSC) is the program memory unit of the microcontroller. The flash memory is readable and writable
from both the Cortex-M and DMA. The flash memory is divided into two blocks; the main block and the information block. Program code
is normally written to the main block, whereas the information block is available for special user data and flash lock bits. There is also a
read-only page in the information block containing system and device calibration data. Read and write operations are supported in en-
ergy modes EM0 Active and EM1 Sleep.
3.10.3 Linked Direct Memory Access Controller (LDMA)
The Linked Direct Memory Access (LDMA) controller features 8 channels capable of performing memory operations independently of
software. This reduces both energy consumption and software workload. The LDMA allows operations to be linked together and stag-
ed, enabling sophisticated operations to be implemented.
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EFM32JG1 Data Sheet
System Overview
3.11 Memory Map
The EFM32JG1 memory map is shown in the figures below. RAM and flash sizes are for the largest memory configuration.
Figure 3.2. EFM32JG1 Memory Map — Core Peripherals and Code Space
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EFM32JG1 Data Sheet
System Overview
Figure 3.3. EFM32JG1 Memory Map — Peripherals
3.12 Configuration Summary
The features of the EFM32JG1 are a subset of the feature set described in the device reference manual. The table below describes
device specific implementation of the features. Remaining modules support full configuration.
Table 3.1. Configuration Summary
Module
USART0
USART1
Configuration
Pin Connections
IrDA SmartCard
US0_TX, US0_RX, US0_CLK, US0_CS
US1_TX, US1_RX, US1_CLK, US1_CS
IrDA I2S SmartCard
with DTI
TIMER0
TIMER1
TIM0_CC[2:0], TIM0_CDTI[2:0]
TIM1_CC[3:0]
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Preliminary Rev. 0.31 | 9
EFM32JG1 Data Sheet
Electrical Specifications
4. Electrical Specifications
4.1 Electrical Characteristics
All electrical parameters in all tables are specified under the following conditions, unless stated otherwise:
• Typical values are based on TAMB=25 °C and VDD= 3.3 V, by production test and/or technology characterization.
• Minimum and maximum values represent the worst conditions of ambient temperature, supply voltage, and process variation.
Refer to Table 4.2 General Operating Conditions on page 11 for more details about operational supply and temperature limits.
4.1.1 Absolute Maximum Ratings
Stresses above those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of
the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect device reliability. For more information on the available quality and relia-
bility data, see the Quality and Reliability Monitor Report at http://www.silabs.com/support/quality/pages/default.aspx.
Table 4.1. Absolute Maximum Ratings
Parameter
Symbol
Test Condition
Min
-50
0
Typ
Max
150
3.8
1
Unit
°C
Storage temperature range
TSTG
-
-
-
External main supply voltage VDDMAX
V
External main supply voltage VDDRAMPMAX
ramp rate
-
V / μs
Voltage on any 5V tolerant
GPIO pin1
VDIGPIN
-0.3
-0.3
-
-
Min of 5.25
and IOVDD
+2
V
V
Voltage on non-5V tolerant
GPIO pins
IOVDD+0.3
Voltage on HFXO pins
VHFXOPIN
-0.3
-
-
-
1.4
V
Total current into VSS ground IVSSMAX
lines (sink)
TBD
mA
Current per I/O pin (sink)
IIOMAX
-
-
-
-
-
-
-
-
50
50
mA
mA
mA
mA
Current per I/O pin (source)
Current for all I/O pins (sink) IIOALLMAX
TBD
TBD
Current for all I/O pins
(source)
Voltage difference between
AVDD and VREGVDD
ΔVDD
-
-
0.3
V
Note:
1. When a GPIO pin is routed to the analog module through the APORT, the maximum voltage = IOVDD.
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EFM32JG1 Data Sheet
Electrical Specifications
4.1.2 Operating Conditions
When assigning supply sources, the following requirements must be observed:
• VREGVDD must be the highest voltage in the system
• VREGVDD = AVDD_n
• DVDD ≤ AVDD_n
• IOVDD ≤ AVDD_n
4.1.2.1 General Operating Conditions
Table 4.2. General Operating Conditions
Parameter
Symbol
Test Condition
Min
-40
Typ
25
Max
85
Unit
°C
Ambient temperature range TAMB
AVDD Supply voltage1
VAVDD
1.85
3.3
3.8
V
VREGVDD Operating supply VVREGVDD
voltage12
DCDC in regulation
2.4
3.3
3.3
3.3
3.8
3.8
3.8
V
V
V
DCDC in bypass 50mA load
TBD
1.85
DCDC not in use. DVDD external-
ly shorted to VREGVDD
DVDD Operating supply volt- VDVDD
age
1.62
1.62
-
-
-
-
VVREGVDD
VVREGVDD
0.1
V
V
V
IOVDD Operating supply
voltage
VIOVDD
Difference between AVDD
and VREGVDD, ABS(AVDD-
VREGVDD)
dVDD
0 wait-states (MODE = WS0) 3
1 wait-states (MODE = WS1) 3
HFCLK frequency
fCORE
-
-
-
26
40
MHz
MHz
38.4
Note:
1. VREGVDD must be tied to AVDD. Both VREGVDD and AVDD minimum voltages must be satisfied for the part to operate.
2. The minimum voltage required in bypass mode is calculated using RBYP from the DCDC specification table. Requirements for
other loads can be calculated as VDVDD_min+ILOAD * RBYP_max
3. in MSC_READCTRL register
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Preliminary Rev. 0.31 | 11
EFM32JG1 Data Sheet
Electrical Specifications
4.1.3 DC-DC Converter
Test conditions: LDCDC=4.7 µH, CDCDC=1.0 µF, VDCDC_I=3.3 V, VDCDC_O=1.8 V, IDCDC_LOAD=50 mA, Heavy Drive configuration,
FDCDC_LN=8 MHz, unless otherwise indicated.
Table 4.3. DC-DC Converter
Parameter
Symbol
Test Condition
Min
TBD
2.4
Typ
Max
3.8
Unit
V
Input voltage range
VDCDC_I
Bypass mode
-
-
Low noise (LN) or low power (LP)
mode, 1.8 V output, 200 mA load
current
3.8
V
Output voltage range
VDCDC_O
VR
1.8V configuration
1.8
-
-
-
-
V
Steady-state output ripple
ESR=50 Ω, ESL=2 nH on 1 μF fil-
ter cap.
3
mVpp
CCM Mode (LNFORCECCM1 =
1), Load changes between 0 mA
and 100 mA
Output voltage under/over-
shoot
VOV
-
-
100
150
-
-
mV
mV
DCM Mode (LNFORCECCM1 =
0), Load changes between 0 mA
and 10 mA
DC line regulation
DC load regulation
Quiescent current
VREG
Input changes between 3.8 V and
2.4 V
-
-
-
0.1
0.1
50
-
-
-
%
%
IREG
Load changes between 0 mA and
100 mA in CCM mode
IDCDC_Q
Low power (LP) mode, lowest
bias setting (LPCMPBIAS1 =
BIAS0)
nA
Low noise (LN) mode, DCM con-
figuration (LNFORCECCM1 = 0)
-
-
0.3
0.8
-
-
-
mA
mA
Low noise (LN) mode, CCM con-
figuration (LNFORCECCM1 = 1)
Regulation DC Accuracy
ACCDC
Low noise (LN) mode, 1.8 V target
output
TBD
TBD
-
-
mV
mV
Low power (LP) mode,
LPCMPBIAS1 = 0, 1.8 V target
output
Low power (LP) mode,
TBD
-
mV
LPCMPBIAS1 = 3, 1.8 V target
output
Max load current
ILOAD_MAX
Low noise (LN) mode
-
-
200
10
mA
mA
Low power (LP) mode,
LPCMPBIAS1 = 3
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EFM32JG1 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Capacitance of DCDC output CDCDC
capacitor
1
-
10
μF
Inductance of DCDC output LDCDC
inductor
-
4.7
-
μH
Resistance in Bypass mode RBYP
TBD
0.8
-
TBD
Ω
Peak current limit range
Peak current limit step
IIPK
20
-
640
mA
mA
mA
mA
Light drive2
IPK_STEP
20
40
80
-
-
-
Medium Drive2
Heavy Drive2
-
-
Note:
1. In EMU_DCDCMISCCTRL register
2. Drive levels are defined by configuration of the PSLICESEL and NSLICESEL registers. Light Drive: PSLICESEL=NSLICESEL=3;
Medium Drive: PSLICESEL=NSLICESEL=7; Heavy Drive: PSLICESEL=NSLICESEL=15.
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EFM32JG1 Data Sheet
Electrical Specifications
4.1.4 Current Consumption
4.1.4.1 Current Consumption 1.85V without DC/DC
Table 4.4. Current Consumption 1.85V without DC/DC
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Current consumption in EM0 IACTIVE
Active mode, All peripherals
disabled
38.4 MHz crystal, CPU running
while loop from flash
-
128
-
μA/MHz
38 MHz HFRCO, CPU running
Prime from flash
-
-
-
-
-
87
-
-
-
-
-
μA/MHz
μA/MHz
μA/MHz
μA/MHz
μA/MHz
38 MHz HFRCO, CPU running
while loop from flash
103
112
105
235
38 MHz HFRCO, CPU running
CoreMark from flash
26 MHz HFRCO, CPU running
while loop from flash
1 MHz HFRCO, CPU running
while loop from flash
Current consumption in EM1 IEM1
Sleep mode. All peripherals
disabled
38.4 MHz crystal
38 MHz HFRCO
26 MHz HFRCO
1 MHz HFRCO
-
-
-
-
-
61
35
-
-
-
-
-
μA/MHz
μA/MHz
μA/MHz
μA/MHz
μA
37
167
3.36
Current consumption in EM2 IEM2
Deep Sleep mode.
Full RAM retention and RTCC
running from LFXO
4 kB RAM retention and RTCC
running from LFRCO
-
-
-
-
3.13
2.84
1.08
0.64
-
-
-
-
μA
μA
μA
μA
Current consumption in EM3 IEM3
Stop mode
Full RAM retention and CRYO-
TIMER running from ULFRCO
Current consumption in
EM4H Hibernate mode
IEM4
128 byte RAM retention, RTCC
running from LFXO
128 byte RAM retention, CRYO-
TIMER running from ULFRCO
128 byte RAM retention, no RTCC
No RAM retention, no RTCC
-
-
0.63
0.02
-
-
μA
μA
Current consumption in
EM4S Shutoff mode
IEM4S
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EFM32JG1 Data Sheet
Electrical Specifications
4.1.4.2 Current Consumption 3.3V without DC/DC
Table 4.5. Current Consumption 3.3V without DC/DC
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Current consumption in EM0 IACTIVE
Active mode, All peripherals
disabled
38.4 MHz crystal, CPU running
while loop from flash
-
129
-
μA/MHz
38 MHz HFRCO, CPU running
Prime from flash
-
-
-
-
-
87
-
-
-
-
-
μA/MHz
μA/MHz
μA/MHz
μA/MHz
μA/MHz
38 MHz HFRCO, CPU running
while loop from flash
103
112
105
237
38 MHz HFRCO, CPU running
CoreMark from flash
26 MHz HFRCO, CPU running
while loop from flash
1 MHz HFRCO, CPU running
while loop from flash
Current consumption in EM1 IEM1
Sleep mode. All peripherals
disabled
38.4 MHz crystal
38 MHz HFRCO
26 MHz HFRCO
1 MHz HFRCO
-
-
-
-
-
61
35
-
-
-
-
-
μA/MHz
μA/MHz
μA/MHz
μA/MHz
μA
37
170
3.47
Current consumption in EM2 IEM2
Deep Sleep mode.
Full RAM retention and RTCC
running from LFXO
4 kB RAM retention and RTCC
running from LFRCO
-
-
-
-
3.35
2.92
1.13
0.67
-
-
-
-
μA
μA
μA
μA
Current consumption in EM3 IEM3
Stop mode
Full RAM retention and CRYO-
TIMER running from ULFRCO
Current consumption in
EM4H Hibernate mode
IEM4
128 byte RAM retention, RTCC
running from LFXO
128 byte RAM retention, CRYO-
TIMER running from ULFRCO
128 byte RAM retention, no RTCC
no RAM retention, no RTCC
-
-
0.66
0.04
-
-
μA
μA
Current consumption in
EM4S Shutoff mode
IEM4S
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EFM32JG1 Data Sheet
Electrical Specifications
4.1.4.3 Current Consumption 3.3V with DC/DC
Table 4.6. Current Consumption 3.3V with DC/DC
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Current consumption in EM0 IACTIVE
Active mode. All peripherals
disabled, DCDC in LowNoise
mode
38.4 MHz crystal, CPU running
while loop from flash.
-
87
-
μA/MHz
38 MHz HFRCO, CPU running
Prime from flash
-
-
-
-
63
72
78
79
-
-
-
-
μA/MHz
μA/MHz
μA/MHz
μA/MHz
38 MHz HFRCO, CPU running
while loop from flash
38 MHz HFRCO, CPU running
CoreMark from flash
26 MHz HFRCO, CPU running
while loop from flash
Current consumption in EM1 IEM1
Sleep mode. All peripherals
disabled, DCDC in LowPow-
er mode.
38.4 MHz crystal
38 MHz HFRCO
26 MHz HFRCO
1 MHz HFRCO
-
-
-
-
-
39
23
-
-
-
-
-
μA/MHz
μA/MHz
μA/MHz
μA/MHz
μA
25
142
1.4
Current consumption in EM2 IEM2
Deep Sleep mode.
Full RAM retention and RTCC
running from LFXO
4 kB RAM retention and RTCC
running from LFRCO
-
-
-
-
1.4
1.1
0.9
0.6
-
-
-
-
μA
μA
μA
μA
Current consumption in EM3 IEM3
Stop mode
Full RAM retention and CRYO-
TIMER running from ULFRCO
Current consumption in
EM4H Hibernate mode
IEM4
128 byte RAM retention, RTCC
running from LFXO
128 byte RAM retention, CRYO-
TIMER running from ULFRCO
128 byte RAM retention, no RTCC
no RAM retention, no RTCC
-
-
0.6
-
-
μA
μA
Current consumption in
EM4S Shutoff mode
IEM4S
0.03
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EFM32JG1 Data Sheet
Electrical Specifications
4.1.5 Wake up times
Table 4.7. Wake up times
Parameter
Symbol
Test Condition
Min
Typ
10.7
3
Max
Unit
μs
Wake up from EM2 Deep
Sleep
tEM2_WU
Code execution from flash
Code execution from RAM
Executing from flash
-
-
-
-
-
-
-
-
-
-
μs
Wake up from EM3 Stop
tEM3_WU
10.7
3
μs
Executing from RAM
μs
Wake up from EM4H Hiber- tEM4H_WU
nate 1
Executing from flash
60
μs
Wake up from EM4S Shut-
off1
tEM4S_WU
-
290
-
μs
Note:
1. Time from wakeup request until first instruction is executed. Wakeup results in device reset.
4.1.6 Brown Out Detector
Table 4.8. Brown Out Detector
Parameter
Symbol
Test Condition
DVDD rising
Min
Typ
Max
Unit
V
DVDDBOD threshold
VDVDDBOD
-
-
-
TBD
DVDD falling
TBD
-
V
DVDD BOD hysteresis
DVDD response time
AVDD BOD threshold
VDVDDBOD_HYST
-
24
2.4
-
-
mV
μs
V
tDVDDBOD_DELAY Supply drops at 0.1V/μs rate
-
-
VAVDDBOD
AVDD rising
AVDD falling
-
1.85
TBD
-
-
V
AVDD BOD hysteresis
AVDD response time
EM4 BOD threshold
VAVDDBOD_HYST
-
21
2.4
-
-
mV
μs
V
tAVDDBOD_DELAY Supply drops at 0.1V/μs rate
-
-
VEM4DBOD
AVDD rising
AVDD falling
-
TBD
TBD
-
-
-
-
V
EM4 BOD hysteresis
EM4 response time
VEM4BOD_HYST
-
-
46
TBD
mV
nS
tEM4BOD_DELAY Supply drops at 0.1V/μs rate
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EFM32JG1 Data Sheet
Electrical Specifications
4.1.7 Oscillators
4.1.7.1 LFXO
Table 4.9. LFXO
Parameter
Symbol
Test Condition
Min
Typ
32.768
-
Max
-
Unit
kHz
kΩ
Crystal frequency
fLFXO
-
-
Supported crystal equivalent ESRLFXO
series resistance (ESR)
70
Supported range of crystal
load capacitance 1
CLFXO_CL
6
8
-
-
18
40
pF
pF
On-chip tuning cap range 2
CLFXO_T
On each of LFXTAL_N and
LFXTAL_P pins
On-chip tuning cap step size SSLFXO
-
-
0.25
273
-
-
pF
nA
ESR = 30 kΩ, CL=12.5 pF, GAIN4
= 3, AGC4 = 1
LFXO current consumption
on AVDD 3after startup
ILFXO_ANA
ESR=30 kΩ, CL=12.5 pF, GAIN4
=2
Start- up time
tLFXO
-
308
-
ms
Note:
1. Total load capacitance as seen by the crystal
2. The effective load capacitance seen by the crystal will be CLFXO_T /2. This is because each XTAL pin has a tuning cap and the
two caps will be seen in series by the crystal.
3. Current consumption on DVDD instead if ANASW=1 in EMU_PWRCTRL register
4. In CMU_LFXOCTRL register
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EFM32JG1 Data Sheet
Electrical Specifications
4.1.7.2 HFXO
Table 4.10. HFXO
Parameter
Symbol
Test Condition
Min
38
-
Typ
38.4
-
Max
40
Unit
MHz
Ω
Crystal Frequency
fHFXO
Supported crystal equivalent ESRHFXO
series resistance (ESR)
Crystal frequency 38.4 MHz
60
Supported range of crystal
load capacitance 1
CHFXO_CL
6
-
12
pF
On-chip tuning cap range 2
CHFXO_T
SSHFXO
tHFXO
On each of HFXTAL_N and
HFXTAL_P pins
9
-
20
25
-
pF
pF
μs
On-chip tuning capacitance
step
0.04
300
Startup time
38.4 MHz: ESR=50 Ω, CL = 10
pF, BOOST3 = 2
-
-
Frequency Tolerance for the FTHFXO
crystal
38.4 MHz, ESR = 50 Ω, CL = 10
pF
-40
-
40
ppm
Note:
1. Total load capacitance as seen by the crystal
2. The effective load capacitance seen by the crystal will be CHFXO_T /2. This is because each XTAL pin has a tuning cap and the
two caps will be seen in series by the crystal.
3. In CMU_HFXOCTRL register
4.1.7.3 LFRCO
Table 4.11. LFRCO
Parameter
Symbol
fLFRCO
Test Condition
Min
Typ
32.768
500
Max
Unit
kHz
μs
Oscillation frequency
Startup time
TBD
TBD
tLFRCO
-
-
-
-
Current consumption on
AVDD 1
ILFRCOANA
TBD
nA
Note:
1. Current consumption on DVDD instead if ANASW=1 in EMU_PWRCTRL register
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EFM32JG1 Data Sheet
Electrical Specifications
4.1.7.4 HFRCO and AUXHFRCO
Table 4.12. HFRCO and AUXHFRCO
Parameter
Symbol
Test Condition
Min
Typ
38
32
26
19
16
13
7
Max
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
Oscillation frequency
fHFRCO
38 MHz frequency band
32 MHz frequency band
26 MHz frequency band
19 MHz frequency band
16 MHz frequency band
13 MHz frequency band
7 MHz frequency band
4 MHz frequency band
2 MHz frequency band
1 MHz frequency band
fHFRCO ≥ 19 MHz
4 < fHFRCO < 19 MHz
fHFRCO ≤ 4 MHz
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
4
TBD
TBD
2
TBD
TBD
1
TBD
Start-up time
tHFRCO
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
300
1
-
-
μs
2.5
43
37
31
25
22
19
12
10
8
-
μs
Current consumption on
DVDD
IHFRCODIG
fHFRCO = 38 MHz
fHFRCO = 32 MHz
fHFRCO = 26 MHz
fHFRCO = 19 MHz
fHFRCO = 16 MHz
fHFRCO = 13 MHz
fHFRCO = 7 MHz
-
μA
-
μA
-
μA
TBD
μA
-
μA
-
μA
-
μA
fHFRCO = 4 MHz
-
μA
fHFRCO = 2 MHz
-
μA
fHFRCO = 1 MHz
7
-
μA
Current consumption on
AVDD 1
IHFRCOANA
fHFRCO = 38 MHz
fHFRCO = 32 MHz
fHFRCO = 26 MHz
fHFRCO = 19 MHz
fHFRCO = 16 MHz
fHFRCO = 13 MHz
fHFRCO = 7 MHz
161
134
116
101
88
81
69
23
23
23
-
μA
-
μA
-
μA
TBD
μA
-
-
-
-
-
-
μA
μA
μA
fHFRCO = 4 MHz
μA
fHFRCO = 2 MHz
μA
fHFRCO = 1 MHz
μA
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EFM32JG1 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
0.8
0.1
0.2
Max
Unit
%
Step size
SSHFRCO
Coarse (% of period)
Fine (% of period)
-
-
-
-
-
-
%
Period Jitter
PJHFRCO
% RMS
Note:
1. Current consumption on DVDD instead if ANASW=1 in EMU_PWRCTRL register
4.1.7.5 ULFRCO
Table 4.13. ULFRCO
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Oscillation frequency
fULFRCO
TBD
1
TBD
kHz
4.1.8 Flash Memory Characteristics
Table 4.14. Flash Memory Characteristics1
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Flash erase cycles before
failure
ECFLASH
10000
-
-
cycles
Flash data retention
RETFLASH
tW_PROG
TAMB<85°C
10
20
-
-
years
μs
Word (32-bit) programming
time
26
40
Page erase time
Mass erase time
tPERASE
tMERASE
tDERASE
IERASE
20
20
-
27
27
60
-
40
40
TBD
3
ms
ms
ms
mA
mA
Device erase time2
Page erase current3
-
Mass or Device erase cur-
rent3
-
-
5
Write current3
IWRITE
-
-
3
mA
Note:
1. Flash data retention information is published in the Quarterly Quality and Reliability Report.
2. Device erase is issued over the AAP interface and erases all flash, SRAM, the Lock Bit (LB) page, and the User data page Lock
Word (ULW)
3. Measured at 25°C
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EFM32JG1 Data Sheet
Electrical Specifications
4.1.9 GPIO
Table 4.15. GPIO
Parameter
Symbol
VIOIL
Test Condition
Min
-
Typ
Max
Unit
V
Input low voltage
Input high voltage
-
-
-
IOVDD*0.3
VIOIH
IOVDD*0.7
IOVDD*0.8
-
-
V
Output high voltage relative VIOOH
to IOVDD
Sourcing 3 mA, VDD ≥ 3 V,
V
DRIVESTRENGTH1 = WEAK
Sourcing 1.2 mA, VDD ≥ 1.62 V,
IOVDD*0.6
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
DRIVESTRENGTH1 = WEAK
Sourcing 20 mA, VDD ≥ 3 V,
IOVDD*0.8
-
DRIVESTRENGTH1 = STRONG
Sourcing 8 mA, VDD ≥ 1.62 V,
IOVDD*0.6
-
DRIVESTRENGTH1 = STRONG
Sinking 3 mA, VDD ≥ 3 V,
Output low voltage relative to VIOOL
IOVDD
-
-
-
-
IOVDD*0.2
IOVDD*0.4
IOVDD*0.2
IOVDD*0.4
DRIVESTRENGTH1 = WEAK
Sinking 1.2 mA, VDD ≥ 1.62 V,
DRIVESTRENGTH1 = WEAK
Sinking 20 mA, VDD ≥ 3 V,
DRIVESTRENGTH1 = STRONG
Sinking 8 mA, VDD ≥ 1.62 V,
DRIVESTRENGTH1 = STRONG
GPIO ≤ IOVDD
Input leakage current
IIOLEAK
-
-
0.1
3.3
TBD
15
nA
μA
Input leakage current on
I5VTOLLEAK
IOVDD < GPIO ≤ IOVDD + 2 V
5VTOL pads above IOVDD
I/O pin pull-up resistor
RPU
TBD
TBD
TBD
43
43
25
TBD
TBD
TBD
kΩ
kΩ
ns
I/O pin pull-down resistor
RPD
Pulse width of pulses re-
moved by the glitch suppres-
sion filter
tIOGLITCH
Output fall time, From 70%
to 30% of VIO
tIOOF
CL = 50pF,
-
-
TBD
TBD
-
-
ns
ns
DRIVESTRENGTH1 = STRONG,
SLEWRATE1 = 0x6
CL = 50pF,
DRIVESTRENGTH1 = WEAK,
SLEWRATE1 = 0x6
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EFM32JG1 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output rise time, From 30% tIOOR
to 70% of VIO
CL = 50pF,
-
TBD
-
ns
DRIVESTRENGTH1 = STRONG,
SLEWRATE = 0x61
CL = 50pF,
-
TBD
-
ns
DRIVESTRENGTH1 = WEAK,
SLEWRATE1 = 0x6
Note:
1. In GPIO_Pn_CTRL register
4.1.10 VMON
Table 4.16. VMON
Test Condition
Parameter
Symbol
IVMON
Min
Typ
Max
Unit
VMON Supply Current
In EM0 or EM1, 1 supply moni-
tored
-
5.8
-
μA
In EM0 or EM1, 4 supplies moni-
tored
-
-
-
11.8
62
-
-
-
μA
nA
nA
In EM2, EM3 or EM4, 1 supply
monitored
In EM2, EM3 or EM4, 4 supplies
monitored
99
VMON Loading of Monitored ISENSE
Supply
In EM0 or EM1
-
2
2
-
μA
nA
V
In EM2, EM3 or EM4
-
-
Threshold range
VVMON_RANGE
TBD
-
TBD
Threshold step size
NVMON_STESP
Coarse
-
-
-
-
200
20
500
26
-
-
-
-
mV
mV
ns
Fine
Response time
Hysteresis
tVMON_RES
Supply drops at 1V/μs rate
VVMON_HYST
mV
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EFM32JG1 Data Sheet
Electrical Specifications
4.1.11 ADC
Table 4.17. ADC
Parameter
Symbol
Test Condition
Min
Typ
Max
12
Unit
Bits
V
Resolution
VRESOLUTION
VADCIN
6
0
-
-
-
-
Input voltage range
Single ended
Differential
2*VREF
VREF
VAVDD
-VREF
1
V
Input range of external refer- VADCREFIN_P
ence voltage, single ended
and differential
V
Power supply rejection1
PSRRADC
At DC
At DC
-
-
80
80
-
-
dB
dB
Analog input common mode CMRRADC
rejection ratio
Current on DVDD, using in- IADCDIG_CONTI-
1 Msps / 16 MHz ADCCLK,
BIASPROG3 = 0
-
145
-
μA
ternal reference buffer. Con-
NOUS
tinous operation. WARMUP-
MODE2 = KEEPADCWARM
250 ksps / 4 MHz ADCCLK, BIA-
SPROG3 = 6
-
-
90
85
-
-
μA
μA
62.5 ksps / 1 MHz ADCCLK,
BIASPROG3 = 15
Current on AVDD4, using in-
ternal reference buffer. Con-
tinous operation. WARMUP-
IADCANA_CONTI- 1 Msps / 16 MHz ADCCLK,
-
286
-
μA
NOUS
BIASPROG3 = 0
MODE2 = KEEPADCWARM
250 ksps / 4 MHz ADCCLK, BIA-
SPROG3 = 6
-
-
155
102
-
-
μA
μA
62.5 ksps / 1 MHz ADCCLK,
BIASPROG3 = 15
Current on AVDD4 , using in-
ternal reference buffer. Duty-
cycled operation. WARMUP-
IADCANA_NORMAL 35 ksps / 16 MHz ADCCLK,
-
-
-
-
44
6
-
-
-
-
μA
μA
μA
μA
BIASPROG3 = 0
MODE2 = NORMAL
5 ksps / 16 MHz ADCCLK,
BIASPROG3 = 0
Current on AVDD4, using in-
ternal reference buffer. Duty-
cycled operation. WARMUP-
MODE2 = KEEPINSTANDBY
or KEEPINSLOWACC
IADCANA_STAND- 125 ksps / 16 MHz ADCCLK,
117
78
BY
BIASPROG3 = 0
5 ksps / 16 MHz ADCCLK,
BIASPROG3 = 0
ADC Clock Frequency
Throughput rate
fADCCLK
-
-
-
-
-
-
-
16
1
-
MHz
Msps
fADCRATE
Conversion time5
tADCCONV
6 bit
7
cycles
cycles
cycles
10 bit
12 bit
11
13
-
-
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Preliminary Rev. 0.31 | 24
EFM32JG1 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
WARMUPMODE2 = NORMAL
Startup time of reference
generator and ADC core in
NORMAL mode
tADCSTART
-
-
5
μs
WARMUPMODE2 = KEEPIN-
From standby mode
-
-
1
μs
STANDBY or KEEPINSLOWACC
SNDR at 1Msps and fin
10kHz
=
SNDRADC
Internal reference, 2.5 V full-scale,
differential (-1.25, 1.25)
TBD
67
68
-
-
-
-
dB
dB
dB
μV
vrefp_in = 1.25 V direct mode with
2.5 V full-scale, differential
-
-
-
Spurious-Free Dynamic
Range (SFDR)
SFDRADC
1 MSamples/s, 10 kHz full-scale
sine wave
75
Input referred ADC noise,
rms
VREF_NOISE
Including quantization noise and
distortion
380
Offset Error
VADCOFFSETERR
VADC_GAIN
TBD
1
-0.2
-1
TBD
TBD
-
LSB
%
Gain error in ADC
Using internal reference
Using external reference
12 bit resolution
-
-
%
Differential non-linearity
(DNL)
DNLADC
INLADC
-1
-
TBD
LSB
Integral non-linearity (INL),
End point method
12 bit resolution
TBD
-
-
TBD
-
LSB
Temperature Sensor Slope
MTSENSE
-1.84
mV/°C
Note:
1. PSRR is referenced to AVDD when ANASW=0 and to DVDD when ANASW=1 in EMU_PWRCTRL
2. In ADCn_CNTL register
3. In ADCn_BIASPROG register
4. Current consumption on DVDD instead if ANASW=1 in EMU_PWRCTRL register
5. Derived from ADCCLK
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Preliminary Rev. 0.31 | 25
EFM32JG1 Data Sheet
Electrical Specifications
4.1.12 IDAC
Table 4.18. IDAC
Parameter
Symbol
Test Condition
Min
-
Typ
Max
-
Unit
-
Number of Ranges
Output Current
NIDAC_RANGES
IIDAC_OUT
4
-
RANGSEL1 = RANGE0
RANGSEL1 = RANGE1
RANGSEL1 = RANGE2
RANGSEL1 = RANGE3
0.05
1.6
μA
1.6
0.5
2
-
-
4.7
16
64
-
μA
μA
μA
-
Linear steps within each
range
NIDAC_STEPS
-
32
RANGSEL1 = RANGE0
RANGSEL1 = RANGE1
RANGSEL1 = RANGE2
RANGSEL1 = RANGE3
Step size
SSIDAC
-
50
100
500
2
-
nA
nA
nA
μA
%
-
-
-
-
-
-
Total Accuracy, STEPSEL1 =
0x10
ACCIDAC
Continuous mode, AVDD=3.3V, T
= 25°C
TBD
-
TBD
Continuous mode
EM2 or EM3
TBD
TBD
-
-
-
TBD
TBD
-
%
%
Start up time
tIDAC_SU
Output within 1% of steady state
value
5
μs
Settling time, (output settled tIDAC_SETTLE
within 1% of steady state val-
ue)
Range setting is changed
Step value is changed
-
-
5
1
-
-
μs
μs
Current consumption in con- IIDAC
tinuous mode 2
Source mode, excluding output
current
-
-
-
8.9
12
-
-
-
μA
μA
%
Sink mode, excluding output cur-
rent
Output voltage compliance in ICOMP_SRC
source mode, source current
change relative to current
sourced at 0 V
RANGESEL1=0, output voltage =
min(VIOVDD, VAVDD2-100 mv)
0.16
RANGESEL1=1, output voltage =
min(VIOVDD, VAVDD2-100 mV)
-
-
-
0.08
0.03
0.03
-
-
-
%
%
%
RANGESEL1=2, output voltage =
min(VIOVDD, VAVDD2-150 mV)
RANGESEL1=3, output voltage =
min(VIOVDD, VAVDD2-250 mV)
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Preliminary Rev. 0.31 | 26
EFM32JG1 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output voltage compliance in ICOMP_SINK
sink mode, sink current
RANGESEL1=0, output voltage =
100 mV
-
0.82
-
%
change relative to current
sunk at IOVDD
RANGESEL1=1, output voltage =
100 mV
-
-
-
0.65
0.4
-
-
-
%
%
%
RANGESEL1=2, output voltage =
150 mV
RANGESEL1=3, output voltage =
250 mV
0.25
Note:
1. In IDAC_CURPROG register
2. The IDAC is supplied by either AVDD, DVDD, or IOVDD based on the setting of ANASW in the EMU_PWRCTRL register and
PWRSEL in the IDAC_CTRL register. Setting PWRSEL to 1 selects IOVDD. With PWRSEL cleared to 0, ANASW selects be-
tween AVDD (0) and DVDD (1).
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Preliminary Rev. 0.31 | 27
EFM32JG1 Data Sheet
Electrical Specifications
4.1.13 Analog Comparator (ACMP)
Table 4.19. ACMP
Parameter
Symbol
VACMPIN
Test Condition
Min
Typ
Max
Unit
Input voltage range
CMPVDD =
ACMPn_CTRL_PWRSEL 1
0
-
CMPVDD
V
BIASPROG2 = 1, FULLBIAS2 = 0
Active current not including
voltage reference
IACMP
-
-
50
-
-
nA
nA
BIASPROG2 = 0x10, FULLBIAS2
= 0
306
BIASPROG2 = 0x20, FULLBIAS2
= 1
-
-
74
50
TBD
-
μA
nA
Current consumption of inter- IACMPREF
nal voltage reference,
VLP selected as input using 2.5V
Reference / 4 (0.625V)
VLP selected as input using VDD
-
-
20
3
-
-
nA
μA
VBDIV selected as input using
1.25 V reference / 1
VADIV selected as input using
VDD/1
-
2
-
μA
HYSTSEL3 = HYST0
HYSTSEL3 = HYST1
HYSTSEL3 = HYST2
HYSTSEL3 = HYST3
HYSTSEL3 = HYST4
HYSTSEL3 = HYST5
HYSTSEL3 = HYST6
HYSTSEL3 = HYST7
Hysteresis
VACMPHYST
-
-
-
-
-
-
-
-
-
0
TBD
mV
mV
mV
mV
mV
mV
mV
mV
μs
12
22
30
36
41
47
52
30
-
-
-
-
-
-
-
-
BIASPROG2 = 1, FULLBIAS2 = 0
4
Comparator delay
tACMPDELAY
BIASPROG2 = 0x10, FULLBIAS2
= 0 4
-
-
-
3.7
35
-
-
μs
ns
μs
BIASPROG2 = 0x20, FULLBIAS2
= 1 4
BIASPROG2 =0x07, FULLBIAS2
= 1 4
Startup time of reference
generator
tACMPREF
TBD
Offset voltage
VACMPOFFSET
VACMPREF
-
-
TBD
TBD
TBD
mV
V
Reference Voltage
Internal 1.25 V reference
Internal 2.5 V reference
TBD
TBD
1.25
2.5
V
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Preliminary Rev. 0.31 | 28
EFM32JG1 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
CSRESSEL5 = 0
CSRESSEL5 = 1
CSRESSEL5 = 2
CSRESSEL5 = 3
CSRESSEL5 = 4
CSRESSEL5 = 5
CSRESSEL5 = 6
CSRESSEL5 = 7
Min
Typ
Max
Unit
Capacitive Sense Internal
Resistance
RCSRES
-
inf
-
kΩ
-
-
-
-
-
-
-
15
27
-
-
-
-
-
-
-
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
39
51
102
164
239
Note:
1. CMPVDD is a supply chosen by the setting in ACMPn_CTRL_PWRSEL and may be IOVDD, AVDD or DVDD
2. In ACMPn_CTRL register
3. In ACMPn_HYSTERESIS register
4. ± 100 mV differential
5. In ACMPn_INPUTSEL register
The total ACMP current is the sum of the contributions from the ACMP and its internal voltage reference as given as:
IACMPTOTAL = IACMP + IACMPREF
IACMPREF is zero if an external voltage reference is used.
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Preliminary Rev. 0.31 | 29
EFM32JG1 Data Sheet
Electrical Specifications
4.1.14 I2C
I2C Standard-mode (Sm)
Table 4.20. I2C Standard-mode (Sm)1
Test Condition
Parameter
Symbol
Min
Typ
Max
Unit
SCL clock frequency2
SCL clock low time
SCL clock high time
SDA set-up time
fSCL
0
-
100
kHz
tLOW
4.7
4
-
-
-
-
-
-
μs
μs
ns
ns
μs
tHIGH
-
tSU,DAT
tHD,DAT
250
100
4.7
-
3450
-
SDA hold time3
Repeated START condition tSU,STA
set-up time
(Repeated) START condition tHD,STA
hold time
4
-
-
μs
STOP condition set-up time tSU,STO
4
-
-
-
-
μs
μs
Bus free time between a
tBUF
4.7
STOP and START condition
Note:
1. For CLHR set to 0 in the I2Cn_CTRL register
2. For the minimum HFPERCLK frequency required in Standard-mode, refer to the I2C chapter in the reference manual
3. The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW
)
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Preliminary Rev. 0.31 | 30
EFM32JG1 Data Sheet
Electrical Specifications
I2C Fast-mode (Fm)
Parameter
Table 4.21. I2C Fast-mode (Fm)1
Test Condition
Symbol
Min
Typ
Max
Unit
SCL clock frequency2
SCL clock low time
SCL clock high time
SDA set-up time
fSCL
0
-
400
kHz
tLOW
1.3
0.6
-
-
-
-
-
-
μs
μs
ns
ns
μs
tHIGH
-
tSU,DAT
tHD,DAT
100
100
0.6
-
900
-
SDA hold time3
Repeated START condition tSU,STA
set-up time
(Repeated) START condition tHD,STA
hold time
0.6
-
-
μs
STOP condition set-up time tSU,STO
0.6
1.3
-
-
-
-
μs
μs
Bus free time between a
tBUF
STOP and START condition
Note:
1. For CLHR set to 1 in the I2Cn_CTRL register
2. For the minimum HFPERCLK frequency required in Fast-mode, refer to the I2C chapter in the reference manual
3. The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW
)
I2C Fast-mode Plus (Fm+)
Table 4.22. I2C Fast-mode Plus (Fm+)1
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCL clock frequency2
SCL clock low time
SCL clock high time
SDA set-up time
fSCL
0
-
1000
kHz
tLOW
0.5
0.26
50
-
-
-
-
-
-
-
-
-
-
μs
μs
ns
ns
μs
tHIGH
tSU,DAT
tHD,DAT
SDA hold time
100
0.26
Repeated START condition tSU,STA
set-up time
(Repeated) START condition tHD,STA
hold time
0.26
-
-
μs
STOP condition set-up time tSU,STO
0.26
0.5
-
-
-
-
μs
μs
Bus free time between a
tBUF
STOP and START condition
Note:
1. For CLHR set to 0 or 1 in the I2Cn_CTRL register
2. For the minimum HFPERCLK frequency required in Fast-mode Plus, refer to the I2C chapter in the reference manual
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EFM32JG1 Data Sheet
Electrical Specifications
4.1.15 USART SPI
SPI Master Timing
Table 4.23. SPI Master Timing
Test Condition
Parameter
Symbol
Min
Typ
Max
Unit
SCLK period 1 2
tSCLK
2 *
tHFPERCLK
-
-
ns
CS to MOSI 1 2
tCS_MO
tSCLK_MO
tSU_MI
0
3
-
-
8
ns
ns
SCLK to MOSI 1 2
MISO setup time 1 2
20
IOVDD = 1.98 V
IOVDD = 3.0 V
56
37
6
-
-
-
-
-
-
ns
ns
ns
MISO hold time 1 2
tH_MI
Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0)
2. Measurement done with 8 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD
)
tCS_MO
CS
tSCKL_MO
SCLK
CLKPOL = 0
tSCLK
SCLK
CLKPOL = 1
MOSI
MISO
tSU_MI
tH_MI
Figure 4.1. SPI Master Timing Diagram
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Preliminary Rev. 0.31 | 32
EFM32JG1 Data Sheet
Electrical Specifications
SPI Slave Timing
Table 4.24. SPI Slave Timing
Test Condition
Parameter
Symbol
Min
Typ
Max
Unit
SCKL period 1 2
tSCLK_sl
2 *
tHFPERCLK
-
-
ns
SCLK high period1 2
SCLK low period 1 2
tSCLK_hi
3 *
tHFPERCLK
-
-
-
-
ns
ns
tSCLK_lo
3 *
tHFPERCLK
CS active to MISO 1 2
CS disable to MISO 1 2
MOSI setup time 1 2
MOSI hold time 1 2
tCS_ACT_MI
tCS_DIS_MI
tSU_MO
4
4
4
-
-
-
-
50
50
-
ns
ns
ns
ns
tH_MO
3 + 2 *
tHFPERCLK
-
SCLK to MISO 1 2
tSCLK_MI
16 +
tHFPERCLK
-
66 + 2 *
tHFPERCLK
ns
Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0)
2. Measurement done with 8 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD
)
tCS_ACT_MI
CS
tCS_DIS_MI
SCLK
CLKPOL = 0
tSCLK_HI
tSCLK_LO
SCLK
tSU_MO
CLKPOL = 1
tSCLK
tH_MO
MOSI
MISO
tSCLK_MI
Figure 4.2. SPI Slave Timing Diagram
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Preliminary Rev. 0.31 | 33
EFM32JG1 Data Sheet
Electrical Specifications
4.2 Typical Performance Curves
Default test conditions: CCM mode, LDCDC = 4.7 μH, CDCDC = 1.0 μF, VDCDC_I = 3.3 V, VDCDC_O = 1.8 V, FDCDC_LN = 8 MHz
Efficiency VS Load Current, LN mode
Efficiency VS Load current, LP mode
100
90
80
70
60
50
40
100
90
80
70
60
50
40
LP _ CMP _ BIAS 3
Heavy Drive
Medium Drive
Light Drive
LP _ CMP _ BIAS 2
LP _ CMP _ BIAS 1
LP _ CMP _ BIAS 0
100
101
Load,mA
102
10-3
10-2
10-1
Load,mA
100
101
Relative output droop VS Load current, LP mode
Ron VS supply voltage in bypass mode
10
5
2
1.5
1
SW _ PFET _ EN 0
SW _ PFET _ EN 1
0
-5
-10
-15
-20
-25
-30
LP _ CMP _ BIAS 3
LP _ CMP _ BIAS 2
LP _ CMP _ BIAS 1
LP _ CMP _ BIAS 0
0.5
10-3
10-2
10-1
Load,mA
100
101
2
2.5
3
3.5
4
VDD,V
LN (CCM) and LP mode transition (load: 5mA)
Load Step Response in LN (CCM) mode (Heavy Drive)
DVDD
60mV/div
offset:1.8V
DVDD
50mV/div
offset:1.8V
100mA
V
2V/div
I
LOAD
1mA
SW
offset:1.8V
10μs/div
100μs/div
Figure 4.3. DC-DC Converter Typical Performance Characteristics
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Preliminary Rev. 0.31 | 34
EFM32JG1 Data Sheet
Typical Connection Diagrams
5. Typical Connection Diagrams
5.1 Power
Typical power supply connections for direct supply, without using the internal dc-dc converter, are shown in the following figure.
VDD
Power plane
DVDD
AVDD_0
AVDD_1
DECOUPLE
IOVDD
CIOVDD
CAVDD_1 CAVDD_0
CDVDD
CDEC
EFM32
VREGVSS
Ground plane
Figure 5.1. EFM32JG1 Typical Application Circuit: Direct Supply Configuration without DC-DC converter
Typical power supply circuits using the internal dc-dc converter are shown below. The MCU operates from the dc-dc converter supply.
VDD
Power plane
VREGVDD
AVDD_0
AVDD_1
LVREGSW
VREGSW
DVDD
IOVDD
CAVDD_0
CAVDD_1
DECOUPLE
VREGVSS
CVREGSW
CDVDD CIOVDD
CDEC
EFM32
Ground plane
Figure 5.2. EFM32JG1 Typical Application Circuit: Configuration with DC-DC Converter
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Preliminary Rev. 0.31 | 35
EFM32JG1 Data Sheet
Typical Connection Diagrams
5.2 Other Connections
Other components or connections may be required to meet the system-level requirements. Application Note AN0002: "Hardware De-
sign Considerations" contains detailed information on these connections. Application Notes can be accessed on the Silicon Labs web-
site (www.silabs.com/32bit-appnotes).
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Preliminary Rev. 0.31 | 36
EFM32JG1 Data Sheet
Pin Definitions
6. Pin Definitions
6.1 EFM32JG1 QFN48 Definition
Figure 6.1. EFM32JG1 QFN48 Pinout
Table 6.1. Device Pinout
QFN48 Pin# and Name
Pin Alternate Functionality / Description
Timers Communication
Pin
Pin Name
#
Analog
Other
0
VSS
Ground
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Preliminary Rev. 0.31 | 37
EFM32JG1 Data Sheet
Pin Definitions
QFN48 Pin# and Name
Pin Alternate Functionality / Description
Pin
#
Pin Name
Analog
Timers
Communication
Other
TIM0_CC0 #24
TIM0_CC1 #23
TIM0_CC2 #22
TIM0_CDTI0 #21
TIM0_CDTI1 #20
TIM0_CDTI2 #19
TIM1_CC0 #24
BUSAX [ADC0:
APORT1XCH16
ACMP0:
APORT1XCH16
ACMP1:
US0_TX #24 US0_RX
#23 US0_CLK #22
US0_CS #21 US0_CTS
#20 US0_RTS #19
US1_TX #24 US1_RX
#23 US1_CLK #22
US1_CS #21 US1_CTS
#20 US1_RTS #19
LEU0_TX #24 LEU0_RX
#23 I2C0_SDA #24
I2C0_SCL #23
PRS_CH0 #0 PRS_CH1
#7 PRS_CH2 #6
APORT1XCH16]
PRS_CH3 #5 ACMP0_O
#24 ACMP1_O #24
DBG_SWCLKTCK #0
BOOT_TX
1
2
3
4
PF0
TIM1_CC1 #23
TIM1_CC2 #22
BUSBY [ADC0:
APORT2YCH16
ACMP0:
APORT2YCH16
ACMP1:
TIM1_CC3 #21 LE-
TIM0_OUT0 #24 LE-
TIM0_OUT1 #23
PCNT0_S0IN #24
PCNT0_S1IN #23
APORT2YCH16]
TIM0_CC0 #25
TIM0_CC1 #24
TIM0_CC2 #23
TIM0_CDTI0 #22
TIM0_CDTI1 #21
TIM0_CDTI2 #20
TIM1_CC0 #25
BUSAY [ADC0:
APORT1YCH17
ACMP0:
APORT1YCH17
ACMP1:
US0_TX #25 US0_RX
#24 US0_CLK #23
US0_CS #22 US0_CTS
#21 US0_RTS #20
US1_TX #25 US1_RX
#24 US1_CLK #23
US1_CS #22 US1_CTS
#21 US1_RTS #20
LEU0_TX #25 LEU0_RX
#24 I2C0_SDA #25
I2C0_SCL #24
PRS_CH0 #1 PRS_CH1
#0 PRS_CH2 #7
PRS_CH3 #6 ACMP0_O
#25 ACMP1_O #25
DBG_SWDIOTMS #0
BOOT_RX
APORT1YCH17]
PF1
PF2
PF3
TIM1_CC1 #24
TIM1_CC2 #23
BUSBX [ADC0:
APORT2XCH17
ACMP0:
APORT2XCH17
ACMP1:
TIM1_CC3 #22 LE-
TIM0_OUT0 #25 LE-
TIM0_OUT1 #24
PCNT0_S0IN #25
PCNT0_S1IN #24
APORT2XCH17]
TIM0_CC0 #26
TIM0_CC1 #25
TIM0_CC2 #24
TIM0_CDTI0 #23
TIM0_CDTI1 #22
TIM0_CDTI2 #21
TIM1_CC0 #26
BUSAX [ADC0:
APORT1XCH18
ACMP0:
APORT1XCH18
ACMP1:
US0_TX #26 US0_RX
#25 US0_CLK #24
US0_CS #23 US0_CTS
#22 US0_RTS #21
US1_TX #26 US1_RX
#25 US1_CLK #24
US1_CS #23 US1_CTS
#22 US1_RTS #21
LEU0_TX #26 LEU0_RX
#25 I2C0_SDA #26
I2C0_SCL #25
CMU_CLK0 #6
PRS_CH0 #2 PRS_CH1
#1 PRS_CH2 #0
PRS_CH3 #7 ACMP0_O
#26 ACMP1_O #26
DBG_TDO #0
APORT1XCH18]
TIM1_CC1 #25
TIM1_CC2 #24
BUSBY [ADC0:
APORT2YCH18
ACMP0:
APORT2YCH18
ACMP1:
TIM1_CC3 #23 LE-
TIM0_OUT0 #26 LE-
TIM0_OUT1 #25
PCNT0_S0IN #26
PCNT0_S1IN #25
DBG_SWO #0
GPIO_EM4WU0
APORT2YCH18]
TIM0_CC0 #27
TIM0_CC1 #26
TIM0_CC2 #25
TIM0_CDTI0 #24
TIM0_CDTI1 #23
TIM0_CDTI2 #22
TIM1_CC0 #27
BUSAY [ADC0:
APORT1YCH19
ACMP0:
APORT1YCH19
ACMP1:
US0_TX #27 US0_RX
#26 US0_CLK #25
US0_CS #24 US0_CTS
#23 US0_RTS #22
US1_TX #27 US1_RX
#26 US1_CLK #25
US1_CS #24 US1_CTS
#23 US1_RTS #22
LEU0_TX #27 LEU0_RX
#26 I2C0_SDA #27
I2C0_SCL #26
CMU_CLK1 #6
PRS_CH0 #3 PRS_CH1
#2 PRS_CH2 #1
PRS_CH3 #0 ACMP0_O
#27 ACMP1_O #27
DBG_TDI #0
APORT1YCH19]
TIM1_CC1 #26
TIM1_CC2 #25
BUSBX [ADC0:
APORT2XCH19
ACMP0:
APORT2XCH19
ACMP1:
TIM1_CC3 #24 LE-
TIM0_OUT0 #27 LE-
TIM0_OUT1 #26
PCNT0_S0IN #27
PCNT0_S1IN #26
APORT2XCH19]
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Preliminary Rev. 0.31 | 38
EFM32JG1 Data Sheet
Pin Definitions
QFN48 Pin# and Name
Pin Alternate Functionality / Description
Pin
#
Pin Name
Analog
Timers
Communication
Other
TIM0_CC0 #28
TIM0_CC1 #27
TIM0_CC2 #26
TIM0_CDTI0 #25
TIM0_CDTI1 #24
TIM0_CDTI2 #23
TIM1_CC0 #28
BUSAX [ADC0:
APORT1XCH20
ACMP0:
APORT1XCH20
ACMP1:
US0_TX #28 US0_RX
#27 US0_CLK #26
US0_CS #25 US0_CTS
#24 US0_RTS #23
US1_TX #28 US1_RX
#27 US1_CLK #26
US1_CS #25 US1_CTS
#24 US1_RTS #23
LEU0_TX #28 LEU0_RX
#27 I2C0_SDA #28
I2C0_SCL #27
PRS_CH0 #4 PRS_CH1
#3 PRS_CH2 #2
PRS_CH3 #1 ACMP0_O
#28 ACMP1_O #28
APORT1XCH20]
5
6
7
PF4
TIM1_CC1 #27
TIM1_CC2 #26
BUSBY [ADC0:
APORT2YCH20
ACMP0:
APORT2YCH20
ACMP1:
TIM1_CC3 #25 LE-
TIM0_OUT0 #28 LE-
TIM0_OUT1 #27
PCNT0_S0IN #28
PCNT0_S1IN #27
APORT2YCH20]
TIM0_CC0 #29
TIM0_CC1 #28
TIM0_CC2 #27
TIM0_CDTI0 #26
TIM0_CDTI1 #25
TIM0_CDTI2 #24
TIM1_CC0 #29
BUSAY [ADC0:
APORT1YCH21
ACMP0:
APORT1YCH21
ACMP1:
US0_TX #29 US0_RX
#28 US0_CLK #27
US0_CS #26 US0_CTS
#25 US0_RTS #24
US1_TX #29 US1_RX
#28 US1_CLK #27
US1_CS #26 US1_CTS
#25 US1_RTS #24
LEU0_TX #29 LEU0_RX
#28 I2C0_SDA #29
I2C0_SCL #28
PRS_CH0 #5 PRS_CH1
#4 PRS_CH2 #3
PRS_CH3 #2 ACMP0_O
#29 ACMP1_O #29
APORT1YCH21]
PF5
TIM1_CC1 #28
TIM1_CC2 #27
BUSBX [ADC0:
APORT2XCH21
ACMP0:
APORT2XCH21
ACMP1:
TIM1_CC3 #26 LE-
TIM0_OUT0 #29 LE-
TIM0_OUT1 #28
PCNT0_S0IN #29
PCNT0_S1IN #28
APORT2XCH21]
TIM0_CC0 #30
TIM0_CC1 #29
TIM0_CC2 #28
TIM0_CDTI0 #27
TIM0_CDTI1 #26
TIM0_CDTI2 #25
TIM1_CC0 #30
BUSAX [ADC0:
APORT1XCH22
ACMP0:
APORT1XCH22
ACMP1:
US0_TX #30 US0_RX
#29 US0_CLK #28
US0_CS #27 US0_CTS
#26 US0_RTS #25
CMU_CLK1 #7
US1_TX #30 US1_RX PRS_CH0 #6 PRS_CH1
#29 US1_CLK #28 #5 PRS_CH2 #4
US1_CS #27 US1_CTS PRS_CH3 #3 ACMP0_O
APORT1XCH22]
PF6
TIM1_CC1 #29
TIM1_CC2 #28
BUSBY [ADC0:
APORT2YCH22
ACMP0:
APORT2YCH22
ACMP1:
#26 US1_RTS #25
LEU0_TX #30 LEU0_RX
#29 I2C0_SDA #30
I2C0_SCL #29
#30 ACMP1_O #30
TIM1_CC3 #27 LE-
TIM0_OUT0 #30 LE-
TIM0_OUT1 #29
PCNT0_S0IN #30
PCNT0_S1IN #29
APORT2YCH22]
TIM0_CC0 #31
TIM0_CC1 #30
TIM0_CC2 #29
TIM0_CDTI0 #28
TIM0_CDTI1 #27
TIM0_CDTI2 #26
TIM1_CC0 #31
BUSAY [ADC0:
APORT1YCH23
ACMP0:
APORT1YCH23
ACMP1:
US0_TX #31 US0_RX
#30 US0_CLK #29
US0_CS #28 US0_CTS
#27 US0_RTS #26
US1_TX #31 US1_RX
#30 US1_CLK #29
US1_CS #28 US1_CTS
#27 US1_RTS #26
LEU0_TX #31 LEU0_RX
#30 I2C0_SDA #31
I2C0_SCL #30
CMU_CLK0 #7
PRS_CH0 #7 PRS_CH1
#6 PRS_CH2 #5
PRS_CH3 #4 ACMP0_O
#31 ACMP1_O #31
GPIO_EM4WU1
APORT1YCH23]
8
9
PF7
TIM1_CC1 #30
TIM1_CC2 #29
BUSBX [ADC0:
APORT2XCH23
ACMP0:
APORT2XCH23
ACMP1:
TIM1_CC3 #28 LE-
TIM0_OUT0 #31 LE-
TIM0_OUT1 #30
PCNT0_S0IN #31
PCNT0_S1IN #30
APORT2XCH23]
AVDD_1
Analog power supply 1.
silabs.com | Smart. Connected. Energy-friendly.
Preliminary Rev. 0.31 | 39
EFM32JG1 Data Sheet
Pin Definitions
QFN48 Pin# and Name
Pin Alternate Functionality / Description
Timers Communication
Pin
Pin Name
Analog
Other
#
10
11
HFXTAL_N
HFXTAL_P
High Frequency Crystal input pin.
High Frequency Crystal output pin.
Reset input, active low.To apply an external reset source to this pin, it is required to only drive this pin low
during reset, and let the internal pull-up ensure that reset is released.
12
RESETn
13
14
15
16
17
NC
NC
NC
NC
NC
No Connect.
No Connect.
No Connect.
No Connect.
No Connect.
TIM0_CC0 #17
TIM0_CC1 #16
US0_TX #17 US0_RX
TIM0_CC2 #15
TIM0_CDTI0 #14
TIM0_CDTI1 #13
TIM0_CDTI2 #12
TIM1_CC0 #17
BUSCY [ADC0:
APORT3YCH1 ACMP0:
APORT3YCH1 ACMP1:
APORT3YCH1 IDAC0:
APORT1YCH1]
#16 US0_CLK #15
US0_CS #14 US0_CTS
#13 US0_RTS #12
US1_TX #17 US1_RX
#16 US1_CLK #15
US1_CS #14 US1_CTS
#13 US1_RTS #12
LEU0_TX #17 LEU0_RX
#16 I2C0_SDA #17
I2C0_SCL #16
CMU_CLK0 #4
PRS_CH3 #8 PRS_CH4
#0 PRS_CH5 #6
PRS_CH6 #11
18
19
20
PD9
PD10
PD11
TIM1_CC1 #16
TIM1_CC2 #15
BUSDX [ADC0:
APORT4XCH1 ACMP0:
APORT4XCH1 ACMP1:
APORT4XCH1]
ACMP0_O #17
ACMP1_O #17
TIM1_CC3 #14 LE-
TIM0_OUT0 #17 LE-
TIM0_OUT1 #16
PCNT0_S0IN #17
PCNT0_S1IN #16
TIM0_CC0 #18
TIM0_CC1 #17
TIM0_CC2 #16
TIM0_CDTI0 #15
TIM0_CDTI1 #14
TIM0_CDTI2 #13
TIM1_CC0 #18
US0_TX #18 US0_RX
#17 US0_CLK #16
US0_CS #15 US0_CTS
#14 US0_RTS #13
US1_TX #18 US1_RX
#17 US1_CLK #16
US1_CS #15 US1_CTS
#14 US1_RTS #13
LEU0_TX #18 LEU0_RX
#17 I2C0_SDA #18
I2C0_SCL #17
BUSCX [ADC0:
APORT3XCH2 ACMP0:
APORT3XCH2 ACMP1:
APORT3XCH2 IDAC0:
APORT1XCH2]
CMU_CLK1 #4
PRS_CH3 #9 PRS_CH4
#1 PRS_CH5 #0
PRS_CH6 #12
TIM1_CC1 #17
TIM1_CC2 #16
BUSDY [ADC0:
APORT4YCH2 ACMP0:
APORT4YCH2 ACMP1:
APORT4YCH2]
ACMP0_O #18
ACMP1_O #18
TIM1_CC3 #15 LE-
TIM0_OUT0 #18 LE-
TIM0_OUT1 #17
PCNT0_S0IN #18
PCNT0_S1IN #17
TIM0_CC0 #19
TIM0_CC1 #18
TIM0_CC2 #17
TIM0_CDTI0 #16
TIM0_CDTI1 #15
TIM0_CDTI2 #14
TIM1_CC0 #19
US0_TX #19 US0_RX
#18 US0_CLK #17
US0_CS #16 US0_CTS
#15 US0_RTS #14
BUSCY [ADC0:
APORT3YCH3 ACMP0:
APORT3YCH3 ACMP1:
APORT3YCH3 IDAC0:
APORT1YCH3]
PRS_CH3 #10
US1_TX #19 US1_RX PRS_CH4 #2 PRS_CH5
#18 US1_CLK #17
US1_CS #16 US1_CTS
#15 US1_RTS #14
LEU0_TX #19 LEU0_RX
#18 I2C0_SDA #19
I2C0_SCL #18
#1 PRS_CH6 #13
ACMP0_O #19
ACMP1_O #19
TIM1_CC1 #18
TIM1_CC2 #17
BUSDX [ADC0:
APORT4XCH3 ACMP0:
APORT4XCH3 ACMP1:
APORT4XCH3]
TIM1_CC3 #16 LE-
TIM0_OUT0 #19 LE-
TIM0_OUT1 #18
PCNT0_S0IN #19
PCNT0_S1IN #18
silabs.com | Smart. Connected. Energy-friendly.
Preliminary Rev. 0.31 | 40
EFM32JG1 Data Sheet
Pin Definitions
QFN48 Pin# and Name
Pin Alternate Functionality / Description
Pin
#
Pin Name
Analog
Timers
Communication
Other
TIM0_CC0 #20
TIM0_CC1 #19
TIM0_CC2 #18
TIM0_CDTI0 #17
TIM0_CDTI1 #16
TIM0_CDTI2 #15
TIM1_CC0 #20
US0_TX #20 US0_RX
#19 US0_CLK #18
US0_CS #17 US0_CTS
#16 US0_RTS #15
BUSCX [ADC0:
APORT3XCH4 ACMP0:
APORT3XCH4 ACMP1:
APORT3XCH4 IDAC0:
APORT1XCH4]
PRS_CH3 #11
US1_TX #20 US1_RX PRS_CH4 #3 PRS_CH5
21
22
23
24
PD12
#19 US1_CLK #18
US1_CS #17 US1_CTS
#16 US1_RTS #15
LEU0_TX #20 LEU0_RX
#19 I2C0_SDA #20
I2C0_SCL #19
#2 PRS_CH6 #14
ACMP0_O #20
ACMP1_O #20
TIM1_CC1 #19
TIM1_CC2 #18
BUSDY [ADC0:
APORT4YCH4 ACMP0:
APORT4YCH4 ACMP1:
APORT4YCH4]
TIM1_CC3 #17 LE-
TIM0_OUT0 #20 LE-
TIM0_OUT1 #19
PCNT0_S0IN #20
PCNT0_S1IN #19
TIM0_CC0 #21
TIM0_CC1 #20
TIM0_CC2 #19
TIM0_CDTI0 #18
TIM0_CDTI1 #17
TIM0_CDTI2 #16
TIM1_CC0 #21
US0_TX #21 US0_RX
#20 US0_CLK #19
US0_CS #18 US0_CTS
#17 US0_RTS #16
BUSCY [ADC0:
APORT3YCH5 ACMP0:
APORT3YCH5 ACMP1:
APORT3YCH5 IDAC0:
APORT1YCH5]
PRS_CH3 #12
US1_TX #21 US1_RX PRS_CH4 #4 PRS_CH5
PD13
PD14
PD15
#20 US1_CLK #19
US1_CS #18 US1_CTS
#17 US1_RTS #16
LEU0_TX #21 LEU0_RX
#20 I2C0_SDA #21
I2C0_SCL #20
#3 PRS_CH6 #15
ACMP0_O #21
ACMP1_O #21
TIM1_CC1 #20
TIM1_CC2 #19
BUSDX [ADC0:
APORT4XCH5 ACMP0:
APORT4XCH5 ACMP1:
APORT4XCH5]
TIM1_CC3 #18 LE-
TIM0_OUT0 #21 LE-
TIM0_OUT1 #20
PCNT0_S0IN #21
PCNT0_S1IN #20
TIM0_CC0 #22
TIM0_CC1 #21
TIM0_CC2 #20
TIM0_CDTI0 #19
TIM0_CDTI1 #18
TIM0_CDTI2 #17
TIM1_CC0 #22
US0_TX #22 US0_RX
#21 US0_CLK #20
US0_CS #19 US0_CTS
#18 US0_RTS #17
BUSCX [ADC0:
APORT3XCH6 ACMP0:
APORT3XCH6 ACMP1:
APORT3XCH6 IDAC0:
APORT1XCH6]
CMU_CLK0 #5
PRS_CH3 #13
US1_TX #22 US1_RX PRS_CH4 #5 PRS_CH5
#21 US1_CLK #20
US1_CS #19 US1_CTS
#18 US1_RTS #17
LEU0_TX #22 LEU0_RX
#21 I2C0_SDA #22
I2C0_SCL #21
#4 PRS_CH6 #16
ACMP0_O #22
ACMP1_O #22
GPIO_EM4WU4
TIM1_CC1 #21
TIM1_CC2 #20
BUSDY [ADC0:
APORT4YCH6 ACMP0:
APORT4YCH6 ACMP1:
APORT4YCH6]
TIM1_CC3 #19 LE-
TIM0_OUT0 #22 LE-
TIM0_OUT1 #21
PCNT0_S0IN #22
PCNT0_S1IN #21
TIM0_CC0 #23
TIM0_CC1 #22
TIM0_CC2 #21
TIM0_CDTI0 #20
TIM0_CDTI1 #19
TIM0_CDTI2 #18
TIM1_CC0 #23
US0_TX #23 US0_RX
#22 US0_CLK #21
US0_CS #20 US0_CTS
#19 US0_RTS #18
BUSCY [ADC0:
APORT3YCH7 ACMP0:
APORT3YCH7 ACMP1:
APORT3YCH7 IDAC0:
APORT1YCH7]
CMU_CLK1 #5
PRS_CH3 #14
US1_TX #23 US1_RX PRS_CH4 #6 PRS_CH5
#22 US1_CLK #21
US1_CS #20 US1_CTS
#19 US1_RTS #18
LEU0_TX #23 LEU0_RX
#22 I2C0_SDA #23
I2C0_SCL #22
#5 PRS_CH6 #17
ACMP0_O #23
ACMP1_O #23
DBG_SWO #2
TIM1_CC1 #22
TIM1_CC2 #21
BUSDX [ADC0:
APORT4XCH7 ACMP0:
APORT4XCH7 ACMP1:
APORT4XCH7]
TIM1_CC3 #20 LE-
TIM0_OUT0 #23 LE-
TIM0_OUT1 #22
PCNT0_S0IN #23
PCNT0_S1IN #22
silabs.com | Smart. Connected. Energy-friendly.
Preliminary Rev. 0.31 | 41
EFM32JG1 Data Sheet
Pin Definitions
QFN48 Pin# and Name
Pin Alternate Functionality / Description
Pin
#
Pin Name
Analog
Timers
Communication
Other
TIM0_CC0 #0
TIM0_CC1 #31
TIM0_CC2 #30
TIM0_CDTI0 #29
TIM0_CDTI1 #28
TIM0_CDTI2 #27
TIM1_CC0 #0
TIM1_CC1 #31
TIM1_CC2 #30
TIM1_CC3 #29 LE-
TIM0_OUT0 #0 LE-
TIM0_OUT1 #31
PCNT0_S0IN #0
PCNT0_S1IN #31
ADC0_EXTN
US0_TX #0 US0_RX
#31 US0_CLK #30
US0_CS #29 US0_CTS
#28 US0_RTS #27
US1_TX #0 US1_RX
#31 US1_CLK #30
BUSCX [ADC0:
APORT3XCH8 ACMP0:
APORT3XCH8 ACMP1:
APORT3XCH8 IDAC0:
APORT1XCH8]
CMU_CLK1 #0
PRS_CH6 #0 PRS_CH7
#10 PRS_CH8 #9
25
26
27
28
PA0
US1_CS #29 US1_CTS PRS_CH9 #8 ACMP0_O
#28 US1_RTS #27
LEU0_TX #0 LEU0_RX
#31 I2C0_SDA #0
I2C0_SCL #31
#0 ACMP1_O #0
BUSDY [ADC0:
APORT4YCH8 ACMP0:
APORT4YCH8 ACMP1:
APORT4YCH8]
TIM0_CC0 #1
TIM0_CC1 #0
ADC0_EXTP
US0_TX #1 US0_RX #0
US0_CLK #31 US0_CS
#30 US0_CTS #29
US0_RTS #28 US1_TX
#1 US1_RX #0
US1_CLK #31 US1_CS
#30 US1_CTS #29
US1_RTS #28 LEU0_TX
#1 LEU0_RX #0
TIM0_CC2 #31
TIM0_CDTI0 #30
TIM0_CDTI1 #29
TIM0_CDTI2 #28
TIM1_CC0 #1
BUSCY [ADC0:
APORT3YCH9 ACMP0:
APORT3YCH9 ACMP1:
APORT3YCH9 IDAC0:
APORT1YCH9]
CMU_CLK0 #0
PRS_CH6 #1 PRS_CH7
#0 PRS_CH8 #10
PRS_CH9 #9 ACMP0_O
#1 ACMP1_O #1
PA1
PA2
PA3
TIM1_CC1 #0
TIM1_CC2 #31
TIM1_CC3 #30 LE-
TIM0_OUT0 #1 LE-
TIM0_OUT1 #0
PCNT0_S0IN #1
PCNT0_S1IN #0
BUSDX [ADC0:
APORT4XCH9 ACMP0:
APORT4XCH9 ACMP1:
APORT4XCH9]
I2C0_SDA #1 I2C0_SCL
#0
TIM0_CC0 #2
TIM0_CC1 #1
TIM0_CC2 #0
TIM0_CDTI0 #31
TIM0_CDTI1 #30
TIM0_CDTI2 #29
TIM1_CC0 #2
BUSCX [ADC0:
APORT3XCH10
ACMP0:
APORT3XCH10
ACMP1:
US0_TX #2 US0_RX #1
US0_CLK #0 US0_CS
#31 US0_CTS #30
US0_RTS #29 US1_TX PRS_CH6 #2 PRS_CH7
APORT3XCH10 IDAC0:
APORT1XCH10]
#2 US1_RX #1
US1_CLK #0 US1_CS
#31 US1_CTS #30
US1_RTS #29 LEU0_TX
#2 LEU0_RX #1
#1 PRS_CH8 #0
PRS_CH9 #10
ACMP0_O #2
ACMP1_O #2
TIM1_CC1 #1
TIM1_CC2 #0
BUSDY [ADC0:
APORT4YCH10
ACMP0:
APORT4YCH10
ACMP1:
TIM1_CC3 #31 LE-
TIM0_OUT0 #2 LE-
TIM0_OUT1 #1
PCNT0_S0IN #2
PCNT0_S1IN #1
I2C0_SDA #2 I2C0_SCL
#1
APORT4YCH10]
TIM0_CC0 #3
TIM0_CC1 #2
TIM0_CC2 #1
TIM0_CDTI0 #0
TIM0_CDTI1 #31
TIM0_CDTI2 #30
TIM1_CC0 #3
BUSCY [ADC0:
APORT3YCH11
ACMP0:
APORT3YCH11
ACMP1:
US0_TX #3 US0_RX #2
US0_CLK #1 US0_CS
#0 US0_CTS #31
US0_RTS #30 US1_TX PRS_CH6 #3 PRS_CH7
#3 US1_RX #2 #2 PRS_CH8 #1
US1_CLK #1 US1_CS PRS_CH9 #0 ACMP0_O
#0 US1_CTS #31
US1_RTS #30 LEU0_TX
#3 LEU0_RX #2
I2C0_SDA #3 I2C0_SCL
#2
APORT3YCH11 IDAC0:
APORT1YCH11]
TIM1_CC1 #2
TIM1_CC2 #1
#3 ACMP1_O #3
GPIO_EM4WU8
BUSDX [ADC0:
APORT4XCH11
ACMP0:
APORT4XCH11
ACMP1:
TIM1_CC3 #0 LE-
TIM0_OUT0 #3 LE-
TIM0_OUT1 #2
PCNT0_S0IN #3
PCNT0_S1IN #2
APORT4XCH11]
silabs.com | Smart. Connected. Energy-friendly.
Preliminary Rev. 0.31 | 42
EFM32JG1 Data Sheet
Pin Definitions
QFN48 Pin# and Name
Pin Alternate Functionality / Description
Pin
#
Pin Name
Analog
Timers
Communication
Other
TIM0_CC0 #4
TIM0_CC1 #3
TIM0_CC2 #2
TIM0_CDTI0 #1
TIM0_CDTI1 #0
TIM0_CDTI2 #31
TIM1_CC0 #4
BUSCX [ADC0:
APORT3XCH12
ACMP0:
APORT3XCH12
ACMP1:
US0_TX #4 US0_RX #3
US0_CLK #2 US0_CS
#1 US0_CTS #0
US0_RTS #31 US1_TX
#4 US1_RX #3
US1_CLK #2 US1_CS
#1 US1_CTS #0
US1_RTS #31 LEU0_TX
#4 LEU0_RX #3
PRS_CH6 #4 PRS_CH7
#3 PRS_CH8 #2
PRS_CH9 #1 ACMP0_O
#4 ACMP1_O #4
APORT3XCH12 IDAC0:
APORT1XCH12]
29
30
31
32
PA4
TIM1_CC1 #3
TIM1_CC2 #2
BUSDY [ADC0:
APORT4YCH12
ACMP0:
APORT4YCH12
ACMP1:
TIM1_CC3 #1 LE-
TIM0_OUT0 #4 LE-
TIM0_OUT1 #3
PCNT0_S0IN #4
PCNT0_S1IN #3
I2C0_SDA #4 I2C0_SCL
#3
APORT4YCH12]
TIM0_CC0 #5
TIM0_CC1 #4
TIM0_CC2 #3
TIM0_CDTI0 #2
TIM0_CDTI1 #1
TIM0_CDTI2 #0
TIM1_CC0 #5
BUSCY [ADC0:
APORT3YCH13
ACMP0:
APORT3YCH13
ACMP1:
US0_TX #5 US0_RX #4
US0_CLK #3 US0_CS
#2 US0_CTS #1
US0_RTS #0 US1_TX
#5 US1_RX #4
US1_CLK #3 US1_CS
#2 US1_CTS #1
US1_RTS #0 LEU0_TX
#5 LEU0_RX #4
PRS_CH6 #5 PRS_CH7
#4 PRS_CH8 #3
PRS_CH9 #2 ACMP0_O
#5 ACMP1_O #5
APORT3YCH13 IDAC0:
APORT1YCH13]
PA5
PB11
PB12
TIM1_CC1 #4
TIM1_CC2 #3
BUSDX [ADC0:
APORT4XCH13
ACMP0:
APORT4XCH13
ACMP1:
TIM1_CC3 #2 LE-
TIM0_OUT0 #5 LE-
TIM0_OUT1 #4
PCNT0_S0IN #5
PCNT0_S1IN #4
I2C0_SDA #5 I2C0_SCL
#4
APORT4XCH13]
TIM0_CC0 #6
TIM0_CC1 #5
TIM0_CC2 #4
TIM0_CDTI0 #3
TIM0_CDTI1 #2
TIM0_CDTI2 #1
TIM1_CC0 #6
BUSCY [ADC0:
APORT3YCH27
ACMP0:
APORT3YCH27
ACMP1:
US0_TX #6 US0_RX #5
US0_CLK #4 US0_CS
#3 US0_CTS #2
US0_RTS #1 US1_TX
#6 US1_RX #5
US1_CLK #4 US1_CS
#3 US1_CTS #2
US1_RTS #1 LEU0_TX
#6 LEU0_RX #5
PRS_CH6 #6 PRS_CH7
#5 PRS_CH8 #4
PRS_CH9 #3 ACMP0_O
#6 ACMP1_O #6
APORT3YCH27 IDAC0:
APORT1YCH27]
TIM1_CC1 #5
TIM1_CC2 #4
BUSDX [ADC0:
APORT4XCH27
ACMP0:
APORT4XCH27
ACMP1:
TIM1_CC3 #3 LE-
TIM0_OUT0 #6 LE-
TIM0_OUT1 #5
PCNT0_S0IN #6
PCNT0_S1IN #5
I2C0_SDA #6 I2C0_SCL
#5
APORT4XCH27]
TIM0_CC0 #7
TIM0_CC1 #6
TIM0_CC2 #5
TIM0_CDTI0 #4
TIM0_CDTI1 #3
TIM0_CDTI2 #2
TIM1_CC0 #7
BUSCX [ADC0:
APORT3XCH28
ACMP0:
APORT3XCH28
ACMP1:
US0_TX #7 US0_RX #6
US0_CLK #5 US0_CS
#4 US0_CTS #3
US0_RTS #2 US1_TX
#7 US1_RX #6
US1_CLK #5 US1_CS
#4 US1_CTS #3
US1_RTS #2 LEU0_TX
#7 LEU0_RX #6
PRS_CH6 #7 PRS_CH7
#6 PRS_CH8 #5
PRS_CH9 #4 ACMP0_O
#7 ACMP1_O #7
APORT3XCH28 IDAC0:
APORT1XCH28]
TIM1_CC1 #6
TIM1_CC2 #5
BUSDY [ADC0:
APORT4YCH28
ACMP0:
APORT4YCH28
ACMP1:
TIM1_CC3 #4 LE-
TIM0_OUT0 #7 LE-
TIM0_OUT1 #6
PCNT0_S0IN #7
PCNT0_S1IN #6
I2C0_SDA #7 I2C0_SCL
#6
APORT4YCH28]
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EFM32JG1 Data Sheet
Pin Definitions
QFN48 Pin# and Name
Pin Alternate Functionality / Description
Pin
#
Pin Name
Analog
Timers
Communication
Other
TIM0_CC0 #8
TIM0_CC1 #7
TIM0_CC2 #6
TIM0_CDTI0 #5
TIM0_CDTI1 #4
TIM0_CDTI2 #3
TIM1_CC0 #8
BUSCY [ADC0:
APORT3YCH29
ACMP0:
APORT3YCH29
ACMP1:
US0_TX #8 US0_RX #7
US0_CLK #6 US0_CS
#5 US0_CTS #4
US0_RTS #3 US1_TX
#8 US1_RX #7
US1_CLK #6 US1_CS
#5 US1_CTS #4
US1_RTS #3 LEU0_TX
#8 LEU0_RX #7
PRS_CH6 #8 PRS_CH7
#7 PRS_CH8 #6
APORT3YCH29 IDAC0:
APORT1YCH29]
PRS_CH9 #5 ACMP0_O
#8 ACMP1_O #8
33
34
PB13
TIM1_CC1 #7
TIM1_CC2 #6
BUSDX [ADC0:
APORT4XCH29
ACMP0:
APORT4XCH29
ACMP1:
DBG_SWO #1
GPIO_EM4WU9
TIM1_CC3 #5 LE-
TIM0_OUT0 #8 LE-
TIM0_OUT1 #7
PCNT0_S0IN #8
PCNT0_S1IN #7
I2C0_SDA #8 I2C0_SCL
#7
APORT4XCH29]
AVDD_0
Analog power supply 0.
LFXTAL_N
TIM0_CC0 #9
TIM0_CC1 #8
TIM0_CC2 #7
TIM0_CDTI0 #6
TIM0_CDTI1 #5
TIM0_CDTI2 #4
TIM1_CC0 #9
BUSCX [ADC0:
APORT3XCH30
ACMP0:
APORT3XCH30
ACMP1:
US0_TX #9 US0_RX #8
US0_CLK #7 US0_CS
#6 US0_CTS #5
US0_RTS #4 US1_TX
#9 US1_RX #8
US1_CLK #7 US1_CS
#6 US1_CTS #5
US1_RTS #4 LEU0_TX
#9 LEU0_RX #8
CMU_CLK1 #1
PRS_CH6 #9 PRS_CH7
#8 PRS_CH8 #7
PRS_CH9 #6 ACMP0_O
#9 ACMP1_O #9
APORT3XCH30 IDAC0:
APORT1XCH30]
35
PB14
TIM1_CC1 #8
TIM1_CC2 #7
BUSDY [ADC0:
APORT4YCH30
ACMP0:
APORT4YCH30
ACMP1:
TIM1_CC3 #6 LE-
TIM0_OUT0 #9 LE-
TIM0_OUT1 #8
PCNT0_S0IN #9
PCNT0_S1IN #8
I2C0_SDA #9 I2C0_SCL
#8
APORT4YCH30]
LFXTAL_P
TIM0_CC0 #10
TIM0_CC1 #9
TIM0_CC2 #8
TIM0_CDTI0 #7
TIM0_CDTI1 #6
TIM0_CDTI2 #5
TIM1_CC0 #10
TIM1_CC1 #9
BUSCY [ADC0:
APORT3YCH31
ACMP0:
APORT3YCH31
ACMP1:
US0_TX #10 US0_RX
#9 US0_CLK #8
US0_CS #7 US0_CTS
#6 US0_RTS #5
US1_TX #10 US1_RX
#9 US1_CLK #8
US1_CS #7 US1_CTS
#6 US1_RTS #5
LEU0_TX #10 LEU0_RX
#9 I2C0_SDA #10
I2C0_SCL #9
CMU_CLK0 #1
PRS_CH6 #10
PRS_CH7 #9 PRS_CH8
#8 PRS_CH9 #7
ACMP0_O #10
APORT3YCH31 IDAC0:
APORT1YCH31]
36
PB15
TIM1_CC2 #8
BUSDX [ADC0:
APORT4XCH31
ACMP0:
APORT4XCH31
ACMP1:
TIM1_CC3 #7 LE-
TIM0_OUT0 #10 LE-
TIM0_OUT1 #9
PCNT0_S0IN #10
PCNT0_S1IN #9
ACMP1_O #10
APORT4XCH31]
37
38
39
40
VREGVSS
VREGSW
VREGVDD
DVDD
Voltage regulator VSS
DCDC regulator switching node
Voltage regulator VDD input
Digital power supply.
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at
this pin.
41
42
DECOUPLE
IOVDD
Digital IO power supply.
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EFM32JG1 Data Sheet
Pin Definitions
QFN48 Pin# and Name
Pin Alternate Functionality / Description
Pin
#
Pin Name
Analog
Timers
Communication
Other
TIM0_CC0 #11
TIM0_CC1 #10
TIM0_CC2 #9
TIM0_CDTI0 #8
TIM0_CDTI1 #7
TIM0_CDTI2 #6
TIM1_CC0 #11
TIM1_CC1 #10
TIM1_CC2 #9
TIM1_CC3 #8 LE-
TIM0_OUT0 #11 LE-
TIM0_OUT1 #10
PCNT0_S0IN #11
PCNT0_S1IN #10
US0_TX #11 US0_RX
#10 US0_CLK #9
US0_CS #8 US0_CTS
#7 US0_RTS #6
US1_TX #11 US1_RX
#10 US1_CLK #9
US1_CS #8 US1_CTS
#7 US1_RTS #6
BUSAX [ADC0:
APORT1XCH6 ACMP0:
APORT1XCH6 ACMP1:
APORT1XCH6]
CMU_CLK0 #2
PRS_CH0 #8 PRS_CH9
#11 PRS_CH10 #0
PRS_CH11 #5
43
44
45
46
PC6
BUSBY [ADC0:
APORT2YCH6 ACMP0:
APORT2YCH6 ACMP1:
APORT2YCH6]
ACMP0_O #11
ACMP1_O #11
LEU0_TX #11 LEU0_RX
#10 I2C0_SDA #11
I2C0_SCL #10
TIM0_CC0 #12
TIM0_CC1 #11
TIM0_CC2 #10
TIM0_CDTI0 #9
TIM0_CDTI1 #8
TIM0_CDTI2 #7
TIM1_CC0 #12
TIM1_CC1 #11
TIM1_CC2 #10
TIM1_CC3 #9 LE-
TIM0_OUT0 #12 LE-
TIM0_OUT1 #11
PCNT0_S0IN #12
PCNT0_S1IN #11
US0_TX #12 US0_RX
#11 US0_CLK #10
US0_CS #9 US0_CTS
#8 US0_RTS #7
US1_TX #12 US1_RX
#11 US1_CLK #10
US1_CS #9 US1_CTS
#8 US1_RTS #7
BUSAY [ADC0:
APORT1YCH7 ACMP0:
APORT1YCH7 ACMP1:
APORT1YCH7]
CMU_CLK1 #2
PRS_CH0 #9 PRS_CH9
#12 PRS_CH10 #1
PRS_CH11 #0
PC7
PC8
PC9
BUSBX [ADC0:
APORT2XCH7 ACMP0:
APORT2XCH7 ACMP1:
APORT2XCH7]
ACMP0_O #12
ACMP1_O #12
LEU0_TX #12 LEU0_RX
#11 I2C0_SDA #12
I2C0_SCL #11
TIM0_CC0 #13
TIM0_CC1 #12
TIM0_CC2 #11
TIM0_CDTI0 #10
TIM0_CDTI1 #9
TIM0_CDTI2 #8
TIM1_CC0 #13
US0_TX #13 US0_RX
#12 US0_CLK #11
US0_CS #10 US0_CTS
#9 US0_RTS #8
US1_TX #13 US1_RX
#12 US1_CLK #11
US1_CS #10 US1_CTS
#9 US1_RTS #8
BUSAX [ADC0:
APORT1XCH8 ACMP0:
APORT1XCH8 ACMP1:
APORT1XCH8]
PRS_CH0 #10
PRS_CH9 #13
PRS_CH10 #2
PRS_CH11 #1
ACMP0_O #13
ACMP1_O #13
TIM1_CC1 #12
TIM1_CC2 #11
BUSBY [ADC0:
APORT2YCH8 ACMP0:
APORT2YCH8 ACMP1:
APORT2YCH8]
TIM1_CC3 #10 LE-
TIM0_OUT0 #13 LE-
TIM0_OUT1 #12
PCNT0_S0IN #13
PCNT0_S1IN #12
LEU0_TX #13 LEU0_RX
#12 I2C0_SDA #13
I2C0_SCL #12
TIM0_CC0 #14
TIM0_CC1 #13
TIM0_CC2 #12
TIM0_CDTI0 #11
TIM0_CDTI1 #10
TIM0_CDTI2 #9
TIM1_CC0 #14
US0_TX #14 US0_RX
#13 US0_CLK #12
US0_CS #11 US0_CTS
#10 US0_RTS #9
US1_TX #14 US1_RX
#13 US1_CLK #12
US1_CS #11 US1_CTS
#10 US1_RTS #9
BUSAY [ADC0:
APORT1YCH9 ACMP0:
APORT1YCH9 ACMP1:
APORT1YCH9]
PRS_CH0 #11
PRS_CH9 #14
PRS_CH10 #3
PRS_CH11 #2
ACMP0_O #14
ACMP1_O #14
TIM1_CC1 #13
TIM1_CC2 #12
BUSBX [ADC0:
APORT2XCH9 ACMP0:
APORT2XCH9 ACMP1:
APORT2XCH9]
TIM1_CC3 #11 LE-
TIM0_OUT0 #14 LE-
TIM0_OUT1 #13
PCNT0_S0IN #14
PCNT0_S1IN #13
LEU0_TX #14 LEU0_RX
#13 I2C0_SDA #14
I2C0_SCL #13
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Preliminary Rev. 0.31 | 45
EFM32JG1 Data Sheet
Pin Definitions
QFN48 Pin# and Name
Pin Alternate Functionality / Description
Pin
#
Pin Name
Analog
Timers
Communication
Other
TIM0_CC0 #15
TIM0_CC1 #14
TIM0_CC2 #13
TIM0_CDTI0 #12
TIM0_CDTI1 #11
TIM0_CDTI2 #10
TIM1_CC0 #15
BUSAX [ADC0:
APORT1XCH10
ACMP0:
APORT1XCH10
ACMP1:
US0_TX #15 US0_RX
#14 US0_CLK #13
US0_CS #12 US0_CTS
#11 US0_RTS #10
US1_TX #15 US1_RX
#14 US1_CLK #13
US1_CS #12 US1_CTS
#11 US1_RTS #10
LEU0_TX #15 LEU0_RX
#14 I2C0_SDA #15
I2C0_SCL #14
CMU_CLK1 #3
PRS_CH0 #12
PRS_CH9 #15
PRS_CH10 #4
PRS_CH11 #3
ACMP0_O #15
ACMP1_O #15
GPIO_EM4WU12
APORT1XCH10]
47
PC10
TIM1_CC1 #14
TIM1_CC2 #13
BUSBY [ADC0:
APORT2YCH10
ACMP0:
APORT2YCH10
ACMP1:
TIM1_CC3 #12 LE-
TIM0_OUT0 #15 LE-
TIM0_OUT1 #14
PCNT0_S0IN #15
PCNT0_S1IN #14
APORT2YCH10]
TIM0_CC0 #16
TIM0_CC1 #15
TIM0_CC2 #14
TIM0_CDTI0 #13
TIM0_CDTI1 #12
TIM0_CDTI2 #11
TIM1_CC0 #16
BUSAY [ADC0:
APORT1YCH11
ACMP0:
APORT1YCH11
ACMP1:
US0_TX #16 US0_RX
#15 US0_CLK #14
US0_CS #13 US0_CTS
#12 US0_RTS #11
US1_TX #16 US1_RX
#15 US1_CLK #14
US1_CS #13 US1_CTS
#12 US1_RTS #11
LEU0_TX #16 LEU0_RX
#15 I2C0_SDA #16
I2C0_SCL #15
CMU_CLK0 #3
PRS_CH0 #13
PRS_CH9 #16
PRS_CH10 #5
PRS_CH11 #4
ACMP0_O #16
ACMP1_O #16
DBG_SWO #3
APORT1YCH11]
48
PC11
TIM1_CC1 #15
TIM1_CC2 #14
BUSBX [ADC0:
APORT2XCH11
ACMP0:
APORT2XCH11
ACMP1:
TIM1_CC3 #13 LE-
TIM0_OUT0 #16 LE-
TIM0_OUT1 #15
PCNT0_S0IN #16
PCNT0_S1IN #15
APORT2XCH11]
6.1.1 GPIO Pinout Overview
The GPIO pins are organized as 16-bit ports indicated by letters A through F, and the individual pins on each port is indicated by a
number from 15 down to 0.
Table 6.2. GPIO Pinout
Port
Pin
15
Pin
14
Pin
13
Pin
12
Pin
11
Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
10
PA5 PA4 PA3 PA2
(5V) (5V) (5V) (5V)
Port A
Port B
Port C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PA1 PA0
PB13 PB12 PB11
(5V) (5V) (5V)
PB15 PB14
-
-
-
-
-
-
-
-
-
-
-
-
PC11 PC10 PC9 PC8 PC7 PC6
(5V) (5V) (5V) (5V) (5V) (5V)
-
-
-
-
PD15 PD14 PD13 PD12 PD11 PD10 PD9
(5V) (5V) (5V) (5V) (5V) (5V) (5V)
Port D
Port E
Port F
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0
(5V) (5V) (5V) (5V) (5V) (5V) (5V) (5V)
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Preliminary Rev. 0.31 | 46
EFM32JG1 Data Sheet
Pin Definitions
6.2 EFM32JG1 QFN32 with DC-DC Definition
Figure 6.2. EFM32JG1 QFN32 with DC-DC Converter Pinout
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Preliminary Rev. 0.31 | 47
EFM32JG1 Data Sheet
Pin Definitions
Table 6.3. Device Pinout
QFN32 Pin# and Name
Pin Alternate Functionality / Description
Pin
#
Pin Name
Analog
Timers
Communication
Other
0
VSS
Ground
TIM0_CC0 #24
TIM0_CC1 #23
TIM0_CC2 #22
TIM0_CDTI0 #21
TIM0_CDTI1 #20
TIM0_CDTI2 #19
TIM1_CC0 #24
BUSAX [ADC0:
APORT1XCH16
ACMP0:
APORT1XCH16
ACMP1:
US0_TX #24 US0_RX
#23 US0_CLK #22
US0_CS #21 US0_CTS
#20 US0_RTS #19
US1_TX #24 US1_RX
#23 US1_CLK #22
US1_CS #21 US1_CTS
#20 US1_RTS #19
LEU0_TX #24 LEU0_RX
#23 I2C0_SDA #24
I2C0_SCL #23
PRS_CH0 #0 PRS_CH1
#7 PRS_CH2 #6
APORT1XCH16]
PRS_CH3 #5 ACMP0_O
#24 ACMP1_O #24
DBG_SWCLKTCK #0
BOOT_TX
1
PF0
PF1
PF2
TIM1_CC1 #23
TIM1_CC2 #22
BUSBY [ADC0:
APORT2YCH16
ACMP0:
APORT2YCH16
ACMP1:
TIM1_CC3 #21 LE-
TIM0_OUT0 #24 LE-
TIM0_OUT1 #23
PCNT0_S0IN #24
PCNT0_S1IN #23
APORT2YCH16]
TIM0_CC0 #25
TIM0_CC1 #24
TIM0_CC2 #23
TIM0_CDTI0 #22
TIM0_CDTI1 #21
TIM0_CDTI2 #20
TIM1_CC0 #25
BUSAY [ADC0:
APORT1YCH17
ACMP0:
APORT1YCH17
ACMP1:
US0_TX #25 US0_RX
#24 US0_CLK #23
US0_CS #22 US0_CTS
#21 US0_RTS #20
US1_TX #25 US1_RX
#24 US1_CLK #23
US1_CS #22 US1_CTS
#21 US1_RTS #20
LEU0_TX #25 LEU0_RX
#24 I2C0_SDA #25
I2C0_SCL #24
PRS_CH0 #1 PRS_CH1
#0 PRS_CH2 #7
PRS_CH3 #6 ACMP0_O
#25 ACMP1_O #25
DBG_SWDIOTMS #0
BOOT_RX
APORT1YCH17]
2
TIM1_CC1 #24
TIM1_CC2 #23
BUSBX [ADC0:
APORT2XCH17
ACMP0:
APORT2XCH17
ACMP1:
TIM1_CC3 #22 LE-
TIM0_OUT0 #25 LE-
TIM0_OUT1 #24
PCNT0_S0IN #25
PCNT0_S1IN #24
APORT2XCH17]
TIM0_CC0 #26
TIM0_CC1 #25
TIM0_CC2 #24
TIM0_CDTI0 #23
TIM0_CDTI1 #22
TIM0_CDTI2 #21
TIM1_CC0 #26
BUSAX [ADC0:
APORT1XCH18
ACMP0:
APORT1XCH18
ACMP1:
US0_TX #26 US0_RX
#25 US0_CLK #24
US0_CS #23 US0_CTS
#22 US0_RTS #21
US1_TX #26 US1_RX
#25 US1_CLK #24
US1_CS #23 US1_CTS
#22 US1_RTS #21
LEU0_TX #26 LEU0_RX
#25 I2C0_SDA #26
I2C0_SCL #25
CMU_CLK0 #6
PRS_CH0 #2 PRS_CH1
#1 PRS_CH2 #0
PRS_CH3 #7 ACMP0_O
#26 ACMP1_O #26
DBG_TDO #0
APORT1XCH18]
3
TIM1_CC1 #25
TIM1_CC2 #24
BUSBY [ADC0:
APORT2YCH18
ACMP0:
APORT2YCH18
ACMP1:
TIM1_CC3 #23 LE-
TIM0_OUT0 #26 LE-
TIM0_OUT1 #25
PCNT0_S0IN #26
PCNT0_S1IN #25
DBG_SWO #0
GPIO_EM4WU0
APORT2YCH18]
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Preliminary Rev. 0.31 | 48
EFM32JG1 Data Sheet
Pin Definitions
QFN32 Pin# and Name
Pin Alternate Functionality / Description
Pin
#
Pin Name
Analog
Timers
Communication
Other
TIM0_CC0 #27
TIM0_CC1 #26
TIM0_CC2 #25
TIM0_CDTI0 #24
TIM0_CDTI1 #23
TIM0_CDTI2 #22
TIM1_CC0 #27
BUSAY [ADC0:
APORT1YCH19
ACMP0:
APORT1YCH19
ACMP1:
US0_TX #27 US0_RX
#26 US0_CLK #25
US0_CS #24 US0_CTS
#23 US0_RTS #22
US1_TX #27 US1_RX
#26 US1_CLK #25
US1_CS #24 US1_CTS
#23 US1_RTS #22
LEU0_TX #27 LEU0_RX
#26 I2C0_SDA #27
I2C0_SCL #26
CMU_CLK1 #6
PRS_CH0 #3 PRS_CH1
#2 PRS_CH2 #1
PRS_CH3 #0 ACMP0_O
#27 ACMP1_O #27
DBG_TDI #0
APORT1YCH19]
4
PF3
TIM1_CC1 #26
TIM1_CC2 #25
BUSBX [ADC0:
APORT2XCH19
ACMP0:
APORT2XCH19
ACMP1:
TIM1_CC3 #24 LE-
TIM0_OUT0 #27 LE-
TIM0_OUT1 #26
PCNT0_S0IN #27
PCNT0_S1IN #26
APORT2XCH19]
5
6
7
AVDD_1
HFXTAL_N
HFXTAL_P
Analog power supply 1.
High Frequency Crystal input pin.
High Frequency Crystal output pin.
Reset input, active low.To apply an external reset source to this pin, it is required to only drive this pin low
during reset, and let the internal pull-up ensure that reset is released.
8
9
RESETn
NC
No Connect.
TIM0_CC0 #17
TIM0_CC1 #16
US0_TX #17 US0_RX
TIM0_CC2 #15
TIM0_CDTI0 #14
TIM0_CDTI1 #13
TIM0_CDTI2 #12
TIM1_CC0 #17
BUSCY [ADC0:
APORT3YCH1 ACMP0:
APORT3YCH1 ACMP1:
APORT3YCH1 IDAC0:
APORT1YCH1]
#16 US0_CLK #15
US0_CS #14 US0_CTS
#13 US0_RTS #12
US1_TX #17 US1_RX
#16 US1_CLK #15
US1_CS #14 US1_CTS
#13 US1_RTS #12
LEU0_TX #17 LEU0_RX
#16 I2C0_SDA #17
I2C0_SCL #16
CMU_CLK0 #4
PRS_CH3 #8 PRS_CH4
#0 PRS_CH5 #6
PRS_CH6 #11
10
PD9
TIM1_CC1 #16
TIM1_CC2 #15
BUSDX [ADC0:
APORT4XCH1 ACMP0:
APORT4XCH1 ACMP1:
APORT4XCH1]
ACMP0_O #17
ACMP1_O #17
TIM1_CC3 #14 LE-
TIM0_OUT0 #17 LE-
TIM0_OUT1 #16
PCNT0_S0IN #17
PCNT0_S1IN #16
TIM0_CC0 #18
TIM0_CC1 #17
TIM0_CC2 #16
TIM0_CDTI0 #15
TIM0_CDTI1 #14
TIM0_CDTI2 #13
TIM1_CC0 #18
US0_TX #18 US0_RX
#17 US0_CLK #16
US0_CS #15 US0_CTS
#14 US0_RTS #13
US1_TX #18 US1_RX
#17 US1_CLK #16
US1_CS #15 US1_CTS
#14 US1_RTS #13
LEU0_TX #18 LEU0_RX
#17 I2C0_SDA #18
I2C0_SCL #17
BUSCX [ADC0:
APORT3XCH2 ACMP0:
APORT3XCH2 ACMP1:
APORT3XCH2 IDAC0:
APORT1XCH2]
CMU_CLK1 #4
PRS_CH3 #9 PRS_CH4
#1 PRS_CH5 #0
PRS_CH6 #12
11
PD10
TIM1_CC1 #17
TIM1_CC2 #16
BUSDY [ADC0:
APORT4YCH2 ACMP0:
APORT4YCH2 ACMP1:
APORT4YCH2]
ACMP0_O #18
ACMP1_O #18
TIM1_CC3 #15 LE-
TIM0_OUT0 #18 LE-
TIM0_OUT1 #17
PCNT0_S0IN #18
PCNT0_S1IN #17
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EFM32JG1 Data Sheet
Pin Definitions
QFN32 Pin# and Name
Pin Alternate Functionality / Description
Pin
#
Pin Name
Analog
Timers
Communication
Other
TIM0_CC0 #19
TIM0_CC1 #18
TIM0_CC2 #17
TIM0_CDTI0 #16
TIM0_CDTI1 #15
TIM0_CDTI2 #14
TIM1_CC0 #19
US0_TX #19 US0_RX
#18 US0_CLK #17
US0_CS #16 US0_CTS
#15 US0_RTS #14
BUSCY [ADC0:
APORT3YCH3 ACMP0:
APORT3YCH3 ACMP1:
APORT3YCH3 IDAC0:
APORT1YCH3]
PRS_CH3 #10
US1_TX #19 US1_RX PRS_CH4 #2 PRS_CH5
12
13
14
15
PD11
#18 US1_CLK #17
US1_CS #16 US1_CTS
#15 US1_RTS #14
LEU0_TX #19 LEU0_RX
#18 I2C0_SDA #19
I2C0_SCL #18
#1 PRS_CH6 #13
ACMP0_O #19
ACMP1_O #19
TIM1_CC1 #18
TIM1_CC2 #17
BUSDX [ADC0:
APORT4XCH3 ACMP0:
APORT4XCH3 ACMP1:
APORT4XCH3]
TIM1_CC3 #16 LE-
TIM0_OUT0 #19 LE-
TIM0_OUT1 #18
PCNT0_S0IN #19
PCNT0_S1IN #18
TIM0_CC0 #20
TIM0_CC1 #19
TIM0_CC2 #18
TIM0_CDTI0 #17
TIM0_CDTI1 #16
TIM0_CDTI2 #15
TIM1_CC0 #20
US0_TX #20 US0_RX
#19 US0_CLK #18
US0_CS #17 US0_CTS
#16 US0_RTS #15
BUSCX [ADC0:
APORT3XCH4 ACMP0:
APORT3XCH4 ACMP1:
APORT3XCH4 IDAC0:
APORT1XCH4]
PRS_CH3 #11
US1_TX #20 US1_RX PRS_CH4 #3 PRS_CH5
PD12
PD13
PD14
#19 US1_CLK #18
US1_CS #17 US1_CTS
#16 US1_RTS #15
LEU0_TX #20 LEU0_RX
#19 I2C0_SDA #20
I2C0_SCL #19
#2 PRS_CH6 #14
ACMP0_O #20
ACMP1_O #20
TIM1_CC1 #19
TIM1_CC2 #18
BUSDY [ADC0:
APORT4YCH4 ACMP0:
APORT4YCH4 ACMP1:
APORT4YCH4]
TIM1_CC3 #17 LE-
TIM0_OUT0 #20 LE-
TIM0_OUT1 #19
PCNT0_S0IN #20
PCNT0_S1IN #19
TIM0_CC0 #21
TIM0_CC1 #20
TIM0_CC2 #19
TIM0_CDTI0 #18
TIM0_CDTI1 #17
TIM0_CDTI2 #16
TIM1_CC0 #21
US0_TX #21 US0_RX
#20 US0_CLK #19
US0_CS #18 US0_CTS
#17 US0_RTS #16
BUSCY [ADC0:
APORT3YCH5 ACMP0:
APORT3YCH5 ACMP1:
APORT3YCH5 IDAC0:
APORT1YCH5]
PRS_CH3 #12
US1_TX #21 US1_RX PRS_CH4 #4 PRS_CH5
#20 US1_CLK #19
US1_CS #18 US1_CTS
#17 US1_RTS #16
LEU0_TX #21 LEU0_RX
#20 I2C0_SDA #21
I2C0_SCL #20
#3 PRS_CH6 #15
ACMP0_O #21
ACMP1_O #21
TIM1_CC1 #20
TIM1_CC2 #19
BUSDX [ADC0:
APORT4XCH5 ACMP0:
APORT4XCH5 ACMP1:
APORT4XCH5]
TIM1_CC3 #18 LE-
TIM0_OUT0 #21 LE-
TIM0_OUT1 #20
PCNT0_S0IN #21
PCNT0_S1IN #20
TIM0_CC0 #22
TIM0_CC1 #21
TIM0_CC2 #20
TIM0_CDTI0 #19
TIM0_CDTI1 #18
TIM0_CDTI2 #17
TIM1_CC0 #22
US0_TX #22 US0_RX
#21 US0_CLK #20
US0_CS #19 US0_CTS
#18 US0_RTS #17
BUSCX [ADC0:
APORT3XCH6 ACMP0:
APORT3XCH6 ACMP1:
APORT3XCH6 IDAC0:
APORT1XCH6]
CMU_CLK0 #5
PRS_CH3 #13
US1_TX #22 US1_RX PRS_CH4 #5 PRS_CH5
#21 US1_CLK #20
US1_CS #19 US1_CTS
#18 US1_RTS #17
LEU0_TX #22 LEU0_RX
#21 I2C0_SDA #22
I2C0_SCL #21
#4 PRS_CH6 #16
ACMP0_O #22
ACMP1_O #22
GPIO_EM4WU4
TIM1_CC1 #21
TIM1_CC2 #20
BUSDY [ADC0:
APORT4YCH6 ACMP0:
APORT4YCH6 ACMP1:
APORT4YCH6]
TIM1_CC3 #19 LE-
TIM0_OUT0 #22 LE-
TIM0_OUT1 #21
PCNT0_S0IN #22
PCNT0_S1IN #21
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EFM32JG1 Data Sheet
Pin Definitions
QFN32 Pin# and Name
Pin Alternate Functionality / Description
Pin
#
Pin Name
Analog
Timers
Communication
Other
TIM0_CC0 #23
TIM0_CC1 #22
TIM0_CC2 #21
TIM0_CDTI0 #20
TIM0_CDTI1 #19
TIM0_CDTI2 #18
TIM1_CC0 #23
US0_TX #23 US0_RX
#22 US0_CLK #21
US0_CS #20 US0_CTS
#19 US0_RTS #18
BUSCY [ADC0:
APORT3YCH7 ACMP0:
APORT3YCH7 ACMP1:
APORT3YCH7 IDAC0:
APORT1YCH7]
CMU_CLK1 #5
PRS_CH3 #14
US1_TX #23 US1_RX PRS_CH4 #6 PRS_CH5
16
17
18
19
PD15
#22 US1_CLK #21
US1_CS #20 US1_CTS
#19 US1_RTS #18
LEU0_TX #23 LEU0_RX
#22 I2C0_SDA #23
I2C0_SCL #22
#5 PRS_CH6 #17
ACMP0_O #23
ACMP1_O #23
DBG_SWO #2
TIM1_CC1 #22
TIM1_CC2 #21
BUSDX [ADC0:
APORT4XCH7 ACMP0:
APORT4XCH7 ACMP1:
APORT4XCH7]
TIM1_CC3 #20 LE-
TIM0_OUT0 #23 LE-
TIM0_OUT1 #22
PCNT0_S0IN #23
PCNT0_S1IN #22
TIM0_CC0 #0
TIM0_CC1 #31
TIM0_CC2 #30
TIM0_CDTI0 #29
TIM0_CDTI1 #28
TIM0_CDTI2 #27
TIM1_CC0 #0
TIM1_CC1 #31
TIM1_CC2 #30
TIM1_CC3 #29 LE-
TIM0_OUT0 #0 LE-
TIM0_OUT1 #31
PCNT0_S0IN #0
PCNT0_S1IN #31
ADC0_EXTN
US0_TX #0 US0_RX
#31 US0_CLK #30
US0_CS #29 US0_CTS
#28 US0_RTS #27
US1_TX #0 US1_RX
#31 US1_CLK #30
BUSCX [ADC0:
APORT3XCH8 ACMP0:
APORT3XCH8 ACMP1:
APORT3XCH8 IDAC0:
APORT1XCH8]
CMU_CLK1 #0
PRS_CH6 #0 PRS_CH7
#10 PRS_CH8 #9
PA0
US1_CS #29 US1_CTS PRS_CH9 #8 ACMP0_O
#28 US1_RTS #27
LEU0_TX #0 LEU0_RX
#31 I2C0_SDA #0
I2C0_SCL #31
#0 ACMP1_O #0
BUSDY [ADC0:
APORT4YCH8 ACMP0:
APORT4YCH8 ACMP1:
APORT4YCH8]
TIM0_CC0 #1
TIM0_CC1 #0
ADC0_EXTP
US0_TX #1 US0_RX #0
US0_CLK #31 US0_CS
#30 US0_CTS #29
US0_RTS #28 US1_TX
#1 US1_RX #0
US1_CLK #31 US1_CS
#30 US1_CTS #29
US1_RTS #28 LEU0_TX
#1 LEU0_RX #0
TIM0_CC2 #31
TIM0_CDTI0 #30
TIM0_CDTI1 #29
TIM0_CDTI2 #28
TIM1_CC0 #1
BUSCY [ADC0:
APORT3YCH9 ACMP0:
APORT3YCH9 ACMP1:
APORT3YCH9 IDAC0:
APORT1YCH9]
CMU_CLK0 #0
PRS_CH6 #1 PRS_CH7
#0 PRS_CH8 #10
PRS_CH9 #9 ACMP0_O
#1 ACMP1_O #1
PA1
TIM1_CC1 #0
TIM1_CC2 #31
TIM1_CC3 #30 LE-
TIM0_OUT0 #1 LE-
TIM0_OUT1 #0
PCNT0_S0IN #1
PCNT0_S1IN #0
BUSDX [ADC0:
APORT4XCH9 ACMP0:
APORT4XCH9 ACMP1:
APORT4XCH9]
I2C0_SDA #1 I2C0_SCL
#0
TIM0_CC0 #6
TIM0_CC1 #5
TIM0_CC2 #4
TIM0_CDTI0 #3
TIM0_CDTI1 #2
TIM0_CDTI2 #1
TIM1_CC0 #6
BUSCY [ADC0:
APORT3YCH27
ACMP0:
APORT3YCH27
ACMP1:
US0_TX #6 US0_RX #5
US0_CLK #4 US0_CS
#3 US0_CTS #2
US0_RTS #1 US1_TX
#6 US1_RX #5
US1_CLK #4 US1_CS
#3 US1_CTS #2
US1_RTS #1 LEU0_TX
#6 LEU0_RX #5
PRS_CH6 #6 PRS_CH7
#5 PRS_CH8 #4
APORT3YCH27 IDAC0:
APORT1YCH27]
PB11
TIM1_CC1 #5
TIM1_CC2 #4
PRS_CH9 #3 ACMP0_O
#6 ACMP1_O #6
BUSDX [ADC0:
APORT4XCH27
ACMP0:
TIM1_CC3 #3 LE-
TIM0_OUT0 #6 LE-
TIM0_OUT1 #5
PCNT0_S0IN #6
PCNT0_S1IN #5
I2C0_SDA #6 I2C0_SCL
#5
APORT4XCH27
ACMP1:
APORT4XCH27]
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Preliminary Rev. 0.31 | 51
EFM32JG1 Data Sheet
Pin Definitions
QFN32 Pin# and Name
Pin Alternate Functionality / Description
Pin
#
Pin Name
Analog
Timers
Communication
Other
TIM0_CC0 #7
TIM0_CC1 #6
TIM0_CC2 #5
TIM0_CDTI0 #4
TIM0_CDTI1 #3
TIM0_CDTI2 #2
TIM1_CC0 #7
BUSCX [ADC0:
APORT3XCH28
ACMP0:
APORT3XCH28
ACMP1:
US0_TX #7 US0_RX #6
US0_CLK #5 US0_CS
#4 US0_CTS #3
US0_RTS #2 US1_TX
#7 US1_RX #6
US1_CLK #5 US1_CS
#4 US1_CTS #3
US1_RTS #2 LEU0_TX
#7 LEU0_RX #6
PRS_CH6 #7 PRS_CH7
#6 PRS_CH8 #5
PRS_CH9 #4 ACMP0_O
#7 ACMP1_O #7
APORT3XCH28 IDAC0:
APORT1XCH28]
20
PB12
TIM1_CC1 #6
TIM1_CC2 #5
BUSDY [ADC0:
APORT4YCH28
ACMP0:
APORT4YCH28
ACMP1:
TIM1_CC3 #4 LE-
TIM0_OUT0 #7 LE-
TIM0_OUT1 #6
PCNT0_S0IN #7
PCNT0_S1IN #6
I2C0_SDA #7 I2C0_SCL
#6
APORT4YCH28]
TIM0_CC0 #8
TIM0_CC1 #7
TIM0_CC2 #6
TIM0_CDTI0 #5
TIM0_CDTI1 #4
TIM0_CDTI2 #3
TIM1_CC0 #8
BUSCY [ADC0:
APORT3YCH29
ACMP0:
APORT3YCH29
ACMP1:
US0_TX #8 US0_RX #7
US0_CLK #6 US0_CS
#5 US0_CTS #4
US0_RTS #3 US1_TX
#8 US1_RX #7
US1_CLK #6 US1_CS
#5 US1_CTS #4
US1_RTS #3 LEU0_TX
#8 LEU0_RX #7
PRS_CH6 #8 PRS_CH7
#7 PRS_CH8 #6
APORT3YCH29 IDAC0:
APORT1YCH29]
PRS_CH9 #5 ACMP0_O
#8 ACMP1_O #8
21
22
PB13
TIM1_CC1 #7
TIM1_CC2 #6
BUSDX [ADC0:
APORT4XCH29
ACMP0:
APORT4XCH29
ACMP1:
DBG_SWO #1
GPIO_EM4WU9
TIM1_CC3 #5 LE-
TIM0_OUT0 #8 LE-
TIM0_OUT1 #7
PCNT0_S0IN #8
PCNT0_S1IN #7
I2C0_SDA #8 I2C0_SCL
#7
APORT4XCH29]
AVDD_0
Analog power supply 0.
LFXTAL_N
TIM0_CC0 #9
TIM0_CC1 #8
TIM0_CC2 #7
TIM0_CDTI0 #6
TIM0_CDTI1 #5
TIM0_CDTI2 #4
TIM1_CC0 #9
BUSCX [ADC0:
APORT3XCH30
ACMP0:
APORT3XCH30
ACMP1:
US0_TX #9 US0_RX #8
US0_CLK #7 US0_CS
#6 US0_CTS #5
US0_RTS #4 US1_TX
#9 US1_RX #8
US1_CLK #7 US1_CS
#6 US1_CTS #5
US1_RTS #4 LEU0_TX
#9 LEU0_RX #8
CMU_CLK1 #1
PRS_CH6 #9 PRS_CH7
#8 PRS_CH8 #7
PRS_CH9 #6 ACMP0_O
#9 ACMP1_O #9
APORT3XCH30 IDAC0:
APORT1XCH30]
23
PB14
TIM1_CC1 #8
TIM1_CC2 #7
BUSDY [ADC0:
APORT4YCH30
ACMP0:
APORT4YCH30
ACMP1:
TIM1_CC3 #6 LE-
TIM0_OUT0 #9 LE-
TIM0_OUT1 #8
PCNT0_S0IN #9
PCNT0_S1IN #8
I2C0_SDA #9 I2C0_SCL
#8
APORT4YCH30]
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Preliminary Rev. 0.31 | 52
EFM32JG1 Data Sheet
Pin Definitions
QFN32 Pin# and Name
Pin Alternate Functionality / Description
Pin
#
Pin Name
Analog
Timers
Communication
Other
LFXTAL_P
TIM0_CC0 #10
TIM0_CC1 #9
TIM0_CC2 #8
TIM0_CDTI0 #7
TIM0_CDTI1 #6
TIM0_CDTI2 #5
TIM1_CC0 #10
TIM1_CC1 #9
BUSCY [ADC0:
APORT3YCH31
ACMP0:
APORT3YCH31
ACMP1:
US0_TX #10 US0_RX
#9 US0_CLK #8
US0_CS #7 US0_CTS
#6 US0_RTS #5
US1_TX #10 US1_RX
#9 US1_CLK #8
US1_CS #7 US1_CTS
#6 US1_RTS #5
LEU0_TX #10 LEU0_RX
#9 I2C0_SDA #10
I2C0_SCL #9
CMU_CLK0 #1
PRS_CH6 #10
PRS_CH7 #9 PRS_CH8
#8 PRS_CH9 #7
ACMP0_O #10
APORT3YCH31 IDAC0:
APORT1YCH31]
24
PB15
TIM1_CC2 #8
BUSDX [ADC0:
APORT4XCH31
ACMP0:
APORT4XCH31
ACMP1:
TIM1_CC3 #7 LE-
TIM0_OUT0 #10 LE-
TIM0_OUT1 #9
PCNT0_S0IN #10
PCNT0_S1IN #9
ACMP1_O #10
APORT4XCH31]
25
26
27
28
VREGVSS
VREGSW
VREGVDD
DVDD
Voltage regulator VSS
DCDC regulator switching node
Voltage regulator VDD input
Digital power supply.
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at
this pin.
29
30
DECOUPLE
IOVDD
Digital IO power supply.
TIM0_CC0 #15
BUSAX [ADC0:
APORT1XCH10
ACMP0:
APORT1XCH10
ACMP1:
APORT1XCH10]
TIM0_CC1 #14
US0_TX #15 US0_RX
#14 US0_CLK #13
US0_CS #12 US0_CTS
#11 US0_RTS #10
US1_TX #15 US1_RX
#14 US1_CLK #13
US1_CS #12 US1_CTS
#11 US1_RTS #10
LEU0_TX #15 LEU0_RX
#14 I2C0_SDA #15
I2C0_SCL #14
TIM0_CC2 #13
TIM0_CDTI0 #12
TIM0_CDTI1 #11
TIM0_CDTI2 #10
TIM1_CC0 #15
CMU_CLK1 #3
PRS_CH0 #12
PRS_CH9 #15
PRS_CH10 #4
PRS_CH11 #3
ACMP0_O #15
ACMP1_O #15
GPIO_EM4WU12
31
PC10
TIM1_CC1 #14
TIM1_CC2 #13
BUSBY [ADC0:
APORT2YCH10
ACMP0:
APORT2YCH10
ACMP1:
TIM1_CC3 #12 LE-
TIM0_OUT0 #15 LE-
TIM0_OUT1 #14
PCNT0_S0IN #15
PCNT0_S1IN #14
APORT2YCH10]
TIM0_CC0 #16
TIM0_CC1 #15
TIM0_CC2 #14
TIM0_CDTI0 #13
TIM0_CDTI1 #12
TIM0_CDTI2 #11
TIM1_CC0 #16
BUSAY [ADC0:
APORT1YCH11
ACMP0:
APORT1YCH11
ACMP1:
US0_TX #16 US0_RX
#15 US0_CLK #14
US0_CS #13 US0_CTS
#12 US0_RTS #11
US1_TX #16 US1_RX
#15 US1_CLK #14
US1_CS #13 US1_CTS
#12 US1_RTS #11
LEU0_TX #16 LEU0_RX
#15 I2C0_SDA #16
I2C0_SCL #15
CMU_CLK0 #3
PRS_CH0 #13
PRS_CH9 #16
PRS_CH10 #5
PRS_CH11 #4
ACMP0_O #16
ACMP1_O #16
DBG_SWO #3
APORT1YCH11]
32
PC11
TIM1_CC1 #15
TIM1_CC2 #14
BUSBX [ADC0:
APORT2XCH11
ACMP0:
APORT2XCH11
ACMP1:
TIM1_CC3 #13 LE-
TIM0_OUT0 #16 LE-
TIM0_OUT1 #15
PCNT0_S0IN #16
PCNT0_S1IN #15
APORT2XCH11]
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Preliminary Rev. 0.31 | 53
EFM32JG1 Data Sheet
Pin Definitions
6.2.1 GPIO Pinout Overview
The GPIO pins are organized as 16-bit ports indicated by letters A through F, and the individual pins on each port is indicated by a
number from 15 down to 0.
Table 6.4. GPIO Pinout
Port
Pin
15
Pin
14
Pin
13
Pin
12
Pin
11
Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
10
Port A
Port B
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PA1 PA0
PB13 PB12 PB11
(5V) (5V) (5V)
PB15 PB14
-
-
-
-
PC11 PC10
(5V) (5V)
Port C
-
-
-
-
-
-
-
-
-
-
-
-
PD15 PD14 PD13 PD12 PD11 PD10 PD9
(5V) (5V) (5V) (5V) (5V) (5V) (5V)
Port D
Port E
Port F
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PF3 PF2 PF1 PF0
(5V) (5V) (5V) (5V)
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Preliminary Rev. 0.31 | 54
EFM32JG1 Data Sheet
Pin Definitions
6.3 EFM32JG1 QFN32 without DC-DC Definition
Figure 6.3. EFM32JG1 QFN32 without DC-DC Converter Pinout
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Preliminary Rev. 0.31 | 55
EFM32JG1 Data Sheet
Pin Definitions
Table 6.5. Device Pinout
QFN32 Pin# and Name
Pin Alternate Functionality / Description
Pin
#
Pin Name
Analog
Timers
Communication
Other
0
VREGVSS
Voltage regulator VSS
TIM0_CC0 #24
TIM0_CC1 #23
TIM0_CC2 #22
TIM0_CDTI0 #21
TIM0_CDTI1 #20
TIM0_CDTI2 #19
TIM1_CC0 #24
BUSAX [ADC0:
APORT1XCH16
ACMP0:
APORT1XCH16
ACMP1:
US0_TX #24 US0_RX
#23 US0_CLK #22
US0_CS #21 US0_CTS
#20 US0_RTS #19
US1_TX #24 US1_RX
#23 US1_CLK #22
US1_CS #21 US1_CTS
#20 US1_RTS #19
LEU0_TX #24 LEU0_RX
#23 I2C0_SDA #24
I2C0_SCL #23
PRS_CH0 #0 PRS_CH1
#7 PRS_CH2 #6
APORT1XCH16]
PRS_CH3 #5 ACMP0_O
#24 ACMP1_O #24
DBG_SWCLKTCK #0
BOOT_TX
1
PF0
PF1
PF2
TIM1_CC1 #23
TIM1_CC2 #22
BUSBY [ADC0:
APORT2YCH16
ACMP0:
APORT2YCH16
ACMP1:
TIM1_CC3 #21 LE-
TIM0_OUT0 #24 LE-
TIM0_OUT1 #23
PCNT0_S0IN #24
PCNT0_S1IN #23
APORT2YCH16]
TIM0_CC0 #25
TIM0_CC1 #24
TIM0_CC2 #23
TIM0_CDTI0 #22
TIM0_CDTI1 #21
TIM0_CDTI2 #20
TIM1_CC0 #25
BUSAY [ADC0:
APORT1YCH17
ACMP0:
APORT1YCH17
ACMP1:
US0_TX #25 US0_RX
#24 US0_CLK #23
US0_CS #22 US0_CTS
#21 US0_RTS #20
US1_TX #25 US1_RX
#24 US1_CLK #23
US1_CS #22 US1_CTS
#21 US1_RTS #20
LEU0_TX #25 LEU0_RX
#24 I2C0_SDA #25
I2C0_SCL #24
PRS_CH0 #1 PRS_CH1
#0 PRS_CH2 #7
PRS_CH3 #6 ACMP0_O
#25 ACMP1_O #25
DBG_SWDIOTMS #0
BOOT_RX
APORT1YCH17]
2
TIM1_CC1 #24
TIM1_CC2 #23
BUSBX [ADC0:
APORT2XCH17
ACMP0:
APORT2XCH17
ACMP1:
TIM1_CC3 #22 LE-
TIM0_OUT0 #25 LE-
TIM0_OUT1 #24
PCNT0_S0IN #25
PCNT0_S1IN #24
APORT2XCH17]
TIM0_CC0 #26
TIM0_CC1 #25
TIM0_CC2 #24
TIM0_CDTI0 #23
TIM0_CDTI1 #22
TIM0_CDTI2 #21
TIM1_CC0 #26
BUSAX [ADC0:
APORT1XCH18
ACMP0:
APORT1XCH18
ACMP1:
US0_TX #26 US0_RX
#25 US0_CLK #24
US0_CS #23 US0_CTS
#22 US0_RTS #21
US1_TX #26 US1_RX
#25 US1_CLK #24
US1_CS #23 US1_CTS
#22 US1_RTS #21
LEU0_TX #26 LEU0_RX
#25 I2C0_SDA #26
I2C0_SCL #25
CMU_CLK0 #6
PRS_CH0 #2 PRS_CH1
#1 PRS_CH2 #0
PRS_CH3 #7 ACMP0_O
#26 ACMP1_O #26
DBG_TDO #0
APORT1XCH18]
3
TIM1_CC1 #25
TIM1_CC2 #24
BUSBY [ADC0:
APORT2YCH18
ACMP0:
APORT2YCH18
ACMP1:
TIM1_CC3 #23 LE-
TIM0_OUT0 #26 LE-
TIM0_OUT1 #25
PCNT0_S0IN #26
PCNT0_S1IN #25
DBG_SWO #0
GPIO_EM4WU0
APORT2YCH18]
silabs.com | Smart. Connected. Energy-friendly.
Preliminary Rev. 0.31 | 56
EFM32JG1 Data Sheet
Pin Definitions
QFN32 Pin# and Name
Pin Alternate Functionality / Description
Pin
#
Pin Name
Analog
Timers
Communication
Other
TIM0_CC0 #27
TIM0_CC1 #26
TIM0_CC2 #25
TIM0_CDTI0 #24
TIM0_CDTI1 #23
TIM0_CDTI2 #22
TIM1_CC0 #27
BUSAY [ADC0:
APORT1YCH19
ACMP0:
APORT1YCH19
ACMP1:
US0_TX #27 US0_RX
#26 US0_CLK #25
US0_CS #24 US0_CTS
#23 US0_RTS #22
US1_TX #27 US1_RX
#26 US1_CLK #25
US1_CS #24 US1_CTS
#23 US1_RTS #22
LEU0_TX #27 LEU0_RX
#26 I2C0_SDA #27
I2C0_SCL #26
CMU_CLK1 #6
PRS_CH0 #3 PRS_CH1
#2 PRS_CH2 #1
PRS_CH3 #0 ACMP0_O
#27 ACMP1_O #27
DBG_TDI #0
APORT1YCH19]
4
PF3
TIM1_CC1 #26
TIM1_CC2 #25
BUSBX [ADC0:
APORT2XCH19
ACMP0:
APORT2XCH19
ACMP1:
TIM1_CC3 #24 LE-
TIM0_OUT0 #27 LE-
TIM0_OUT1 #26
PCNT0_S0IN #27
PCNT0_S1IN #26
APORT2XCH19]
TIM0_CC0 #28
TIM0_CC1 #27
TIM0_CC2 #26
TIM0_CDTI0 #25
TIM0_CDTI1 #24
TIM0_CDTI2 #23
TIM1_CC0 #28
BUSAX [ADC0:
APORT1XCH20
ACMP0:
APORT1XCH20
ACMP1:
US0_TX #28 US0_RX
#27 US0_CLK #26
US0_CS #25 US0_CTS
#24 US0_RTS #23
US1_TX #28 US1_RX
#27 US1_CLK #26
US1_CS #25 US1_CTS
#24 US1_RTS #23
LEU0_TX #28 LEU0_RX
#27 I2C0_SDA #28
I2C0_SCL #27
PRS_CH0 #4 PRS_CH1
#3 PRS_CH2 #2
PRS_CH3 #1 ACMP0_O
#28 ACMP1_O #28
APORT1XCH20]
5
PF4
TIM1_CC1 #27
TIM1_CC2 #26
BUSBY [ADC0:
APORT2YCH20
ACMP0:
APORT2YCH20
ACMP1:
TIM1_CC3 #25 LE-
TIM0_OUT0 #28 LE-
TIM0_OUT1 #27
PCNT0_S0IN #28
PCNT0_S1IN #27
APORT2YCH20]
6
7
8
AVDD_1
HFXTAL_N
HFXTAL_P
Analog power supply 1.
High Frequency Crystal input pin.
High Frequency Crystal output pin.
Reset input, active low.To apply an external reset source to this pin, it is required to only drive this pin low
during reset, and let the internal pull-up ensure that reset is released.
9
RESETn
TIM0_CC0 #17
TIM0_CC1 #16
US0_TX #17 US0_RX
TIM0_CC2 #15
TIM0_CDTI0 #14
TIM0_CDTI1 #13
TIM0_CDTI2 #12
TIM1_CC0 #17
BUSCY [ADC0:
APORT3YCH1 ACMP0:
APORT3YCH1 ACMP1:
APORT3YCH1 IDAC0:
APORT1YCH1]
#16 US0_CLK #15
US0_CS #14 US0_CTS
#13 US0_RTS #12
US1_TX #17 US1_RX
#16 US1_CLK #15
US1_CS #14 US1_CTS
#13 US1_RTS #12
LEU0_TX #17 LEU0_RX
#16 I2C0_SDA #17
I2C0_SCL #16
CMU_CLK0 #4
PRS_CH3 #8 PRS_CH4
#0 PRS_CH5 #6
PRS_CH6 #11
10
PD9
TIM1_CC1 #16
TIM1_CC2 #15
BUSDX [ADC0:
APORT4XCH1 ACMP0:
APORT4XCH1 ACMP1:
APORT4XCH1]
ACMP0_O #17
ACMP1_O #17
TIM1_CC3 #14 LE-
TIM0_OUT0 #17 LE-
TIM0_OUT1 #16
PCNT0_S0IN #17
PCNT0_S1IN #16
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Preliminary Rev. 0.31 | 57
EFM32JG1 Data Sheet
Pin Definitions
QFN32 Pin# and Name
Pin Alternate Functionality / Description
Pin
#
Pin Name
Analog
Timers
Communication
Other
TIM0_CC0 #18
TIM0_CC1 #17
TIM0_CC2 #16
TIM0_CDTI0 #15
TIM0_CDTI1 #14
TIM0_CDTI2 #13
TIM1_CC0 #18
US0_TX #18 US0_RX
#17 US0_CLK #16
US0_CS #15 US0_CTS
#14 US0_RTS #13
US1_TX #18 US1_RX
#17 US1_CLK #16
US1_CS #15 US1_CTS
#14 US1_RTS #13
LEU0_TX #18 LEU0_RX
#17 I2C0_SDA #18
I2C0_SCL #17
BUSCX [ADC0:
APORT3XCH2 ACMP0:
APORT3XCH2 ACMP1:
APORT3XCH2 IDAC0:
APORT1XCH2]
CMU_CLK1 #4
PRS_CH3 #9 PRS_CH4
#1 PRS_CH5 #0
PRS_CH6 #12
11
12
13
14
PD10
TIM1_CC1 #17
TIM1_CC2 #16
BUSDY [ADC0:
APORT4YCH2 ACMP0:
APORT4YCH2 ACMP1:
APORT4YCH2]
ACMP0_O #18
ACMP1_O #18
TIM1_CC3 #15 LE-
TIM0_OUT0 #18 LE-
TIM0_OUT1 #17
PCNT0_S0IN #18
PCNT0_S1IN #17
TIM0_CC0 #19
TIM0_CC1 #18
TIM0_CC2 #17
TIM0_CDTI0 #16
TIM0_CDTI1 #15
TIM0_CDTI2 #14
TIM1_CC0 #19
US0_TX #19 US0_RX
#18 US0_CLK #17
US0_CS #16 US0_CTS
#15 US0_RTS #14
BUSCY [ADC0:
APORT3YCH3 ACMP0:
APORT3YCH3 ACMP1:
APORT3YCH3 IDAC0:
APORT1YCH3]
PRS_CH3 #10
US1_TX #19 US1_RX PRS_CH4 #2 PRS_CH5
PD11
PD12
PD13
#18 US1_CLK #17
US1_CS #16 US1_CTS
#15 US1_RTS #14
LEU0_TX #19 LEU0_RX
#18 I2C0_SDA #19
I2C0_SCL #18
#1 PRS_CH6 #13
ACMP0_O #19
ACMP1_O #19
TIM1_CC1 #18
TIM1_CC2 #17
BUSDX [ADC0:
APORT4XCH3 ACMP0:
APORT4XCH3 ACMP1:
APORT4XCH3]
TIM1_CC3 #16 LE-
TIM0_OUT0 #19 LE-
TIM0_OUT1 #18
PCNT0_S0IN #19
PCNT0_S1IN #18
TIM0_CC0 #20
TIM0_CC1 #19
TIM0_CC2 #18
TIM0_CDTI0 #17
TIM0_CDTI1 #16
TIM0_CDTI2 #15
TIM1_CC0 #20
US0_TX #20 US0_RX
#19 US0_CLK #18
US0_CS #17 US0_CTS
#16 US0_RTS #15
BUSCX [ADC0:
APORT3XCH4 ACMP0:
APORT3XCH4 ACMP1:
APORT3XCH4 IDAC0:
APORT1XCH4]
PRS_CH3 #11
US1_TX #20 US1_RX PRS_CH4 #3 PRS_CH5
#19 US1_CLK #18
US1_CS #17 US1_CTS
#16 US1_RTS #15
LEU0_TX #20 LEU0_RX
#19 I2C0_SDA #20
I2C0_SCL #19
#2 PRS_CH6 #14
ACMP0_O #20
ACMP1_O #20
TIM1_CC1 #19
TIM1_CC2 #18
BUSDY [ADC0:
APORT4YCH4 ACMP0:
APORT4YCH4 ACMP1:
APORT4YCH4]
TIM1_CC3 #17 LE-
TIM0_OUT0 #20 LE-
TIM0_OUT1 #19
PCNT0_S0IN #20
PCNT0_S1IN #19
TIM0_CC0 #21
TIM0_CC1 #20
TIM0_CC2 #19
TIM0_CDTI0 #18
TIM0_CDTI1 #17
TIM0_CDTI2 #16
TIM1_CC0 #21
US0_TX #21 US0_RX
#20 US0_CLK #19
US0_CS #18 US0_CTS
#17 US0_RTS #16
BUSCY [ADC0:
APORT3YCH5 ACMP0:
APORT3YCH5 ACMP1:
APORT3YCH5 IDAC0:
APORT1YCH5]
PRS_CH3 #12
US1_TX #21 US1_RX PRS_CH4 #4 PRS_CH5
#20 US1_CLK #19
US1_CS #18 US1_CTS
#17 US1_RTS #16
LEU0_TX #21 LEU0_RX
#20 I2C0_SDA #21
I2C0_SCL #20
#3 PRS_CH6 #15
ACMP0_O #21
ACMP1_O #21
TIM1_CC1 #20
TIM1_CC2 #19
BUSDX [ADC0:
APORT4XCH5 ACMP0:
APORT4XCH5 ACMP1:
APORT4XCH5]
TIM1_CC3 #18 LE-
TIM0_OUT0 #21 LE-
TIM0_OUT1 #20
PCNT0_S0IN #21
PCNT0_S1IN #20
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Preliminary Rev. 0.31 | 58
EFM32JG1 Data Sheet
Pin Definitions
QFN32 Pin# and Name
Pin Alternate Functionality / Description
Pin
#
Pin Name
Analog
Timers
Communication
Other
TIM0_CC0 #22
TIM0_CC1 #21
TIM0_CC2 #20
TIM0_CDTI0 #19
TIM0_CDTI1 #18
TIM0_CDTI2 #17
TIM1_CC0 #22
US0_TX #22 US0_RX
#21 US0_CLK #20
US0_CS #19 US0_CTS
#18 US0_RTS #17
BUSCX [ADC0:
APORT3XCH6 ACMP0:
APORT3XCH6 ACMP1:
APORT3XCH6 IDAC0:
APORT1XCH6]
CMU_CLK0 #5
PRS_CH3 #13
US1_TX #22 US1_RX PRS_CH4 #5 PRS_CH5
15
16
17
18
PD14
#21 US1_CLK #20
US1_CS #19 US1_CTS
#18 US1_RTS #17
LEU0_TX #22 LEU0_RX
#21 I2C0_SDA #22
I2C0_SCL #21
#4 PRS_CH6 #16
ACMP0_O #22
ACMP1_O #22
GPIO_EM4WU4
TIM1_CC1 #21
TIM1_CC2 #20
BUSDY [ADC0:
APORT4YCH6 ACMP0:
APORT4YCH6 ACMP1:
APORT4YCH6]
TIM1_CC3 #19 LE-
TIM0_OUT0 #22 LE-
TIM0_OUT1 #21
PCNT0_S0IN #22
PCNT0_S1IN #21
TIM0_CC0 #23
TIM0_CC1 #22
TIM0_CC2 #21
TIM0_CDTI0 #20
TIM0_CDTI1 #19
TIM0_CDTI2 #18
TIM1_CC0 #23
US0_TX #23 US0_RX
#22 US0_CLK #21
US0_CS #20 US0_CTS
#19 US0_RTS #18
BUSCY [ADC0:
APORT3YCH7 ACMP0:
APORT3YCH7 ACMP1:
APORT3YCH7 IDAC0:
APORT1YCH7]
CMU_CLK1 #5
PRS_CH3 #14
US1_TX #23 US1_RX PRS_CH4 #6 PRS_CH5
PD15
#22 US1_CLK #21
US1_CS #20 US1_CTS
#19 US1_RTS #18
LEU0_TX #23 LEU0_RX
#22 I2C0_SDA #23
I2C0_SCL #22
#5 PRS_CH6 #17
ACMP0_O #23
ACMP1_O #23
DBG_SWO #2
TIM1_CC1 #22
TIM1_CC2 #21
BUSDX [ADC0:
APORT4XCH7 ACMP0:
APORT4XCH7 ACMP1:
APORT4XCH7]
TIM1_CC3 #20 LE-
TIM0_OUT0 #23 LE-
TIM0_OUT1 #22
PCNT0_S0IN #23
PCNT0_S1IN #22
TIM0_CC0 #0
TIM0_CC1 #31
TIM0_CC2 #30
TIM0_CDTI0 #29
TIM0_CDTI1 #28
TIM0_CDTI2 #27
TIM1_CC0 #0
TIM1_CC1 #31
TIM1_CC2 #30
TIM1_CC3 #29 LE-
TIM0_OUT0 #0 LE-
TIM0_OUT1 #31
PCNT0_S0IN #0
PCNT0_S1IN #31
ADC0_EXTN
US0_TX #0 US0_RX
#31 US0_CLK #30
US0_CS #29 US0_CTS
#28 US0_RTS #27
US1_TX #0 US1_RX
#31 US1_CLK #30
BUSCX [ADC0:
APORT3XCH8 ACMP0:
APORT3XCH8 ACMP1:
APORT3XCH8 IDAC0:
APORT1XCH8]
CMU_CLK1 #0
PRS_CH6 #0 PRS_CH7
#10 PRS_CH8 #9
PA0
US1_CS #29 US1_CTS PRS_CH9 #8 ACMP0_O
#28 US1_RTS #27
LEU0_TX #0 LEU0_RX
#31 I2C0_SDA #0
I2C0_SCL #31
#0 ACMP1_O #0
BUSDY [ADC0:
APORT4YCH8 ACMP0:
APORT4YCH8 ACMP1:
APORT4YCH8]
TIM0_CC0 #1
TIM0_CC1 #0
ADC0_EXTP
US0_TX #1 US0_RX #0
US0_CLK #31 US0_CS
#30 US0_CTS #29
US0_RTS #28 US1_TX
#1 US1_RX #0
US1_CLK #31 US1_CS
#30 US1_CTS #29
US1_RTS #28 LEU0_TX
#1 LEU0_RX #0
TIM0_CC2 #31
TIM0_CDTI0 #30
TIM0_CDTI1 #29
TIM0_CDTI2 #28
TIM1_CC0 #1
BUSCY [ADC0:
APORT3YCH9 ACMP0:
APORT3YCH9 ACMP1:
APORT3YCH9 IDAC0:
APORT1YCH9]
CMU_CLK0 #0
PRS_CH6 #1 PRS_CH7
#0 PRS_CH8 #10
PA1
TIM1_CC1 #0
PRS_CH9 #9 ACMP0_O
#1 ACMP1_O #1
TIM1_CC2 #31
TIM1_CC3 #30 LE-
TIM0_OUT0 #1 LE-
TIM0_OUT1 #0
PCNT0_S0IN #1
PCNT0_S1IN #0
BUSDX [ADC0:
APORT4XCH9 ACMP0:
APORT4XCH9 ACMP1:
APORT4XCH9]
I2C0_SDA #1 I2C0_SCL
#0
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Preliminary Rev. 0.31 | 59
EFM32JG1 Data Sheet
Pin Definitions
QFN32 Pin# and Name
Pin Alternate Functionality / Description
Pin
#
Pin Name
Analog
Timers
Communication
Other
TIM0_CC0 #6
TIM0_CC1 #5
TIM0_CC2 #4
TIM0_CDTI0 #3
TIM0_CDTI1 #2
TIM0_CDTI2 #1
TIM1_CC0 #6
BUSCY [ADC0:
APORT3YCH27
ACMP0:
APORT3YCH27
ACMP1:
US0_TX #6 US0_RX #5
US0_CLK #4 US0_CS
#3 US0_CTS #2
US0_RTS #1 US1_TX
#6 US1_RX #5
US1_CLK #4 US1_CS
#3 US1_CTS #2
US1_RTS #1 LEU0_TX
#6 LEU0_RX #5
PRS_CH6 #6 PRS_CH7
#5 PRS_CH8 #4
PRS_CH9 #3 ACMP0_O
#6 ACMP1_O #6
APORT3YCH27 IDAC0:
APORT1YCH27]
19
PB11
TIM1_CC1 #5
TIM1_CC2 #4
BUSDX [ADC0:
APORT4XCH27
ACMP0:
APORT4XCH27
ACMP1:
TIM1_CC3 #3 LE-
TIM0_OUT0 #6 LE-
TIM0_OUT1 #5
PCNT0_S0IN #6
PCNT0_S1IN #5
I2C0_SDA #6 I2C0_SCL
#5
APORT4XCH27]
TIM0_CC0 #7
TIM0_CC1 #6
TIM0_CC2 #5
TIM0_CDTI0 #4
TIM0_CDTI1 #3
TIM0_CDTI2 #2
TIM1_CC0 #7
BUSCX [ADC0:
APORT3XCH28
ACMP0:
APORT3XCH28
ACMP1:
US0_TX #7 US0_RX #6
US0_CLK #5 US0_CS
#4 US0_CTS #3
US0_RTS #2 US1_TX
#7 US1_RX #6
US1_CLK #5 US1_CS
#4 US1_CTS #3
US1_RTS #2 LEU0_TX
#7 LEU0_RX #6
PRS_CH6 #7 PRS_CH7
#6 PRS_CH8 #5
PRS_CH9 #4 ACMP0_O
#7 ACMP1_O #7
APORT3XCH28 IDAC0:
APORT1XCH28]
20
PB12
TIM1_CC1 #6
TIM1_CC2 #5
BUSDY [ADC0:
APORT4YCH28
ACMP0:
APORT4YCH28
ACMP1:
TIM1_CC3 #4 LE-
TIM0_OUT0 #7 LE-
TIM0_OUT1 #6
PCNT0_S0IN #7
PCNT0_S1IN #6
I2C0_SDA #7 I2C0_SCL
#6
APORT4YCH28]
TIM0_CC0 #8
TIM0_CC1 #7
TIM0_CC2 #6
TIM0_CDTI0 #5
TIM0_CDTI1 #4
TIM0_CDTI2 #3
TIM1_CC0 #8
BUSCY [ADC0:
APORT3YCH29
ACMP0:
APORT3YCH29
ACMP1:
US0_TX #8 US0_RX #7
US0_CLK #6 US0_CS
#5 US0_CTS #4
US0_RTS #3 US1_TX
#8 US1_RX #7
US1_CLK #6 US1_CS
#5 US1_CTS #4
US1_RTS #3 LEU0_TX
#8 LEU0_RX #7
PRS_CH6 #8 PRS_CH7
#7 PRS_CH8 #6
APORT3YCH29 IDAC0:
APORT1YCH29]
PRS_CH9 #5 ACMP0_O
#8 ACMP1_O #8
21
22
PB13
TIM1_CC1 #7
TIM1_CC2 #6
BUSDX [ADC0:
APORT4XCH29
ACMP0:
APORT4XCH29
ACMP1:
DBG_SWO #1
GPIO_EM4WU9
TIM1_CC3 #5 LE-
TIM0_OUT0 #8 LE-
TIM0_OUT1 #7
PCNT0_S0IN #8
PCNT0_S1IN #7
I2C0_SDA #8 I2C0_SCL
#7
APORT4XCH29]
AVDD_0
Analog power supply 0.
LFXTAL_N
TIM0_CC0 #9
TIM0_CC1 #8
TIM0_CC2 #7
TIM0_CDTI0 #6
TIM0_CDTI1 #5
TIM0_CDTI2 #4
TIM1_CC0 #9
BUSCX [ADC0:
APORT3XCH30
ACMP0:
APORT3XCH30
ACMP1:
US0_TX #9 US0_RX #8
US0_CLK #7 US0_CS
#6 US0_CTS #5
US0_RTS #4 US1_TX
#9 US1_RX #8
US1_CLK #7 US1_CS
#6 US1_CTS #5
US1_RTS #4 LEU0_TX
#9 LEU0_RX #8
CMU_CLK1 #1
PRS_CH6 #9 PRS_CH7
#8 PRS_CH8 #7
PRS_CH9 #6 ACMP0_O
#9 ACMP1_O #9
APORT3XCH30 IDAC0:
APORT1XCH30]
23
PB14
TIM1_CC1 #8
TIM1_CC2 #7
BUSDY [ADC0:
APORT4YCH30
ACMP0:
APORT4YCH30
ACMP1:
TIM1_CC3 #6 LE-
TIM0_OUT0 #9 LE-
TIM0_OUT1 #8
PCNT0_S0IN #9
PCNT0_S1IN #8
I2C0_SDA #9 I2C0_SCL
#8
APORT4YCH30]
silabs.com | Smart. Connected. Energy-friendly.
Preliminary Rev. 0.31 | 60
EFM32JG1 Data Sheet
Pin Definitions
QFN32 Pin# and Name
Pin Alternate Functionality / Description
Pin
#
Pin Name
Analog
Timers
Communication
Other
LFXTAL_P
TIM0_CC0 #10
TIM0_CC1 #9
TIM0_CC2 #8
TIM0_CDTI0 #7
TIM0_CDTI1 #6
TIM0_CDTI2 #5
TIM1_CC0 #10
TIM1_CC1 #9
BUSCY [ADC0:
APORT3YCH31
ACMP0:
APORT3YCH31
ACMP1:
US0_TX #10 US0_RX
#9 US0_CLK #8
US0_CS #7 US0_CTS
#6 US0_RTS #5
US1_TX #10 US1_RX
#9 US1_CLK #8
US1_CS #7 US1_CTS
#6 US1_RTS #5
LEU0_TX #10 LEU0_RX
#9 I2C0_SDA #10
I2C0_SCL #9
CMU_CLK0 #1
PRS_CH6 #10
PRS_CH7 #9 PRS_CH8
#8 PRS_CH9 #7
ACMP0_O #10
APORT3YCH31 IDAC0:
APORT1YCH31]
24
PB15
TIM1_CC2 #8
BUSDX [ADC0:
APORT4XCH31
ACMP0:
APORT4XCH31
ACMP1:
TIM1_CC3 #7 LE-
TIM0_OUT0 #10 LE-
TIM0_OUT1 #9
PCNT0_S0IN #10
PCNT0_S1IN #9
ACMP1_O #10
APORT4XCH31]
25
26
27
DVDD
DECOUPLE
IOVDD
Digital power supply.
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at
this pin.
Digital IO power supply.
TIM0_CC0 #12
TIM0_CC1 #11
US0_TX #12 US0_RX
TIM0_CC2 #10
#11 US0_CLK #10
US0_CS #9 US0_CTS
#8 US0_RTS #7
BUSAY [ADC0:
APORT1YCH7 ACMP0:
APORT1YCH7 ACMP1:
APORT1YCH7]
TIM0_CDTI0 #9
TIM0_CDTI1 #8
TIM0_CDTI2 #7
TIM1_CC0 #12
TIM1_CC1 #11
TIM1_CC2 #10
TIM1_CC3 #9 LE-
TIM0_OUT0 #12 LE-
TIM0_OUT1 #11
PCNT0_S0IN #12
PCNT0_S1IN #11
CMU_CLK1 #2
PRS_CH0 #9 PRS_CH9
#12 PRS_CH10 #1
PRS_CH11 #0
US1_TX #12 US1_RX
#11 US1_CLK #10
US1_CS #9 US1_CTS
#8 US1_RTS #7
28
PC7
BUSBX [ADC0:
APORT2XCH7 ACMP0:
APORT2XCH7 ACMP1:
APORT2XCH7]
ACMP0_O #12
ACMP1_O #12
LEU0_TX #12 LEU0_RX
#11 I2C0_SDA #12
I2C0_SCL #11
TIM0_CC0 #13
TIM0_CC1 #12
TIM0_CC2 #11
TIM0_CDTI0 #10
TIM0_CDTI1 #9
TIM0_CDTI2 #8
TIM1_CC0 #13
US0_TX #13 US0_RX
#12 US0_CLK #11
US0_CS #10 US0_CTS
#9 US0_RTS #8
US1_TX #13 US1_RX
#12 US1_CLK #11
US1_CS #10 US1_CTS
#9 US1_RTS #8
BUSAX [ADC0:
APORT1XCH8 ACMP0:
APORT1XCH8 ACMP1:
APORT1XCH8]
PRS_CH0 #10
PRS_CH9 #13
PRS_CH10 #2
PRS_CH11 #1
ACMP0_O #13
ACMP1_O #13
29
PC8
TIM1_CC1 #12
TIM1_CC2 #11
BUSBY [ADC0:
APORT2YCH8 ACMP0:
APORT2YCH8 ACMP1:
APORT2YCH8]
TIM1_CC3 #10 LE-
TIM0_OUT0 #13 LE-
TIM0_OUT1 #12
PCNT0_S0IN #13
PCNT0_S1IN #12
LEU0_TX #13 LEU0_RX
#12 I2C0_SDA #13
I2C0_SCL #12
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EFM32JG1 Data Sheet
Pin Definitions
QFN32 Pin# and Name
Pin Alternate Functionality / Description
Pin
#
Pin Name
Analog
Timers
Communication
Other
TIM0_CC0 #14
TIM0_CC1 #13
TIM0_CC2 #12
TIM0_CDTI0 #11
TIM0_CDTI1 #10
TIM0_CDTI2 #9
TIM1_CC0 #14
US0_TX #14 US0_RX
#13 US0_CLK #12
US0_CS #11 US0_CTS
#10 US0_RTS #9
US1_TX #14 US1_RX
#13 US1_CLK #12
US1_CS #11 US1_CTS
#10 US1_RTS #9
BUSAY [ADC0:
APORT1YCH9 ACMP0:
APORT1YCH9 ACMP1:
APORT1YCH9]
PRS_CH0 #11
PRS_CH9 #14
PRS_CH10 #3
PRS_CH11 #2
ACMP0_O #14
ACMP1_O #14
30
31
32
PC9
TIM1_CC1 #13
TIM1_CC2 #12
BUSBX [ADC0:
APORT2XCH9 ACMP0:
APORT2XCH9 ACMP1:
APORT2XCH9]
TIM1_CC3 #11 LE-
TIM0_OUT0 #14 LE-
TIM0_OUT1 #13
PCNT0_S0IN #14
PCNT0_S1IN #13
LEU0_TX #14 LEU0_RX
#13 I2C0_SDA #14
I2C0_SCL #13
TIM0_CC0 #15
TIM0_CC1 #14
TIM0_CC2 #13
TIM0_CDTI0 #12
TIM0_CDTI1 #11
TIM0_CDTI2 #10
TIM1_CC0 #15
BUSAX [ADC0:
APORT1XCH10
ACMP0:
APORT1XCH10
ACMP1:
US0_TX #15 US0_RX
#14 US0_CLK #13
US0_CS #12 US0_CTS
#11 US0_RTS #10
US1_TX #15 US1_RX
#14 US1_CLK #13
US1_CS #12 US1_CTS
#11 US1_RTS #10
LEU0_TX #15 LEU0_RX
#14 I2C0_SDA #15
I2C0_SCL #14
CMU_CLK1 #3
PRS_CH0 #12
PRS_CH9 #15
PRS_CH10 #4
PRS_CH11 #3
ACMP0_O #15
ACMP1_O #15
GPIO_EM4WU12
APORT1XCH10]
PC10
TIM1_CC1 #14
TIM1_CC2 #13
BUSBY [ADC0:
APORT2YCH10
ACMP0:
APORT2YCH10
ACMP1:
TIM1_CC3 #12 LE-
TIM0_OUT0 #15 LE-
TIM0_OUT1 #14
PCNT0_S0IN #15
PCNT0_S1IN #14
APORT2YCH10]
TIM0_CC0 #16
TIM0_CC1 #15
TIM0_CC2 #14
TIM0_CDTI0 #13
TIM0_CDTI1 #12
TIM0_CDTI2 #11
TIM1_CC0 #16
BUSAY [ADC0:
APORT1YCH11
ACMP0:
APORT1YCH11
ACMP1:
US0_TX #16 US0_RX
#15 US0_CLK #14
US0_CS #13 US0_CTS
#12 US0_RTS #11
US1_TX #16 US1_RX
#15 US1_CLK #14
US1_CS #13 US1_CTS
#12 US1_RTS #11
LEU0_TX #16 LEU0_RX
#15 I2C0_SDA #16
I2C0_SCL #15
CMU_CLK0 #3
PRS_CH0 #13
PRS_CH9 #16
PRS_CH10 #5
PRS_CH11 #4
ACMP0_O #16
ACMP1_O #16
DBG_SWO #3
APORT1YCH11]
PC11
TIM1_CC1 #15
TIM1_CC2 #14
BUSBX [ADC0:
APORT2XCH11
ACMP0:
APORT2XCH11
ACMP1:
TIM1_CC3 #13 LE-
TIM0_OUT0 #16 LE-
TIM0_OUT1 #15
PCNT0_S0IN #16
PCNT0_S1IN #15
APORT2XCH11]
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Preliminary Rev. 0.31 | 62
EFM32JG1 Data Sheet
Pin Definitions
6.3.1 GPIO Pinout Overview
The GPIO pins are organized as 16-bit ports indicated by letters A through F, and the individual pins on each port is indicated by a
number from 15 down to 0.
Table 6.6. GPIO Pinout
Port
Pin
15
Pin
14
Pin
13
Pin
12
Pin
11
Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
10
Port A
Port B
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PA1 PA0
PB13 PB12 PB11
(5V) (5V) (5V)
PB15 PB14
-
-
-
-
PC11 PC10 PC9 PC8 PC7
(5V) (5V) (5V) (5V) (5V)
Port C
-
-
-
-
-
-
-
-
-
PD15 PD14 PD13 PD12 PD11 PD10 PD9
(5V) (5V) (5V) (5V) (5V) (5V) (5V)
Port D
Port E
Port F
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PF4 PF3 PF2 PF1 PF0
(5V) (5V) (5V) (5V) (5V)
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EFM32JG1 Data Sheet
Pin Definitions
6.4 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. The following table shows the name of the alter-
nate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.
Table 6.7. Alternate functionality overview
Alternate
LOCATION
12 - 15 16 - 19
16: PC11 20: PD12 24: PF0
Functionality
0 - 3
4 - 7
8 - 11
20 - 23
24 - 27
28 - 31
Description
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
12: PC7
13: PC8
28: PF4
29: PF5
30: PF6
31: PF7
Analog comparator
ACMP0, digital out-
put.
17: PD9 21: PD13 25: PF1
18: PD10 22: PD14 26: PF2
15: PC10 19: PD11 23: PD15 27: PF3
ACMP0_O
ACMP1_O
ADC0_EXTN
ADC0_EXTP
BOOT_RX
BOOT_TX
10: PB15 14: PC9
11: PC6
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
12: PC7
16: PC11 20: PD12 24: PF0
17: PD9 21: PD13 25: PF1
18: PD10 22: PD14 26: PF2
15: PC10 19: PD11 23: PD15 27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
Analog comparator
ACMP1, digital out-
put.
13: PC8
10: PB15 14: PC9
11: PC6
0: PA0
0: PA1
0: PF1
0: PF0
Analog to digital
converter ADC0 ex-
ternal reference in-
put negative pin
Analog to digital
converter ADC0 ex-
ternal reference in-
put positive pin
Bootloader RX
Bootloader TX
0: PA1
4: PD9
5: PD14
6: PF2
7: PF7
Clock Management
Unit, clock output
number 0.
1: PB15
2: PC6
3: PC11
CMU_CLK0
CMU_CLK1
0: PA0
4: PD10
5: PD15
6: PF3
Clock Management
Unit, clock output
number 1.
1: PB14
2: PC7
3: PC10
7: PF6
Debug-interface
Serial Wire clock
input and JTAG
Test Clock.
0: PF0
DBG_SWCLKTCK
Note that this func-
tion is enabled to
the pin out of reset,
and has a built-in
pull down.
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EFM32JG1 Data Sheet
Pin Definitions
Alternate
LOCATION
12 - 15 16 - 19
Functionality
0 - 3
4 - 7
8 - 11
20 - 23
24 - 27
28 - 31
Description
Debug-interface
Serial Wire data in-
put / output and
JTAG Test Mode
Select.
0: PF1
DBG_SWDIOTMS
Note that this func-
tion is enabled to
the pin out of reset,
and has a built-in
pull up.
Debug-interface
Serial Wire viewer
Output.
0: PF2
Note that this func-
tion is not enabled
after reset, and
must be enabled by
software to be
used.
1: PB13
2: PD15
3: PC11
DBG_SWO
Debug-interface
JTAG Test Data In.
0: PF3
Note that this func-
tion is enabled to
pin out of reset,
and has a built-in
pull up.
DBG_TDI
Debug-interface
JTAG Test Data
Out.
0: PF2
DBG_TDO
Note that this func-
tion is enabled to
pin out of reset.
0: PF2
0: PF7
0: PD14
0: PA3
0: PB13
Pin can be used to
wake the system
up from EM4
GPIO_EM4WU0
GPIO_EM4WU1
GPIO_EM4WU4
GPIO_EM4WU8
GPIO_EM4WU9
Pin can be used to
wake the system
up from EM4
Pin can be used to
wake the system
up from EM4
Pin can be used to
wake the system
up from EM4
Pin can be used to
wake the system
up from EM4
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Preliminary Rev. 0.31 | 65
EFM32JG1 Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0 - 3
4 - 7
8 - 11
12 - 15
16 - 19
20 - 23
24 - 27
28 - 31
Description
0: PC10
Pin can be used to
wake the system
up from EM4
GPIO_EM4WU12
I2C0_SCL
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
16: PD9
17: PD10 21: PD14 25: PF2
20: PD13 24: PF1
28: PF5
29: PF6
30: PF7
31: PA0
5: PB11
6: PB12
7: PB13
I2C0 Serial Clock
Line input / output.
14: PC10 18: PD11 22: PD15 26: PF3
15: PC11 19: PD12 23: PF0 27: PF4
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15 14: PC9
12: PC7
13: PC8
16: PC11 20: PD12 24: PF0
17: PD9 21: PD13 25: PF1
18: PD10 22: PD14 26: PF2
15: PC10 19: PD11 23: PD15 27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
I2C0 Serial Data in-
put / output.
I2C0_SDA
11: PC6
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15 14: PC9
12: PC7
13: PC8
16: PC11 20: PD12 24: PF0
17: PD9 21: PD13 25: PF1
18: PD10 22: PD14 26: PF2
15: PC10 19: PD11 23: PD15 27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
Low Energy Timer
LETIM0, output
channel 0.
LETIM0_OUT0
LETIM0_OUT1
LEU0_RX
11: PC6
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
16: PD9
20: PD13 24: PF1
28: PF5
29: PF6
30: PF7
31: PA0
Low Energy Timer
LETIM0, output
channel 1.
5: PB11
6: PB12
7: PB13
17: PD10 21: PD14 25: PF2
14: PC10 18: PD11 22: PD15 26: PF3
15: PC11 19: PD12 23: PF0 27: PF4
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
16: PD9
20: PD13 24: PF1
28: PF5
29: PF6
30: PF7
31: PA0
5: PB11
6: PB12
7: PB13
17: PD10 21: PD14 25: PF2
LEUART0 Receive
input.
14: PC10 18: PD11 22: PD15 26: PF3
15: PC11 19: PD12 23: PF0 27: PF4
LEUART0 Transmit
output. Also used
as receive input in
half duplex commu-
nication.
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15 14: PC9
12: PC7
13: PC8
16: PC11 20: PD12 24: PF0
17: PD9 21: PD13 25: PF1
18: PD10 22: PD14 26: PF2
15: PC10 19: PD11 23: PD15 27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
LEU0_TX
11: PC6
Low Frequency
Crystal (typically
32.768 kHz) nega-
tive pin. Also used
as an optional ex-
ternal clock input
pin.
0: PB14
0: PB15
LFXTAL_N
Low Frequency
Crystal (typically
32.768 kHz) posi-
tive pin.
LFXTAL_P
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15 14: PC9
12: PC7
13: PC8
16: PC11 20: PD12 24: PF0
17: PD9 21: PD13 25: PF1
18: PD10 22: PD14 26: PF2
15: PC10 19: PD11 23: PD15 27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
Pulse Counter
PCNT0 input num-
ber 0.
PCNT0_S0IN
PCNT0_S1IN
PRS_CH0
11: PC6
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
16: PD9
20: PD13 24: PF1
28: PF5
29: PF6
30: PF7
31: PA0
Pulse Counter
PCNT0 input num-
ber 1.
5: PB11
6: PB12
7: PB13
17: PD10 21: PD14 25: PF2
14: PC10 18: PD11 22: PD15 26: PF3
15: PC11 19: PD12 23: PF0
27: PF4
0: PF0
1: PF1
2: PF2
3: PF3
4: PF4
5: PF5
6: PF6
7: PF7
8: PC6
9: PC7
10: PC8
11: PC9
12: PC10
13: PC11
Peripheral Reflex
System PRS, chan-
nel 0.
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EFM32JG1 Data Sheet
Pin Definitions
Alternate
LOCATION
12 - 15 16 - 19
Functionality
0 - 3
4 - 7
8 - 11
20 - 23
24 - 27
28 - 31
Description
0: PF1
1: PF2
2: PF3
3: PF4
4: PF5
5: PF6
6: PF7
7: PF0
Peripheral Reflex
System PRS, chan-
nel 1.
PRS_CH1
PRS_CH2
PRS_CH3
PRS_CH4
PRS_CH5
PRS_CH6
PRS_CH7
PRS_CH8
PRS_CH9
PRS_CH10
PRS_CH11
TIM0_CC0
TIM0_CC1
0: PF2
1: PF3
2: PF4
3: PF5
4: PF6
5: PF7
6: PF0
7: PF1
Peripheral Reflex
System PRS, chan-
nel 2.
0: PF3
1: PF4
2: PF5
3: PF6
4: PF7
5: PF0
6: PF1
7: PF2
8: PD9
9: PD10
10: PD11 14: PD15
11: PD12
12: PD13
13: PD14
Peripheral Reflex
System PRS, chan-
nel 3.
0: PD9
4: PD13
5: PD14
6: PD15
Peripheral Reflex
System PRS, chan-
nel 4.
1: PD10
2: PD11
3: PD12
0: PD10
1: PD11
2: PD12
3: PD13
4: PD14
5: PD15
6: PD9
Peripheral Reflex
System PRS, chan-
nel 5.
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15 14: PD12
12: PD10 16: PD14
13: PD11 17: PD15
Peripheral Reflex
System PRS, chan-
nel 6.
11: PD9
15: PD13
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
8: PB14
9: PB15
10: PA0
Peripheral Reflex
System PRS, chan-
nel 7.
5: PB11
6: PB12
7: PB13
0: PA2
1: PA3
2: PA4
3: PA5
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PA0
10: PA1
Peripheral Reflex
System PRS, chan-
nel 8.
0: PA3
1: PA4
2: PA5
3: PB11
4: PB12
5: PB13
6: PB14
7: PB15
8: PA0
9: PA1
10: PA2
11: PC6
12: PC7
13: PC8
14: PC9
15: PC10
16: PC11
Peripheral Reflex
System PRS, chan-
nel 9.
0: PC6
1: PC7
2: PC8
3: PC9
4: PC10
5: PC11
Peripheral Reflex
System PRS, chan-
nel 10.
0: PC7
1: PC8
2: PC9
3: PC10
4: PC11
5: PC6
Peripheral Reflex
System PRS, chan-
nel 11.
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15 14: PC9
12: PC7
16: PC11 20: PD12 24: PF0
17: PD9 21: PD13 25: PF1
18: PD10 22: PD14 26: PF2
15: PC10 19: PD11 23: PD15 27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
Timer 0 Capture
Compare input /
output channel 0.
13: PC8
11: PC6
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
16: PD9
17: PD10 21: PD14 25: PF2
20: PD13 24: PF1
28: PF5
29: PF6
30: PF7
31: PA0
Timer 0 Capture
Compare input /
output channel 1.
5: PB11
6: PB12
7: PB13
14: PC10 18: PD11 22: PD15 26: PF3
15: PC11 19: PD12 23: PF0 27: PF4
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EFM32JG1 Data Sheet
Pin Definitions
Alternate
LOCATION
12 - 15 16 - 19
12: PC9 16: PD10 20: PD14 24: PF2
Functionality
0 - 3
4 - 7
8 - 11
20 - 23
24 - 27
28 - 31
Description
0: PA2
1: PA3
2: PA4
3: PA5
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PC6
10: PC7
11: PC8
28: PF6
29: PF7
30: PA0
31: PA1
Timer 0 Capture
Compare input /
output channel 2.
13: PC10 17: PD11 21: PD15 25: PF3
TIM0_CC2
TIM0_CDTI0
TIM0_CDTI1
TIM0_CDTI2
TIM1_CC0
TIM1_CC1
TIM1_CC2
TIM1_CC3
US0_CLK
US0_CS
14: PC11 18: PD12 22: PF0
15: PD9 19: PD13 23: PF1
26: PF4
27: PF5
0: PA3
1: PA4
2: PA5
3: PB11
4: PB12
5: PB13
6: PB14
7: PB15
8: PC6
9: PC7
10: PC8
11: PC9
12: PC10 16: PD11 20: PD15 24: PF3
28: PF7
29: PA0
30: PA1
31: PA2
Timer 0 Compli-
mentary Dead Time
Insertion channel 0.
13: PC11 17: PD12 21: PF0
14: PD9 18: PD13 22: PF1
15: PD10 19: PD14 23: PF2
25: PF4
26: PF5
27: PF6
0: PA4
1: PA5
2: PB11
3: PB12
4: PB13
5: PB14
6: PB15
7: PC6
8: PC7
9: PC8
10: PC9
12: PC11 16: PD12 20: PF0
24: PF4
25: PF5
26: PF6
27: PF7
28: PA0
29: PA1
30: PA2
31: PA3
Timer 0 Compli-
mentary Dead Time
Insertion channel 1.
13: PD9
17: PD13 21: PF1
14: PD10 18: PD14 22: PF2
11: PC10 15: PD11 19: PD15 23: PF3
0: PA5
4: PB14
5: PB15
6: PC6
7: PC7
8: PC8
9: PC9
12: PD9
13: PD10 17: PD14 21: PF2
10: PC10 14: PD11 18: PD15 22: PF3
11: PC11 15: PD12 19: PF0 23: PF4
16: PD13 20: PF1
24: PF5
25: PF6
26: PF7
27: PA0
28: PA1
29: PA2
30: PA3
31: PA4
Timer 0 Compli-
mentary Dead Time
Insertion channel 2.
1: PB11
2: PB12
3: PB13
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
12: PC7
16: PC11 20: PD12 24: PF0
17: PD9 21: PD13 25: PF1
18: PD10 22: PD14 26: PF2
15: PC10 19: PD11 23: PD15 27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
Timer 1 Capture
Compare input /
output channel 0.
13: PC8
10: PB15 14: PC9
11: PC6
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
16: PD9
17: PD10 21: PD14 25: PF2
20: PD13 24: PF1
28: PF5
29: PF6
30: PF7
31: PA0
Timer 1 Capture
Compare input /
output channel 1.
5: PB11
6: PB12
7: PB13
14: PC10 18: PD11 22: PD15 26: PF3
15: PC11 19: PD12 23: PF0 27: PF4
0: PA2
1: PA3
2: PA4
3: PA5
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PC6
10: PC7
11: PC8
12: PC9 16: PD10 20: PD14 24: PF2
13: PC10 17: PD11 21: PD15 25: PF3
28: PF6
29: PF7
30: PA0
31: PA1
Timer 1 Capture
Compare input /
output channel 2.
14: PC11 18: PD12 22: PF0
15: PD9 19: PD13 23: PF1
26: PF4
27: PF5
0: PA3
1: PA4
2: PA5
3: PB11
4: PB12
5: PB13
6: PB14
7: PB15
8: PC6
9: PC7
10: PC8
11: PC9
12: PC10 16: PD11 20: PD15 24: PF3
28: PF7
29: PA0
30: PA1
31: PA2
Timer 1 Capture
Compare input /
output channel 3.
13: PC11 17: PD12 21: PF0
14: PD9 18: PD13 22: PF1
15: PD10 19: PD14 23: PF2
25: PF4
26: PF5
27: PF6
0: PA2
1: PA3
2: PA4
3: PA5
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PC6
10: PC7
11: PC8
12: PC9
16: PD10 20: PD14 24: PF2
28: PF6
29: PF7
30: PA0
31: PA1
13: PC10 17: PD11 21: PD15 25: PF3
USART0 clock in-
put / output.
14: PC11 18: PD12 22: PF0
15: PD9 19: PD13 23: PF1
26: PF4
27: PF5
0: PA3
1: PA4
2: PA5
3: PB11
4: PB12
5: PB13
6: PB14
7: PB15
8: PC6
9: PC7
10: PC8
11: PC9
12: PC10 16: PD11 20: PD15 24: PF3
28: PF7
29: PA0
30: PA1
31: PA2
13: PC11 17: PD12 21: PF0
14: PD9 18: PD13 22: PF1
15: PD10 19: PD14 23: PF2
25: PF4
26: PF5
27: PF6
USART0 chip se-
lect input / output.
0: PA4
1: PA5
2: PB11
3: PB12
4: PB13
5: PB14
6: PB15
7: PC6
8: PC7
9: PC8
10: PC9
12: PC11 16: PD12 20: PF0
24: PF4
25: PF5
26: PF6
27: PF7
28: PA0
29: PA1
30: PA2
31: PA3
USART0 Clear To
Send hardware
flow control input.
13: PD9
17: PD13 21: PF1
US0_CTS
US0_RTS
14: PD10 18: PD14 22: PF2
11: PC10 15: PD11 19: PD15 23: PF3
0: PA5
4: PB14
5: PB15
6: PC6
7: PC7
8: PC8
9: PC9
12: PD9
16: PD13 20: PF1
24: PF5
25: PF6
26: PF7
27: PA0
28: PA1
29: PA2
30: PA3
31: PA4
USART0 Request
To Send hardware
flow control output.
1: PB11
2: PB12
3: PB13
13: PD10 17: PD14 21: PF2
10: PC10 14: PD11 18: PD15 22: PF3
11: PC11 15: PD12 19: PF0 23: PF4
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EFM32JG1 Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
0 - 3
4 - 7
8 - 11
12 - 15
16 - 19
20 - 23
24 - 27
28 - 31
Description
USART0 Asynchro-
nous Receive.
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
16: PD9
17: PD10 21: PD14 25: PF2
20: PD13 24: PF1
28: PF5
29: PF6
30: PF7
31: PA0
5: PB11
6: PB12
7: PB13
USART0 Synchro-
nous mode Master
Input / Slave Out-
put (MISO).
US0_RX
14: PC10 18: PD11 22: PD15 26: PF3
15: PC11 19: PD12 23: PF0 27: PF4
USART0 Asynchro-
nous Transmit. Al-
so used as receive
input in half duplex
communication.
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15 14: PC9
12: PC7
13: PC8
16: PC11 20: PD12 24: PF0
17: PD9 21: PD13 25: PF1
18: PD10 22: PD14 26: PF2
15: PC10 19: PD11 23: PD15 27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
US0_TX
USART0 Synchro-
nous mode Master
Output / Slave In-
put (MOSI).
11: PC6
0: PA2
1: PA3
2: PA4
3: PA5
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PC6
10: PC7
11: PC8
12: PC9
16: PD10 20: PD14 24: PF2
28: PF6
29: PF7
30: PA0
31: PA1
13: PC10 17: PD11 21: PD15 25: PF3
14: PC11 18: PD12 22: PF0
15: PD9 19: PD13 23: PF1
USART1 clock in-
put / output.
US1_CLK
US1_CS
26: PF4
27: PF5
0: PA3
1: PA4
2: PA5
3: PB11
4: PB12
5: PB13
6: PB14
7: PB15
8: PC6
9: PC7
10: PC8
11: PC9
12: PC10 16: PD11 20: PD15 24: PF3
13: PC11 17: PD12 21: PF0
14: PD9 18: PD13 22: PF1
28: PF7
29: PA0
30: PA1
31: PA2
25: PF4
26: PF5
27: PF6
USART1 chip se-
lect input / output.
15: PD10 19: PD14 23: PF2
0: PA4
1: PA5
2: PB11
3: PB12
4: PB13
5: PB14
6: PB15
7: PC6
8: PC7
9: PC8
10: PC9
12: PC11 16: PD12 20: PF0
24: PF4
25: PF5
26: PF6
27: PF7
28: PA0
29: PA1
30: PA2
31: PA3
USART1 Clear To
Send hardware
flow control input.
13: PD9
17: PD13 21: PF1
US1_CTS
US1_RTS
14: PD10 18: PD14 22: PF2
11: PC10 15: PD11 19: PD15 23: PF3
0: PA5
4: PB14
5: PB15
6: PC6
7: PC7
8: PC8
9: PC9
12: PD9
16: PD13 20: PF1
24: PF5
25: PF6
26: PF7
27: PA0
28: PA1
29: PA2
30: PA3
31: PA4
USART1 Request
To Send hardware
flow control output.
1: PB11
2: PB12
3: PB13
13: PD10 17: PD14 21: PF2
10: PC10 14: PD11 18: PD15 22: PF3
11: PC11 15: PD12 19: PF0 23: PF4
USART1 Asynchro-
nous Receive.
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
16: PD9
17: PD10 21: PD14 25: PF2
20: PD13 24: PF1
28: PF5
29: PF6
30: PF7
31: PA0
5: PB11
6: PB12
7: PB13
USART1 Synchro-
nous mode Master
Input / Slave Out-
put (MISO).
US1_RX
14: PC10 18: PD11 22: PD15 26: PF3
15: PC11 19: PD12 23: PF0 27: PF4
USART1 Asynchro-
nous Transmit. Al-
so used as receive
input in half duplex
communication.
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15 14: PC9
11: PC6
12: PC7
13: PC8
16: PC11 20: PD12 24: PF0
17: PD9 21: PD13 25: PF1
18: PD10 22: PD14 26: PF2
15: PC10 19: PD11 23: PD15 27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
US1_TX
USART1 Synchro-
nous mode Master
Output / Slave In-
put (MOSI).
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Preliminary Rev. 0.31 | 69
EFM32JG1 Data Sheet
Pin Definitions
6.5 Analog Port (APORT)
The Analog Port (APORT) is an infrastructure used to connect chip pins with on-chip analog clients such as analog comparators, ADCs,
and DACs. The APORT consists of wires, switches, and control needed to configurably implement the routes. Please see the device
Reference Manual for a complete description.
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Preliminary Rev. 0.31 | 70
EFM32JG1 Data Sheet
Pin Definitions
PC6
PC8
PC10
PF0
PF2
PF4
PF6
BUSAX
BUSBY
PC7
PC9
PC11
PF1
PF3
PF5
PF7
BUSAY
BUSBX
PD10
PD12
PD14
PA0
BUSCX
PA2
PA4
PB12
PB14
BUSDY
PD9
PD11
PD13
PD15
PA1
BUSCY
PA3
PA5
PB11
PB13
PB15
BUSDX
1X1Y2X2Y3X3Y4X4Y
ACMP0
1X1Y2X2Y3X3Y4X4Y
ACMP1
1X1Y2X2Y3X3Y4X4Y
ADC0
1X1Y
IDAC0
Figure 6.4. EFM32JG1 APORT
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Preliminary Rev. 0.31 | 71
EFM32JG1 Data Sheet
Pin Definitions
Table 6.8. APORT Client Map
Analog Module
Analog Module Channel
Shared Bus
Pin
ACMP0
ACMP0
ACMP0
ACMP0
APORT1XCH6
APORT1XCH8
APORT1XCH10
APORT1XCH16
APORT1XCH18
APORT1XCH20
APORT1XCH22
APORT1YCH7
APORT1YCH9
APORT1YCH11
APORT1YCH17
APORT1YCH19
APORT1YCH21
APORT1YCH23
APORT2XCH7
APORT2XCH9
APORT2XCH11
APORT2XCH17
APORT2XCH19
APORT2XCH21
APORT2XCH23
APORT2YCH6
APORT2YCH8
APORT2YCH10
APORT2YCH16
APORT2YCH18
APORT2YCH20
APORT2YCH22
BUSAX
BUSAY
BUSBX
BUSBY
PC6
PC8
PC10
PF0
PF2
PF4
PF6
PC7
PC9
PC11
PF1
PF3
PF5
PF7
PC7
PC9
PC11
PF1
PF3
PF5
PF7
PC6
PC8
PC10
PF0
PF2
PF4
PF6
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EFM32JG1 Data Sheet
Pin Definitions
Analog Module
Analog Module Channel
APORT3XCH2
APORT3XCH4
APORT3XCH6
APORT3XCH8
APORT3XCH10
APORT3XCH12
APORT3XCH28
APORT3XCH30
APORT3YCH1
APORT3YCH3
APORT3YCH5
APORT3YCH7
APORT3YCH9
APORT3YCH11
APORT3YCH13
APORT3YCH27
APORT3YCH29
APORT3YCH31
APORT4XCH1
APORT4XCH3
APORT4XCH5
APORT4XCH7
APORT4XCH9
APORT4XCH11
APORT4XCH13
APORT4XCH27
APORT4XCH29
APORT4XCH31
APORT4YCH2
APORT4YCH4
APORT4YCH6
APORT4YCH8
APORT4YCH10
APORT4YCH12
APORT4YCH28
APORT4YCH30
Shared Bus
Pin
ACMP0
BUSCX
PD10
PD12
PD14
PA0
PA2
PA4
PB12
PB14
PD9
ACMP0
BUSCY
PD11
PD13
PD15
PA1
PA3
PA5
PB11
PB13
PB15
PD9
ACMP0
BUSDX
PD11
PD13
PD15
PA1
PA3
PA5
PB11
PB13
PB15
PD10
PD12
PD14
PA0
ACMP0
BUSDY
PA2
PA4
PB12
PB14
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Preliminary Rev. 0.31 | 73
EFM32JG1 Data Sheet
Pin Definitions
Analog Module
Analog Module Channel
APORT1XCH6
APORT1XCH8
APORT1XCH10
APORT1XCH16
APORT1XCH18
APORT1XCH20
APORT1XCH22
APORT1YCH7
APORT1YCH9
APORT1YCH11
APORT1YCH17
APORT1YCH19
APORT1YCH21
APORT1YCH23
APORT2XCH7
APORT2XCH9
APORT2XCH11
APORT2XCH17
APORT2XCH19
APORT2XCH21
APORT2XCH23
APORT2YCH6
APORT2YCH8
APORT2YCH10
APORT2YCH16
APORT2YCH18
APORT2YCH20
APORT2YCH22
APORT3XCH2
APORT3XCH4
APORT3XCH6
APORT3XCH8
APORT3XCH10
APORT3XCH12
APORT3XCH28
APORT3XCH30
Shared Bus
Pin
ACMP1
ACMP1
ACMP1
ACMP1
ACMP1
BUSAX
BUSAY
BUSBX
BUSBY
BUSCX
PC6
PC8
PC10
PF0
PF2
PF4
PF6
PC7
PC9
PC11
PF1
PF3
PF5
PF7
PC7
PC9
PC11
PF1
PF3
PF5
PF7
PC6
PC8
PC10
PF0
PF2
PF4
PF6
PD10
PD12
PD14
PA0
PA2
PA4
PB12
PB14
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Preliminary Rev. 0.31 | 74
EFM32JG1 Data Sheet
Pin Definitions
Analog Module
Analog Module Channel
APORT3YCH1
APORT3YCH3
APORT3YCH5
APORT3YCH7
APORT3YCH9
APORT3YCH11
APORT3YCH13
APORT3YCH27
APORT3YCH29
APORT3YCH31
APORT4XCH1
APORT4XCH3
APORT4XCH5
APORT4XCH7
APORT4XCH9
APORT4XCH11
APORT4XCH13
APORT4XCH27
APORT4XCH29
APORT4XCH31
APORT4YCH2
APORT4YCH4
APORT4YCH6
APORT4YCH8
APORT4YCH10
APORT4YCH12
APORT4YCH28
APORT4YCH30
APORT1XCH6
APORT1XCH8
APORT1XCH10
APORT1XCH16
APORT1XCH18
APORT1XCH20
APORT1XCH22
Shared Bus
Pin
ACMP1
BUSCY
PD9
PD11
PD13
PD15
PA1
PA3
PA5
PB11
PB13
PB15
PD9
ACMP1
BUSDX
PD11
PD13
PD15
PA1
PA3
PA5
PB11
PB13
PB15
PD10
PD12
PD14
PA0
ACMP1
BUSDY
PA2
PA4
PB12
PB14
PC6
ADC0
BUSAX
PC8
PC10
PF0
PF2
PF4
PF6
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Preliminary Rev. 0.31 | 75
EFM32JG1 Data Sheet
Pin Definitions
Analog Module
Analog Module Channel
APORT1YCH7
APORT1YCH9
APORT1YCH11
APORT1YCH17
APORT1YCH19
APORT1YCH21
APORT1YCH23
APORT2XCH7
APORT2XCH9
APORT2XCH11
APORT2XCH17
APORT2XCH19
APORT2XCH21
APORT2XCH23
APORT2YCH6
APORT2YCH8
APORT2YCH10
APORT2YCH16
APORT2YCH18
APORT2YCH20
APORT2YCH22
APORT3XCH2
APORT3XCH4
APORT3XCH6
APORT3XCH8
APORT3XCH10
APORT3XCH12
APORT3XCH28
APORT3XCH30
Shared Bus
Pin
ADC0
ADC0
ADC0
ADC0
BUSAY
BUSBX
BUSBY
BUSCX
PC7
PC9
PC11
PF1
PF3
PF5
PF7
PC7
PC9
PC11
PF1
PF3
PF5
PF7
PC6
PC8
PC10
PF0
PF2
PF4
PF6
PD10
PD12
PD14
PA0
PA2
PA4
PB12
PB14
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Preliminary Rev. 0.31 | 76
EFM32JG1 Data Sheet
Pin Definitions
Analog Module
Analog Module Channel
APORT3YCH1
APORT3YCH3
APORT3YCH5
APORT3YCH7
APORT3YCH9
APORT3YCH11
APORT3YCH13
APORT3YCH27
APORT3YCH29
APORT3YCH31
APORT4XCH1
APORT4XCH3
APORT4XCH5
APORT4XCH7
APORT4XCH9
APORT4XCH11
APORT4XCH13
APORT4XCH27
APORT4XCH29
APORT4XCH31
APORT4YCH2
APORT4YCH4
APORT4YCH6
APORT4YCH8
APORT4YCH10
APORT4YCH12
APORT4YCH28
APORT4YCH30
APORT1XCH2
APORT1XCH4
APORT1XCH6
APORT1XCH8
APORT1XCH10
APORT1XCH12
APORT1XCH28
APORT1XCH30
Shared Bus
Pin
ADC0
BUSCY
PD9
PD11
PD13
PD15
PA1
PA3
PA5
PB11
PB13
PB15
PD9
ADC0
BUSDX
PD11
PD13
PD15
PA1
PA3
PA5
PB11
PB13
PB15
PD10
PD12
PD14
PA0
ADC0
BUSDY
PA2
PA4
PB12
PB14
PD10
PD12
PD14
PA0
IDAC0
BUSCX
PA2
PA4
PB12
PB14
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Preliminary Rev. 0.31 | 77
EFM32JG1 Data Sheet
Pin Definitions
Analog Module
Analog Module Channel
APORT1YCH1
Shared Bus
Pin
IDAC0
BUSCY
PD9
APORT1YCH3
PD11
PD13
PD15
PA1
APORT1YCH5
APORT1YCH7
APORT1YCH9
APORT1YCH11
APORT1YCH13
APORT1YCH27
APORT1YCH29
APORT1YCH31
PA3
PA5
PB11
PB13
PB15
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Preliminary Rev. 0.31 | 78
EFM32JG1 Data Sheet
QFN48 Package Specifications
7. QFN48 Package Specifications
7.1 QFN48 Package Dimensions
Figure 7.1. QFN48 Package Drawing
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Preliminary Rev. 0.31 | 79
EFM32JG1 Data Sheet
QFN48 Package Specifications
Table 7.1. QFN48 Package Dimensions
Dimension
Min
0.80
0.00
Typ
0.85
Max
0.90
0.05
A
A1
A3
b
0.02
0.20 REF
0.25
0.18
6.90
6.90
4.60
4.60
0.30
7.10
7.10
4.80
4.80
D
7.00
E
7.00
D2
E2
e
4.70
4.70
0.50 BSC
0.40
L
0.30
0.20
0.09
0.50
—
K
—
R
—
0.14
aaa
bbb
ccc
ddd
eee
fff
0.15
0.10
0.10
0.05
0.08
0.10
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, Variation VKKD-4.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Preliminary Rev. 0.31 | 80
EFM32JG1 Data Sheet
QFN48 Package Specifications
7.2 QFN48 PCB Land Pattern
Figure 7.2. QFN48 PCB Land Pattern Drawing
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Preliminary Rev. 0.31 | 81
EFM32JG1 Data Sheet
QFN48 Package Specifications
Table 7.2. QFN48 PCB Land Pattern Dimensions
Dimension
Typ
S1
S
6.01
6.01
4.70
4.70
0.50
0.26
0.86
L1
W1
e
W
L
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size can be 1:1 for all perimeter pads.
7. A 4x4 array of 0.75 mm square openings on a 1.00 mm pitch can be used for the center ground pad.
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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EFM32JG1 Data Sheet
QFN48 Package Specifications
7.3 QFN48 Package Marking
EFM32
PPPPPPPPPP
TTTTTT
YYWW #
Figure 7.3. QFN48 Package Marking
The package marking consists of:
• PPPPPPPPPP – The part number designation.
• TTTTTT – A trace or manufacturing code. The first letter is the device revision.
• YY – The last 2 digits of the assembly year.
• WW – The 2-digit workweek when the device was assembled.
• # – Reserved for future use. Current value is 0.
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EFM32JG1 Data Sheet
QFN32 Package Specifications
8. QFN32 Package Specifications
8.1 QFN32 Package Dimensions
Figure 8.1. QFN32 Package Drawing
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EFM32JG1 Data Sheet
QFN32 Package Specifications
Table 8.1. QFN32 Package Dimensions
Dimension
Min
0.80
0.00
Typ
0.85
Max
0.90
0.05
A
A1
A3
b
0.02
0.20 REF
0.25
0.18
4.90
3.40
0.30
5.10
3.60
D/E
D2/E2
E
5.00
3.50
0.50 BSC
0.40
L
0.30
0.20
0.09
0.50
—
K
—
R
—
0.14
aaa
bbb
ccc
ddd
eee
fff
0.15
0.10
0.10
0.05
0.08
0.10
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, Variation VKKD-4.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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EFM32JG1 Data Sheet
QFN32 Package Specifications
8.2 QFN32 PCB Land Pattern
Figure 8.2. QFN32 PCB Land Pattern Drawing
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EFM32JG1 Data Sheet
QFN32 Package Specifications
Table 8.2. QFN32 PCB Land Pattern Dimensions
Dimension
Typ
S1
S
4.01
4.01
3.50
3.50
0.50
0.26
0.86
L1
W1
e
W
L
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size can be 1:1 for all perimeter pads.
7. A 3x3 array of 0.85 mm square openings on a 1.00 mm pitch can be used for the center ground pad.
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Preliminary Rev. 0.31 | 87
EFM32JG1 Data Sheet
QFN32 Package Specifications
8.3 QFN32 Package Marking
EFM32
PPPPPPPPPP
TTTTTT
YYWW #
Figure 8.3. QFN32 Package Marking
The package marking consists of:
• PPPPPPPPPP – The part number designation.
• TTTTTT – A trace or manufacturing code. The first letter is the device revision.
• YY – The last 2 digits of the assembly year.
• WW – The 2-digit workweek when the device was assembled.
• # – Reserved for future use. Current value is 0.
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Preliminary Rev. 0.31 | 88
EFM32JG1 Data Sheet
Revision History
9. Revision History
9.1 Revision 0.31
• Engineering samples note added to ordering information table.
9.2 Revision 0.3
• Re-formatted ordering information table and OPN decoder.
• Removed extraneous sections from dc-dc from system overview.
• Updated table formatting for electrical specifications.
• Updated electrical specifications with latest available data.
• Added I2C and USART SPI timing tables.
• Moved dc-dc graph to typical performance curves.
• Updated APORT tables and APORT references to correct nomenclature.
• Updated top marking description.
9.3 Revision 0.2
Updated ordering table.
Changed "1.62 V to 3.8 V Single Power Supply" to "1.62 V to 3.8 V Power Supply" in the Feature List.
9.4 Revision 0.1
Initial release.
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Preliminary Rev. 0.31 | 89
Table of Contents
1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.2 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2.1 Energy Management Unit (EMU) . . . . . . . . . . . . . . . . . . . . . . . 4
3.2.2 DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.3 General Purpose Input/Output (GPIO). . . . . . . . . . . . . . . . . . . . . . 4
3.4 Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.4.1 Clock Management Unit (CMU) . . . . . . . . . . . . . . . . . . . . . . . 4
3.4.2 Internal and External Oscillators . . . . . . . . . . . . . . . . . . . . . . . 4
3.5 Counters/Timers and PWM . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.5.1 Timer/Counter (TIMER) . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.5.2 Real Time Counter and Calendar (RTCC) . . . . . . . . . . . . . . . . . . . . 5
3.5.3 Low Energy Timer (LETIMER). . . . . . . . . . . . . . . . . . . . . . . . 5
3.5.4 Ultra Low Power Wake-up Timer (CRYOTIMER) . . . . . . . . . . . . . . . . . 5
3.5.5 Pulse Counter (PCNT) . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.5.6 Watchdog Timer (WDOG) . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.6 Communications and Other Digital Peripherals . . . . . . . . . . . . . . . . . . . 5
3.6.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) . . . . . . . . . . 5
3.6.2 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) . . . . . . . . . . 6
2
3.6.3 Inter-Integrated Circuit Interface (I C) . . . . . . . . . . . . . . . . . . . . . 6
3.6.4 Peripheral Reflex System (PRS) . . . . . . . . . . . . . . . . . . . . . . . 6
3.7 Security Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.7.1 GPCRC (General Purpose Cyclic Redundancy Check) . . . . . . . . . . . . . . . 6
3.7.2 Crypto Accelerator (CRYPTO). . . . . . . . . . . . . . . . . . . . . . . . 6
3.8 Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.8.1 Analog Port (APORT) . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.8.2 Analog Comparator (ACMP) . . . . . . . . . . . . . . . . . . . . . . . . 6
3.8.3 Analog to Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . 7
3.8.4 Digital to Analog Current Converter (IDAC) . . . . . . . . . . . . . . . . . . . 7
3.9 Reset Management Unit (RMU) . . . . . . . . . . . . . . . . . . . . . . . . 7
3.10 Core and Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.10.1 Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.10.2 Memory System Controller (MSC) . . . . . . . . . . . . . . . . . . . . . . 7
3.10.3 Linked Direct Memory Access Controller (LDMA) . . . . . . . . . . . . . . . . . 7
3.11 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.12 Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .10
4.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . .10
4.1.2 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Table of Contents 90
4.1.2.1 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . .11
4.1.3 DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
4.1.4 Current Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . .14
4.1.4.1 Current Consumption 1.85V without DC/DC . . . . . . . . . . . . . . . . . .14
4.1.4.2 Current Consumption 3.3V without DC/DC . . . . . . . . . . . . . . . . . . .15
4.1.4.3 Current Consumption 3.3V with DC/DC . . . . . . . . . . . . . . . . . . . .16
4.1.5 Wake up times . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.1.6 Brown Out Detector . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.1.7 Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.1.7.1 LFXO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.1.7.2 HFXO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.1.7.3 LFRCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.1.7.4 HFRCO and AUXHFRCO . . . . . . . . . . . . . . . . . . . . . . . .20
4.1.7.5 ULFRCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.1.8 Flash Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . .21
4.1.9 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.1.10 VMON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.1.11 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.1.12 IDAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.1.13 Analog Comparator (ACMP) . . . . . . . . . . . . . . . . . . . . . . . .28
4.1.14 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
4.1.15 USART SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
4.2 Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . .34
5. Typical Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
5.2 Other Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
6. Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.1 EFM32JG1 QFN48 Definition . . . . . . . . . . . . . . . . . . . . . . . .37
6.1.1 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . .46
6.2 EFM32JG1 QFN32 with DC-DC Definition . . . . . . . . . . . . . . . . . . . .47
6.2.1 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . .54
6.3 EFM32JG1 QFN32 without DC-DC Definition . . . . . . . . . . . . . . . . . . .55
6.3.1 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . .63
6.4 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . . . .64
6.5 Analog Port (APORT) . . . . . . . . . . . . . . . . . . . . . . . . . . .70
7. QFN48 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . . 79
7.1 QFN48 Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . . .79
7.2 QFN48 PCB Land Pattern. . . . . . . . . . . . . . . . . . . . . . . . . .81
7.3 QFN48 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . .83
8. QFN32 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . . 84
8.1 QFN32 Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . . .84
8.2 QFN32 PCB Land Pattern. . . . . . . . . . . . . . . . . . . . . . . . . .86
8.3 QFN32 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . .88
Table of Contents 91
9. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
9.1 Revision 0.31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
9.2 Revision 0.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
9.3 Revision 0.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
9.4 Revision 0.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table of Contents 92
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Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers
using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific
device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories
reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy
or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply
or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products must not be used within any Life Support System without the specific
written consent of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected
to result in significant personal injury or death. Silicon Laboratories products are generally not intended for military applications. Silicon Laboratories products shall under no
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