EFM32LG330F64-QFN64 [SILICON]
High Performance 32-bit processor up to 48 MHz memory Protection Unit; 高性能32位处理器高达48 MHz的内存保护单元
| 型号： | EFM32LG330F64-QFN64 |
| 厂家： | 
SILICON |
| 描述： | High Performance 32-bit processor up to 48 MHz memory Protection Unit |
| 文件： | 总66页 (文件大小：1713K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EFM32LG330 DATASHEET
F256/F128/F64
Preliminary
• ARM Cortex-M3 CPU platform
• Communication interfaces
• High Performance 32-bit processor @ up to 48 MHz
• Memory Protection Unit
• 3× Universal Synchronous/Asynchronous Receiv-
er/Transmitter
• UART/SPI/SmartCard (ISO 7816)/IrDA/I2S
• 2× Low Energy UART
• Flexible Energy Management System
• 20 nA @ 3 V Shutoff Mode
• Autonomous operation with DMA in Deep Sleep
Mode
• 0.4µA @ 3 V Shutoff Mode with RTC
• 0.9 µA @ 3 V Stop Mode, including Power-on Reset, Brown-out
Detector, RAM and CPU retention
• 1.1 µA @ 3 V Deep Sleep Mode, including RTC with 32.768 kHz
oscillator, Power-on Reset, Brown-out Detector, RAM and CPU
retention
• 2× I2C Interface with SMBus support
• Address recognition in Stop Mode
• Universal Serial Bus (USB) with Host & OTG support
• Fully USB 2.0 compliant
• 50 µA/MHz @ 3 V Sleep Mode
• 200 µA/MHz @ 3 V Run Mode, with code executed from flash
• 256/128/64 KB Flash
• 32/32/32 KB RAM
• 52 General Purpose I/O pins
• On-chip PHY and embedded 5V to 3.3V regulator
• Ultra low power precision analog peripherals
• 12-bit 1 Msamples/s Analog to Digital Converter
• 8 single ended channels/4 differential channels
• On-chip temperature sensor
• Configurable push-pull, open-drain, pull-up/down, input filter, drive
strength
• 12-bit 500 ksamples/s Digital to Analog Converter
• 2× Analog Comparator
• Configurable peripheral I/O locations
• 16 asynchronous external interrupts
• Output state retention and wake-up from Shutoff Mode
• 12 Channel DMA Controller
• Capacitive sensing with up to 16 inputs
• 3× Operational Amplifier
• 6.1 MHz GBW, Rail-to-rail, Programmable Gain
• Supply Voltage Comparator
• 12 Channel Peripheral Reflex System (PRS) for autonomous in-
ter-peripheral signaling
• Hardware AES with 128/256-bit keys in 54/75 cycles
• Timers/Counters
• Low Energy Sensor Interface (LESENSE)
• Autonomous sensor monitoring in Deep Sleep Mode
• Wide range of sensors supported, including LC sen-
sors and capacitive buttons
• 4× 16-bit Timer/Counter
• 4×3 Compare/Capture/PWM channels
• Dead-Time Insertion on TIMER0
• Ultra efficient Power-on Reset and Brown-Out Detec-
tor
• Debug Interface
• 16-bit Low Energy Timer
• 1× 24-bit Real-Time Counter and 1× 32-bit Real-Time Counter
• 3× 16/8-bit Pulse Counter
• Watchdog Timer with dedicated RC oscillator @ 50 nA
• Backup Power Domain
• RTC and retention registers in a separate power domain, avail-
able in all energy modes
• 2-pin Serial Wire Debug interface
• 1-pin Serial Wire Viewer
• Embedded Trace Module v3.5 (ETM)
• Pre-Programmed Serial Bootloader
• Temperature range -40 to 85 ºC
• Single power supply 1.85 to 3.8 V
• QFN64 package
• Operation from backup battery when main power drains out
32-bit ARM Cortex-M0+, Cortex-M3 and Cortex-M4 microcontrollers for:
• Energy, gas, water and smart metering
• Health and fitness applications
• Smart accessories
• Alarm and security systems
• Industrial and home automation
• www.energymicro.com/gecko
Preliminary
...the world's most energy friendly microcontrollers
1 Ordering Information
Table 1.1 (p. 2) shows the available EFM32LG330 devices.
Table 1.1. Ordering Information
Ordering Code
Flash (kB) RAM (kB) Max
Speed
Supply
Voltage
(V)
Temperature
(ºC)
Package
(MHz)
EFM32LG330F64-QFN64
EFM32LG330F128-QFN64
EFM32LG330F256-QFN64
64
32
32
32
48
1.85 - 3.8 -40 - 85
1.85 - 3.8 -40 - 85
1.85 - 3.8 -40 - 85
QFN64
QFN64
QFN64
128
256
48
48
Visit www.energymicro.com for information on global distributors and representatives or contact
sales@energymicro.com for additional information.
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2 System Summary
2.1 System Introduction
The EFM32 MCUs are the world’s most energy friendly microcontrollers. With a unique combination of
the powerful 32-bit ARM Cortex-M3, innovative low energy techniques, short wake-up time from ener-
gy saving modes, and a wide selection of peripherals, the EFM32LG microcontroller is well suited for
any battery operated application as well as other systems requiring high performance and low-energy
consumption. This section gives a short introduction to each of the modules in general terms and also
shows a summary of the configuration for the EFM32LG330 devices. For a complete feature set and in-
depth information on the modules, the reader is referred to the EFM32LG Reference Manual.
A block diagram of the EFM32LG330 is shown in Figure 2.1 (p. 3) .
Figure 2.1. Block Diagram
LG330F64/128/256
Core and Memory
Clock Management
Energy Management
High Freq.
Crystal
Oscillator
High Freq
RC
Oscillator
Voltage
Regulator
Voltage
Comparator
Memory
Protection
Unit
ARM Cortex™-M3 processor
Low Freq.
Crystal
Oscillator
Low Freq.
RC
Oscillator
Brown-out
Detector
Power-on
Reset
Flash
Program
Memory
Debug
Interface
w/ ETM
DMA
Controller
RAM
Memory
Ultra Low Freq.
RC
Oscillator
Back-up
Power
Domain
32-bit bus
Peripheral Reflex System
Serial Interfaces
I/O Ports
Analog Interfaces
Security
Timers and Triggers
Timer/
Counter
LESENSE
ADC
USART
UART
Hardware
AES
Low Energy Real Time
General
Purpose
I/O
Low
Energy
UART
Timer
Counter
Operational
Amplifier
External
Interrupts
I 2C
DAC
Watchdog
Timer
Pulse
Counter
Pin
Reset
Pin
Wakeup
Pulse
Counter
USB
Back-up
RTC
2.1.1 ARM Cortex-M3 Core
The ARM Cortex-M3 includes a 32-bit RISC processor which can achieve as much as 1.25 Dhrystone
MIPS/MHz. A Memory Protection Unit with support for up to 8 memory segments is included, as well
as a Wake-up Interrupt Controller handling interrupts triggered while the CPU is asleep. The EFM32
implementation of the Cortex-M3 is described in detail in EFM32 Cortex-M3 Reference Manual.
2.1.2 Debug Interface (DBG)
This device includes hardware debug support through a 2-pin serial-wire debug interface and an Embed-
ded Trace Module (ETM) for data/instruction tracing. In addition there is also a 1-wire Serial Wire Viewer
pin which can be used to output profiling information, data trace and software-generated messages.
2.1.3 Memory System Controller (MSC)
The Memory System Controller (MSC) is the program memory unit of the EFM32LG microcontroller. The
flash memory is readable and writable from both the Cortex-M3 and DMA. The flash memory is divided
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into two blocks; the main block and the information block. Program code is normally written to the main
block. Additionally, the information block is available for special user data and flash lock bits. There is
also a read-only page in the information block containing system and device calibration data. Read and
write operations are supported in the energy modes EM0 and EM1.
2.1.4 Direct Memory Access Controller (DMA)
The Direct Memory Access (DMA) controller performs memory operations independently of the CPU.
This has the benefit of reducing the energy consumption and the workload of the CPU, and enables
the system to stay in low energy modes when moving for instance data from the USART to RAM or
from the External Bus Interface to a PWM-generating timer. The DMA controller uses the PL230 µDMA
controller licensed from ARM.
2.1.5 Reset Management Unit (RMU)
The RMU is responsible for handling the reset functionality of the EFM32LG.
2.1.6 Energy Management Unit (EMU)
The Energy Management Unit (EMU) manage all the low energy modes (EM) in EFM32LG microcon-
trollers. Each energy mode manages if the CPU and the various peripherals are available. The EMU
can also be used to turn off the power to unused SRAM blocks.
2.1.7 Clock Management Unit (CMU)
The Clock Management Unit (CMU) is responsible for controlling the oscillators and clocks on-board
the EFM32LG. The CMU provides the capability to turn on and off the clock on an individual basis to all
peripheral modules in addition to enable/disable and configure the available oscillators. The high degree
of flexibility enables software to minimize energy consumption in any specific application by not wasting
power on peripherals and oscillators that are inactive.
2.1.8 Watchdog (WDOG)
The purpose of the watchdog timer is to generate a reset in case of a system failure, to increase appli-
cation reliability. The failure may e.g. be caused by an external event, such as an ESD pulse, or by a
software failure.
2.1.9 Peripheral Reflex System (PRS)
The Peripheral Reflex System (PRS) system is a network which lets the different peripheral module
communicate directly with each other without involving the CPU. Peripheral modules which send out
Reflex signals are called producers. The PRS routes these reflex signals to consumer peripherals which
apply actions depending on the data received. The format for the Reflex signals is not given, but edge
triggers and other functionality can be applied by the PRS.
2.1.10 Universal Serial Bus Controller (USB)
The USB is a full-speed USB 2.0 compliant OTG host/device controller. The USB can be used in Device,
On-the-go (OTG) Dual Role Device or Host-only configuration. In OTG mode the USB supports both
Host Negotiation Protocol (HNP) and Session Request Protocol (SRP). The device supports both full-
speed (12MBit/s) and low speed (1.5MBit/s) operation. The USB device includes an internal dedicated
Descriptor-Based Scatter/Garther DMA and supports up to 6 OUT endpoints and 6 IN endpoints, in
addition to endpoint 0. The on-chip PHY includes all OTG features, except for the voltage booster for
supplying 5V to VBUS when operating as host.
2.1.11 Inter-Integrated Circuit Interface (I2C)
The I2C module provides an interface between the MCU and a serial I2C-bus. It is capable of acting as
both a master and a slave, and supports multi-master buses. Both standard-mode, fast-mode and fast-
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mode plus speeds are supported, allowing transmission rates all the way from 10 kbit/s up to 1 Mbit/s.
Slave arbitration and timeouts are also provided to allow implementation of an SMBus compliant system.
The interface provided to software by the I2C module, allows both fine-grained control of the transmission
process and close to automatic transfers. Automatic recognition of slave addresses is provided in all
energy modes.
2.1.12 Universal Synchronous/Asynchronous Receiver/Transmitter (US-
ART)
The Universal Synchronous Asynchronous serial Receiver and Transmitter (USART) is a very flexible
serial I/O module. It supports full duplex asynchronous UART communication as well as RS-485, SPI,
MicroWire and 3-wire. It can also interface with ISO7816 SmartCards, IrDA and I2S devices.
2.1.13 Pre-Programmed Serial Bootloader
The bootloader presented in application note AN0003 is pre-programmed in the device at factory. Auto-
baud and destructive write are supported. The autobaud feature, interface and commands are described
further in the application note.
2.1.14 Low Energy Universal Asynchronous Receiver/Transmitter
(LEUART)
The unique LEUARTTM, the Low Energy UART, is a UART that allows two-way UART communication on
a strict power budget. Only a 32.768 kHz clock is needed to allow UART communication up to 9600 baud/
s. The LEUART includes all necessary hardware support to make asynchronous serial communication
possible with minimum of software intervention and energy consumption.
2.1.15 Timer/Counter (TIMER)
The 16-bit general purpose Timer has 3 compare/capture channels for input capture and compare/Pulse-
Width Modulation (PWM) output. TIMER0 also includes a Dead-Time Insertion module suitable for motor
control applications.
2.1.16 Real Time Counter (RTC)
The Real Time Counter (RTC) contains a 24-bit counter and is clocked either by a 32.768 kHz crystal
oscillator, or a 32.768 kHz RC oscillator. In addition to energy modes EM0 and EM1, the RTC is also
available in EM2. This makes it ideal for keeping track of time since the RTC is enabled in EM2 where
most of the device is powered down.
2.1.17 Backup Real Time Counter (BURTC)
The Backup Real Time Counter (BURTC) contains a 32-bit counter and is clocked either by a 32.768 kHz
crystal oscillator, a 32.768 kHz RC oscillator or a 1 kHz ULFRCO. The BURTC is available in all Energy
Modes and it can also run in backup mode, making it operational even if the main power should drain out.
2.1.18 Low Energy Timer (LETIMER)
The unique LETIMERTM, the Low Energy Timer, is a 16-bit timer that is available in energy mode EM2
in addition to EM1 and EM0. Because of this, it can be used for timing and output generation when most
of the device is powered down, allowing simple tasks to be performed while the power consumption of
the system is kept at an absolute minimum. The LETIMER can be used to output a variety of waveforms
with minimal software intervention. It is also connected to the Real Time Counter (RTC), and can be
configured to start counting on compare matches from the RTC.
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2.1.19 Pulse Counter (PCNT)
The Pulse Counter (PCNT) can be used for counting pulses on a single input or to decode quadrature
encoded inputs. It runs off either the internal LFACLK or the PCNTn_S0IN pin as external clock source.
The module may operate in energy mode EM0 – EM3.
2.1.20 Analog Comparator (ACMP)
The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indi-
cating which input voltage is higher. Inputs can either be one of the selectable internal references or from
external pins. Response time and thereby also the current consumption can be configured by altering
the current supply to the comparator.
2.1.21 Voltage Comparator (VCMP)
The Voltage Supply Comparator is used to monitor the supply voltage from software. An interrupt can
be generated when the supply falls below or rises above a programmable threshold. Response time and
thereby also the current consumption can be configured by altering the current supply to the comparator.
2.1.22 Analog to Digital Converter (ADC)
The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits
at up to one million samples per second. The integrated input mux can select inputs from 8 external
pins and 6 internal signals.
2.1.23 Digital to Analog Converter (DAC)
The Digital to Analog Converter (DAC) can convert a digital value to an analog output voltage. The DAC
is fully differential rail-to-rail, with 12-bit resolution. It has two single ended output buffers which can be
combined into one differential output. The DAC may be used for a number of different applications such
as sensor interfaces or sound output.
2.1.24 Operational Amplifier (OPAMP)
The EFM32LG330 features 3 Operational Amplifiers. The Operational Amplifier is a versatile general
purpose amplifier with rail-to-rail differential input and rail-to-rail single ended output. The input can be set
to pin, DAC or OPAMP, whereas the output can be pin, OPAMP or ADC. The current is programmable
and the OPAMP has various internal configurations such as unity gain, programmable gain using internal
resistors etc.
2.1.25 Low Energy Sensor Interface (LESENSE)
The Low Energy Sensor Interface (LESENSETM), is a highly configurable sensor interface with support
for up to 16 individually configurable sensors. By controlling the analog comparators and DAC, LESENSE
is capable of supporting a wide range of sensors and measurement schemes, and can for instance mea-
sure LC sensors, resistive sensors and capacitive sensors. LESENSE also includes a programmable
FSM which enables simple processing of measurement results without CPU intervention. LESENSE is
available in energy mode EM2, in addition to EM0 and EM1, making it ideal for sensor monitoring in
applications with a strict energy budget.
2.1.26 Backup Power Domain
The backup power domain is a separate power domain containing a Backup Real Time Counter, BURTC,
and a set of retention registers, available in all energy modes. This power domain can be configured to
automatically change power source to a backup battery when the main power drains out. The backup
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power domain enables the EFM32LG330 to keep track of time and retain data, even if the main power
source should drain out.
2.1.27 Advanced Encryption Standard Accelerator (AES)
The AES accelerator performs AES encryption and decryption with 128-bit or 256-bit keys. Encrypting or
decrypting one 128-bit data block takes 52 HFCORECLK cycles with 128-bit keys and 75 HFCORECLK
cycles with 256-bit keys. The AES module is an AHB slave which enables efficient access to the data
and key registers. All write accesses to the AES module must be 32-bit operations, i.e. 8- or 16-bit
operations are not supported.
2.1.28 General Purpose Input/Output (GPIO)
In the EFM32LG330, there are 52 General Purpose Input/Output (GPIO) pins, which are divided into
ports with up to 16 pins each. These pins can individually be configured as either an output or input. More
advanced configurations like open-drain, filtering and drive strength can also be configured individually
for the pins. The GPIO pins can also be overridden by peripheral pin connections, like Timer PWM
outputs or USART communication, which can be routed to several locations on the device. The GPIO
supports up to 16 asynchronous external pin interrupts, which enables interrupts from any pin on the
device. Also, the input value of a pin can be routed through the Peripheral Reflex System to other
peripherals.
2.2 Configuration Summary
The features of the EFM32LG330 is a subset of the feature set described in the EFM32LG Reference
Manual. Table 2.1 (p. 7) describes device specific implementation of the features.
Table 2.1. Configuration Summary
Module
Cortex-M3
DBG
Configuration
Pin Connections
Full configuration
Full configuration
NA
DBG_SWCLK, DBG_SWDIO,
DBG_SWO
MSC
DMA
RMU
EMU
CMU
WDOG
PRS
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
NA
NA
NA
NA
CMU_OUT0, CMU_OUT1
NA
NA
USB
USB_VBUS, USB_VBUSEN,
USB_VREGI, USB_VREGO, USB_DM,
USB_DMPU, USB_DP, USB_ID
I2C0
Full configuration
Full configuration
IrDA
I2C0_SDA, I2C0_SCL
I2C1
I2C1_SDA, I2C1_SCL
USART0
USART1
USART2
LEUART0
US0_TX, US0_RX. US0_CLK, US0_CS
US1_TX, US1_RX, US1_CLK, US1_CS
US2_TX, US2_RX, US2_CLK, US2_CS
LEU0_TX, LEU0_RX
I2S
I2S
Full configuration
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Module
LEUART1
TIMER0
TIMER1
TIMER2
TIMER3
RTC
Configuration
Pin Connections
Full configuration
Full configuration with DTI
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
LEU1_TX, LEU1_RX
TIM0_CC[2:0], TIM0_CDTI[2:0]
TIM1_CC[2:0]
TIM2_CC[2:0]
TIM3_CC[2:0]
NA
BURTC
LETIMER0
PCNT0
PCNT1
PCNT2
ACMP0
ACMP1
VCMP
NA
LET0_O[1:0]
PCNT0_S[1:0]
8-bit count register
8-bit count register
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
PCNT1_S[1:0]
PCNT2_S[1:0]
ACMP0_CH[7:0], ACMP0_O
ACMP1_CH[7:0], ACMP1_O
NA
ADC0
ADC0_CH[7:0]
DAC0
DAC0_OUT[1:0], DAC0_OUTxALT
OPAMP
Outputs: OPAMP_OUTx,
OPAMP_OUTxALT, Inputs:
OPAMP_Px, OPAMP_Nx
AES
Full configuration
52 pins
NA
GPIO
Available pins are shown in
Table 4.3 (p. 52)
2.3 Memory Map
The EFM32LG330 memory map is shown in Figure 2.2 (p. 9), with RAM and Flash sizes for the
largest memory configuration.
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Figure 2.2. EFM32LG330 Memory Map with largest RAM and Flash sizes
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3 Electrical Characteristics
3.1 Test Conditions
3.1.1 Typical Values
The typical data are based on TAMB=25°C and VDD=3.0 V, as defined in Table 3.2 (p. 10), by simu-
lation and/or technology characterisation unless otherwise specified.
3.1.2 Minimum and Maximum Values
The minimum and maximum values represent the worst conditions of ambient temperature, supply volt-
age and frequencies, as defined in Table 3.2 (p. 10), by simulation and/or technology characterisa-
tion unless otherwise specified.
3.2 Absolute Maximum Ratings
The absolute maximum ratings are stress ratings, and functional operation under such conditions are
not guaranteed. Stress beyond the limits specified in Table 3.1 (p. 10) may affect the device reliability
or cause permanent damage to the device. Functional operating conditions are given in Table 3.2 (p.
10) .
Table 3.1. Absolute Maximum Ratings
Symbol
TSTG
TS
Parameter
Condition
Min
Typ
Max
Unit
1501 °C
Storage temperature range
-40
Maximum soldering tem-
perature
Latest IPC/JEDEC J-STD-020
Standard
260 °C
VDDMAX
External main supply volt-
age
0
3.8
V
VIOPIN
Voltage on any I/O pin
-0.3
VDD+0.3
V
1Based on programmed devices tested for 10000 hours at 150ºC. Storage temperature affects retention of preprogrammed cal-
ibration values stored in flash. Please refer to the Flash section in the Electrical Characteristics for information on flash data re-
tention for different temperatures.
3.3 General Operating Conditions
3.3.1 General Operating Conditions
Table 3.2. General Operating Conditions
Symbol
TAMB
VDDOP
fAPB
Parameter
Min
Typ
Max
Unit
85 °C
3.8
Ambient temperature range
Operating supply voltage
Internal APB clock frequency
Internal AHB clock frequency
-40
1.85
V
48 MHz
48 MHz
fAHB
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3.3.2 Environmental
Table 3.3. Environmental
Symbol
Parameter
Condition
Min
Typ
Max
Unit
VESDHBM
ESD (Human Body Model
HBM)
TAMB=25°C
2
1
kV
VESDCDM
ESD (Charged Device
Model, CDM)
TAMB=25°C
kV
Latch-up sensitivity test passed level A according to JEDEC JESD 78B method Class II, 85°C.
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3.4 Current Consumption
Table 3.4. Current Consumption
Symbol
Parameter
Condition
Min
Typ
Max
Unit
32 MHz HFXO, all peripheral
clocks disabled, VDD= 3.0 V
200
201
203
204
207
212
244
50
µA/
MHz
28 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V
261 µA/
MHz
21 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V
263 µA/
MHz
EM0 current. No prescal-
ing. Running prime num-
ber calculation code from
Flash.
14 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V
270 µA/
MHz
IEM0
11 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V
273 µA/
MHz
6.6 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V
282 µA/
MHz
1.2 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V
µA/
MHz
32 MHz HFXO, all peripheral
clocks disabled, VDD= 3.0 V
µA/
MHz
28 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V
52
69 µA/
MHz
21 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V
53
71 µA/
MHz
14 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V
56
77 µA/
MHz
IEM1
EM1 current
11 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V
57
80 µA/
MHz
6.6 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V
62
92 µA/
MHz
1.2 MHz HFRCO. all peripher-
al clocks disabled, VDD= 3.0 V
114
1.1
µA/
MHz
EM2 current with RTC
prescaled to 1 Hz, 32.768
kHz LFRCO, VDD= 3.0 V,
TAMB=25°C
µA
IEM2
EM2 current
EM2 current with RTC
prescaled to 1 Hz, 32.768
kHz LFRCO, VDD= 3.0 V,
TAMB=85°C
4.0
8.0 µA
VDD= 3.0 V, TAMB=25°C
VDD= 3.0 V, TAMB=85°C
VDD= 3.0 V, TAMB=25°C
VDD= 3.0 V, TAMB=85°C
0.9
3.8
µA
7.8 µA
µA
IEM3
EM3 current
EM4 current
0.02
0.25
IEM4
0.7 µA
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3.5 Transition between Energy Modes
Table 3.5. Energy Modes Transitions
Symbol
Parameter
Min
Typ
Max
Unit
tEM10
Transition time from EM1 to EM0
01
HF
core
CLK
cycles
tEM20
tEM30
tEM40
Transition time from EM2 to EM0
Transition time from EM3 to EM0
Transition time from EM4 to EM0
2
2
µs
µs
µs
163
1Core wakeup time only.
3.6 Power Management
The EFM32LG requires the AVDD_x, VDD_DREG and IOVDD_x pins to be connected together at the
PCB level. For practical schematic recommendations, please see the application note, "AN0002 EFM32
Hardware Design Considerations".
Table 3.6. Power Management
Symbol
Parameter
Condition
Min
Typ
Max
Unit
VBODextthr-
BOD threshold on falling
external supply voltage
1.82
1.62
1.85
1.68
V
VBODintthr-
BOD threshold on falling
internally regulated supply
voltage
V
VBODextthr+
BOD threshold on rising ex-
ternal supply voltage
1.85
V
V
VPORthr+
Power-on Reset (POR)
threshold on rising external
supply voltage
1.98
tRESET
Delay from reset is re-
leased until program execu- Brown-out Reset and pin re-
tion starts
Applies to Power-on Reset,
163
1
µs
µF
µF
µF
set.
CDECOUPLE
CUSB_VREGO
CUSB_VREGI
Voltage regulator decou-
pling capacitor.
X5R capacitor recommended.
Apply between DECOUPLE
pin and GROUND
USB voltage regulator out
decoupling capacitor.
X5R capacitor recommended.
Apply between USB_VREGO
pin and GROUND
1
USB voltage regulator in
decoupling capacitor.
X5R capacitor recommended.
Apply between USB_VREGI
pin and GROUND
4.7
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2013-06-28 - EFM32LG330FXX - d0110_Rev1.10
13
Preliminary
...the world's most energy friendly microcontrollers
3.7 Flash
Table 3.7. Flash
Symbol
Parameter
Flash erase cycles before
Condition
Min
Typ
Max
Unit
ECFLASH
20000
cycles
failure
TAMB<150°C
TAMB<85°C
TAMB<70°C
10000
10
h
RETFLASH
Flash data retention
years
years
µs
20
tW_PROG
tPERASE
tDERASE
Word (32-bit) programming
time
20
Page erase time
20
40
20.4
40.8
20.8 ms
41.6 ms
161.6 ms
71 mA
Device erase time
IERASE
IWRITE
VFLASH
Erase current
Write current
71 mA
Supply voltage during flash
erase and write
1.8
3.8 V
1Measured at 25°C
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2013-06-28 - EFM32LG330FXX - d0110_Rev1.10
14
Preliminary
...the world's most energy friendly microcontrollers
3.8 General Purpose Input Output
Table 3.8. GPIO
Symbol
VIOIL
Parameter
Condition
Min
Typ
Max
0.3VDD
Unit
V
Input low voltage
Input high voltage
VIOIH
0.7VDD
V
Sourcing 6 mA, VDD=1.8V,
GPIO_Px_CTRL DRIVE-
MODE = STANDARD
0.75VDD
0.95VDD
0.7VDD
0.9VDD
V
Sourcing 6 mA, VDD=3.0V,
GPIO_Px_CTRL DRIVE-
MODE = STANDARD
V
V
V
V
V
V
V
VIOOH
Output high voltage
Sourcing 20 mA, VDD=1.8V,
GPIO_Px_CTRL DRIVE-
MODE = HIGH
Sourcing 20 mA, VDD=3.0V,
GPIO_Px_CTRL DRIVE-
MODE = HIGH
Sinking 6 mA, VDD=1.8V,
GPIO_Px_CTRL DRIVE-
MODE = STANDARD
0.25VDD
0.05VDD
0.3VDD
0.1VDD
Sinking 6 mA, VDD=3.0V,
GPIO_Px_CTRL DRIVE-
MODE = STANDARD
VIOOL
Output low voltage
Sinking 20 mA, VDD=1.8V,
GPIO_Px_CTRL DRIVE-
MODE = HIGH
Sinking 20 mA, VDD=3.0V,
GPIO_Px_CTRL DRIVE-
MODE = HIGH
IIOLEAK
Input leakage current
High Impedance IO connect-
ed to GROUND or Vdd
+/-25 nA
RPU
I/O pin pull-up resistor
40
40
kOhm
kOhm
Ohm
RPD
I/O pin pull-down resistor
Internal ESD series resistor
RIOESD
tIOGLITCH
200
Pulse width of pulses to be
removed by the glitch sup-
pression filter
10
50 ns
0.5 mA drive strength
and load capacitance
CL=12.5-25pF.
20+0.1CL
250 ns
tIOOF
Output fall time
2mA drive strength and load
capacitance CL=350-600pF
20+0.1CL
0.1VDD
250 ns
V
VIOHYST
I/O pin hysteresis (VIOTHR+
VDD = 1.8 - 3.8 V
- VIOTHR-
)
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2013-06-28 - EFM32LG330FXX - d0110_Rev1.10
15
Preliminary
...the world's most energy friendly microcontrollers
Figure 3.1. Typical Low-Level Output Current, 2V Supply Voltage
0.20
0.15
0.10
0.05
0.00
5
4
3
2
1
-40°C
25°C
85°C
-40°C
25°C
85°C
0
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
Low-Level Output Voltage [V]
Low-Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = LOWEST
GPIO_Px_CTRL DRIVEMODE = LOW
20
45
40
35
30
25
20
15
10
5
15
10
5
-40°C
25°C
-40°C
25°C
85°C
85°C
0
0.0
0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
Low-Level Output Voltage [V]
Low-Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
GPIO_Px_CTRL DRIVEMODE = HIGH
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2013-06-28 - EFM32LG330FXX - d0110_Rev1.10
16
Preliminary
...the world's most energy friendly microcontrollers
Figure 3.2. Typical High-Level Output Current, 2V Supply Voltage
0.00
–0.05
–0.10
–0.15
–0.20
0.0
–0.5
–1.0
–1.5
–2.0
–2.5
-40°C
25°C
85°C
-40°C
25°C
85°C
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
High-Level Output Voltage [V]
High-Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = LOWEST
GPIO_Px_CTRL DRIVEMODE = LOW
0
0
-40°C
-40°C
25°C
85°C
25°C
85°C
–10
–20
–30
–40
–50
–5
–10
–15
–20
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
High-Level Output Voltage [V]
High-Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
GPIO_Px_CTRL DRIVEMODE = HIGH
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2013-06-28 - EFM32LG330FXX - d0110_Rev1.10
17
Preliminary
...the world's most energy friendly microcontrollers
Figure 3.3. Typical Low-Level Output Current, 3V Supply Voltage
0.5
0.4
0.3
0.2
0.1
0.0
10
8
6
4
2
-40°C
25°C
85°C
-40°C
25°C
85°C
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Low-Level Output Voltage [V]
Low-Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = LOWEST
GPIO_Px_CTRL DRIVEMODE = LOW
40
35
30
25
20
15
10
50
40
30
20
10
0
5
-40°C
-40°C
25°C
85°C
25°C
85°C
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Low-Level Output Voltage [V]
Low-Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
GPIO_Px_CTRL DRIVEMODE = HIGH
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2013-06-28 - EFM32LG330FXX - d0110_Rev1.10
18
Preliminary
...the world's most energy friendly microcontrollers
Figure 3.4. Typical High-Level Output Current, 3V Supply Voltage
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
0
-40°C
25°C
85°C
-40°C
25°C
85°C
–1
–2
–3
–4
–5
–6
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
High-Level Output Voltage [V]
High-Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = LOWEST
GPIO_Px_CTRL DRIVEMODE = LOW
0
0
-40°C
-40°C
25°C
85°C
25°C
85°C
–10
–20
–30
–40
–50
–10
–20
–30
–40
–50
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
High-Level Output Voltage [V]
High-Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
GPIO_Px_CTRL DRIVEMODE = HIGH
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2013-06-28 - EFM32LG330FXX - d0110_Rev1.10
19
Preliminary
...the world's most energy friendly microcontrollers
Figure 3.5. Typical Low-Level Output Current, 3.8V Supply Voltage
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
14
12
10
8
6
4
2
-40°C
25°C
85°C
-40°C
25°C
85°C
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Low-Level Output Voltage [V]
Low-Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = LOWEST
GPIO_Px_CTRL DRIVEMODE = LOW
50
40
30
20
10
50
40
30
20
10
0
-40°C
25°C
-40°C
25°C
85°C
85°C
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Low-Level Output Voltage [V]
Low-Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
GPIO_Px_CTRL DRIVEMODE = HIGH
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2013-06-28 - EFM32LG330FXX - d0110_Rev1.10
20
Preliminary
...the world's most energy friendly microcontrollers
Figure 3.6. Typical High-Level Output Current, 3.8V Supply Voltage
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
0
-40°C
25°C
85°C
-40°C
25°C
85°C
–1
–2
–3
–4
–5
–6
–7
–8
–9
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
High-Level Output Voltage [V]
High-Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = LOWEST
GPIO_Px_CTRL DRIVEMODE = LOW
0
0
-40°C
-40°C
25°C
85°C
25°C
85°C
–10
–20
–30
–40
–50
–10
–20
–30
–40
–50
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
High-Level Output Voltage [V]
High-Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
GPIO_Px_CTRL DRIVEMODE = HIGH
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2013-06-28 - EFM32LG330FXX - d0110_Rev1.10
21
Preliminary
...the world's most energy friendly microcontrollers
3.9 Oscillators
3.9.1 LFXO
Table 3.9. LFXO
Symbol
Parameter
Supported nominal crystal
Condition
Min
Typ
32.768
Max
Unit
fLFXO
kHz
frequency
ESRLFXO
Supported crystal equiv-
alent series resistance
(ESR)
30
120 kOhm
25 pF
CLFXOL
Supported crystal external
load range
X1
48
DCLFXO
ILFXO
Duty cycle
50
53.5
%
Current consumption for
core and buffer after start-
up.
ESR=30 kOhm, CL=10 pF,
LFXOBOOST in CMU_CTRL
is 1
190
nA
tLFXO
Start- up time.
ESR=30 kOhm, CL=10 pF,
40% - 60% duty cycle has
been reached, LFXOBOOST
in CMU_CTRL is 1
400
ms
1See Minimum Load Capacitance (CLFXOL) Requirement For Safe Crystal Startup in energyAware Designer in Simplicity Studio
For safe startup of a given crystal, the energyAware Designer in Simplicity Studio contains a tool to help
users configure both load capacitance and software settings for using the LFXO. For details regarding
the crystal configuration, the reader is referred to application note "AN0016 EFM32 Oscillator Design
Consideration".
3.9.2 HFXO
Table 3.10. HFXO
Symbol
Parameter
Condition
Min
Typ
Max
Unit
fHFXO
Supported nominal crystal
Frequency
4
48 MHz
Supported crystal equiv-
alent series resistance
(ESR)
Crystal frequency 32 MHz
Crystal frequency 4 MHz
30
60 Ohm
ESRHFXO
400
1500 Ohm
gmHFXO
The transconductance of
the HFXO input transistor
at crystal startup
HFXOBOOST in CMU_CTRL
equals 0b11
20
mS
CHFXOL
Supported crystal external
load range
5
25 pF
DCHFXO
Duty cycle
46
50
85
54
%
4 MHz: ESR=400 Ohm,
CL=20 pF, HFXOBOOST in
CMU_CTRL equals 0b11
µA
Current consumption for
HFXO after startup
IHFXO
32 MHz: ESR=30 Ohm,
CL=10 pF, HFXOBOOST in
CMU_CTRL equals 0b11
165
400
µA
µs
tHFXO
Startup time
32 MHz: ESR=30 Ohm,
CL=10 pF, HFXOBOOST in
CMU_CTRL equals 0b11
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2013-06-28 - EFM32LG330FXX - d0110_Rev1.10
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Preliminary
...the world's most energy friendly microcontrollers
3.9.3 LFRCO
Table 3.11. LFRCO
Symbol
Parameter
Oscillation frequency ,
Condition
Min
Typ
32.768
Max
Unit
fLFRCO
kHz
VDD= 3.0 V, TAMB=25°C
tLFRCO
Startup time not including
software calibration
150
µs
ILFRCO
Current consumption
190
1.5
nA
%
TUNESTEPL- Frequency step for LSB
change in TUNING value
FRCO
Figure 3.7. Calibrated LFRCO Frequency vs Temperature and Supply Voltage
42
40
38
36
34
32
30
42
40
38
36
34
32
30
-40°C
25°C
85°C
1.8 V
3 V
3.8 V
1.8
2.2
2.6
3.0
3.4
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
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2013-06-28 - EFM32LG330FXX - d0110_Rev1.10
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Preliminary
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3.9.4 HFRCO
Table 3.12. HFRCO
Symbol
Parameter
Condition
Min
Typ
Max
Unit
MHz
MHz
MHz
MHz
MHz
MHz
Cycles
µA
28 MHz frequency band
21 MHz frequency band
14 MHz frequency band
11 MHz frequency band
7 MHz frequency band
1 MHz frequency band
fHFRCO = 14 MHz
28
21
14
Oscillation frequency, VDD
3.0 V, TAMB=25°C
=
fHFRCO
11
6.61
1.22
0.6
106
93
tHFRCO_settling Settling time after start-up
fHFRCO = 28 MHz
fHFRCO = 21 MHz
µA
fHFRCO = 14 MHz
77
µA
IHFRCO
Current consumption
fHFRCO = 11 MHz
72
µA
fHFRCO = 6.6 MHz
63
µA
fHFRCO = 1.2 MHz
22
µA
DCHFRCO
Duty cycle
fHFRCO = 14 MHz
48.5
50
51
%
TUNESTEPH- Frequency step for LSB
0.3
%
change in TUNING value
FRCO
17 MHz for devices with prod. rev. < 19.
21 MHz for devices with prod. rev. < 19.
Figure 3.8. Calibrated HFRCO 11 MHz Band Frequency vs Temperature and Supply Voltage
11.15
11.10
11.05
11.00
10.95
10.90
10.85
10.80
11.20
11.15
11.10
11.05
11.00
10.95
10.90
10.85
10.80
1.8 V
3 V
3.8 V
-40°C
25°C
85°C
1.8
2.2
2.6
3.0
3.4
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
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Preliminary
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Figure 3.9. Calibrated HFRCO 14 MHz Band Frequency vs Temperature and Supply Voltage
14.15
14.10
14.05
14.00
13.95
13.90
13.85
14.15
14.10
14.05
14.00
13.95
13.90
13.85
-40°C
25°C
85°C
1.8 V
3 V
3.8 V
1.8
2.2
2.6
3.0
3.4
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
Figure 3.10. Calibrated HFRCO 21 MHz Band Frequency vs Temperature and Supply Voltage
21.2
21.1
21.0
20.9
20.8
20.7
20.6
21.2
21.1
21.0
20.9
20.8
20.7
20.6
-40°C
25°C
85°C
1.8 V
3 V
3.8 V
1.8
2.2
2.6
3.0
3.4
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
Figure 3.11. Calibrated HFRCO 28 MHz Band Frequency vs Temperature and Supply Voltage
28.1
28.0
27.9
27.8
27.7
27.6
27.5
27.4
28.1
28.0
27.9
27.8
27.7
27.6
27.5
27.4
1.8 V
3 V
3.8 V
-40°C
25°C
85°C
1.8
2.2
2.6
3.0
3.4
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
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2013-06-28 - EFM32LG330FXX - d0110_Rev1.10
25
Preliminary
...the world's most energy friendly microcontrollers
3.9.5 ULFRCO
Table 3.13. ULFRCO
Symbol
fULFRCO
Parameter
Condition
Min
Typ
Max
Unit
1.5 kHz
%/°C
Oscillation frequency
25°C, 3V
0.8
TCULFRCO
VCULFRCO
Temperature coefficient
Supply voltage coefficient
0.05
-18.2
%/V
3.10 Analog Digital Converter (ADC)
Table 3.14. ADC
Symbol
VADCIN
Parameter
Condition
Single ended
Differential
Min
Typ
Max
Unit
0
VREF
VREF/2
V
V
V
Input voltage range
-VREF/2
1.25
VADCREFIN
Input range of external ref-
erence voltage, single end-
ed and differential
VDD
VDD - 1.1
VDD
VADCREFIN_CH7 Input range of external neg- See VADCREFIN
0
0.625
0
V
V
ative reference voltage on
channel 7
VADCREFIN_CH6 Input range of external pos- See VADCREFIN
itive reference voltage on
channel 6
VADCCMIN
IADCIN
Common mode input range
Input current
VDD
V
2pF sampling capacitors
<100
65
nA
dB
CMRRADC
Analog input common
mode rejection ratio
1 MSamples/s, 12 bit, exter-
nal reference
351
67
µA
µA
10 kSamples/s 12 bit, internal
1.25 V reference, WARMUP-
MODE in ADCn_CTRL set to
0b00
10 kSamples/s 12 bit, internal
1.25 V reference, WARMUP-
MODE in ADCn_CTRL set to
0b01
63
64
µA
µA
µA
IADC
Average active current
10 kSamples/s 12 bit, internal
1.25 V reference, WARMUP-
MODE in ADCn_CTRL set to
0b10
IADCREF
Current consumption of in-
ternal voltage reference
Internal voltage reference
65
2
CADCIN
Input capacitance
pF
RADCIN
Input ON resistance
Input RC filter resistance
1
MOhm
kOhm
fF
RADCFILT
CADCFILT
10
Input RC filter/decoupling
capacitance
250
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2013-06-28 - EFM32LG330FXX - d0110_Rev1.10
26
Preliminary
...the world's most energy friendly microcontrollers
Symbol
Parameter
Condition
Min
Typ
Max
Unit
fADCCLK
ADC Clock Frequency
13 MHz
6 bit
7
11
13
1
ADC-
CLK
Cycles
10 bit
ADC-
CLK
Cycles
tADCCONV
Conversion time
12 bit
ADC-
CLK
Cycles
tADCACQ
Acquisition time
Programmable
256 ADC-
CLK
Cycles
tADCACQVDD3
Required acquisition time
for VDD/3 reference
2
µs
µs
Startup time of reference
generator and ADC core in
NORMAL mode
5
1
tADCSTART
Startup time of reference
generator and ADC core in
KEEPADCWARM mode
µs
1 MSamples/s, 12 bit, single
ended, internal 1.25V refer-
ence
59
63
dB
dB
1 MSamples/s, 12 bit, single
ended, internal 2.5V refer-
ence
1 MSamples/s, 12 bit, single
ended, VDD reference
65
60
dB
dB
1 MSamples/s, 12 bit, differ-
ential, internal 1.25V refer-
ence
1 MSamples/s, 12 bit, differ-
ential, internal 2.5V reference
65
54
67
69
62
dB
dB
dB
dB
dB
1 MSamples/s, 12 bit, differ-
ential, 5V reference
Signal to Noise Ratio
(SNR)
SNRADC
1 MSamples/s, 12 bit, differ-
ential, VDD reference
1 MSamples/s, 12 bit, differ-
ential, 2xVDD reference
200 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V ref-
erence
200 kSamples/s, 12 bit, sin-
gle ended, internal 2.5V refer-
ence
63
dB
200 kSamples/s, 12 bit, single
ended, VDD reference
67
63
dB
dB
200 kSamples/s, 12 bit, dif-
ferential, internal 1.25V refer-
ence
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Preliminary
...the world's most energy friendly microcontrollers
Symbol
Parameter
Condition
Min
Typ
Max
Unit
200 kSamples/s, 12 bit, differ-
ential, internal 2.5V reference
66
66
69
70
58
dB
200 kSamples/s, 12 bit, differ-
ential, 5V reference
dB
dB
dB
dB
200 kSamples/s, 12 bit, differ-
ential, VDD reference
200 kSamples/s, 12 bit, differ-
ential, 2xVDD reference
1 MSamples/s, 12 bit, single
ended, internal 1.25V refer-
ence
1 MSamples/s, 12 bit, single
ended, internal 2.5V refer-
ence
62
dB
1 MSamples/s, 12 bit, single
ended, VDD reference
64
60
dB
dB
1 MSamples/s, 12 bit, differ-
ential, internal 1.25V refer-
ence
1 MSamples/s, 12 bit, differ-
ential, internal 2.5V reference
64
54
66
68
61
dB
dB
dB
dB
dB
1 MSamples/s, 12 bit, differ-
ential, 5V reference
1 MSamples/s, 12 bit, differ-
ential, VDD reference
1 MSamples/s, 12 bit, differ-
ential, 2xVDD reference
Signal to Noise-puls-Distor-
tion Ratio (SNDR)
SNDRADC
200 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V ref-
erence
200 kSamples/s, 12 bit, sin-
gle ended, internal 2.5V refer-
ence
65
dB
200 kSamples/s, 12 bit, single
ended, VDD reference
66
63
dB
dB
200 kSamples/s, 12 bit, dif-
ferential, internal 1.25V refer-
ence
200 kSamples/s, 12 bit, differ-
ential, internal 2.5V reference
66
66
68
69
64
dB
dB
dB
dB
dBc
200 kSamples/s, 12 bit, differ-
ential, 5V reference
200 kSamples/s, 12 bit, differ-
ential, VDD reference
200 kSamples/s, 12 bit, differ-
ential, 2xVDD reference
1 MSamples/s, 12 bit, single
ended, internal 1.25V refer-
ence
Spurious-Free Dynamic
Range (SFDR)
SFDRADC
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Preliminary
...the world's most energy friendly microcontrollers
Symbol
Parameter
Condition
Min
Typ
Max
Unit
1 MSamples/s, 12 bit, single
ended, internal 2.5V refer-
ence
76
dBc
1 MSamples/s, 12 bit, single
ended, VDD reference
73
66
dBc
dBc
1 MSamples/s, 12 bit, differ-
ential, internal 1.25V refer-
ence
1 MSamples/s, 12 bit, differ-
ential, internal 2.5V reference
77
76
75
69
75
dBc
dBc
dBc
dBc
dBc
1 MSamples/s, 12 bit, differ-
ential, VDD reference
1 MSamples/s, 12 bit, differ-
ential, 2xVDD reference
1 MSamples/s, 12 bit, differ-
ential, 5V reference
200 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V ref-
erence
200 kSamples/s, 12 bit, sin-
gle ended, internal 2.5V refer-
ence
75
dBc
200 kSamples/s, 12 bit, single
ended, VDD reference
76
79
dBc
dBc
200 kSamples/s, 12 bit, dif-
ferential, internal 1.25V refer-
ence
200 kSamples/s, 12 bit, differ-
ential, internal 2.5V reference
79
78
79
79
dBc
dBc
dBc
dBc
200 kSamples/s, 12 bit, differ-
ential, 5V reference
200 kSamples/s, 12 bit, differ-
ential, VDD reference
200 kSamples/s, 12 bit, differ-
ential, 2xVDD reference
After calibration, single ended
After calibration, differential
0.3
0.3
mV
VADCOFFSET
Offset voltage
mV
-1.92
-6.3
mV/°C
Thermometer output gradi-
ent
ADC
Codes/
°C
TGRADADCTH
DNLADC
INLADC
MCADC
GAINED
Differential non-linearity
(DNL)
±0.7
±1.2
12
LSB
LSB
bits
Integral non-linearity (INL),
End point method
No missing codes
11.9991
1.25V reference
2.5V reference
0.012
0.012
0.0333 %/°C
0.033 %/°C
Gain error drift
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Preliminary
...the world's most energy friendly microcontrollers
Symbol
Parameter
Condition
Min
Typ
Max
Unit
1.25V reference
2.5V reference
0.22
0.22
0.73 LSB/°C
0.623 LSB/°C
OFFSETED
Offset error drift
1On the average every ADC will have one missing code, most likely to appear around 2048 +/- n*512 where n can be a value in
the set {-3, -2, -1, 1, 2, 3}. There will be no missing code around 2048, and in spite of the missing code the ADC will be monotonic
at all times so that a response to a slowly increasing input will always be a slowly increasing output. Around the one code that is
missing, the neighbour codes will look wider in the DNL plot. The spectra will show spurs on the level of -78dBc for a full scale
input for chips that have the missing code issue.
2Typical numbers given by abs(Mean) / (85 - 25).
3Max number given by (abs(Mean) + 3x stddev) / (85 - 25).
The integral non-linearity (INL) and differential non-linearity parameters are explained in Figure 3.12 (p.
30) and Figure 3.13 (p. 31) , respectively.
Figure 3.12. Integral Non-Linearity (INL)
Digital ouput code
INL= |[(VD-VSS)/VLSBIDEAL] - D| where 0 < D < 2N - 1
4095
4094
Actual ADC
tranfer function
before offset and
4093
Actual ADC
gain correction
4092
tranfer function
after offset and
gain correction
INL Error
(End Point INL)
Ideal transfer
curve
3
2
1
0
VOFFSET
Analog Input
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Preliminary
...the world's most energy friendly microcontrollers
Figure 3.13. Differential Non-Linearity (DNL)
Digital
ouput
DNL= |[(VD+ 1 - VD)/VLSBIDEAL] - 1| where 0 < D < 2N - 2
code
4095
4094
4093
4092
Full Scale Range
Example: Adjacent
input value VD+ 1
corrresponds to digital
output code D+ 1
Actual transfer
function with one
missing code.
Example: Input value
VD corrresponds to
digital output code D
Code width = 2 LSB
DNL= 1 LSB
Ideal transfer
curve
0.5
LSB
Ideal spacing
between two
adjacent codes
VLSBIDEAL= 1 LSB
5
4
3
2
1
0
Ideal 50%
Transition Point
Ideal Code Center
Analog Input
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Preliminary
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3.10.1 Typical performance
Figure 3.14. ADC Frequency Spectrum, Vdd = 3V, Temp = 25°
1.25V Reference
2XVDDVSS Reference
VDD Reference
2.5V Reference
5VDIFF Reference
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Preliminary
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Figure 3.15. ADC Integral Linearity Error vs Code, Vdd = 3V, Temp = 25°
1.25V Reference
2.5V Reference
2XVDDVSS Reference
5VDIFF Reference
VDD Reference
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Preliminary
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Figure 3.16. ADC Differential Linearity Error vs Code, Vdd = 3V, Temp = 25°
1.25V Reference
2.5V Reference
2XVDDVSS Reference
5VDIFF Reference
VDD Reference
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Preliminary
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Figure 3.17. ADC Absolute Offset, Common Mode = Vdd /2
5
4
3
2
1
0
2.0
1.5
Vref= 1V25
VRef= 1V25
Vref= 2V5
VRef= 2V5
Vref= 2XVDDVSS
Vref= 5VDIFF
Vref= VDD
VRef= 2XVDDVSS
VRef= 5VDIFF
VRef= VDD
1.0
0.5
–1
0.0
–2
–3
–4
–0.5
–1.0
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd (V)
Temp (C)
Offset vs Supply Voltage, Temp = 25°
Offset vs Temperature, Vdd = 3V
Figure 3.18. ADC Dynamic Performance vs Temperature for all ADC References, Vdd = 3V
71
70
69
68
67
66
65
64
63
79.4
79.2
79.0
78.8
78.6
78.4
78.2
78.0
2XVDDV
Vdd
1V25
Vdd
2V5
5VDIFF
2V5
2XVDDV
5VDIFF
85
1V25
–40
–15
5
25
45
65
85
–40
–15
5
25
45
65
Temperature [°C]
Temperature [°C]
Signal to Noise Ratio (SNR)
Spurious-Free Dynamic Range (SFDR)
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Preliminary
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Figure 3.19. ADC Temperature sensor readout
2600
Vdd= 1.8
Vdd= 3
Vdd= 3.8
2500
2400
2300
2200
2100
–40
–25 –15 –5
5
15 25 35 45 55 65 75 85
Temperature [°C]
3.11 Digital Analog Converter (DAC)
Table 3.15. DAC
Symbol
VDACOUT
VDACCM
Parameter
Condition
Min
Typ
Max
Unit
VDD voltage reference, single
ended
0
-VDD
0
VDD
VDD
VDD
V
Output voltage range
VDD voltage reference, differ-
ential
V
V
Output common mode volt-
age range
500 kSamples/s, 12bit
400
200
38
µA
µA
µA
Active current including ref-
erences for 2 channels
IDAC
100 kSamples/s, 12 bit
1 kSamples/s 12 bit NORMAL
SRDAC
Sample rate
500 ksam-
ples/s
Continuous Mode
Sample/Hold Mode
Sample/Off Mode
1000 kHz
250 kHz
250 kHz
fDAC
DAC clock frequency
CYCDACCONV Clock cyckles per conver-
sion
2
tDACCONV
Conversion time
Settling time
2
µs
µs
dB
tDACSETTLE
5
500 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V ref-
erence
58
500 kSamples/s, 12 bit, sin-
gle ended, internal 2.5V refer-
ence
59
58
dB
dB
Signal to Noise Ratio
(SNR)
SNRDAC
500 kSamples/s, 12 bit, dif-
ferential, internal 1.25V refer-
ence
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Preliminary
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Symbol
Parameter
Condition
Min
Typ
Max
Unit
500 kSamples/s, 12 bit, differ-
ential, internal 2.5V reference
58
59
57
dB
500 kSamples/s, 12 bit, differ-
ential, VDD reference
dB
dB
500 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V ref-
erence
500 kSamples/s, 12 bit, sin-
gle ended, internal 2.5V refer-
ence
54
56
dB
dB
Signal to Noise-pulse Dis-
tortion Ratio (SNDR)
SNDRDAC
500 kSamples/s, 12 bit, dif-
ferential, internal 1.25V refer-
ence
500 kSamples/s, 12 bit, differ-
ential, internal 2.5V reference
53
55
62
dB
500 kSamples/s, 12 bit, differ-
ential, VDD reference
dB
500 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V ref-
erence
dBc
500 kSamples/s, 12 bit, sin-
gle ended, internal 2.5V refer-
ence
56
61
dBc
dBc
Spurious-Free Dynamic
Range(SFDR)
SFDRDAC
500 kSamples/s, 12 bit, dif-
ferential, internal 1.25V refer-
ence
500 kSamples/s, 12 bit, differ-
ential, internal 2.5V reference
55
60
dBc
dBc
500 kSamples/s, 12 bit, differ-
ential, VDD reference
After calibration, single ended
After calibration, differential
2
2
mV
VDACOFFSET
Offset voltage
mV
DNLDAC
INLDAC
MCDAC
Differential non-linearity
Integral non-linearity
No missing codes
±1
±5
12
LSB
LSB
bits
3.12 Operational Amplifier (OPAMP)
The electrical characteristics for the Operational Amplifiers are based on simulations.
Table 3.16. OPAMP
Symbol
Parameter
Condition
Min
Typ
Max
Unit
(OPA2)BIASPROG=0xF,
(OPA2)HALFBIAS=0x0, Unity
Gain
400
100
µA
IOPAMP
Active Current
(OPA2)BIASPROG=0x7,
(OPA2)HALFBIAS=0x1, Unity
Gain
µA
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Preliminary
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Symbol
Parameter
Condition
Min
Typ
Max
Unit
(OPA2)BIASPROG=0x0,
(OPA2)HALFBIAS=0x1, Unity
Gain
13
µA
(OPA2)BIASPROG=0xF,
(OPA2)HALFBIAS=0x0
101
98
dB
(OPA2)BIASPROG=0x7,
(OPA2)HALFBIAS=0x1
dB
GOL
Open Loop Gain
(OPA2)BIASPROG=0x0,
(OPA2)HALFBIAS=0x1
91
dB
(OPA2)BIASPROG=0xF,
(OPA2)HALFBIAS=0x0
6.1
1.8
0.25
64
MHz
MHz
MHz
°
(OPA2)BIASPROG=0x7,
(OPA2)HALFBIAS=0x1
GBWOPAMP
Gain Bandwidth Product
(OPA2)BIASPROG=0x0,
(OPA2)HALFBIAS=0x1
(OPA2)BIASPROG=0xF,
(OPA2)HALFBIAS=0x0,
CL=75 pF
(OPA2)BIASPROG=0x7,
(OPA2)HALFBIAS=0x1,
CL=75 pF
58
58
°
°
PMOPAMP
Phase Margin
(OPA2)BIASPROG=0x0,
(OPA2)HALFBIAS=0x1,
CL=75 pF
RINPUT
RLOAD
Input Resistance
Load Resistance
DC Load Current
100
Mohm
Ohm
200
ILOAD_DC
11 mA
OPAxHCMDIS=0
OPAxHCMDIS=1
VSS
VSS
VSS
VDD
V
VINPUT
Input Voltage
VDD-1.2
VDD
V
VOUTPUT
Output Voltage
V
Unity Gain, VSS<Vin<DD
OPAxHCMDIS=0
,
6
1
mV
VOFFSET
Input Offset Voltage
Unity Gain, VSS<Vin<DD-1.2,
OPAxHCMDIS=1
mV
VOFFSET_DRIFT Input Offset Voltage Drift
0.02 mV/°C
V/µs
(OPA2)BIASPROG=0xF,
(OPA2)HALFBIAS=0x0
3.2
0.8
0.1
101
(OPA2)BIASPROG=0x7,
(OPA2)HALFBIAS=0x1
V/µs
SROPAMP
Slew Rate
(OPA2)BIASPROG=0x0,
(OPA2)HALFBIAS=0x1
V/µs
Vout=1V, RESSEL=0,
0.1 Hz<f<10 kHz, OPAx-
HCMDIS=0
µVRMS
NOPAMP
Voltage Noise
Vout=1V, RESSEL=0,
0.1 Hz<f<10 kHz, OPAx-
HCMDIS=1
141
µVRMS
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2013-06-28 - EFM32LG330FXX - d0110_Rev1.10
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Preliminary
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Symbol
Parameter
Condition
Min
Typ
Max
Unit
Vout=1V, RESSEL=0,
0.1 Hz<f<1 MHz, OPAx-
HCMDIS=0
196
229
µVRMS
Vout=1V, RESSEL=0,
0.1 Hz<f<1 MHz, OPAx-
HCMDIS=1
µVRMS
RESSEL=7, 0.1 Hz<f<10 kHz,
OPAxHCMDIS=0
1230
2130
1630
2590
µVRMS
µVRMS
µVRMS
µVRMS
RESSEL=7, 0.1 Hz<f<10 kHz,
OPAxHCMDIS=1
RESSEL=7, 0.1 Hz<f<1 MHz,
OPAxHCMDIS=0
RESSEL=7, 0.1 Hz<f<1 MHz,
OPAxHCMDIS=1
Figure 3.20. OPAMP Common Mode Rejection Ratio
Figure 3.21. OPAMP Positive Power Supply Rejection Ratio
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Preliminary
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Figure 3.22. OPAMP Negative Power Supply Rejection Ratio
Figure 3.23. OPAMP Voltage Noise Spectral Density (Unity Gain) Vout=1V
Figure 3.24. OPAMP Voltage Noise Spectral Density (Non-Unity Gain)
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Preliminary
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3.13 Analog Comparator (ACMP)
Table 3.17. ACMP
Symbol
VACMPIN
VACMPCM
Parameter
Condition
Min
Typ
Max
Unit
V
Input voltage range
0
0
VDD
VDD
ACMP Common Mode volt-
age range
V
BIASPROG=0b0000, FULL-
BIAS=0 and HALFBIAS=1 in
ACMPn_CTRL register
0.1
2.87
195
0
µA
µA
µA
µA
BIASPROG=0b1111, FULL-
BIAS=0 and HALFBIAS=0 in
ACMPn_CTRL register
IACMP
Active current
BIASPROG=0b1111, FULL-
BIAS=1 and HALFBIAS=0 in
ACMPn_CTRL register
Internal voltage reference off.
Using external voltage refer-
ence
Current consumption of in-
ternal voltage reference
IACMPREF
Internal voltage reference
Single ended
5
10
10
17
39
µA
mV
VACMPOFFSET Offset voltage
Differential
mV
VACMPHYST
ACMP hysteresis
Programmable
mV
CSRESSEL=0b00 in
ACMPn_INPUTSEL
kOhm
CSRESSEL=0b01 in
ACMPn_INPUTSEL
71
104
136
kOhm
kOhm
kOhm
Capacitive Sense Internal
Resistance
RCSRES
CSRESSEL=0b10 in
ACMPn_INPUTSEL
CSRESSEL=0b11 in
ACMPn_INPUTSEL
The total ACMP current is the sum of the contributions from the ACMP and its internal voltage reference
as given in Equation 3.1 (p. 41) . IACMPREF is zero if an external voltage reference is used.
Total ACMP Active Current
IACMPTOTAL = IACMP + IACMPREF
(3.1)
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Figure 3.25. Typical ACMP Characteristics
2.5
2.0
1.5
1.0
0.5
0.0
4.5
HYSTSEL= 0.0
HYSTSEL= 2.0
4.0
HYSTSEL= 4.0
HYSTSEL= 6.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
4
8
12
0
2
4
6
8
10
12
14
ACMP_CTRL_BIASPROG
ACMP_CTRL_BIASPROG
Current consumption
Response time
100
80
60
40
20
0
BIASPROG= 0.0
BIASPROG= 4.0
BIASPROG= 8.0
BIASPROG= 12.0
0
1
2
3
4
5
6
7
ACMP_CTRL_HYSTSEL
Hysteresis
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Preliminary
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3.14 Voltage Comparator (VCMP)
Table 3.18. VCMP
Symbol
VVCMPIN
VVCMPCM
Parameter
Condition
Min
Typ
Max
Unit
V
Input voltage range
VDD
VDD
VCMP Common Mode volt-
age range
V
BIASPROG=0b0000
and HALFBIAS=1 in
VCMPn_CTRL register
0.1
µA
µA
IVCMP
Active current
BIASPROG=0b1111
and HALFBIAS=0 in
VCMPn_CTRL register.
LPREF=0.
14.7
tVCMPREF
Startup time reference gen- NORMAL
erator
10
µs
Single ended
Differential
10
10
17
mV
mV
mV
VVCMPOFFSET Offset voltage
VVCMPHYST
VCMP hysteresis
The VDD trigger level can be configured by setting the TRIGLEVEL field of the VCMP_CTRL register in
accordance with the following equation:
VCMP Trigger Level as a Function of Level Setting
VDD Trigger Level=1.667V+0.034 ×TRIGLEVEL
(3.2)
3.15 Digital Peripherals
Table 3.19. Digital Peripherals
Symbol
Parameter
Condition
Min
Typ
Max
Unit
IUSART
USART current
USART idle current, clock en-
abled
7.5
5.63
150
6.25
8.75
150
100
100
2.5
µA/
MHz
IUART
ILEUART
II2C
UART current
LEUART current
I2C current
UART idle current, clock en-
abled
µA/
MHz
LEUART idle current, clock
enabled
nA
I2C idle current, clock en-
abled
µA/
MHz
ITIMER
ILETIMER
IPCNT
IRTC
TIMER current
LETIMER current
PCNT current
RTC current
TIMER_0 idle current, clock
enabled
µA/
MHz
LETIMER idle current, clock
enabled
nA
nA
nA
PCNT idle current, clock en-
abled
RTC idle current, clock en-
abled
IAES
AES current
AES idle current, clock en-
abled
µA/
MHz
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Preliminary
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Symbol
Parameter
Condition
Min
Typ
Max
Unit
IGPIO
GPIO current
GPIO idle current, clock en-
abled
5.31
2,81
8.12
µA/
MHz
IPRS
PRS current
DMA current
PRS idle current
µA/
MHz
IDMA
Clock enable
µA/
MHz
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4 Pinout and Package
Note
Please refer to the application note "AN0002 EFM32 Hardware Design Considerations" for
guidelines on designing Printed Circuit Boards (PCB's) for the EFM32LG330.
4.1 Pinout
The EFM32LG330 pinout is shown in Figure 4.1 (p. 45) and Table 4.1 (p. 45). Alternate locations
are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/").
Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module
in question.
Figure 4.1. EFM32LG330 Pinout (top view, not to scale)
Table 4.1. Device Pinout
QFN64 Pin#
and Name
Pin Alternate Functionality / Description
Pin Name
Analog
Timers
Communication
Other
0
1
VSS
PA0
Ground
LEU0_RX #4
I2C0_SDA #0
PRS_CH0 #0
GPIO_EM4WU0
TIM0_CC0 #0/1/4
TIM0_CC1 #0/1
CMU_CLK1 #0
PRS_CH1 #0
2
PA1
I2C0_SCL #0
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QFN64 Pin#
and Name
Pin Alternate Functionality / Description
Pin Name
Analog
Timers
Communication
Other
CMU_CLK0 #0
ETM_TD0 #3
3
4
5
6
PA2
PA3
PA4
PA5
TIM0_CC2 #0/1
TIM0_CDTI0 #0
TIM0_CDTI1 #0
TIM0_CDTI2 #0
LES_ALTEX2 #0
ETM_TD1 #3
LES_ALTEX3 #0
ETM_TD2 #3
LES_ALTEX4 #0
ETM_TD3 #3
LEU1_TX #1
LEU1_RX #1
ETM_TCLK #3
GPIO_EM4WU1
7
8
PA6
IOVDD_0
Digital IO power supply 0.
DAC0_OUT0ALT #0/
OPAMP_OUT0ALT
ACMP0_CH0
US0_TX #5
US1_TX #0
I2C0_SDA #4
TIM0_CC1 #4
PCNT0_S0IN #2
LES_CH0 #0
PRS_CH2 #0
9
PC0
PC1
PC2
PC3
PC4
PC5
DAC0_OUT0ALT #1/
OPAMP_OUT0ALT
ACMP0_CH1
US0_RX #5
US1_RX #0
I2C0_SCL #4
TIM0_CC2 #4
PCNT0_S1IN #2
LES_CH1 #0
PRS_CH3 #0
10
11
12
13
14
DAC0_OUT0ALT #2/
OPAMP_OUT0ALT
ACMP0_CH2
TIM0_CDTI0 #4
TIM0_CDTI1 #4
US2_TX #0
US2_RX #0
LES_CH2 #0
LES_CH3 #0
LES_CH4 #0
LES_CH5 #0
DAC0_OUT0ALT #3/
OPAMP_OUT0ALT
ACMP0_CH3
DAC0_P0 /
OPAMP_P0
ACMP0_CH4
TIM0_CDTI2 #4
LETIM0_OUT0 #3
PCNT1_S0IN #0
US2_CLK #0
I2C1_SDA #0
DAC0_N0 /
OPAMP_N0
ACMP0_CH5
LETIM0_OUT1 #3
PCNT1_S1IN #0
US2_CS #0
I2C1_SCL #0
US0_TX #4
US1_CLK #0
15
16
PB7
PB8
LFXTAL_P
LFXTAL_N
TIM1_CC0 #3
TIM1_CC1 #3
US0_RX #4
US1_CS #0
17
18
19
PA8
PA9
TIM2_CC0 #0
TIM2_CC1 #0
TIM2_CC2 #0
PA10
Reset input, active low.
20
21
RESETn
PB11
To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up en-
sure that reset is released.
DAC0_OUT0 /
OPAMP_OUT0
TIM1_CC2 #3
LETIM0_OUT0 #1
I2C1_SDA #1
I2C1_SCL #1
DAC0_OUT1 /
OPAMP_OUT1
22
23
24
PB12
AVDD_1
PB13
LETIM0_OUT1 #1
Analog power supply 1.
HFXTAL_P
US0_CLK #4/5
LEU0_TX #1
US0_CS #4/5
LEU0_RX #1
25
PB14
HFXTAL_N
26
27
IOVDD_3
AVDD_0
Digital IO power supply 3.
Analog power supply 0.
ADC0_CH0
28
PD0
DAC0_OUT0ALT #4/
OPAMP_OUT0ALT
PCNT2_S0IN #0
US1_TX #1
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QFN64 Pin#
and Name
Pin Alternate Functionality / Description
Pin Name
Analog
Timers
Communication
Other
DAC0_OUT2 #1/
OPAMP_OUT2
ADC0_CH1
DAC0_OUT1ALT #4/
OPAMP_OUT1ALT
TIM0_CC0 #3
PCNT2_S1IN #0
29
30
31
PD1
PD2
PD3
US1_RX #1
DBG_SWO #2
DBG_SWO #3
ETM_TD1 #0/2
US1_CLK #1
USB_DMPU #0
ADC0_CH2
TIM0_CC1 #3
TIM0_CC2 #3
ADC0_CH3
DAC0_N2 /
OPAMP_N2
US1_CS #1
LEU0_TX #0
LEU0_RX #0
ADC0_CH4
DAC0_P2 /
OPAMP_P2
32
33
34
PD4
PD5
PD6
ETM_TD2 #0/2
ETM_TD3 #0/2
ADC0_CH5
DAC0_OUT2 #0/
OPAMP_OUT2
ADC0_CH6
DAC0_P1 /
OPAMP_P1
TIM1_CC0 #4
LETIM0_OUT0 #0
PCNT0_S0IN #3
LES_ALTEX0 #0
ACMP0_O #2
ETM_TD0 #0
US1_RX #2
I2C0_SDA #1
CMU_CLK0 #2
LES_ALTEX1 #0
ACMP1_O #2
ADC0_CH7
DAC0_N1 /
OPAMP_N1
TIM1_CC1 #4
LETIM0_OUT1 #0
PCNT0_S1IN #3
US1_TX #2
I2C0_SCL #1
35
PD7
ETM_TCLK #0
36
37
PD8
PC6
BU_VIN
CMU_CLK1 #1
LEU1_TX #0
I2C0_SDA #2
LES_CH6 #0
ETM_TCLK #2
ACMP0_CH6
LEU1_RX #0
I2C0_SCL #2
LES_CH7 #0
ETM_TD0 #2
38
PC7
ACMP0_CH7
39
40
41
VDD_DREG
DECOUPLE
PC8
Power supply for on-chip voltage regulator.
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin.
ACMP1_CH0
ACMP1_CH1
TIM2_CC0 #2
TIM2_CC1 #2
TIM2_CC2 #2
US0_CS #2
LES_CH8 #0
LES_CH9 #0
GPIO_EM4WU2
42
PC9
US0_CLK #2
43
44
45
46
47
48
PC10
PC11
ACMP1_CH2
US0_RX #2
US0_TX #2
LES_CH10 #0
LES_CH11 #0
ACMP1_CH3
USB_VREGI
USB_VREGO
PF10
USB Input to internal 3.3 V regulator.
USB Decoupling for internal 3.3 V USB regulator and regulator output.
USB_DM
USB_DP
PF11
US1_CLK #2
LEU0_TX #3
I2C0_SDA #5
TIM0_CC0 #5
LETIM0_OUT0 #2
49
50
51
PF0
PF1
PF2
DBG_SWCLK #0/1/2/3
US1_CS #2
LEU0_RX #3
I2C0_SCL #5
TIM0_CC1 #5
LETIM0_OUT1 #2
DBG_SWDIO #0/1/2/3
GPIO_EM4WU3
ACMP1_O #0
DBG_SWO #0
GPIO_EM4WU4
TIM0_CC2 #5
LEU0_TX #4
52
53
54
USB_VBUS
PF12
USB 5.0 V VBUS input.
USB_ID
PF5
TIM0_CDTI2 #2/5
USB_VBUSEN #0
PRS_CH2 #1
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QFN64 Pin#
and Name
Pin Alternate Functionality / Description
Pin Name
Analog
Timers
Communication
Other
55
56
57
58
IOVDD_5
PE8
Digital IO power supply 5.
PCNT2_S0IN #1
PCNT2_S1IN #1
TIM1_CC0 #1
PRS_CH3 #1
BOOT_TX
PE9
PE10
US0_TX #0
US0_RX #0
LES_ALTEX5 #0
BOOT_RX
59
60
PE11
PE12
TIM1_CC1 #1
TIM1_CC2 #1
US0_RX #3
US0_CLK #0
I2C0_SDA #6
CMU_CLK1 #2
LES_ALTEX6 #0
US0_TX #3
US0_CS #0
I2C0_SCL #6
LES_ALTEX7 #0
ACMP0_O #0
GPIO_EM4WU5
61
PE13
62
63
64
PE14
PE15
PA15
TIM3_CC0 #0
TIM3_CC1 #0
TIM3_CC2 #0
LEU0_TX #2
LEU0_RX #2
4.2 Alternate functionality pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in
Table 4.2 (p. 48). The table shows the name of the alternate functionality in the first column, followed
by columns showing the possible LOCATION bitfield settings.
Note
Some functionality, such as analog interfaces, do not have alternate settings or a LOCA-
TION bitfield. In these cases, the pinout is shown in the column corresponding to LOCA-
TION 0.
Table 4.2. Alternate functionality overview
Alternate
LOCATION
Functionality
ACMP0_CH0
ACMP0_CH1
ACMP0_CH2
ACMP0_CH3
ACMP0_CH4
ACMP0_CH5
ACMP0_CH6
ACMP0_CH7
ACMP0_O
0
1
2
3
4
5
6
Description
Analog comparator ACMP0, channel 0.
Analog comparator ACMP0, channel 1.
Analog comparator ACMP0, channel 2.
Analog comparator ACMP0, channel 3.
Analog comparator ACMP0, channel 4.
Analog comparator ACMP0, channel 5.
Analog comparator ACMP0, channel 6.
Analog comparator ACMP0, channel 7.
Analog comparator ACMP0, digital output.
Analog comparator ACMP1, channel 0.
Analog comparator ACMP1, channel 1.
Analog comparator ACMP1, channel 2.
Analog comparator ACMP1, channel 3.
Analog comparator ACMP1, digital output.
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PE13
PC8
PC9
PC10
PC11
PF2
PD6
ACMP1_CH0
ACMP1_CH1
ACMP1_CH2
ACMP1_CH3
ACMP1_O
PD7
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Alternate
LOCATION
Functionality
ADC0_CH0
ADC0_CH1
ADC0_CH2
ADC0_CH3
ADC0_CH4
ADC0_CH5
ADC0_CH6
ADC0_CH7
BOOT_RX
BOOT_TX
0
1
2
3
4
5
6
Description
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PE11
PE10
PD8
PA2
PA1
Analog to digital converter ADC0, input channel number 0.
Analog to digital converter ADC0, input channel number 1.
Analog to digital converter ADC0, input channel number 2.
Analog to digital converter ADC0, input channel number 3.
Analog to digital converter ADC0, input channel number 4.
Analog to digital converter ADC0, input channel number 5.
Analog to digital converter ADC0, input channel number 6.
Analog to digital converter ADC0, input channel number 7.
Bootloader RX
Bootloader TX
BU_VIN
Battery input for Backup Power Domain
CMU_CLK0
CMU_CLK1
PD7
Clock Management Unit, clock output number 0.
Clock Management Unit, clock output number 1.
PD8
PE12
DAC0_N0 /
OPAMP_N0
PC5
PD7
PD3
PB11
PC0
PB12
Operational Amplifier 0 external negative input.
Operational Amplifier 1 external negative input.
Operational Amplifier 2 external negative input.
DAC0_N1 /
OPAMP_N1
DAC0_N2 /
OPAMP_N2
DAC0_OUT0 /
OPAMP_OUT0
Digital to Analog Converter DAC0_OUT0 /
OPAMP output channel number 0.
DAC0_OUT0ALT /
OPAMP_OUT0ALT
Digital to Analog Converter DAC0_OUT0ALT /
OPAMP alternative output for channel 0.
PC1
PC2
PC3
PD0
DAC0_OUT1 /
OPAMP_OUT1
Digital to Analog Converter DAC0_OUT1 /
OPAMP output channel number 1.
DAC0_OUT1ALT /
OPAMP_OUT1ALT
Digital to Analog Converter DAC0_OUT1ALT /
OPAMP alternative output for channel 1.
PD1
DAC0_OUT2 /
OPAMP_OUT2
Digital to Analog Converter DAC0_OUT2 /
OPAMP output channel number 2.
PD5
PC4
PD6
PD4
PD0
DAC0_P0 /
OPAMP_P0
Operational Amplifier 0 external positive input.
Operational Amplifier 1 external positive input.
DAC0_P1 /
OPAMP_P1
DAC0_P2 /
OPAMP_P2
Operational Amplifier 2 external positive input.
Debug-interface Serial Wire clock input.
DBG_SWCLK
DBG_SWDIO
DBG_SWO
PF0
PF1
PF2
PF0
PF1
PF0
PF1
PD1
PF0
PF1
PD2
Note that this function is enabled to pin out of reset, and
has a built-in pull down.
Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, and
has a built-in pull up.
Debug-interface Serial Wire viewer Output.
Note that this function is not enabled after reset, and must
be enabled by software to be used.
ETM_TCLK
ETM_TD0
ETM_TD1
ETM_TD2
ETM_TD3
PD7
PD6
PD3
PD4
PD5
PC6
PC7
PD3
PD4
PD5
PA6
PA2
PA3
PA4
PA5
Embedded Trace Module ETM clock .
Embedded Trace Module ETM data 0.
Embedded Trace Module ETM data 1.
Embedded Trace Module ETM data 2.
Embedded Trace Module ETM data 3.
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Alternate
LOCATION
Functionality
GPIO_EM4WU0
GPIO_EM4WU1
GPIO_EM4WU2
GPIO_EM4WU3
GPIO_EM4WU4
GPIO_EM4WU5
0
1
2
3
4
5
6
Description
PA0
PA6
PC9
PF1
PF2
PE13
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
High Frequency Crystal negative pin. Also used as exter-
nal optional clock input pin.
HFXTAL_N
PB14
HFXTAL_P
I2C0_SCL
PB13
PA1
PA0
PC5
PC4
PD6
PD7
PA3
PA4
PA5
PE11
PE12
PE13
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PD6
PD7
PD5
High Frequency Crystal positive pin.
I2C0 Serial Clock Line input / output.
I2C0 Serial Data input / output.
I2C1 Serial Clock Line input / output.
I2C1 Serial Data input / output.
LESENSE alternate exite output 0.
LESENSE alternate exite output 1.
LESENSE alternate exite output 2.
LESENSE alternate exite output 3.
LESENSE alternate exite output 4.
LESENSE alternate exite output 5.
LESENSE alternate exite output 6.
LESENSE alternate exite output 7.
LESENSE channel 0.
PD7
PC7
PC6
PC1
PF1
PF0
PE13
PE12
I2C0_SDA
I2C1_SCL
PD6
PC0
PB12
PB11
I2C1_SDA
LES_ALTEX0
LES_ALTEX1
LES_ALTEX2
LES_ALTEX3
LES_ALTEX4
LES_ALTEX5
LES_ALTEX6
LES_ALTEX7
LES_CH0
LES_CH1
LESENSE channel 1.
LES_CH2
LESENSE channel 2.
LES_CH3
LESENSE channel 3.
LES_CH4
LESENSE channel 4.
LES_CH5
LESENSE channel 5.
LES_CH6
LESENSE channel 6.
LES_CH7
LESENSE channel 7.
LES_CH8
LESENSE channel 8.
LES_CH9
LESENSE channel 9.
LES_CH10
LES_CH11
LETIM0_OUT0
LETIM0_OUT1
LEU0_RX
LESENSE channel 10.
LESENSE channel 11.
PB11
PB12
PB14
PF0
PC4
PC5
PF1
Low Energy Timer LETIM0, output channel 0.
Low Energy Timer LETIM0, output channel 1.
LEUART0 Receive input.
PF1
PE15
PA0
PF2
LEUART0 Transmit output. Also used as receive input in
half duplex communication.
LEU0_TX
LEU1_RX
LEU1_TX
PD4
PC7
PC6
PB13
PA6
PA5
PE14
PF0
LEUART1 Receive input.
LEUART1 Transmit output. Also used as receive input in
half duplex communication.
Low Frequency Crystal (typically 32.768 kHz) negative
pin. Also used as an optional external clock input pin.
LFXTAL_N
PB8
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Alternate
LOCATION
Functionality
LFXTAL_P
PCNT0_S0IN
PCNT0_S1IN
PCNT1_S0IN
PCNT1_S1IN
PCNT2_S0IN
PCNT2_S1IN
PRS_CH0
0
1
2
3
4
5
6
Description
PB7
Low Frequency Crystal (typically 32.768 kHz) positive pin.
Pulse Counter PCNT0 input number 0.
PC0
PC1
PD6
PD7
Pulse Counter PCNT0 input number 1.
PC4
PC5
PD0
PD1
PA0
PA1
PC0
PC1
PA0
PA1
PA2
PA3
PA4
PA5
Pulse Counter PCNT1 input number 0.
Pulse Counter PCNT1 input number 1.
PE8
Pulse Counter PCNT2 input number 0.
PE9
Pulse Counter PCNT2 input number 1.
Peripheral Reflex System PRS, channel 0.
Peripheral Reflex System PRS, channel 1.
Peripheral Reflex System PRS, channel 2.
Peripheral Reflex System PRS, channel 3.
Timer 0 Capture Compare input / output channel 0.
Timer 0 Capture Compare input / output channel 1.
Timer 0 Capture Compare input / output channel 2.
Timer 0 Complimentary Deat Time Insertion channel 0.
Timer 0 Complimentary Deat Time Insertion channel 1.
Timer 0 Complimentary Deat Time Insertion channel 2.
Timer 1 Capture Compare input / output channel 0.
Timer 1 Capture Compare input / output channel 1.
Timer 1 Capture Compare input / output channel 2.
Timer 2 Capture Compare input / output channel 0.
Timer 2 Capture Compare input / output channel 1.
Timer 2 Capture Compare input / output channel 2.
Timer 3 Capture Compare input / output channel 0.
Timer 3 Capture Compare input / output channel 1.
Timer 3 Capture Compare input / output channel 2.
USART0 clock input / output.
PRS_CH1
PRS_CH2
PF5
PE8
PA0
PA1
PA2
PRS_CH3
TIM0_CC0
TIM0_CC1
TIM0_CC2
TIM0_CDTI0
TIM0_CDTI1
TIM0_CDTI2
TIM1_CC0
TIM1_CC1
TIM1_CC2
TIM2_CC0
TIM2_CC1
TIM2_CC2
TIM3_CC0
TIM3_CC1
TIM3_CC2
US0_CLK
PD1
PD2
PD3
PA0
PF0
PF1
PF2
PC0
PC1
PC2
PC3
PC4
PD6
PD7
PF5
PF5
PE10
PE11
PE12
PB7
PB8
PB11
PA8
PC8
PC9
PC10
PA9
PA10
PE14
PE15
PA15
PE12
PE13
PC9
PC8
PB13
PB14
PB13
PB14
US0_CS
USART0 chip select input / output.
USART0 Asynchronous Receive.
US0_RX
US0_TX
PE11
PE10
PC10
PC11
PE12
PE13
PB8
PB7
PC1
PC0
USART0 Synchronous mode Master Input / Slave Output
(MISO).
USART0 Asynchronous Transmit.Also used as receive in-
put in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input
(MOSI).
US1_CLK
US1_CS
PB7
PB8
PD2
PD3
PF0
PF1
USART1 clock input / output.
USART1 chip select input / output.
USART1 Asynchronous Receive.
US1_RX
PC1
PD1
PD0
PD6
PD7
USART1 Synchronous mode Master Input / Slave Output
(MISO).
USART1 Asynchronous Transmit.Also used as receive in-
put in half duplex communication.
US1_TX
PC0
PC4
USART1 Synchronous mode Master Output / Slave Input
(MOSI).
US2_CLK
USART2 clock input / output.
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Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
USART2 chip select input / output.
USART2 Asynchronous Receive.
US2_CS
PC5
PC3
US2_RX
US2_TX
USART2 Synchronous mode Master Input / Slave Output
(MISO).
USART2 Asynchronous Transmit.Also used as receive in-
put in half duplex communication.
PC2
USART2 Synchronous mode Master Output / Slave Input
(MOSI).
USB_DM
PF10
PD2
USB D- pin.
USB_DMPU
USB_DP
USB D- Pullup control.
USB D+ pin.
PF11
PF12
USB_ID
USB ID pin. Used in OTG mode.
USB 5 V VBUS input.
USB 5 V VBUS enable.
USB Input to internal 3.3 V regulator
USB_VBUS
USB_VBUSEN
USB_VREGI
USB_VBUS
PF5
USB_VREGI
USB Decoupling for internal 3.3 V USB regulator and reg-
ulator output
USB_VREGO
USB_VREGO
4.3 GPIO pinout overview
The specific GPIO pins available in EFM32LG330 is shown in Table 4.3 (p. 52). Each GPIO port is
organized as 16-bit ports indicated by letters A through F, and the individual pin on this port in indicated
by a number from 15 down to 0.
Table 4.3. GPIO Pinout
Port
Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin
Pin
0
15
14
13
12
11
10
PA10
-
9
PA9
-
8
7
6
PA6
-
5
PA5
-
4
PA4
-
3
PA3
-
2
PA2
-
1
PA1
-
Port A
Port B
Port C
Port D
Port E
Port F
PA15
-
-
-
-
PA8
PB8
PC8
PD8
PE8
-
-
PA0
-
-
-
-
PB14 PB13 PB12 PB11
PB7
PC7
PD7
-
-
-
-
-
-
-
PC11 PC10
PC9
-
PC6
PD6
-
PC5
PD5
-
PC4
PD4
-
PC3
PD3
-
PC2
PD2
-
PC1
PD1
-
PC0
PD0
-
-
-
PE15 PE14 PE13 PE12 PE11 PE10
PF12 PF11 PF10
PE9
-
-
-
-
-
-
PF5
-
-
PF2
PF1
PF0
4.4 Opamp pinout overview
The specific opamp terminals available in EFM32LG330 is shown in Figure 4.2 (p. 53) .
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Figure 4.2. Opamp Pinout
PB11
PB12
OUT0ALT
PC4
PC5
+
PC0
OPA0
-
OUT0
PC1
PC2
PC3
+
PD4
PD3
PC12
PC13
PC14
PC15
PD0
OPA2
-
OUT2
PD6
PD7
OUT1ALT
OUT1
+
OPA1
-
PD1
PD5
4.5 QFN64 Package
Figure 4.3. QFN64
Note:
1. Dimensioning & tolerancing confirm to ASME Y14.5M-1994.
2. All dimensions are in millimeters. Angles are in degrees.
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3. Dimension 'b' applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from
the terminal tip. Dimension L1 represents terminal full back from package edge up to 0.1 mm is
acceptable.
4. Coplanarity applies to the exposed heat slug as well as the terminal.
5. Radius on terminal is optional
Table 4.4. QFN64 (Dimensions in mm)
Symbol
Min
A
A1
A3
b
D
E
D2
E2
e
L
L1
aaa bbb ccc ddd
eee
0.80 0.00
0.20
0.25
0.30
7.10 7.10
7.20 7.20
7.30 7.30
0.40 0.00
0.45
0.203
REF
9.00 9.00
BSC BSC
0.50
BSC
Nom
Max
0.85
-
0.10 0.10 0.10 0.05 0.08
0.90 0.05
0.50 0.10
The QFN64 Package uses Nickel-Palladium-Gold preplated leadframe.
All EFM32 packages are RoHS compliant and free of Bromine (Br) and Antimony (Sb).
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5 PCB Layout and Soldering
5.1 Recommended PCB Layout
Figure 5.1. QFN64 PCB Land Pattern
a
p8
p7
p1
p6
b
p9
e
g
c
p2
p5
p3
p4
f
d
Table 5.1. QFN64 PCB Land Pattern Dimensions (Dimensions in mm)
Symbol
Dim. (mm)
0.85
Symbol
P1
Pin number
Symbol
Pin number
a
b
c
d
e
f
1
P8
64
65
-
0.30
P2
16
17
32
33
48
49
P9
0.50
P3
-
-
-
-
-
8.90
P4
-
8.90
P5
-
7.20
P6
-
g
7.20
P7
-
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Figure 5.2. QFN64 PCB Solder Mask
a
b
c
e
g
f
d
Table 5.2. QFN64 PCB Solder Mask Dimensions (Dimensions in mm)
Symbol
Dim. (mm)
0.97
Symbol
Dim. (mm)
a
b
c
d
e
f
8.90
7.32
7.32
-
0.42
0.50
g
-
8.90
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Figure 5.3. QFN64 PCB Stencil Design
a
b
c
x
y
e
z
d
Table 5.3. QFN64 PCB Stencil Design Dimensions (Dimensions in mm)
Symbol
Dim. (mm)
0.75
Symbol
Dim. (mm)
8.90
a
b
c
d
e
x
y
z
0.22
2.70
0.50
2.70
8.90
0.80
1. The drawings are not to scale.
2. All dimensions are in millimeters.
3. All drawings are subject to change without notice.
4. The PCB Land Pattern drawing is in compliance with IPC-7351B.
5. Stencil thickness 0.125 mm.
6. For detailed pin-positioning, see Figure 4.3 (p. 53) .
5.2 Soldering Information
The latest IPC/JEDEC J-STD-020 recommendations for Pb-Free reflow soldering should be followed.
The packages have a Moisture Sensitivity Level rating of 3, please see the latest IPC/JEDEC J-STD-033
standard for MSL description and level 3 bake conditions.
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6 Chip Marking, Revision and Errata
6.1 Chip Marking
In the illustration below package fields and position are shown.
Figure 6.1. Example Chip Marking
6.2 Revision
The revision of a chip can be determined from the "Revision" field in Figure 6.1 (p. 58). If the revision
says "ES" (Engineering Sample), the revision must be read out electronically as specified in the reference
manual.
6.3 Errata
Please see the errata document for EFM32LG330 for description and resolution of device erratas.
This document is available in Simplicity Studio and online at http://www.energymicro.com/down-
loads/datasheets.
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7 Revision History
7.1 Revision 1.10
June 28th, 2013
Updated power requirements in the Power Management section.
Removed minimum load capacitance figure and table. Added reference to application note.
Other minor corrections.
7.2 Revision 1.00
September 11th, 2012
Updated the HFRCO 1 MHz band typical value to 1.2 MHz.
Updated the HFRCO 7 MHz band typical value to 6.6 MHz.
Other minor corrections.
7.3 Revision 0.92
May 25th, 2012
Corrected EM3 current consumption in the Electrical Characteristics section.
7.4 Revision 0.90
April 27th, 2012
Initial preliminary release.
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A Disclaimer and Trademarks
A.1 Disclaimer
Energy Micro AS intends to provide customers with the latest, accurate, and in-depth documentation of
all peripherals and modules available for system and software implementers using or intending to use
the Energy Micro products. Characterization data, available modules and peripherals, memory sizes and
memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in
different applications. Application examples described herein are for illustrative purposes only. Energy
Micro reserves the right to make changes without further notice and limitation to product information,
specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness
of the included information. Energy Micro shall have no liability for the consequences of use of the infor-
mation supplied herein. This document does not imply or express copyright licenses granted hereunder
to design or fabricate any integrated circuits. The products must not be used within any Life Support
System without the specific written consent of Energy Micro. A "Life Support System" is any product or
system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected
to result in significant personal injury or death. Energy Micro products are generally not intended for
military applications. Energy Micro products shall under no circumstances be used in weapons of mass
destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable
of delivering such weapons.
A.2 Trademark Information
Energy Micro, EFM32, EFR, logo and combinations thereof, and others are the registered trademarks or
trademarks of Energy Micro AS. ARM, CORTEX, THUMB are the registered trademarks of ARM Limited.
Other terms and product names may be trademarks of others.
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B Contact Information
B.1 Energy Micro Corporate Headquarters
Postal Address
Visitor Address
Technical Support
Energy Micro AS
P.O. Box 4633 Nydalen
N-0405 Oslo
Energy Micro AS
Sandakerveien 118
N-0484 Oslo
support.energymicro.com
Phone: +47 40 10 03 01
NORWAY
NORWAY
www.energymicro.com
Phone: +47 23 00 98 00
Fax: + 47 23 00 98 01
B.2 Global Contacts
Visit www.energymicro.com for information on global distributors and representatives or contact
sales@energymicro.com for additional information.
Americas
Europe, Middle East and Africa Asia and Pacific
www.energymicro.com/americas www.energymicro.com/emea
www.energymicro.com/asia
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Table of Contents
1. Ordering Information .................................................................................................................................. 2
2. System Summary ...................................................................................................................................... 3
2.1. System Introduction ......................................................................................................................... 3
2.2. Configuration Summary .................................................................................................................... 7
2.3. Memory Map ................................................................................................................................. 8
3. Electrical Characteristics ........................................................................................................................... 10
3.1. Test Conditions ............................................................................................................................. 10
3.2. Absolute Maximum Ratings ............................................................................................................. 10
3.3. General Operating Conditions .......................................................................................................... 10
3.4. Current Consumption ..................................................................................................................... 12
3.5. Transition between Energy Modes .................................................................................................... 13
3.6. Power Management ....................................................................................................................... 13
3.7. Flash .......................................................................................................................................... 14
3.8. General Purpose Input Output ......................................................................................................... 15
3.9. Oscillators .................................................................................................................................... 22
3.10. Analog Digital Converter (ADC) ...................................................................................................... 26
3.11. Digital Analog Converter (DAC) ...................................................................................................... 36
3.12. Operational Amplifier (OPAMP) ...................................................................................................... 37
3.13. Analog Comparator (ACMP) .......................................................................................................... 41
3.14. Voltage Comparator (VCMP) ......................................................................................................... 43
3.15. Digital Peripherals ....................................................................................................................... 43
4. Pinout and Package ................................................................................................................................. 45
4.1. Pinout ......................................................................................................................................... 45
4.2. Alternate functionality pinout ............................................................................................................ 48
4.3. GPIO pinout overview .................................................................................................................... 52
4.4. Opamp pinout overview .................................................................................................................. 52
4.5. QFN64 Package ........................................................................................................................... 53
5. PCB Layout and Soldering ........................................................................................................................ 55
5.1. Recommended PCB Layout ............................................................................................................ 55
5.2. Soldering Information ..................................................................................................................... 57
6. Chip Marking, Revision and Errata .............................................................................................................. 58
6.1. Chip Marking ................................................................................................................................ 58
6.2. Revision ...................................................................................................................................... 58
6.3. Errata ......................................................................................................................................... 58
7. Revision History ...................................................................................................................................... 59
7.1. Revision 1.10 ............................................................................................................................... 59
7.2. Revision 1.00 ............................................................................................................................... 59
7.3. Revision 0.92 ............................................................................................................................... 59
7.4. Revision 0.90 ............................................................................................................................... 59
A. Disclaimer and Trademarks ....................................................................................................................... 60
A.1. Disclaimer ................................................................................................................................... 60
A.2. Trademark Information ................................................................................................................... 60
B. Contact Information ................................................................................................................................. 61
B.1. Energy Micro Corporate Headquarters .............................................................................................. 61
B.2. Global Contacts ............................................................................................................................ 61
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List of Figures
2.1. Block Diagram ....................................................................................................................................... 3
2.2. EFM32LG330 Memory Map with largest RAM and Flash sizes ........................................................................ 9
3.1. Typical Low-Level Output Current, 2V Supply Voltage .................................................................................. 16
3.2. Typical High-Level Output Current, 2V Supply Voltage ................................................................................. 17
3.3. Typical Low-Level Output Current, 3V Supply Voltage .................................................................................. 18
3.4. Typical High-Level Output Current, 3V Supply Voltage ................................................................................. 19
3.5. Typical Low-Level Output Current, 3.8V Supply Voltage ............................................................................... 20
3.6. Typical High-Level Output Current, 3.8V Supply Voltage ............................................................................... 21
3.7. Calibrated LFRCO Frequency vs Temperature and Supply Voltage ................................................................ 23
3.8. Calibrated HFRCO 11 MHz Band Frequency vs Temperature and Supply Voltage ............................................ 24
3.9. Calibrated HFRCO 14 MHz Band Frequency vs Temperature and Supply Voltage ............................................ 25
3.10. Calibrated HFRCO 21 MHz Band Frequency vs Temperature and Supply Voltage ........................................... 25
3.11. Calibrated HFRCO 28 MHz Band Frequency vs Temperature and Supply Voltage ........................................... 25
3.12. Integral Non-Linearity (INL) ................................................................................................................... 30
3.13. Differential Non-Linearity (DNL) .............................................................................................................. 31
3.14. ADC Frequency Spectrum, Vdd = 3V, Temp = 25° ................................................................................... 32
3.15. ADC Integral Linearity Error vs Code, Vdd = 3V, Temp = 25° ..................................................................... 33
3.16. ADC Differential Linearity Error vs Code, Vdd = 3V, Temp = 25° ................................................................. 34
3.17. ADC Absolute Offset, Common Mode = Vdd /2 ........................................................................................ 35
3.18. ADC Dynamic Performance vs Temperature for all ADC References, Vdd = 3V .............................................. 35
3.19. ADC Temperature sensor readout ......................................................................................................... 36
3.20. OPAMP Common Mode Rejection Ratio ................................................................................................. 39
3.21. OPAMP Positive Power Supply Rejection Ratio ........................................................................................ 39
3.22. OPAMP Negative Power Supply Rejection Ratio ...................................................................................... 40
3.23. OPAMP Voltage Noise Spectral Density (Unity Gain) Vout=1V ..................................................................... 40
3.24. OPAMP Voltage Noise Spectral Density (Non-Unity Gain) .......................................................................... 40
3.25. Typical ACMP Characteristics ............................................................................................................... 42
4.1. EFM32LG330 Pinout (top view, not to scale) .............................................................................................. 45
4.2. Opamp Pinout ...................................................................................................................................... 53
4.3. QFN64 ................................................................................................................................................ 53
5.1. QFN64 PCB Land Pattern ...................................................................................................................... 55
5.2. QFN64 PCB Solder Mask ....................................................................................................................... 56
5.3. QFN64 PCB Stencil Design .................................................................................................................... 57
6.1. Example Chip Marking ........................................................................................................................... 58
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List of Tables
1.1. Ordering Information ................................................................................................................................ 2
2.1. Configuration Summary ............................................................................................................................ 7
3.1. Absolute Maximum Ratings ..................................................................................................................... 10
3.2. General Operating Conditions .................................................................................................................. 10
3.3. Environmental ....................................................................................................................................... 11
3.4. Current Consumption ............................................................................................................................. 12
3.5. Energy Modes Transitions ...................................................................................................................... 13
3.6. Power Management ............................................................................................................................... 13
3.7. Flash .................................................................................................................................................. 14
3.8. GPIO .................................................................................................................................................. 15
3.9. LFXO .................................................................................................................................................. 22
3.10. HFXO ................................................................................................................................................ 22
3.11. LFRCO .............................................................................................................................................. 23
3.12. HFRCO ............................................................................................................................................. 24
3.13. ULFRCO ............................................................................................................................................ 26
3.14. ADC .................................................................................................................................................. 26
3.15. DAC .................................................................................................................................................. 36
3.16. OPAMP ............................................................................................................................................. 37
3.17. ACMP ............................................................................................................................................... 41
3.18. VCMP ............................................................................................................................................... 43
3.19. Digital Peripherals ............................................................................................................................... 43
4.1. Device Pinout ....................................................................................................................................... 45
4.2. Alternate functionality overview ................................................................................................................ 48
4.3. GPIO Pinout ........................................................................................................................................ 52
4.4. QFN64 (Dimensions in mm) .................................................................................................................... 54
5.1. QFN64 PCB Land Pattern Dimensions (Dimensions in mm) .......................................................................... 55
5.2. QFN64 PCB Solder Mask Dimensions (Dimensions in mm) ........................................................................... 56
5.3. QFN64 PCB Stencil Design Dimensions (Dimensions in mm) ........................................................................ 57
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List of Equations
3.1. Total ACMP Active Current ..................................................................................................................... 41
3.2. VCMP Trigger Level as a Function of Level Setting ..................................................................................... 43
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相关型号：
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SILICON
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