EFM32TG108F4-D-QFN24 [SILICON]
RISC Microcontroller, 32-Bit, FLASH, 32MHz, CMOS, PQCC24, QFN-24;型号: | EFM32TG108F4-D-QFN24 |
厂家: | SILICON |
描述: | RISC Microcontroller, 32-Bit, FLASH, 32MHz, CMOS, PQCC24, QFN-24 时钟 微控制器 外围集成电路 |
文件: | 总202页 (文件大小:2966K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
EFM32 Gecko Family
EFM32TG Data Sheet
The EFM32 Gecko MCUs are the world’s most energy-friendly mi-
crocontrollers.
KEY FEATURES
• ARM Cortex-M3 at 32 MHz
The EFM32TG offers unmatched performance and ultra low power consumption in both
active and sleep modes. EFM32TG devices consume as little as 0.6 μA in Stop mode
and 150 μA/MHz in Run mode. It also features autonomous peripherals, high overall chip
and analog integration, and the performance of the industry standard 32-bit ARM Cortex-
M3 processor, making it perfect for battery-powered systems and systems with high-per-
formance, low-energy requirements.
• Ultra low power operation
• 0.6 μA current in Stop (EM3), with
brown-out detection and RAM retention
• 51 μA/MHz in EM1
• 150 μA/MHz in Run mode (EM0)
• Fast wake-up time of 2 µs
EFM32TG applications include the following:
• Hardware cryptography (AES)
• Up to 32 kB of Flash and 4 kB of RAM
• Industrial and home automation
• Smart metering
• Alarm and security systems
• Water metering
• Health and fitness applications
• Gas metering
Core / Memory
Clock Management
Energy Management
Security
High Frequency
High Frequency
Voltage
Regulator
Voltage
Comparator
Crystal Oscillator
RC Oscillator
ARM CortexTM M3 processor
Hardware AES
Auxiliary High
Freq. RC Osc.
Low Freq.
RC Oscillator
Flash Program
Memory
Debug Interface
DMA Controller
Power-on
Reset
Brown-out
Detector
Low Frequency
Crystal Oscillator
Watchdog
Oscillator
RAM Memory
32-bit bus
Peripheral Reflex System
Serial Interfaces
I/O Ports
Timers and Triggers
Analog Interfaces
Timer/Counter
Low Energy Timer
Pulse Counter
LESENSE
ADC
DAC
External
Interrupts
General
Purpose I/O
I2C
USART
Operational
Amplifier
Analog
Comparator
Real Time Counter
Watchdog Timer
Low Energy
UARTTM
Pin Reset
LCD Controller
Lowest power mode with peripheral operational:
EM0 - Active
EM2 – Deep Sleep
EM1 - Sleep
EM3 - Stop
EM4 - Shutoff
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Rev. 2.10
EFM32TG Data Sheet
Feature List
1. Feature List
• ARM Cortex-M3 CPU platform
• High Performance 32-bit processor @ up to 32 MHz
• Wake-up Interrupt Controller
• SysTick System Timer
• Flexible Energy Management System
• 20 nA @ 3 V Shutoff Mode
• 0.6 µA @ 3 V Stop Mode, including Power-on Reset, Brown-out Detector, RAM and CPU retention
• 1.0 µA @ 3 V Deep Sleep Mode, including RTC with 32.768 kHz oscillator, Power-on Reset, Brown-out Detector, RAM and CPU
retention
• 51 µA/MHz @ 3 V Sleep Mode
• 150 µA/MHz @ 3 V Run Mode, with code executed from flash
• 32/16/8 KB Flash
• 4/2 KB RAM
• Up to 56 General Purpose I/O pins
• Configurable push-pull, open-drain, pull-up/down, input filter, drive strength
• Configurable peripheral I/O locations
• 16 asynchronous external interrupts
• Output state retention and wake-up from Shutoff Mode
• 8 Channel DMA Controller
• 8 Channel Peripheral Reflex System (PRS) for autonomous inter- peripheral signaling
• Hardware AES with 128/256-bit keys in 54/75 cycles
• Timers/Counters
• 2× 16-bit Timer/Counter
• 2×3 Compare/Capture/PWM channels
• 16-bit Low Energy Timer
• 1× 24-bit Real-Time Counter
• 1× 16-bit Pulse Counter
• Watchdog Timer with dedicated RC oscillator @ 50 nA
• Integrated LCD Controller for up to 8×20 segments
• Voltage boost, adjustable contrast and autonomous animation
• Communication interfaces
• Up to 2× Universal Synchronous/Asynchronous Receiver/ Transmitter
• UART/SPI/SmartCard (ISO 7816)/IrDA/I2S
• Low Energy UART
• Autonomous operation with DMA in Deep Sleep Mode
I2C Interface with SMBus support
• Address recognition in Stop Mode
•
• Ultra low power precision analog peripherals
• 12-bit 1 Msamples/s Analog to Digital Converter
• 8 single ended channels/4 differential channels
• On-chip temperature sensor
• 12-bit 500 ksamples/s Digital to Analog Converter
• Up to 2× Analog Comparator
• Capacitive sensing with up to 8 inputs
• 3× Operational Amplifier
• 6.1 MHz GBW, Rail-to-rail, Programmable Gain
• Supply Voltage Comparator
• Low Energy Sensor Interface (LESENSE)
• Autonomous sensor monitoring in Deep Sleep Mode
• Wide range of sensors supported, including LC sensors and capacitive buttons
• Ultra efficient Power-on Reset and Brown-Out Detector
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Rev. 2.10 | 2
EFM32TG Data Sheet
Feature List
• 2-pin Serial Wire Debug interface
• 1-pin Serial Wire Viewer
• Pre-Programmed UART Bootloader
• Temperature range -40 to 85 ºC
• Single power supply 1.98 to 3.8 V
• Packages:
• BGA48
• QFN24
• QFN32
• QFN64
• TQFP48
• TQFP64
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Rev. 2.10 | 3
EFM32TG Data Sheet
Ordering Information
2. Ordering Information
The following table shows the available EFM32TG devices.
Table 2.1. Ordering Information
Max Speed
(MHz)
Supply
Voltage (V)
Temperature
Ordering Code
Flash (kB)
RAM (kB)
(ºC)
Package
QFN24
QFN24
QFN24
QFN24
QFN24
QFN24
QFN24
QFN24
QFN32
QFN32
QFN32
TQFP48
TQFP48
TQFP48
BGA48
BGA48
BGA48
QFN64
QFN64
QFN64
TQFP64
TQFP64
TQFP64
TQFP48
TQFP48
TQFP48
BGA48
BGA48
BGA48
QFN64
QFN64
QFN64
EFM32TG108F4-D-QFN24
EFM32TG108F8-D-QFN24
EFM32TG108F16-D-QFN24
EFM32TG108F32-D-QFN24
EFM32TG110F4-D-QFN24
EFM32TG110F8-D-QFN24
EFM32TG110F16-D-QFN24
EFM32TG110F32-D-QFN24
EFM32TG210F8-D-QFN32
EFM32TG210F16-D-QFN32
EFM32TG210F32-D-QFN32
EFM32TG222F8-D-QFP48
EFM32TG222F16-D-QFP48
EFM32TG222F32-D-QFP48
EFM32TG225F8-D-BGA48
EFM32TG225F16-D-BGA48
EFM32TG225F32-D-BGA48
EFM32TG230F8-D-QFN64
EFM32TG230F16-D-QFN64
EFM32TG230F32-D-QFN64
EFM32TG232F8-D-QFP64
EFM32TG232F16-D-QFP64
EFM32TG232F32-D-QFP64
EFM32TG822F8-D-QFP48
EFM32TG822F16-D-QFP48
EFM32TG822F32-D-QFP48
EFM32TG825F8-D-BGA48
EFM32TG825F16-D-BGA48
EFM32TG825F32-D-BGA48
EFM32TG840F8-D-QFN64
EFM32TG840F16-D-QFN64
EFM32TG840F32-D-QFN64
4
8
2
2
4
4
2
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
1.98 - 3.8
1.98 - 3.8
1.98 - 3.8
1.98 - 3.8
1.98 - 3.8
1.98 - 3.8
1.98 - 3.8
1.98 - 3.8
1.98 - 3.8
1.98 - 3.8
1.98 - 3.8
1.98 - 3.8
1.98 - 3.8
1.98 - 3.8
1.98 - 3.8
1.98 - 3.8
1.98 - 3.8
1.98 - 3.8
1.98 - 3.8
1.98 - 3.8
1.98 - 3.8
1.98 - 3.8
1.98 - 3.8
1.98 - 3.8
1.98 - 3.8
1.98 - 3.8
1.98 - 3.8
1.98 - 3.8
1.98 - 3.8
1.98 - 3.8
1.98 - 3.8
1.98 - 3.8
-40 - 85
-40 - 85
-40 - 85
-40 - 85
-40 - 85
-40 - 85
-40 - 85
-40 - 85
-40 - 85
-40 - 85
-40 - 85
-40 - 85
-40 - 85
-40 - 85
-40 - 85
-40 - 85
-40 - 85
-40 - 85
-40 - 85
-40 - 85
-40 - 85
-40 - 85
-40 - 85
-40 - 85
-40 - 85
-40 - 85
-40 - 85
-40 - 85
-40 - 85
-40 - 85
-40 - 85
-40 - 85
16
32
4
8
16
32
8
16
32
8
16
32
8
16
32
8
16
32
8
16
32
8
16
32
8
16
32
8
16
32
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Rev. 2.10 | 4
EFM32TG Data Sheet
Ordering Information
Max Speed
(MHz)
Supply
Voltage (V)
Temperature
Ordering Code
Flash (kB)
RAM (kB)
(ºC)
Package
TQFP64
TQFP64
TQFP64
EFM32TG842F8-D-QFP64
EFM32TG842F16-D-QFP64
EFM32TG842F32-D-QFP64
8
2
4
4
32
32
32
1.98 - 3.8
1.98 - 3.8
1.98 - 3.8
-40 - 85
-40 - 85
-40 - 85
16
32
EFM32 TG 842 F 32 – D – QFP 64 T
Tray (Optional)
Pin Count
Package
Revision
Memory Size in kB
Memory Type (Flash)
Feature Set Code
Gecko
Energy Friendly Microcontroller 32-bit
Figure 2.1. Ordering Code Decoder
Adding the suffix 'T' to the part number (e.g. EFM32TG842F32-D-QFP64T) denotes tray.
Visit http://www.silabs.com for information on global distributors and representatives.
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Rev. 2.10 | 5
Table of Contents
1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3. System Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 System Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.1.1 ARM Cortex-M3 Core . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.1.2 Debug Interface (DBG). . . . . . . . . . . . . . . . . . . . . . . . . .10
3.1.3 Memory System Controller (MSC) . . . . . . . . . . . . . . . . . . . . . .10
3.1.4 Direct Memory Access Controller (DMA) . . . . . . . . . . . . . . . . . . . .11
3.1.5 Reset Management Unit (RMU) . . . . . . . . . . . . . . . . . . . . . . .11
3.1.6 Energy Management Unit (EMU) . . . . . . . . . . . . . . . . . . . . . .11
3.1.7 Clock Management Unit (CMU) . . . . . . . . . . . . . . . . . . . . . . .11
3.1.8 Watchdog (WDOG) . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.1.9 Peripheral Reflex System (PRS) . . . . . . . . . . . . . . . . . . . . . .11
3.1.10 Inter-Integrated Circuit Interface (I2C) . . . . . . . . . . . . . . . . . . . .11
3.1.11 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) . . . . . . . . .11
3.1.12 Pre-Programmed UART Bootloader . . . . . . . . . . . . . . . . . . . . .11
3.1.13 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) . . . . . . . . .11
3.1.14 Timer/Counter (TIMER) . . . . . . . . . . . . . . . . . . . . . . . . .12
3.1.15 Real Time Counter (RTC) . . . . . . . . . . . . . . . . . . . . . . . .12
3.1.16 Low Energy Timer (LETIMER) . . . . . . . . . . . . . . . . . . . . . . .12
3.1.17 Pulse Counter (PCNT) . . . . . . . . . . . . . . . . . . . . . . . . .12
3.1.18 Analog Comparator (ACMP) . . . . . . . . . . . . . . . . . . . . . . .12
3.1.19 Voltage Comparator (VCMP) . . . . . . . . . . . . . . . . . . . . . . .12
3.1.20 Analog to Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . .12
3.1.21 Digital to Analog Converter (DAC) . . . . . . . . . . . . . . . . . . . . .12
3.1.22 Operational Amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . .12
3.1.23 Low Energy Sensor Interface (LESENSE) . . . . . . . . . . . . . . . . . . .12
3.1.24 Advanced Encryption Standard Accelerator (AES) . . . . . . . . . . . . . . . .13
3.1.25 General Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . .13
3.1.26 Liquid Crystal Display Driver (LCD) . . . . . . . . . . . . . . . . . . . . .13
3.2 Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.2.1 EFM32TG108 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.2.2 EFM32TG110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.2.3 EFM32TG210 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.2.4 EFM32TG222 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3.2.5 EFM32TG225 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.2.6 EFM32TG230 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.2.7 EFM32TG232 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3.2.8 EFM32TG822 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.2.9 EFM32TG825 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3.2.10 EFM32TG840 . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.2.11 EFM32TG842 . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
3.3 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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4.1 Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.1.1 Typical Values . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.1.2 Minimum and Maximum Values . . . . . . . . . . . . . . . . . . . . . . .27
4.2 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . .27
4.3 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . .27
4.4 Current Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . .28
4.4.1 EM2 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . .29
4.4.2 EM3 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . .29
4.4.3 EM4 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . .30
4.5 Transition between Energy Modes . . . . . . . . . . . . . . . . . . . . . . .30
4.6 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
4.7 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
4.8 General Purpose Input Output . . . . . . . . . . . . . . . . . . . . . . . . .32
4.9 Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
4.9.1 LFXO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.9.2 HFXO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.9.3 LFRCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
4.9.4 HFRCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
4.9.5 AUXHFRCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
4.9.6 ULFRCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
4.10 Analog Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . .47
4.10.1 Typical Performance . . . . . . . . . . . . . . . . . . . . . . . . . .53
4.11 Digital Analog Converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . .57
4.12 Operational Amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . .59
4.13 Analog Comparator (ACMP) . . . . . . . . . . . . . . . . . . . . . . . . .64
4.14 Voltage Comparator (VCMP) . . . . . . . . . . . . . . . . . . . . . . . . .66
4.15 LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
4.16 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
4.17 Digital Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
5. Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.1 EFM32TG108 (QFN24) . . . . . . . . . . . . . . . . . . . . . . . . . . .71
5.1.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
5.1.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . . .74
5.1.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . .76
5.2 EFM32TG110 (QFN24) . . . . . . . . . . . . . . . . . . . . . . . . . . .77
5.2.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
5.2.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . . .80
5.2.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . .82
5.2.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . .83
5.3 EFM32TG210 (QFN32) . . . . . . . . . . . . . . . . . . . . . . . . . . .84
5.3.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
5.3.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . . .87
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5.3.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . .90
5.3.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . .90
5.4 EFM32TG222 (TQFP48) . . . . . . . . . . . . . . . . . . . . . . . . . .91
5.4.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
5.4.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . . .95
5.4.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . .98
5.4.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . .98
5.5 EFM32TG225 (BGA48) . . . . . . . . . . . . . . . . . . . . . . . . . . .99
5.5.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
5.5.2 Alternate Functionality Pinout
5.5.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 106
5.5.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . .106
5.6 EFM32TG230 (QFN64) . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.6.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 07
5.6.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . 1.12
5.6.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 116
. . . . . . . . . . . . . . . . . . . . . 1.03
5.6.4 Opamp Pinout Overview
. . . . . . . . . . . . . . . . . . . . . . . .116
5.7 EFM32TG232 (TQFP64)
. . . . . . . . . . . . . . . . . . . . . . . . 1.17
5.7.1 Pinout
5.7.2 Alternate Functionality Pinout
5.7.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 126
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 17
. . . . . . . . . . . . . . . . . . . . . 1.22
5.7.4 Opamp Pinout Overview
. . . . . . . . . . . . . . . . . . . . . . . .126
5.8 EFM32TG822 (TQFP48)
. . . . . . . . . . . . . . . . . . . . . . . . 1.27
5.8.1 Pinout
5.8.2 Alternate Functionality Pinout
5.8.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 135
5.8.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . .135
5.9 EFM32TG825 (BGA48) . . . . . . . . . . . . . . . . . . . . . . . . . . 136
5.9.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 36
5.9.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . 1.40
5.9.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . . 144
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 27
. . . . . . . . . . . . . . . . . . . . . 1.31
5.9.4 Opamp Pinout Overview
. . . . . . . . . . . . . . . . . . . . . . . .144
5.10 EFM32TG840 (QFN64)
. . . . . . . . . . . . . . . . . . . . . . . . 1.45
5.10.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
5.10.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .150
5.10.3 GPIO Pinout Overview
. . . . . . . . . . . . . . . . . . . . . . . 1. 55
5.10.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 155
5.11 EFM32TG842 (TQFP64) . . . . . . . . . . . . . . . . . . . . . . . . .156
5.11.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
5.11.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .160
5.11.3 GPIO Pinout Overview
. . . . . . . . . . . . . . . . . . . . . . . 1. 65
5.11.4 Opamp Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 165
6. BGA48 Package Specifications . . . . . . . . . . . . . . . . . . . . . . 1.66
6.1 BGA48 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . .166
6.2 BGA48 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . .167
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6.3 BGA48 Package Marking
. . . . . . . . . . . . . . . . . . . . . . . . .169
7. QFN24 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . . 170
7.1 QFN24 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . .170
7.2 QFN24 PCB Layout
. . . . . . . . . . . . . . . . . . . . . . . . . . .171
. . . . . . . . . . . . . . . . . . . . . . . . .173
7.3 QFN24 Package Marking
8. QFN32 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . . 174
8.1 QFN32 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . .174
8.2 QFN32 PCB Layout
. . . . . . . . . . . . . . . . . . . . . . . . . . .175
. . . . . . . . . . . . . . . . . . . . . . . . .177
8.3 QFN32 Package Marking
9. QFN64 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . . 178
9.1 QFN64 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . .178
9.2 QFN64 PCB Layout
. . . . . . . . . . . . . . . . . . . . . . . . . . .180
. . . . . . . . . . . . . . . . . . . . . . . . .182
9.3 QFN64 Package Marking
10. TQFP48 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . 183
10.1 TQFP48 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . .183
10.2 TQFP48 PCB Layout
. . . . . . . . . . . . . . . . . . . . . . . . . .185
. . . . . . . . . . . . . . . . . . . . . . . 1. 87
10.3 TQFP48 Package Marking
11. TQFP64 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . 188
11.1 TQFP64 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . .188
11.2 TQFP64 PCB Layout
. . . . . . . . . . . . . . . . . . . . . . . . . .190
. . . . . . . . . . . . . . . . . . . . . . . 1. 92
11.3 TQFP64 Package Marking
12. Chip Revision, Solder Information, Errata . . . . . . . . . . . . . . . . . . .193
12.1 Chip Revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
12.2 Soldering Information
12.3 Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 93
13. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
. . . . . . . . . . . . . . . . . . . . . . . . . .193
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Rev. 2.10 | 9
EFM32TG Data Sheet
System Summary
3. System Summary
3.1 System Introduction
The EFM32 MCUs are the world’s most energy friendly microcontrollers. With a unique combination of the powerful 32-bit ARM Cortex-
M3, innovative low energy techniques, short wake-up time from energy saving modes, and a wide selection of peripherals, the
EFM32TG microcontroller is well suited for any battery operated application as well as other systems requiring high performance and
low-energy consumption. This section gives a short introduction to each of the modules in general terms and also shows a summary of
the configuration for the EFM32TG devices. For a complete feature set and in-depth information on the modules, refer to the .
A block diagram of the EFM32TG is shown in the following figure.
Core / Memory
Clock Management
Energy Management
Security
High Frequency
High Frequency
Voltage
Regulator
Voltage
Comparator
Crystal Oscillator
RC Oscillator
ARM CortexTM M3 processor
Hardware AES
Auxiliary High
Freq. RC Osc.
Low Freq.
RC Oscillator
Flash Program
Memory
Debug Interface
DMA Controller
Power-on
Reset
Brown-out
Detector
Low Frequency
Crystal Oscillator
Watchdog
Oscillator
RAM Memory
32-bit bus
Peripheral Reflex System
Serial Interfaces
I/O Ports
Timers and Triggers
Analog Interfaces
Timer/Counter
Low Energy Timer
Pulse Counter
LESENSE
ADC
DAC
External
Interrupts
General
Purpose I/O
I2C
USART
Operational
Amplifier
Analog
Comparator
Real Time Counter
Watchdog Timer
Low Energy
UARTTM
Pin Reset
LCD Controller
Lowest power mode with peripheral operational:
EM0 - Active
EM2 – Deep Sleep
EM1 - Sleep
EM3 - Stop
EM4 - Shutoff
Figure 3.1. Block Diagram
3.1.1 ARM Cortex-M3 Core
The ARM Cortex-M3 includes a 32-bit RISC processor which can achieve as much as 1.25 Dhrystone MIPS/MHz. A wake-up Interrupt
Controller handling interrupts triggered while the CPU is asleep. The EFM32 implementation of the Cortex-M3 is described in detail in
EFM32TG Reference Manual.
3.1.2 Debug Interface (DBG)
This device includes hardware debug support through a 2-pin serial-wire debug interface. In addition there is also a 1-wire Serial Wire
Viewer pin which can be used to output profiling information, data trace and software-generated messages.
3.1.3 Memory System Controller (MSC)
The Memory System Controller (MSC) is the program memory unit of the EFM32TG microcontroller. The flash memory is readable and
writable from both the Cortex-M3 and DMA. The flash memory is divided into two blocks; the main block and the information block.
Program code is normally written to the main block. Additionally, the information block is available for special user data and flash lock
bits. There is also a read-only page in the information block containing system and device calibration data. Read and write operations
are supported in the energy modes EM0 and EM1.
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EFM32TG Data Sheet
System Summary
3.1.4 Direct Memory Access Controller (DMA)
The Direct Memory Access (DMA) controller performs memory operations independently of the CPU. This has the benefit of reducing
the energy consumption and the workload of the CPU, and enables the system to stay in low energy modes when moving for instance
data from the USART to RAM or from the External Bus Interface to a PWM-generating timer. The DMA controller uses the PL230
µDMA controller licensed from ARM.
3.1.5 Reset Management Unit (RMU)
The RMU is responsible for handling the reset functionality of the EFM32TG.
3.1.6 Energy Management Unit (EMU)
The Energy Management Unit (EMU) manage all the low energy modes (EM) in EFM32TG microcontrollers. Each energy mode man-
ages if the CPU and the various peripherals are available. The EMU can also be used to turn off the power to unused SRAM blocks.
3.1.7 Clock Management Unit (CMU)
The Clock Management Unit (CMU) is responsible for controlling the oscillators and clocks on-board the EFM32TG. The CMU provides
the capability to turn on and off the clock on an individual basis to all peripheral modules in addition to enable/disable and configure the
available oscillators. The high degree of flexibility enables software to minimize energy consumption in any specific application by not
wasting power on peripherals and oscillators that are inactive.
3.1.8 Watchdog (WDOG)
The purpose of the watchdog timer is to generate a reset in case of a system failure, to increase application reliability. The failure may
e.g. be caused by an external event, such as an ESD pulse, or by a software failure.
3.1.9 Peripheral Reflex System (PRS)
The Peripheral Reflex System (PRS) system is a network which lets the different peripheral module communicate directly with each
other without involving the CPU. Peripheral modules which send out Reflex signals are called producers. The PRS routes these reflex
signals to consumer peripherals which apply actions depending on the data received. The format for the Reflex signals is not given, but
edge triggers and other functionality can be applied by the PRS.
3.1.10 Inter-Integrated Circuit Interface (I2C)
The I2C module provides an interface between the MCU and a serial I2C-bus. It is capable of acting as both a master and a slave, and
supports multi-master buses. Both standard-mode, fast-mode and fastmode plus speeds are supported, allowing transmission rates all
the way from 10 kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also provided to allow implementation of an SMBus compliant
system. The interface provided to software by the I2C module, allows both fine-grained control of the transmission process and close to
automatic transfers. Automatic recognition of slave addresses is provided in all energy modes.
3.1.11 Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
The Universal Synchronous Asynchronous serial Receiver and Transmitter (USART) is a very flexible serial I/O module. It supports full
duplex asynchronous UART communication as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with ISO7816 Smart-
Cards, IrDA, and I2S devices.
3.1.12 Pre-Programmed UART Bootloader
The bootloader presented in application note AN0003 is pre-programmed in the device at factory. Autobaud and destructive write are
supported. The autobaud feature, interface and commands are described further in the application note.
3.1.13 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART)
The unique LEUARTTM, the Low Energy UART, is a UART that allows two-way UART communication on a strict power budget. Only a
32.768 kHz clock is needed to allow UART communication up to 9600 baud/ s. The LEUART includes all necessary hardware support
to make asynchronous serial communication possible with minimum of software intervention and energy consumption.
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EFM32TG Data Sheet
System Summary
3.1.14 Timer/Counter (TIMER)
The 16-bit general purpose Timer has 3 compare/capture channels for input capture and compare/Pulse- Width Modulation (PWM) out-
put.
3.1.15 Real Time Counter (RTC)
The Real Time Counter (RTC) contains a 24-bit counter and is clocked either by a 32.768 kHz crystal oscillator, or a 32.768 kHz RC
oscillator. In addition to energy modes EM0 and EM1, the RTC is also available in EM2. This makes it ideal for keeping track of time
since the RTC is enabled in EM2 where most of the device is powered down.
3.1.16 Low Energy Timer (LETIMER)
The unique LETIMERTM, the Low Energy Timer, is a 16-bit timer that is available in energy mode EM2 in addition to EM1 and EM0.
Because of this, it can be used for timing and output generation when most of the device is powered down, allowing simple tasks to be
performed while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of
waveforms with minimal software intervention. It is also connected to the Real Time Counter (RTC), and can be configured to start
counting on compare matches from the RTC.
3.1.17 Pulse Counter (PCNT)
The Pulse Counter (PCNT) can be used for counting pulses on a single input or to decode quadrature encoded inputs. It runs off either
the internal LFACLK or the PCNTn_S0IN pin as external clock source. The module may operate in energy mode EM0 - EM3.
3.1.18 Analog Comparator (ACMP)
The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is high-
er. Inputs can either be one of the selectable internal references or from external pins. Response time and thereby also the current
consumption can be configured by altering the current supply to the comparator.
3.1.19 Voltage Comparator (VCMP)
The Voltage Supply Comparator is used to monitor the supply voltage from software. An interrupt can be generated when the supply
falls below or rises above a programmable threshold. Response time and thereby also the current consumption can be configured by
altering the current supply to the comparator.
3.1.20 Analog to Digital Converter (ADC)
The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to one million samples per
second. The integrated input mux can select inputs from 8 external pins and 6 internal signals.
3.1.21 Digital to Analog Converter (DAC)
The Digital to Analog Converter (DAC) can convert a digital value to an analog output voltage. The DAC is fully differential rail-to-rail,
with 12-bit resolution. It has two single-ended output buffers which can be combined into one differential output. The DAC may be used
for a number of different applications such as sensor interfaces or sound output.
3.1.22 Operational Amplifier (OPAMP)
The EFM32TG features up to three Operational Amplifiers. The Operational Amplifier is a versatile general purpose amplifier with rail-
to-rail differential input and rail-to-rail single-ended output. The input can be set to pin, DAC or OPAMP, whereas the output can be pin,
OPAMP or ADC. The current is programmable and the OPAMP has various internal configurations such as unity gain, programmable
gain using internal resistors etc.
3.1.23 Low Energy Sensor Interface (LESENSE)
The Low Energy Sensor Interface (LESENSETM), is a highly configurable sensor interface with support for up to 8 individually configu-
rable sensors. By controlling the analog comparators and DAC, LESENSE is capable of supporting a wide range of sensors and meas-
urement schemes, and can for instance measure LC sensors, resistive sensors and capacitive sensors. LESENSE also includes a pro-
grammable FSM which enables simple processing of measurement results without CPU intervention. LESENSE is available in energy
mode EM2, in addition to EM0 and EM1, making it ideal for sensor monitoring in applications with a strict energy budget.
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Rev. 2.10 | 12
EFM32TG Data Sheet
System Summary
3.1.24 Advanced Encryption Standard Accelerator (AES)
The AES accelerator performs AES encryption and decryption with 128-bit or 256-bit keys. Encrypting or decrypting one 128-bit data
block takes 52 HFCORECLK cycles with 128-bit keys and 75 HFCORECLK cycles with 256-bit keys. The AES module is an AHB slave
which enables efficient access to the data and key registers. All write accesses to the AES module must be 32-bit operations, i.e. 8- or
16-bit operations are not supported.
3.1.25 General Purpose Input/Output (GPIO)
In the EFM32TG, there are up to 56 General Purpose Input/Output (GPIO) pins, which are divided into ports with up to 16 pins each.
These pins can individually be configured as either an output or input. More advanced configurations like open-drain, filtering and drive
strength can also be configured individually for the pins. The GPIO pins can also be overridden by peripheral pin connections, like Tim-
er PWM outputs or USART communication, which can be routed to several locations on the device. The GPIO supports up to 16 asyn-
chronous external pin interrupts, which enables interrupts from any pin on the device. Also, the input value of a pin can be routed
through the Peripheral Reflex System to other peripherals.
3.1.26 Liquid Crystal Display Driver (LCD)
The LCD driver is capable of driving a segmented LCD display with up to 8x20 segments. A voltage boost function enables it to provide
the LCD display with higher voltage than the supply voltage for the device. In addition, an animation feature can run custom animations
on the LCD display without any CPU intervention. The LCD driver can also remain active even in Energy Mode 2 and provides a Frame
Counter interrupt that can wake-up the device on a regular basis for updating data.
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Rev. 2.10 | 13
EFM32TG Data Sheet
System Summary
3.2 Configuration Summary
3.2.1 EFM32TG108
The features of the EFM32TG108 is a subset of the feature set described in the EFM32TG Reference Manual. The following table de-
scribes device specific implementation of the features.
Table 3.1. EFM32TG108 Configuration Summary
Module
Cortex-M3
DBG
Configuration
Pin Connections
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration with I2S
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration, 16-bit count register
Full configuration
Full configuration
Full configuration
17 pins
NA
DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC
NA
DMA
NA
RMU
NA
EMU
NA
CMU
CMU_OUT0, CMU_OUT1
WDOG
PRS
NA
NA
I2C0
I2C0_SDA, I2C0_SCL
USART1
LEUART0
TIMER0
TIMER1
RTC
US1_TX, US1_RX, US1_CLK, US1_CS
LEU0_TX, LEU0_RX
TIM0_CC[2:0]
TIM1_CC[2:0]
NA
LETIMER0
PCNT0
ACMP0
ACMP1
VCMP
GPIO
LET0_O[1:0]
PCNT0_S[1:0]
ACMP0_CH[1:0], ACMP0_O
ACMP1_CH[1:0], ACMP1_O
NA
Available pins are shown in 5.1.3 GPIO Pinout Overview
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Rev. 2.10 | 14
EFM32TG Data Sheet
System Summary
3.2.2 EFM32TG110
The features of the EFM32TG110 is a subset of the feature set described in the EFM32TG Reference Manual. The following table de-
scribes device specific implementation of the features.
Table 3.2. EFM32TG110 Configuration Summary
Module
Cortex-M3
DBG
Configuration
Pin Connections
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration with IrDA
Full configuration with I2S
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration, 16-bit count register
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
NA
DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC
NA
DMA
NA
RMU
NA
EMU
NA
CMU
CMU_OUT0, CMU_OUT1
NA
WDOG
PRS
NA
I2C0
I2C0_SDA, I2C0_SCL
US0_TX, US0_RX. US0_CLK, US0_CS
US1_TX, US1_RX, US1_CLK, US1_CS
LEU0_TX, LEU0_RX
TIM0_CC[2:0]
USART0
USART1
LEUART0
TIMER0
TIMER1
RTC
TIM1_CC[2:0]
NA
LETIMER0
PCNT0
ACMP0
ACMP1
VCMP
ADC0
LET0_O[1:0]
PCNT0_S[1:0]
ACMP0_CH[1:0], ACMP0_O
ACMP1_CH[1:0], ACMP1_O
NA
ADC0_CH[7:6]
DAC0
DAC0_OUT[0], DAC0_OUTxALT
OPAMP
Outputs: OPAMP_OUT0, OPAMP_OUT0ALT, OPAMP_OUT1ALT, In-
puts: OPAMP_P1, OPAMP_N1
AES
Full configuration
17 pins
NA
GPIO
Available pins are shown in 5.2.3 GPIO Pinout Overview
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Rev. 2.10 | 15
EFM32TG Data Sheet
System Summary
3.2.3 EFM32TG210
The features of the EFM32TG210 is a subset of the feature set described in the EFM32TG Reference Manual. The following table de-
scribes device specific implementation of the features.
Table 3.3. EFM32TG210 Configuration Summary
Module
Cortex-M3
DBG
Configuration
Pin Connections
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration with IrDA
Full configuration with I2S
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration, 16-bit count register
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
NA
DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC
NA
DMA
NA
RMU
NA
EMU
NA
CMU
CMU_OUT0, CMU_OUT1
NA
WDOG
PRS
NA
I2C0
I2C0_SDA, I2C0_SCL
US0_TX, US0_RX. US0_CLK, US0_CS
US1_TX, US1_RX, US1_CLK, US1_CS
LEU0_TX, LEU0_RX
TIM0_CC[2:0]
USART0
USART1
LEUART0
TIMER0
TIMER1
RTC
TIM1_CC[2:0]
NA
LETIMER0
PCNT0
ACMP0
ACMP1
VCMP
ADC0
LET0_O[1:0]
PCNT0_S[1:0]
ACMP0_CH[1:0], ACMP0_O
ACMP1_CH[7:5], ACMP1_O
NA
ADC0_CH[7:4]
DAC0
DAC0_OUT[0], DAC0_OUTxALT
OPAMP
Outputs: OPAMP_OUT0, OPAMP_OUT0ALT, OPAMP_OUT1ALT,
OPAMP_OUT2, Inputs: OPAMP_P1, OPAMP_N1, OPAMP_P2
AES
Full configuration
24 pins
NA
GPIO
Available pins are shown in 5.3.3 GPIO Pinout Overview
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Rev. 2.10 | 16
EFM32TG Data Sheet
System Summary
3.2.4 EFM32TG222
The features of the EFM32TG222 is a subset of the feature set described in the EFM32TG Reference Manual. The following table de-
scribes device specific implementation of the features.
Table 3.4. EFM32TG222 Configuration Summary
Module
Cortex-M3
DBG
Configuration
Pin Connections
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration with IrDA
Full configuration with I2S
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration, 16-bit count register
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
NA
DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC
NA
DMA
NA
RMU
NA
EMU
NA
CMU
CMU_OUT0, CMU_OUT1
NA
WDOG
PRS
NA
I2C0
I2C0_SDA, I2C0_SCL
US0_TX, US0_RX. US0_CLK, US0_CS
US1_TX, US1_RX, US1_CLK, US1_CS
LEU0_TX, LEU0_RX
TIM0_CC[2:0]
USART0
USART1
LEUART0
TIMER0
TIMER1
RTC
TIM1_CC[2:0]
NA
LETIMER0
PCNT0
ACMP0
ACMP1
VCMP
ADC0
LET0_O[1:0]
PCNT0_S[1:0]
ACMP0_CH[4:0], ACMP0_O
ACMP1_CH[7:0], ACMP1_O
NA
ADC0_CH[7:4]
DAC0
DAC0_OUT[1], DAC0_OUTxALT
OPAMP
Outputs: OPAMP_OUT0, OPAMP_OUT0ALT, OPAMP_OUT1ALT,
OPAMP_OUT2, Inputs: OPAMP_P0, OPAMP_P1, OPAMP_N1,
OPAMP_P2
AES
Full configuration
37 pins
NA
GPIO
Available pins are shown in 5.4.3 GPIO Pinout Overview
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Rev. 2.10 | 17
EFM32TG Data Sheet
System Summary
3.2.5 EFM32TG225
The features of the EFM32TG225 is a subset of the feature set described in the EFM32TG Reference Manual. The following table de-
scribes device specific implementation of the features.
Table 3.5. EFM32TG225 Configuration Summary
Module
Cortex-M3
DBG
Configuration
Pin Connections
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration with IrDA
Full configuration with I2S
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration, 16-bit count register
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
NA
DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC
NA
DMA
NA
RMU
NA
EMU
NA
CMU
CMU_OUT0, CMU_OUT1
NA
WDOG
PRS
NA
I2C0
I2C0_SDA, I2C0_SCL
US0_TX, US0_RX. US0_CLK, US0_CS
US1_TX, US1_RX, US1_CLK, US1_CS
LEU0_TX, LEU0_RX
TIM0_CC[2:0]
USART0
USART1
LEUART0
TIMER0
TIMER1
RTC
TIM1_CC[2:0]
NA
LETIMER0
PCNT0
ACMP0
ACMP1
VCMP
ADC0
LET0_O[1:0]
PCNT0_S[1:0]
ACMP0_CH[3:0], ACMP0_O
ACMP1_CH[7:0], ACMP1_O
NA
ADC0_CH[7:4]
DAC0
DAC0_OUT[0], DAC0_OUTxALT
OPAMP
Outputs: OPAMP_OUT0, OPAMP_OUT0ALT, OPAMP_OUT1ALT,
OPAMP_OUT2, Inputs: OPAMP_P0, OPAMP_P1, OPAMP_N1,
OPAMP_P2
AES
Full configuration
37 pins
NA
GPIO
Available pins are shown in 5.5.3 GPIO Pinout Overview
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Rev. 2.10 | 18
EFM32TG Data Sheet
System Summary
3.2.6 EFM32TG230
The features of the EFM32TG230 is a subset of the feature set described in the EFM32TG Reference Manual. The following table de-
scribes device specific implementation of the features.
Table 3.6. EFM32TG230 Configuration Summary
Module
Cortex-M3
DBG
Configuration
Pin Connections
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration with IrDA
Full configuration with I2S
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration, 16-bit count register
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
NA
DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC
NA
DMA
NA
RMU
NA
EMU
NA
CMU
CMU_OUT0, CMU_OUT1
NA
WDOG
PRS
NA
I2C0
I2C0_SDA, I2C0_SCL
US0_TX, US0_RX. US0_CLK, US0_CS
US1_TX, US1_RX, US1_CLK, US1_CS
LEU0_TX, LEU0_RX
TIM0_CC[2:0]
USART0
USART1
LEUART0
TIMER0
TIMER1
RTC
TIM1_CC[2:0]
NA
LETIMER0
PCNT0
ACMP0
ACMP1
VCMP
ADC0
LET0_O[1:0]
PCNT0_S[1:0]
ACMP0_CH[7:0], ACMP0_O
ACMP1_CH[7:0], ACMP1_O
NA
ADC0_CH[7:0]
DAC0
DAC0_OUT[1:0], DAC0_OUTxALT
OPAMP
Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px,
OPAMP_Nx
AES
Full configuration
56 pins
NA
GPIO
Available pins are shown in 5.6.3 GPIO Pinout Overview
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Rev. 2.10 | 19
EFM32TG Data Sheet
System Summary
3.2.7 EFM32TG232
The features of the EFM32TG232 is a subset of the feature set described in the EFM32TG Reference Manual. The following table de-
scribes device specific implementation of the features.
Table 3.7. EFM32TG232 Configuration Summary
Module
Cortex-M3
DBG
Configuration
Pin Connections
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration with IrDA
Full configuration with I2S
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration, 16-bit count register
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
NA
DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC
NA
DMA
NA
RMU
NA
EMU
NA
CMU
CMU_OUT0, CMU_OUT1
NA
WDOG
PRS
NA
I2C0
I2C0_SDA, I2C0_SCL
US0_TX, US0_RX. US0_CLK, US0_CS
US1_TX, US1_RX, US1_CLK, US1_CS
LEU0_TX, LEU0_RX
TIM0_CC[2:0]
USART0
USART1
LEUART0
TIMER0
TIMER1
RTC
TIM1_CC[2:0]
NA
LETIMER0
PCNT0
ACMP0
ACMP1
VCMP
ADC0
LET0_O[1:0]
PCNT0_S[1:0]
ACMP0_CH[7:0], ACMP0_O
ACMP1_CH[7:0], ACMP1_O
NA
ADC0_CH[7:0]
DAC0
DAC0_OUT[0], DAC0_OUTxALT
OPAMP
Outputs: OPAMP_OUTx, OPAMP_OUTxALT, Inputs: OPAMP_Px,
OPAMP_Nx
AES
Full configuration
53 pins
NA
GPIO
Available pins are shown in 5.7.3 GPIO Pinout Overview
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Rev. 2.10 | 20
EFM32TG Data Sheet
System Summary
3.2.8 EFM32TG822
The features of the EFM32TG822 is a subset of the feature set described in the EFM32TG Reference Manual. The following table de-
scribes device specific implementation of the features.
Table 3.8. EFM32TG822 Configuration Summary
Module
Cortex-M3
DBG
Configuration
Pin Connections
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration with IrDA
Full configuration with I2S
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration, 16-bit count register
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
NA
DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC
NA
DMA
NA
RMU
NA
EMU
NA
CMU
CMU_OUT0, CMU_OUT1
NA
WDOG
PRS
NA
I2C0
I2C0_SDA, I2C0_SCL
US0_TX, US0_RX. US0_CLK, US0_CS
US1_TX, US1_RX, US1_CLK, US1_CS
LEU0_TX, LEU0_RX
TIM0_CC[2:0]
USART0
USART1
LEUART0
TIMER0
TIMER1
RTC
TIM1_CC[2:0]
NA
LETIMER0
PCNT0
ACMP0
ACMP1
VCMP
ADC0
LET0_O[1:0]
PCNT0_S[1:0]
ACMP0_CH[4], ACMP0_O
ACMP1_CH[7:5], ACMP1_O
NA
ADC0_CH[7:4]
DAC0
DAC0_OUT[0], DAC0_OUTxALT
OPAMP
Outputs: OPAMP_OUT0, OPAMP_OUT1ALT, OPAMP_OUT2, Inputs:
OPAMP_P0, OPAMP_P1, OPAMP_N1, OPAMP_P2
AES
GPIO
LCD
Full configuration
37 pins
NA
Available pins are shown in 5.8.3 GPIO Pinout Overview
Full configuration
LCD_SEG[10:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N,
LCD_BEXT
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Rev. 2.10 | 21
EFM32TG Data Sheet
System Summary
3.2.9 EFM32TG825
The features of the EFM32TG825 is a subset of the feature set described in the EFM32TG Reference Manual. The following table de-
scribes device specific implementation of the features.
Table 3.9. EFM32TG825 Configuration Summary
Module
Cortex-M3
DBG
Configuration
Pin Connections
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration with IrDA
Full configuration with I2S
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration, 16-bit count register
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
NA
DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC
NA
DMA
NA
RMU
NA
EMU
NA
CMU
CMU_OUT0, CMU_OUT1
NA
WDOG
PRS
NA
I2C0
I2C0_SDA, I2C0_SCL
US0_TX, US0_RX. US0_CLK, US0_CS
US1_TX, US1_RX, US1_CLK, US1_CS
LEU0_TX, LEU0_RX
TIM0_CC[2:0]
USART0
USART1
LEUART0
TIMER0
TIMER1
RTC
TIM1_CC[2:0]
NA
LETIMER0
PCNT0
ACMP0
ACMP1
VCMP
ADC0
LET0_O[1:0]
PCNT0_S[1:0]
ACMP0_CH[4], ACMP0_O
ACMP1_CH[7:5], ACMP1_O
NA
ADC0_CH[7:4]
DAC0
DAC0_OUT[0], DAC0_OUTxALT
OPAMP
Outputs: OPAMP_OUT0, OPAMP_OUT1ALT, OPAMP_OUT2, Inputs:
OPAMP_P0, OPAMP_P1, OPAMP_N1, OPAMP_P2
AES
GPIO
LCD
Full configuration
37 pins
NA
Available pins are shown in 5.9.3 GPIO Pinout Overview
Full configuration
LCD_SEG[10:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N,
LCD_BEXT
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Rev. 2.10 | 22
EFM32TG Data Sheet
System Summary
3.2.10 EFM32TG840
The features of the EFM32TG840 is a subset of the feature set described in the EFM32TG Reference Manual. The following table de-
scribes device specific implementation of the features.
Table 3.10. EFM32TG840 Configuration Summary
Module
Cortex-M3
DBG
Configuration
Pin Connections
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration with IrDA
Full configuration with I2S
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration, 16-bit count register
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
NA
DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC
NA
DMA
NA
RMU
NA
EMU
NA
CMU
CMU_OUT0, CMU_OUT1
NA
WDOG
PRS
NA
I2C0
I2C0_SDA, I2C0_SCL
US0_TX, US0_RX. US0_CLK, US0_CS
US1_TX, US1_RX, US1_CLK, US1_CS
LEU0_TX, LEU0_RX
TIM0_CC[2:0]
USART0
USART1
LEUART0
TIMER0
TIMER1
RTC
TIM1_CC[2:0]
NA
LETIMER0
PCNT0
ACMP0
ACMP1
VCMP
ADC0
LET0_O[1:0]
PCNT0_S[1:0]
ACMP0_CH[7:4], ACMP0_O
ACMP1_CH[7:4], ACMP1_O
NA
ADC0_CH[7:0]
DAC0
DAC0_OUT[0], DAC0_OUTxALT
OPAMP
Outputs: OPAMP_OUT0, OPAMP_OUT0ALT, OPAMP_OUT1ALT,
OPAMP_OUT2, Inputs: OPAMP_Px, OPAMP_Nx
AES
GPIO
LCD
Full configuration
56 pins
NA
Available pins are shown in 5.10.3 GPIO Pinout Overview
Full configuration
LCD_SEG[19:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N,
LCD_BEXT
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Rev. 2.10 | 23
EFM32TG Data Sheet
System Summary
3.2.11 EFM32TG842
The features of the EFM32TG842 is a subset of the feature set described in the EFM32TG Reference Manual. The following table de-
scribes device specific implementation of the features.
Table 3.11. EFM32TG842 Configuration Summary
Module
Cortex-M3
DBG
Configuration
Pin Connections
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration with IrDA
Full configuration with I2S
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration, 16-bit count register
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
NA
DBG_SWCLK, DBG_SWDIO, DBG_SWO
MSC
NA
DMA
NA
RMU
NA
EMU
NA
CMU
CMU_OUT0, CMU_OUT1
NA
WDOG
PRS
NA
I2C0
I2C0_SDA, I2C0_SCL
US0_TX, US0_RX. US0_CLK, US0_CS
US1_TX, US1_RX, US1_CLK, US1_CS
LEU0_TX, LEU0_RX
TIM0_CC[2:0]
USART0
USART1
LEUART0
TIMER0
TIMER1
RTC
TIM1_CC[2:0]
NA
LETIMER0
PCNT0
ACMP0
ACMP1
VCMP
ADC0
LET0_O[1:0]
PCNT0_S[1:0]
ACMP0_CH[7:4], ACMP0_O
ACMP1_CH[7:4], ACMP1_O
NA
ADC0_CH[7:0]
DAC0
DAC0_OUT[0], DAC0_OUTxALT
OPAMP
Outputs: OPAMP_OUT0, OPAMP_OUT0ALT, OPAMP_OUT1ALT,
OPAMP_OUT2, Inputs: OPAMP_Px, OPAMP_Nx
AES
GPIO
LCD
Full configuration
53 pins
NA
Available pins are shown in 5.11.3 GPIO Pinout Overview
Full configuration
LCD_SEG[17:0], LCD_COM[7:0], LCD_BCAP_P, LCD_BCAP_N,
LCD_BEXT
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Rev. 2.10 | 24
EFM32TG Data Sheet
System Summary
3.3 Memory Map
The EFM32TG memory map is shown in the following figure, with RAM and Flash sizes for the largest memory configuration.
Figure 3.2. System Address Space with Core and Code Space Listing
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Rev. 2.10 | 25
EFM32TG Data Sheet
System Summary
Figure 3.3. System Address Space with Peripheral Listing
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Rev. 2.10 | 26
EFM32TG Data Sheet
Electrical Characteristics
4. Electrical Characteristics
4.1 Test Conditions
4.1.1 Typical Values
The typical data are based on TAMB=25°C and VDD=3.0 V, as defined in 4.3 General Operating Conditions, unless otherwise specified.
4.1.2 Minimum and Maximum Values
The minimum and maximum values represent the worst conditions of ambient temperature, supply voltage and frequencies, as defined
in 4.3 General Operating Conditions, unless otherwise specified.
4.2 Absolute Maximum Ratings
The absolute maximum ratings are stress ratings, and functional operation under such conditions are not guaranteed. Stress beyond
the limits specified in the following table may affect the device reliability or cause permanent damage to the device. Functional operat-
ing conditions are given in 4.3 General Operating Conditions.
Table 4.1. Absolute Maximum Ratings
Parameter
Symbol
TSTG
TS
Test Condition
Min
-40
—
Typ
—
Max
150
260
Unit
°C
Storage temperature range
Maximum soldering temperature
Latest IPC/JEDEC J-
STD-020 Standard
—
°C
External main supply voltage
Voltage on any I/O pin
VDDMAX
0
-0.3
—
—
—
—
—
3.8
VDD+0.3
100
V
V
VIOPIN
Current per I/O pin (sink)
Current per I/O pin (source)
IIOMAX_SINK
IIOMAX_SOURCE
mA
mA
—
-100
4.3 General Operating Conditions
Table 4.2. General Operating Conditions
Parameter
Symbol
TAMB
VDDOP
fAPB
Min
-40
1.98
—
Typ
Max
85
Unit
°C
Ambient temperature range
Operating supply voltage
Internal APB clock frequency
Internal AHB clock frequency
—
—
—
—
3.8
32
V
MHz
MHz
fAHB
—
32
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Rev. 2.10 | 27
EFM32TG Data Sheet
Electrical Characteristics
4.4 Current Consumption
Table 4.3. Current Consumption
Parameter
Symbol Test Condition
Min
Typ
Max
Unit
32 MHz HFXO, all peripheral clocks disa-
bled, VDD= 3.0 V
—
157
—
µA/MHz
28 MHz HFRCO, all peripheral clocks disa-
bled, VDD= 3.0 V
—
—
—
—
—
—
—
—
—
—
—
—
—
—
150
153
155
157
162
200
53
170
172
175
178
183
240
—
µA/MHz
µA/MHz
µA/MHz
µA/MHz
µA/MHz
µA/MHz
µA/MHz
µA/MHz
µA/MHz
µA/MHz
µA/MHz
µA/MHz
µA/MHz
µA
21 MHz HFRCO, all peripheral clocks disa-
bled, VDD= 3.0 V
EM0 current. No prescaling.
Running prime number calcula-
tion code from Flash. (Produc-
tion test condition = 14 MHz)
14 MHz HFRCO, all peripheral clocks disa-
bled, VDD= 3.0 V
IEM0
11 MHz HFRCO, all peripheral clocks disa-
bled, VDD= 3.0 V
6.6 MHz HFRCO, all peripheral clocks disa-
bled, VDD= 3.0 V
1.2 MHz HFRCO, all peripheral clocks disa-
bled, VDD= 3.0 V
32 MHz HFXO, all peripheral clocks disa-
bled, VDD= 3.0 V
28 MHz HFRCO, all peripheral clocks disa-
bled, VDD= 3.0 V
51
57
21 MHz HFRCO, all peripheral clocks disa-
bled, VDD= 3.0 V
55
59
14 MHz HFRCO, all peripheral clocks disa-
bled, VDD= 3.0 V
56
61
EM1 current (Production test
condition = 14 MHz)
IEM1
11 MHz HFRCO, all peripheral clocks disa-
bled, VDD= 3.0 V
58
63
6.6 MHz HFRCO, all peripheral clocks disa-
bled, VDD= 3.0 V
63
68
1.2 MHz HFRCO. all peripheral clocks disa-
bled, VDD= 3.0 V
100
1.0
122
1.2
EM2 current with RTC prescaled to 1 Hz,
32.768 kHz LFRCO, VDD= 3.0 V,
TAMB=25ºC
IEM2
EM2 current
EM2 current with RTC prescaled to 1 Hz,
32.768 kHz LFRCO, VDD= 3.0 V,
TAMB=85ºC
—
2.4
5.0
µA
VDD= 3.0 V, TAMB=25ºC
VDD= 3.0 V, TAMB=85ºC
VDD= 3.0 V, TAMB=25ºC
VDD= 3.0 V, TAMB=85ºC
—
—
—
—
0.59
2.0
1.0
4.5
µA
µA
µA
µA
IEM3
EM3 current
EM4 current
0.02
0.25
0.055
0.70
IEM4
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Rev. 2.10 | 28
EFM32TG Data Sheet
Electrical Characteristics
4.4.1 EM2 Current Consumption
Figure 4.1. EM2 Current Consumption, RTC prescaled to 1 kHz, 32.768 kHz LFRCO
4.4.2 EM3 Current Consumption
Figure 4.2. EM3 Current Consumption
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Rev. 2.10 | 29
EFM32TG Data Sheet
Electrical Characteristics
4.4.3 EM4 Current Consumption
Figure 4.3. EM4 Current Consumption
4.5 Transition between Energy Modes
The transition times are measured from the trigger to the first clock edge in the CPU.
Table 4.4. Energy Modes Transitions
Parameter
Symbol
tEM10
Min
—
Typ
0
Max
—
Unit
Transition time from EM1 to EM0
Transition time from EM2 to EM0
Transition time from EM3 to EM0
Transition time from EM4 to EM0
HFCORECLK cycles
tEM20
—
2
—
µs
µs
µs
tEM30
—
2
—
tEM40
—
163
—
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Rev. 2.10 | 30
EFM32TG Data Sheet
Electrical Characteristics
4.6 Power Management
The EFM32TG requires the AVDD_x, VDD_DREG and IOVDD_x pins to be connected together (with optional filter) at the PCB level.
For practical schematic recommendations, please see the application note, AN0002 EFM32 Hardware Design Considerations.
Table 4.5. Power Management
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
BOD threshold on falling exter- VBODextthr-
nal supply voltage
1.74
—
1.96
V
BOD threshold on rising exter-
nal supply voltage
VBODextthr+
—
—
1.85
—
1.98
1.98
V
V
Power-on Reset (POR) thresh- VPORthr+
old on rising external supply
voltage
Delay from reset is released un- tRESET
til program execution starts
Applies to Power-on Reset, Brown-
out Reset and pin reset.
—
—
163
1
—
—
µs
Voltage regulator decoupling
capacitor.
CDECOUPLE
X5R capacitor recommended. Apply
between DECOUPLE pin and
GROUND
µF
4.7 Flash
Table 4.6. Flash
Test Condition
Parameter
Symbol
Min
Typ
Max
Unit
Flash erase cycles before fail-
ure
ECFLASH
20000
—
—
cycles
21
Flash word write cycles be-
tween erase
WWCFLASH
—
—
cycles
TAMB<150ºC
TAMB<85ºC
TAMB<70ºC
10000
10
—
—
—
—
h
years
years
µs
RETFLASH
Flash data retention
20
—
—
Word (32-bit) programming time tW_PROG
20
—
—
Page erase time
Device erase time
Erase current
tP_ERASE
tD_ERASE
IERASE
20
20.4
40.8
—
20.8
41.6
ms
40
ms
72
—
mA
mA
V
72
Write current
IWRITE
—
—
Supply voltage during flash
erase and write
VFLASH
1.98
—
3.8
Note:
1. There is a maximum of two writes to the same word between each erase due to a physical limitation of the flash. No bit should be
written to ‘0’ more than once between erases. To write a word twice between erases, any bit written to ‘0’ by the first write should
be written to ‘1’ by the second write. This preserves the specified flash write/erase endurance and does not change the ‘0’ written
by the first write.
2. Measured at 25°C
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Rev. 2.10 | 31
EFM32TG Data Sheet
Electrical Characteristics
4.8 General Purpose Input Output
Table 4.7. GPIO
Parameter
Symbol Test Condition
VIOIL
Min
—
Typ
—
Max
0.30×VDD
—
Unit
V
Input low voltage
Input high voltage
VIOIH
0.70×VDD
—
—
V
Sourcing 0.1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE = LOW-
EST
0.80×VDD
—
V
Sourcing 0.1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE = LOW-
EST
—
0.90×VDD
—
V
Sourcing 1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE = LOW
—
—
0.85×VDD
0.90×VDD
—
—
—
—
V
V
V
Sourcing 1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE = LOW
Output high voltage (Produc-
tion test condition = 3.0V,
DRIVEMODE = STANDARD)
VIOOH
Sourcing 6 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE =
STANDARD
0.75×VDD
Sourcing 6 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE =
STANDARD
0.85×VDD
—
—
V
Sourcing 20 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE = HIGH
0.60×VDD
0.80×VDD
—
—
—
—
—
—
V
V
V
Sourcing 20 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE = HIGH
Sinking 0.1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE = LOW-
EST
0.20×VDD
Sinking 0.1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE = LOW-
EST
—
0.10×VDD
—
V
Sinking 1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE = LOW
—
—
—
0.10×VDD
0.05×VDD
—
—
—
V
V
V
Sinking 1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE = LOW
Output low voltage (Produc-
tion test condition = 3.0V,
DRIVEMODE = STANDARD)
VIOOL
Sinking 6 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE =
STANDARD
0.30×VDD
Sinking 6 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE =
STANDARD
—
—
0.20×VDD
V
Sinking 20 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE = HIGH
—
—
—
—
0.35×VDD
0.20×VDD
V
V
Sinking 20 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE = HIGH
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Rev. 2.10 | 32
EFM32TG Data Sheet
Electrical Characteristics
Parameter
Symbol Test Condition
Min
Typ
Max
Unit
Input leakage current
IIOLEAK
High Impedance IO connected to
—
±0.1
±100
nA
GROUND or VDD
I/O pin pull-up resistor
RPU
—
—
—
10
40
40
—
—
—
50
kΩ
kΩ
Ω
I/O pin pull-down resistor
Internal ESD series resistor
RPD
RIOESD
200
—
Pulse width of pulses to be re- tIO-
moved by the glitch suppres-
ns
GLITCH
sion filter
tIOOF
GPIO_Px_CTRL DRIVEMODE = LOW-
EST and load capacitance
CL=12.5-25pF.
20+0.1×CL
—
250
ns
Output fall time
GPIO_Px_CTRL DRIVEMODE = LOW
and load capacitance CL=350-600pF
20+0.1×CL
0.1×VDD
—
—
250
—
ns
V
I/O pin hysteresis (VIOTHR+
-
VIOHYST VDD = 1.98 - 3.8 V
VIOTHR-
)
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Rev. 2.10 | 33
EFM32TG Data Sheet
Electrical Characteristics
GPIO_Px_CTRL DRIVEMODE = LOWEST
GPIO_Px_CTRL DRIVEMODE = LOW
0.20
0.15
0.10
0.05
0.00
5
4
3
2
1
-40°C
25°C
85°C
-40°C
25°C
85°C
0
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
Low-Level Output Voltage [V]
Low-Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
GPIO_Px_CTRL DRIVEMODE = HIGH
20
15
10
5
45
40
35
30
25
20
15
10
5
-40°C
-40°C
25°C
85°C
25°C
85°C
0
0
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
Low-Level Output Voltage [V]
Low-Level Output Voltage [V]
Figure 4.4. Typical Low-Level Output Current, 2V Supply Voltage
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Rev. 2.10 | 34
EFM32TG Data Sheet
Electrical Characteristics
GPIO_Px_CTRL DRIVEMODE = LOWEST
GPIO_Px_CTRL DRIVEMODE = LOW
0.00
–0.05
–0.10
–0.15
–0.20
0.0
–0.5
–1.0
–1.5
–2.0
–2.5
-40°C
25°C
85°C
-40°C
25°C
85°C
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
High-Level Output Voltage [V]
High-Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
GPIO_Px_CTRL DRIVEMODE = HIGH
0
0
-40°C
25°C
85°C
-40°C
25°C
85°C
–10
–5
–20
–30
–40
–50
–10
–15
–20
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
High-Level Output Voltage [V]
High-Level Output Voltage [V]
Figure 4.5. Typical High-Level Output Current, 2 V Supply Voltage
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Rev. 2.10 | 35
EFM32TG Data Sheet
Electrical Characteristics
GPIO_Px_CTRL DRIVEMODE = LOWEST
GPIO_Px_CTRL DRIVEMODE = LOW
0.5
0.4
0.3
0.2
0.1
0.0
10
8
6
4
2
-40°C
25°C
85°C
-40°C
25°C
85°C
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Low-Level Output Voltage [V]
Low-Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
GPIO_Px_CTRL DRIVEMODE = HIGH
40
35
30
25
20
15
10
5
50
40
30
20
10
0
-40°C
-40°C
25°C
85°C
25°C
85°C
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Low-Level Output Voltage [V]
Low-Level Output Voltage [V]
Figure 4.6. Typical Low-Level Output Current, 3 V Supply Voltage
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Rev. 2.10 | 36
EFM32TG Data Sheet
Electrical Characteristics
GPIO_Px_CTRL DRIVEMODE = LOWEST
GPIO_Px_CTRL DRIVEMODE = LOW
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
0
-40°C
25°C
85°C
-40°C
25°C
85°C
–1
–2
–3
–4
–5
–6
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
High-Level Output Voltage [V]
High-Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
GPIO_Px_CTRL DRIVEMODE = HIGH
0
0
-40°C
25°C
85°C
-40°C
25°C
85°C
–10
–10
–20
–30
–40
–50
–20
–30
–40
–50
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
High-Level Output Voltage [V]
High-Level Output Voltage [V]
Figure 4.7. Typical High-Level Output Current, 3 V Supply Voltage
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Rev. 2.10 | 37
EFM32TG Data Sheet
Electrical Characteristics
GPIO_Px_CTRL DRIVEMODE = LOWEST
GPIO_Px_CTRL DRIVEMODE = LOW
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
14
12
10
8
6
4
2
-40°C
25°C
85°C
-40°C
25°C
85°C
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Low-Level Output Voltage [V]
Low-Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
GPIO_Px_CTRL DRIVEMODE = HIGH
50
40
30
20
10
0
50
40
30
20
10
0
-40°C
-40°C
25°C
85°C
25°C
85°C
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Low-Level Output Voltage [V]
Low-Level Output Voltage [V]
Figure 4.8. Typical Low-Level Output Current, 3.8 V Supply Voltage
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Rev. 2.10 | 38
EFM32TG Data Sheet
Electrical Characteristics
GPIO_Px_CTRL DRIVEMODE = LOWEST
GPIO_Px_CTRL DRIVEMODE = LOW
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
0
-40°C
25°C
85°C
-40°C
25°C
85°C
–1
–2
–3
–4
–5
–6
–7
–8
–9
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
High-Level Output Voltage [V]
High-Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
GPIO_Px_CTRL DRIVEMODE = HIGH
0
0
-40°C
25°C
85°C
-40°C
25°C
85°C
–10
–10
–20
–30
–40
–50
–20
–30
–40
–50
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
High-Level Output Voltage [V]
High-Level Output Voltage [V]
Figure 4.9. Typical High-Level Output Current, 3.8 V Supply Voltage
4.9 Oscillators
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Rev. 2.10 | 39
EFM32TG Data Sheet
Electrical Characteristics
4.9.1 LFXO
Parameter
Table 4.8. LFXO
Symbol
Test Condition
Min
Typ
Max
Unit
Supported nominal crystal
frequency
fLFXO
—
32.768
—
kHz
Supported crystal equivalent ESRLFXO
series resistance (ESR)
—
30
—
120
25
—
kΩ
pF
nA
ms
X1
—
Supported crystal external
load range
CLFXOL
Current consumption for core ILFXO
and buffer after startup.
ESR=30 kOhm, CL=10 pF, LFXO-
BOOST in CMU_CTRL is 1
190
400
Start- up time.
tLFXO
ESR=30 kOhm, CL=10 pF, 40% - 60%
duty cycle has been reached, LFXO-
BOOST in CMU_CTRL is 1
—
—
Note:
1. See Minimum Load Capacitance (CLFXOL) Requirement For Safe Crystal Startup in Configurator in Simplicity Studio.
For safe startup of a given crystal, the Configurator tool in Simplicity Studio contains a tool to help users configure both load capaci-
tance and software settings for using the LFXO. For details regarding the crystal configuration, the reader is referred to application note
AN0016 EFM32 Oscillator Design Consideration.
4.9.2 HFXO
Table 4.9. HFXO
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Supported nominal crystal
Frequency
fHFXO
4
—
32
MHz
ESRHFXO
Crystal frequency 32 MHz
Crystal frequency 4 MHz
—
—
20
30
400
—
60
1500
—
Ω
Ω
Supported crystal equivalent
series resistance (ESR)
The transconductance of the gmHFXO
HFXO input transistor at crys-
tal startup
HFXOBOOST in CMU_CTRL equals
0b11
mS
Supported crystal external
load range
CHFXOL
5
—
25
—
pF
µA
4 MHz: ESR=400 Ohm, CL=20 pF,
HFXOBOOST in CMU_CTRL equals
0b11
—
85
Current consumption for
HFXO after startup
gmHFXO
32 MHz: ESR=30 Ohm, CL=10 pF,
HFXOBOOST in CMU_CTRL equals
0b11
—
—
165
400
—
—
µA
µs
Startup time
tHFXO
32 MHz: ESR=30 Ohm, CL=10 pF,
HFXOBOOST in CMU_CTRL equals
0b11
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Rev. 2.10 | 40
EFM32TG Data Sheet
Electrical Characteristics
4.9.3 LFRCO
Parameter
Table 4.10. LFRCO
Symbol
Test Condition
Min
Typ
Max
Unit
Oscillation frequency, VDD
=
fLFRCO
31.29
32.768
34.24
kHz
3.0 V, TAMB=25°C
Startup time not including
software calibration
tLFRCO
—
150
—
µs
Current consumption
ILFRCO
—
—
210
1.5
380
—
nA
%
Frequency step for LSB
change in TUNING value
TUNESTEPLFRCO
42
40
38
36
34
32
30
42
40
38
36
34
32
30
-40°C
25°C
85°C
2.0 V
3.0 V
3.8 V
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
Figure 4.10. Calibrated LFRCO Frequency vs Temperature and Supply Voltage
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Rev. 2.10 | 41
EFM32TG Data Sheet
Electrical Characteristics
4.9.4 HFRCO
Parameter
Table 4.11. HFRCO
Symbol
Test Condition
Min
Typ
28.0
21.0
14.0
11.0
Max
Unit
MHz
MHz
MHz
MHz
MHz
28 MHz frequency band
21 MHz frequency band
14 MHz frequency band
11 MHz frequency band
7 MHz frequency band
27.16
20.37
13.58
10.67
28.84
21.63
14.42
11.33
Oscillation frequency, VDD
3.0 V, TAMB=25ºC
=
fHFRCO
6.401
6.601
6.801
1.162
—
1.202
0.6
160
125
104
94
1.242
—
1 MHz frequency band
fHFRCO = 14 MHz
fHFRCO = 28 MHz
fHFRCO = 21 MHz
fHFRCO = 14 MHz
fHFRCO = 11 MHz
fHFRCO = 6.6 MHz
fHFRCO = 1.2 MHz
MHz
Cycles
µA
tHFRCO_settling
Settling time after start-up
—
190
155
120
110
90
—
µA
Current consumption (Pro-
duction test condition = 14
MHz)
—
µA
IHFRCO
—
µA
—
63
µA
—
22
32
µA
0.33
Frequency step for LSB
change in TUNING value
TUNESTEPHFRCO
—
—
%
Note:
1. For devices with prod. rev. < 19, Typ = 7MHz and Min/Max values not applicable.
2. For devices with prod. rev. < 19, Typ = 1MHz and Min/Max values not applicable.
3. The TUNING field in the CMU_HFRCOCTRL register may be used to adjust the HFRCO frequency. There is enough adjustment
range to ensure that the frequency bands above 7 MHz will always have some overlap across supply voltage and temperature.
By using a stable frequency reference such as the LFXO or HFXO, a firmware calibration routine can vary the TUNING bits and
the frequency band to maintain the HFRCO frequency at any arbitrary value between 7 MHz and 28 MHz across operating condi-
tions.
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Rev. 2.10 | 42
EFM32TG Data Sheet
Electrical Characteristics
1.45
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
1.45
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
-40°C
25°C
85°C
2.0 V
3.0 V
3.8 V
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
Figure 4.11. Calibrated HFRCO 1 MHz Band Frequency vs Supply Voltage and Temperature
6.70
6.65
6.60
6.55
6.50
6.45
6.40
6.35
6.30
6.70
6.65
6.60
6.55
6.50
6.45
6.40
-40°C
6.35
2.0 V
3.0 V
3.8 V
25°C
85°C
6.30
–40
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
Figure 4.12. Calibrated HFRCO 7 MHz Band Frequency vs Supply Voltage and Temperature
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Rev. 2.10 | 43
EFM32TG Data Sheet
Electrical Characteristics
11.2
11.1
11.0
10.9
10.8
10.7
10.6
11.2
11.1
11.0
10.9
10.8
10.7
10.6
-40°C
25°C
85°C
2.0 V
3.0 V
3.8 V
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
Figure 4.13. Calibrated HFRCO 11 MHz Band Frequency vs Supply Voltage and Temperature
14.2
14.1
14.0
13.9
13.8
13.7
13.6
13.5
13.4
14.2
14.1
14.0
13.9
13.8
13.7
13.6
-40°C
13.5
2.0 V
3.0 V
3.8 V
25°C
85°C
13.4
–40
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
Figure 4.14. Calibrated HFRCO 14 MHz Band Frequency vs Supply Voltage and Temperature
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Rev. 2.10 | 44
EFM32TG Data Sheet
Electrical Characteristics
21.2
21.0
20.8
20.6
20.4
20.2
21.2
21.0
20.8
20.6
20.4
20.2
-40°C
25°C
85°C
2.0 V
3.0 V
3.8 V
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
Figure 4.15. Calibrated HFRCO 21 MHz Band Frequency vs Supply Voltage and Temperature
28.2
28.0
27.8
27.6
27.4
27.2
27.0
26.8
28.4
28.2
28.0
27.8
27.6
27.4
27.2
-40°C
27.0
2.0 V
3.0 V
3.8 V
25°C
85°C
26.8
–40
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
Figure 4.16. Calibrated HFRCO 28 MHz Band Frequency vs Supply Voltage and Temperature
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Rev. 2.10 | 45
EFM32TG Data Sheet
Electrical Characteristics
4.9.5 AUXHFRCO
Parameter
Table 4.12. AUXHFRCO
Symbol
Test Condition
Min
Typ
28.0
21.0
14.0
11.0
Max
28.84
21.63
14.42
11.33
Unit
MHz
MHz
MHz
MHz
MHz
28 MHz frequency band
21 MHz frequency band
14 MHz frequency band
11 MHz frequency band
7 MHz frequency band
27.16
20.37
13.58
10.67
Oscillation frequency, VDD
3.0 V, TAMB=25ºC
=
fAUXHFRCO
6.401
6.601
6.801
1.162
—
1.202
0.6
1.242
—
1 MHz frequency band
MHz
Cycles
%
Settling time after start-up
tAUXHFRCO_settling fAUXHFRCO = 14 MHz
0.33
Frequency step for LSB
change in TUNING value
TUNE-
STEPAUXHFRCO
—
—
Note:
1. For devices with prod. rev. < 19, Typ = 7MHz and Min/Max values not applicable
2. For devices with prod. rev. < 19, Typ = 1MHz and Min/Max values not applicable.
3. The TUNING field in the CMU_AUXHFRCOCTRL register may be used to adjust the AUXHFRCO frequency. There is enough
adjustment range to ensure that the frequency bands above 7 MHz will always have some overlap across supply voltage and
temperature. By using a stable frequency reference such as the LFXO or HFXO, a firmware calibration routine can vary the TUN-
ING bits and the frequency band to maintain the AUXHFRCO frequency at any arbitrary value between 7 MHz and 28 MHz
across operating conditions.
4.9.6 ULFRCO
Table 4.13. ULFRCO
Parameter
Symbol
Test Condition
Min
0.7
—
Typ
—
Max
1.75
—
Unit
kHz
Oscillation frequency
Temperature coefficient
Supply voltage coefficient
fULFRCO
25°C, 3V
TCULFRCO
VCULFRCO
0.05
-18.2
%/°C
%/V
—
—
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Rev. 2.10 | 46
EFM32TG Data Sheet
Electrical Characteristics
4.10 Analog Digital Converter (ADC)
Table 4.14. ADC
Parameter
Symbol
Test Condition
Single ended
Differential
Min
0
Typ
—
Max
VREF
VREF/2
VDD
Unit
V
VADCIN
Input voltage range
-VREF/2
1.25
—
V
Input range of external refer-
ence voltage, single ended and
differential
VADCREFIN
—
V
Input range of external negative VADCREFIN_CH7
reference voltage on channel 7
See VADCREFIN
0
—
—
VDD-1.1
VDD
V
V
Input range of external positive VADCREFIN_CH6
reference voltage on channel 6
See VADCREFIN
0.625
Common mode input range
Input current
VADCCMIN
IADCIN
0
—
<100
65
VDD
—
V
2pF sampling capacitors
—
—
nA
dB
Analog input common mode re- CMRRADC
jection ratio
—
1 MSamples/s, 12 bit, external
reference
—
—
377
67
—
—
µA
µA
10 kSamples/s 12 bit, internal
1.25 V reference, WARMUP-
MODE in ADCn_CTRL set to
0b00
10 kSamples/s 12 bit, internal
1.25 V reference, WARMUP-
MODE in ADCn_CTRL set to
0b01
—
—
—
—
68
71
—
—
—
—
µA
µA
µA
µA
IADC
Average active current
10 kSamples/s 12 bit, internal
1.25 V reference, WARMUP-
MODE in ADCn_CTRL set to
0b10
10 kSamples/s 12 bit, internal
1.25 V reference, WARMUP-
MODE in ADCn_CTRL set to
0b11
244
65
Current consumption of internal IADCREF
voltage reference
Internal voltage reference
Input capacitance
CADCIN
—
300
—
2
—
—
800
—
pF
Ω
Input ON resistance
Input RC filter resistance
RADCIN
RADCFILT
CADCFILT
10
250
kΩ
fF
Input RC filter/decoupling ca-
pacitance
—
—
ADC Clock Frequency
fADCCLK
—
—
13
MHz
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Rev. 2.10 | 47
EFM32TG Data Sheet
Electrical Characteristics
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
6 bit
7
—
—
ADCCLK
Cycles
8 bit
11
13
1
—
—
—
—
—
—
ADCCLK
Cycles
tADCCONV
Conversion time
12 bit
ADCCLK
Cycles
Acquisition time
tADCACQ
Programmable
256
—
ADCCLK
Cycles
Required acquisition time for
VDD/3 reference
tADCACQVDD3
2
µs
Startup time of reference gener- tADCSTART
ator and ADC core in NORMAL
modeStartup time of reference
generator and ADC core in
—
—
5
1
—
—
µs
µs
KEEPADCWARM mode
1 MSamples/s, 12 bit, single
ended, internal 1.25V reference
—
—
—
—
—
—
—
—
—
—
63
—
—
—
—
—
59
63
65
60
65
54
67
69
62
63
67
63
66
66
69
70
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
1 MSamples/s, 12 bit, single
ended, internal 2.5V reference
1 MSamples/s, 12 bit, single
ended, VDD reference
1 MSamples/s, 12 bit, differen-
tial, internal 1.25V reference
1 MSamples/s, 12 bit, differen-
tial, internal 2.5V reference
1 MSamples/s, 12 bit, differen-
tial, 5V reference
1 MSamples/s, 12 bit, differen-
tial, VDD reference
1 MSamples/s, 12 bit, differen-
tial, 2xVDD reference
SNRADC
Signal to Noise Ratio (SNR)
200 kSamples/s, 12 bit, single
ended, internal 1.25V reference
200 kSamples/s, 12 bit, single
ended, internal 2.5V reference
200 kSamples/s, 12 bit, single
ended, VDD reference
200 kSamples/s, 12 bit, differen-
tial, internal 1.25V reference
200 kSamples/s, 12 bit, differen-
tial, internal 2.5V reference
200 kSamples/s, 12 bit, differen-
tial, 5V reference
200 kSamples/s, 12 bit, differen-
tial, VDD reference
200 kSamples/s, 12 bit, differen-
tial, 2xVDD reference
silabs.com | Building a more connected world.
Rev. 2.10 | 48
EFM32TG Data Sheet
Electrical Characteristics
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
1 MSamples/s, 12 bit, single
—
58
—
dB
ended, internal 1.25V reference
1 MSamples/s, 12 bit, single
ended, internal 2.5V reference
—
—
—
—
—
—
—
—
—
—
—
—
—
62
—
62
64
60
64
54
66
68
61
65
66
63
66
66
68
69
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
1 MSamples/s, 12 bit, single
ended, VDD reference
1 MSamples/s, 12 bit, differen-
tial, internal 1.25V reference
1 MSamples/s, 12 bit, differen-
tial, internal 2.5V reference
1 MSamples/s, 12 bit, differen-
tial, 5V reference
1 MSamples/s, 12 bit, differen-
tial, VDD reference
1 MSamples/s, 12 bit, differen-
tial, 2xVDD reference
SIgnal-to-Noise And Distortion-
ratio (SINAD)
SINADADC
200 kSamples/s, 12 bit, single
ended, internal 1.25V reference
200 kSamples/s, 12 bit, single
ended, internal 2.5V reference
200 kSamples/s, 12 bit, single
ended, VDD reference
200 kSamples/s, 12 bit, differen-
tial, internal 1.25V reference
200 kSamples/s, 12 bit, differen-
tial, internal 2.5V reference
200 kSamples/s, 12 bit, differen-
tial, 5V reference
200 kSamples/s, 12 bit, differen-
tial, VDD reference
200 kSamples/s, 12 bit, differen-
tial, 2xVDD reference
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Rev. 2.10 | 49
EFM32TG Data Sheet
Electrical Characteristics
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
1 MSamples/s, 12 bit, single
—
64
—
dBc
ended, internal 1.25V reference
1 MSamples/s, 12 bit, single
ended, internal 2.5V reference
—
—
—
—
—
—
—
—
—
68
—
—
—
—
—
76
73
66
77
76
75
69
75
75
76
79
79
78
79
79
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
1 MSamples/s, 12 bit, single
ended, VDD reference
1 MSamples/s, 12 bit, differen-
tial, internal 1.25V reference
1 MSamples/s, 12 bit, differen-
tial, internal 2.5V reference
1 MSamples/s, 12 bit, differen-
tial, VDD reference
1 MSamples/s, 12 bit, differen-
tial, 2xVDD reference
1 MSamples/s, 12 bit, differen-
tial, 5V reference
Spurious-Free Dynamic Range
(SFDR)
SFDRADC
200 kSamples/s, 12 bit, single
ended, internal 1.25V reference
200 kSamples/s, 12 bit, single
ended, internal 2.5V reference
200 kSamples/s, 12 bit, single
ended, VDD reference
200 kSamples/s, 12 bit, differen-
tial, internal 1.25V reference
200 kSamples/s, 12 bit, differen-
tial, internal 2.5V reference
200 kSamples/s, 12 bit, differen-
tial, 5V reference
200 kSamples/s, 12 bit, differen-
tial, VDD reference
200 kSamples/s, 12 bit, differen-
tial, 2xVDD reference
After calibration, single ended
After calibration, differential
-4
—
—
—
0.3
0.3
4
mV
mV
VADCOFFSET
Offset voltage
—
—
—
-1.92
-6.3
mV/ºC
TGRADADCTH
DNLADC
Thermometer output gradient
Differential non-linearity (DNL)
ADC Co-
des/ºC
VDD= 3.0 V, external 2.5V refer-
ence
-1
±0.7
±1.2
12
4
LSB
Integral non-linearity (INL), End INLADC
point method
VDD= 3.0 V, external 2.5V refer-
ence
—
±3
—
LSB
11.9991
—
No missing codes
MCADC
bits
0.012
0.012
0.0333
0.033
1.25V reference
2.5V reference
%/ºC
%/ºC
GAINED
Gain error drift
—
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Rev. 2.10 | 50
EFM32TG Data Sheet
Electrical Characteristics
Parameter
Offset error drift
Note:
Symbol
Test Condition
Min
Typ
0.22
0.22
Max
0.73
Unit
1.25V reference
—
LSB/ºC
OFFSETED
0.623
2.5V reference
—
LSB/ºC
1. On the average every ADC will have one missing code, most likely to appear around 2048 ± n*512 where n can be a value in the
set {-3, -2, -1, 1, 2, 3}. There will be no missing code around 2048, and in spite of the missing code the ADC will be monotonic at
all times so that a response to a slowly increasing input will always be a slowly increasing output. Around the one code that is
missing, the neighbour codes will look wider in the DNL plot. The spectra will show spurs on the level of -78dBc for a full scale
input for chips that have the missing code issue.
2. Typical numbers given by abs(Mean) / (85 - 25).
3. Max number given by (abs(Mean) + 3x stddev) / (85 - 25).
The integral non-linearity (INL) and differential non-linearity parameters are explained in the following two figures.
Digital output code
INL=|[(VD-VSS)/VLSBIDEAL] - D| where 0 < D < 2N
- 1
4095
4094
4093
4092
Actual ADC
tranfer function
before offset and
gain correction
Actual ADC
tranfer function
after offset and
gain correction
INL Error
(End Point INL)
Ideal transfer
curve
3
2
1
0
VOFFSET
Analog Input
Figure 4.17. Integral Non-Linearity (INL)
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Rev. 2.10 | 51
EFM32TG Data Sheet
Electrical Characteristics
Digital
output
code
DNL=|[(VD+1 - VD)/VLSBIDEAL] - 1| where 0 < D < 2N
- 2
Full Scale Range
4095
4094
4093
4092
Example: Adjacent
input value VD+1
corrresponds to digital
output code D+1
Actual transfer
function with one
missing code.
Example: Input value
VDcorrresponds to
digital output code D
Code width =2 LSB
DNL=1 LSB
Ideal transfer
curve
0.5
LSB
Ideal spacing
between two
adjacent codes
VLSBIDEAL=1 LSB
5
4
3
2
1
0
Ideal 50%
Transition Point
Ideal Code Center
Analog Input
Figure 4.18. Differential Non-Linearity (DNL)
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Rev. 2.10 | 52
EFM32TG Data Sheet
Electrical Characteristics
4.10.1 Typical Performance
1.25V Reference
2.5V Reference
2XVDDVSS Reference
5VDIFF Reference
VDD Reference
Figure 4.19. ADC Frequency Spectrum, VDD = 3 V, Temp = 25 °C
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Rev. 2.10 | 53
EFM32TG Data Sheet
Electrical Characteristics
1.25V Reference
2.5V Reference
2XVDDVSS Reference
5VDIFF Reference
VDD Reference
Figure 4.20. ADC Integral Linearity Error vs Code, VDD = 3 V, Temp = 25 °C
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Rev. 2.10 | 54
EFM32TG Data Sheet
Electrical Characteristics
1.25V Reference
2.5V Reference
2XVDDVSS Reference
5VDIFF Reference
VDD Reference
Figure 4.21. ADC Differential Linearity Error vs Code, VDD = 3 V, Temp = 25 °C
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Rev. 2.10 | 55
EFM32TG Data Sheet
Electrical Characteristics
Offset vs Supply Voltage, Temp = 25°C
Offset vs Temperature, VDD = 3V
5
4
3
2
1
0
2.0
1.5
Vref=1V25
Vref=2V5
VRef=1V25
VRef=2V5
Vref=2XVDDVSS
VRef=2XVDDVSS
VRef=5VDIFF
VRef=VDD
Vref=5VDIFF
Vref=VDD
1.0
0.5
–1
0.0
–2
–3
–4
–0.5
–1.0
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd (V)
Temp (C)
Figure 4.22. ADC Absolute Offset, Common Mode = VDD/2
Signal to Noise Ratio (SNR)
Spurious-Free Dynamic Range (SFDR)
71
70
69
68
67
66
65
64
63
79.4
79.2
79.0
78.8
78.6
78.4
78.2
78.0
2XVDDVSS
Vdd
1V25
Vdd
2V5
5VDIFF
2V5
2XVDDVSS
5VDIFF
85
1V25
–40
–15
5
25
45
65
85
–40
–15
5
25
45
65
Temperature [°C]
Temperature [°C]
Figure 4.23. ADC Dynamic Performance vs Temperature for all ADC References, VDD = 3 V
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Rev. 2.10 | 56
EFM32TG Data Sheet
Electrical Characteristics
4.11 Digital Analog Converter (DAC)
Table 4.15. DAC
Parameter
Symbol
Test Condition
Min
0
Typ
—
Max
VDD
VDD
VDD
Unit
V
Output voltage range
VDACOUT VDD voltage reference, single ended
VDD voltage reference, differential
VDACCM
-VDD
0
—
V
Output common mode voltage
range
—
V
500 kSamples/s, 12bit
—
—
—
—
400
200
17
650
250
25
µA
µA
µA
Active current including referen-
ces for 2 channels
IDAC
100 kSamples/s, 12 bit
1 kSamples/s 12 bit NORMAL
Sample rate
SRDAC
—
500
ksamples/
s
Continuous Mode
Sample/Hold Mode
Sample/Off Mode
—
—
—
—
—
—
—
2
1000
250
250
—
kHz
kHz
fDAC
DAC clock frequency
kHz
Clock cycles per conversion
CYCDAC-
cycles
CONV
Conversion time
Settling time
tDACCONV
2
—
5
—
—
µs
µs
tDACSET-
—
TLE
500 kSamples/s, 12 bit, single ended,
internal 1.25V reference
—
—
—
—
—
—
—
—
—
—
58
59
58
58
59
57
54
56
53
55
—
—
—
—
—
—
—
—
—
—
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
500 kSamples/s, 12 bit, single ended,
internal 2.5V reference
500 kSamples/s, 12 bit, differential, in-
ternal 1.25V reference
SNRDAC
Signal to Noise Ratio (SNR)
500 kSamples/s, 12 bit, differential, in-
ternal 2.5V reference
500 kSamples/s, 12 bit, differential,
VDD reference
500 kSamples/s, 12 bit, single ended,
internal 1.25V reference
500 kSamples/s, 12 bit, single ended,
internal 2.5V reference
500 kSamples/s, 12 bit, differential, in-
ternal 1.25V reference
Signal to Noise-pulse Distortion
Ratio (SNDR)
SNDRDAC
500 kSamples/s, 12 bit, differential, in-
ternal 2.5V reference
500 kSamples/s, 12 bit, differential,
VDD reference
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Rev. 2.10 | 57
EFM32TG Data Sheet
Electrical Characteristics
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
500 kSamples/s, 12 bit, single ended,
internal 1.25V reference
—
62
—
dBc
500 kSamples/s, 12 bit, single ended,
internal 2.5V reference
—
—
—
—
56
61
55
60
—
—
—
—
dBc
dBc
dBc
dBc
500 kSamples/s, 12 bit, differential, in-
ternal 1.25V reference
Spurious-Free Dynamic
Range(SFDR)
SFDRDAC
500 kSamples/s, 12 bit, differential, in-
ternal 2.5V reference
500 kSamples/s, 12 bit, differential,
VDD reference
Offset voltage
VDACOFF- After calibration, single ended
—
—
—
—
—
—
2
—
—
—
—
—
11
mV
mV
SET
After calibration, differential
2
Differential non-linearity
Integral non-linearity
No missing codes
Load current
DNLDAC
INLDAC
MCDAC
ILOAD_DC
VDD= 3.0 V, VDD reference
VDD= 3.0 V, VDD reference
±1
±5
12
—
LSB
LSB
bits
mA
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Rev. 2.10 | 58
EFM32TG Data Sheet
Electrical Characteristics
4.12 Operational Amplifier (OPAMP)
The electrical characteristics for the Operational Amplifiers are based on simulations.
Table 4.16. OPAMP
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
(OPA2)BIASPROG=0xF,
—
350
405
µA
(OPA2)HALFBIAS=0x0, Unity Gain
(OPA2)BIASPROG=0x7,
(OPA2)HALFBIAS=0x1, Unity Gain
—
—
—
—
—
—
—
—
—
—
—
—
—
—
95
13
115
17
—
—
—
—
—
—
—
—
—
—
—
—
µA
µA
IOPAMP
Active Current
(OPA2)BIASPROG=0x0,
(OPA2)HALFBIAS=0x1, Unity Gain
(OPA2)BIASPROG=0xF,
(OPA2)HALFBIAS=0x0
101
98
dB
(OPA2)BIASPROG=0x7,
(OPA2)HALFBIAS=0x1
dB
GOL
Open Loop Gain
(OPA2)BIASPROG=0x0,
(OPA2)HALFBIAS=0x1
91
dB
OPA0/OPA1 BIASPROG=0xF,
HALFBIAS=0x0
16.36
0.81
0.11
2.11
0.72
0.09
64
MHz
MHz
MHz
MHz
MHz
MHz
º
OPA0/OPA1 BIASPROG=0x7,
HALFBIAS=0x1
OPA0/OPA1 BIASPROG=0x0,
HALFBIAS=0x1
Gain Bandwidth Prod-
uct
GBWOPAMP
OPA2 BIASPROG=0xF, HALF-
BIAS=0x0
OPA2 BIASPROG=0x7, HALF-
BIAS=0x1
OPA2 BIASPROG=0x0, HALF-
BIAS=0x1
BIASPROG=0xF, HALFBIAS=0x0,
CL=75 pF
BIASPROG=0x7, HALFBIAS=0x1,
CL=75 pF
58
º
PMOPAMP
Phase Margin
BIASPROG=0x0, HALFBIAS=0x1,
CL=75 pF
58
º
Input Resistance
Load Resistance
RINPUT
—
200
2000
—
100
—
—
—
—
—
—
—
—
—
MΩ
Ω
OPA0/OPA1
OPA2
RLOAD
—
Ω
OPA0/OPA1
OPA2
11
mA
mA
V
ILOAD_DC
Load Current
—
1.5
OPAxHCMDIS=0
OPAxHCMDIS=1
VSS
VSS
VSS
VDD
VDD-1.2
VDD
VINPUT
Input Voltage
V
Output Voltage
VOUTPUT
V
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Rev. 2.10 | 59
EFM32TG Data Sheet
Electrical Characteristics
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Unity Gain, VSS<Vin<VDD
OPAxHCMDIS=0
,
—
6
—
mV
VOFFSET
Input Offset Voltage
Unity Gain, VSS<Vin<VDD-1.2,
OPAxHCMDIS=1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
—
0.02
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
mV
mV/ºC
V/µs
V/µs
V/µs
V/µs
V/µs
V/µs
µs
Input Offset Voltage
Drift
VOFFSET_DRIFT
—
OPA0/OPA1 BIASPROG=0xF,
HALFBIAS=0x0
46.11
1.21
0.16
4.43
1.30
0.16
0.09
1.52
12.74
0.09
0.13
0.17
101
OPA0/OPA1 BIASPROG=0x7,
HALFBIAS=0x1
OPA0/OPA1 BIASPROG=0x0,
HALFBIAS=0x1
SROPAMP
Slew Rate
OPA2 BIASPROG=0xF, HALF-
BIAS=0x0
OPA2 BIASPROG=0x7, HALF-
BIAS=0x1
OPA2 BIASPROG=0x0, HALF-
BIAS=0x1
OPA0/OPA1 BIASPROG=0xF,
HALFBIAS=0x0
OPA0/OPA1 BIASPROG=0x7,
HALFBIAS=0x1
µs
OPA0/OPA1 BIASPROG=0x0,
HALFBIAS=0x1
µs
PUOPAMP
Power-up Time
OPA2 BIASPROG=0xF, HALF-
BIAS=0x0
µs
OPA2 BIASPROG=0x7, HALF-
BIAS=0x1
µs
OPA2 BIASPROG=0x0, HALF-
BIAS=0x1
µs
Vout=1V, RESSEL=0, 0.1 Hz<f<10
kHz, OPAxHCMDIS=0
µVRMS
µVRMS
µVRMS
µVRMS
µVRMS
µVRMS
µVRMS
µVRMS
Vout=1V, RESSEL=0, 0.1 Hz<f<10
kHz, OPAxHCMDIS=1
141
Vout=1V, RESSEL=0, 0.1 Hz<f<1
MHz, OPAxHCMDIS=0
196
Vout=1V, RESSEL=0, 0.1 Hz<f<1
MHz, OPAxHCMDIS=1
229
NOPAMP
Voltage Noise
RESSEL=7, 0.1 Hz<f<10 kHz,
OPAxHCMDIS=0
1230
2130
1630
2590
RESSEL=7, 0.1 Hz<f<10 kHz,
OPAxHCMDIS=1
RESSEL=7, 0.1 Hz<f<1 MHz,
OPAxHCMDIS=0
RESSEL=7, 0.1 Hz<f<1 MHz,
OPAxHCMDIS=1
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Rev. 2.10 | 60
EFM32TG Data Sheet
Electrical Characteristics
Figure 4.24. OPAMP Common Mode Rejection Ratio
Figure 4.25. OPAMP Positive Power Supply Rejection Ratio
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Rev. 2.10 | 61
EFM32TG Data Sheet
Electrical Characteristics
Figure 4.26. OPAMP Negative Power Supply Rejection Ratio
Figure 4.27. OPAMP Voltage Noise Spectral Density (Unity Gain) Vout=1V
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Rev. 2.10 | 62
EFM32TG Data Sheet
Electrical Characteristics
Figure 4.28. OPAMP Voltage Noise Spectral Density (Non-Unity Gain)
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Rev. 2.10 | 63
EFM32TG Data Sheet
Electrical Characteristics
4.13 Analog Comparator (ACMP)
Table 4.17. ACMP
Test Condition
Parameter
Symbol
VACMPIN
Min
0
Typ
—
Max
VDD
VDD
Unit
V
Input voltage range
ACMP Common Mode voltage VACMPCM
range
0
—
V
BIASPROG=0b0000, FULL-
BIAS=0 and HALFBIAS=1 in
ACMPn_CTRL register
—
—
—
—
0.1
2.87
195
0.0
0.6
12
µA
µA
µA
µA
BIASPROG=0b1111, FULL-
BIAS=0 and HALFBIAS=0 in
ACMPn_CTRL register
IACMP
Active current
BIASPROG=0b1111, FULL-
BIAS=1 and HALFBIAS=0 in
ACMPn_CTRL register
520
0.5
Internal voltage reference off.
Using external voltage refer-
ence
Current consumption of internal
voltage reference
IACMPREF
Internal voltage reference
—
2.15
0
3.00
12
µA
Offset voltage
VACMPOFFSET
BIASPROG= 0b1010, FULL-
BIAS=0 and HALFBIAS=0 in
ACMPn_CTRL register
-12
mV
ACMP hysteresis
VACMPHYST
Programmable
—
—
17
39
—
—
mV
kΩ
CSRESSEL=0b00 in
ACMPn_INPUTSEL
CSRESSEL=0b01 in
ACMPn_INPUTSEL
—
—
—
—
71
104
136
—
—
—
—
10
kΩ
kΩ
kΩ
µs
Capacitive Sense Internal Re-
sistance
RCSRES
CSRESSEL=0b10 in
ACMPn_INPUTSEL
CSRESSEL=0b11 in
ACMPn_INPUTSEL
Startup time
tACMPSTART
The total ACMP current is the sum of the contributions from the ACMP and its internal voltage reference as given in in the following
equation. IACMPREF is zero if an external voltage reference is used.
I
= I
+ I
ACMP ACMPREF
ACMPTOTAL
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EFM32TG Data Sheet
Electrical Characteristics
Current Consumption, HYSTSEL = 4
Response Time, Vcm = 1.25V, CP+ to CP- = 100mV
2.5
2.0
1.5
1.0
0.5
0.0
20
15
10
5
HYSTSEL=0
HYSTSEL=2
HYSTSEL=4
HYSTSEL=6
0
0
4
8
12
0
2
4
6
8
10
12
14
ACMP_CTRL_BIASPROG
ACMP_CTRL_BIASPROG
Hysteresis
100
80
60
40
20
0
BIASPROG=0.0
BIASPROG=4.0
BIASPROG=8.0
BIASPROG=12.0
0
1
2
3
4
5
6
7
ACMP_CTRL_HYSTSEL
Figure 4.29. ACMP Characteristics, Vdd = 3 V, Temp = 25 °C, FULLBIAS = 0, HALFBIAS = 1
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Rev. 2.10 | 65
EFM32TG Data Sheet
Electrical Characteristics
4.14 Voltage Comparator (VCMP)
Table 4.18. VCMP
Test Condition
Parameter
Symbol
VVCMPIN
Min
—
Typ
VDD
VDD
Max
—
Unit
V
Input voltage range
VCMP Common Mode voltage VVCMPCM
range
—
—
V
Active current
IVCMP
BIASPROG=0b0000 and HALF-
BIAS=1 in VCMPn_CTRL regis-
ter
—
—
—
0.3
22
10
0.6
30
—
µA
µA
µs
BIASPROG=0b1111 and HALF-
BIAS=0 in VCMPn_CTRL regis-
ter. LPREF=0.
Startup time reference genera- tVCMPREF
tor
NORMAL
Offset voltage
VVCMPOFFSET
Single ended
Differential
—
—
—
—
10
10
17
—
—
—
—
10
mV
mV
mV
µs
VCMP hysteresis
Startup time
VVCMPHYST
tVCMPSTART
The VDD trigger level can be configured by setting the TRIGLEVEL field of the VCMP_CTRL register in accordance with the following
equation:
V
= 1.667V + 0.034 × TRIGLEVEL
DD Trigger Level
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EFM32TG Data Sheet
Electrical Characteristics
4.15 LCD
Table 4.19. LCD
Test Condition
Parameter
Symbol
fLCDFR
NUMSEG
VLCD
Min
30
Typ
—
Max
200
—
Unit
Hz
seg
V
Frame rate
Number of segments supported
LCD supply voltage range
—
20×8
—
Internal boost circuit enabled
2.0
—
3.8
—
Display disconnected, static
mode, framerate 32 Hz, all
segments on.
250
nA
Display disconnected, quad-
ruplex mode, framerate 32
Hz, all segments on, bias
mode to ONETHIRD in
—
550
—
nA
ILCD
Steady state current consumption.
LCD_DISPCTRL register.
Internal voltage boost off
—
—
0
—
—
µA
µA
Steady state Current contribution
of internal boost.
ILCDBOOST
Internal voltage boost on,
boosting from 2.2 V to 3.0 V.
8.4
VBLEV of LCD_DISPCTRL
register to LEVEL0
—
—
—
—
—
—
—
—
3.0
—
—
—
—
—
—
—
—
V
V
V
V
V
V
V
V
VBLEV of LCD_DISPCTRL
register to LEVEL1
3.08
3.17
3.26
3.34
3.43
3.52
3.6
VBLEV of LCD_DISPCTRL
register to LEVEL2
VBLEV of LCD_DISPCTRL
register to LEVEL3
VBOOST
Boost Voltage
VBLEV of LCD_DISPCTRL
register to LEVEL4
VBLEV of LCD_DISPCTRL
register to LEVEL5
VBLEV of LCD_DISPCTRL
register to LEVEL6
VBLEV of LCD_DISPCTRL
register to LEVEL7
The total LCD current is given by the following equation. ILCDBOOST is zero if internal boost is off.
= I + I
I
LCDTOTAL
LCD
LCDBOOST
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EFM32TG Data Sheet
Electrical Characteristics
4.16 I2C
Table 4.20. I2C Standard-mode (Sm)
Parameter
Symbol
Min
Typ
Max
Unit
1001
—
SCL clock frequency
fSCL
0
—
kHz
SCL clock low time
tLOW
4.7
4.0
250
8
—
—
—
—
—
—
—
—
µs
µs
ns
ns
µs
µs
µs
µs
SCL clock high time
tHIGH
—
SDA set-up time
tSU,DAT
tHD,DAT
tSU,STA
tHD,STA
tSU,STO
—
34502,3
—
SDA hold time
Repeated START condition set-up time
(Repeated) START condition hold time
STOP condition set-up time
4.7
4.0
4.0
4.7
—
—
Bus free time between a STOP and a START condition
tBUF
—
Note:
1. For the minimum HFPERCLK frequency required in Standard-mode, see the I2C chapter in the EFM32TG Reference Manual.
2. The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).
3. When transmitting data, this number is guaranteed only when I2Cn_CLKDIV < ((3450*10-9 [s] * fHFPERCLK [Hz]) - 4).
Table 4.21. I2C Fast-mode (Fm)
Parameter
Symbol
Min
Typ
Max
Unit
4001
—
SCL clock frequency
fSCL
0
—
kHz
SCL clock low time
tLOW
1.3
0.6
100
8
—
—
—
—
—
—
—
—
µs
µs
ns
ns
µs
µs
µs
µs
SCL clock high time
tHIGH
—
SDA set-up time
tSU,DAT
tHD,DAT
tSU,STA
tHD,STA
tSU,STO
tBUF
—
9002,3
—
SDA hold time
Repeated START condition set-up time
(Repeated) START condition hold time
STOP condition set-up time
Bus free time between a STOP and a START condition
Note:
0.6
0.6
0.6
1.3
—
—
—
1. For the minimum HFPERCLK frequency required in Fast-mode, see the I2C chapter in the EFM32TG Reference Manual.
2. The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).
3. When transmitting data, this number is guaranteed only when I2Cn_CLKDIV < ((900*10-9 [s] * fHFPERCLK [Hz]) - 4).
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EFM32TG Data Sheet
Electrical Characteristics
Table 4.22. I2C Fast-mode Plus (Fm+)
Parameter
Symbol
Min
Typ
Max
Unit
10001
—
SCL clock frequency
fSCL
0
—
kHz
SCL clock low time
tLOW
0.5
0.26
50
—
—
—
—
—
—
—
—
µs
µs
ns
ns
µs
µs
µs
µs
SCL clock high time
tHIGH
—
SDA set-up time
tSU,DAT
tHD,DAT
tSU,STA
tHD,STA
tSU,STO
—
SDA hold time
8
—
Repeated START condition set-up time
(Repeated) START condition hold time
STOP condition set-up time
0.26
0.26
0.26
0.5
—
—
—
Bus free time between a STOP and a START condition
tBUF
—
Note:
1. For the minimum HFPERCLK frequency required in Fast-mode Plus, see the I2C chapter in the EFM32TG Reference Manual.
4.17 Digital Peripherals
Table 4.23. Digital Peripherals
Parameter
Symbol Test Condition
Min
—
—
—
—
—
—
—
—
—
—
—
—
Typ
7.5
Max
—
—
—
—
—
—
—
—
—
—
—
—
Unit
µA/MHz
nA
USART current
LEUART current
I2C current
IUSART
ILEUART
II2C
USART idle current, clock enabled
LEUART idle current, clock enabled
I2C idle current, clock enabled
150
6.25
8.75
75
µA/MHz
µA/MHz
nA
TIMER current
LETIMER current
PCNT current
RTC current
LCD current
ITIMER
TIMER_0 idle current, clock enabled
ILETIMER LETIMER idle current, clock enabled
IPCNT
IRTC
ILCD
IAES
IGPIO
IPRS
IDMA
PCNT idle current, clock enabled
RTC idle current, clock enabled
LCD idle current, clock enabled
AES idle current, clock enabled
GPIO idle current, clock enabled
PRS idle current
60
nA
40
nA
50
nA
AES current
2.5
µA/MHz
µA/MHz
µA/MHz
µA/MHz
GPIO current
PRS current
DMA current
5.31
2.81
8.12
Clock enable
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EFM32TG Data Sheet
Pin Definitions
5. Pin Definitions
Note: Please refer to the application note AN0002 EFM32 Hardware Design Considerations for guidelines on designing Printed Circuit
Boards (PCBs) for the EFM32TG.
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EFM32TG Data Sheet
Pin Definitions
5.1 EFM32TG108 (QFN24)
5.1.1 Pinout
The EFM32TG108 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location
number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the
*_ROUTE register in the module in question.
Figure 5.1. EFM32TG108 Pinout (top view, not to scale)
Table 5.1. Device Pinout
QFN24 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
Analog
Timers
Communication
Other
0
1
2
VSS
Ground.
LEU0_RX #4
I2C0_SDA #0
PRS_CH0 #0
PA0
TIM0_CC0 #0/1/4
GPIO_EM4WU0
IOVDD_0
Digital IO power supply 0.
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EFM32TG Data Sheet
Pin Definitions
QFN24 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
Analog
Timers
Communication
US1_TX #0
Other
TIM0_CC1 #4
PCNT0_S0IN #2
TIM0_CC2 #4
PCNT0_S1IN #2
TIM1_CC0 #3
TIM1_CC1 #3
LES_CH0 #0
PRS_CH2 #0
LES_CH1 #0
PRS_CH3 #0
3
4
PC0
ACMP0_CH0
I2C0_SDA #4
US1_RX #0
PC1
ACMP0_CH1
I2C0_SCL #4
US1_CLK #0
US1_CS #0
5
6
PB7
PB8
LFXTAL_P
LFXTAL_N
Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin
low during reset, and let the internal pull-up ensure that reset is released.
7
8
RESETn
PB11
TIM1_CC2 #3
LETIM0_OUT0 #1
9
AVDD_2
PB13
Analog power supply 2.
10
11
12
HFXTAL_P
HFXTAL_N
LEU0_TX #1
LEU0_RX #1
PB14
AVDD_0
Analog power supply 0.
TIM1_CC0 #4
LETIM0_OUT0 #0
PCNT0_S0IN #3
TIM1_CC1 #4
US1_RX #2
LES_ALTEX0 #0
ACMP0_O #2
13
14
PD6
PD7
I2C0_SDA #1
CMU_CLK0 #2
LES_ALTEX1 #0
ACMP1_O #2
US1_TX #2
LETIM0_OUT1 #0
PCNT0_S1IN #3
I2C0_SCL #1
15
16
VDD_DREG
DECOUPLE
Power supply for on-chip voltage regulator.
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required
at this pin.
TIM1_CC1 #0
17
18
PC14
PC15
ACMP1_CH6
ACMP1_CH7
LES_CH14 #0
PCNT0_S1IN #0
LES_CH15 #0
DBG_SWO #1
TIM1_CC2 #0
US1_CLK #2
LEU0_TX #3
I2C0_SDA #5
US1_CS #2
TIM0_CC0 #5
DBG_SWCLK #0/1
BOOT_TX
19
20
21
PF0
PF1
PF2
LETIM0_OUT0 #2
DBG_SWDIO #0/1
GPIO_EM4WU3
BOOT_RX
TIM0_CC1 #5
LEU0_RX #3
I2C0_SCL #5
LETIM0_OUT1 #2
ACMP1_O #0
DBG_SWO #0
GPIO_EM4WU4
TIM0_CC2 #5
LEU0_TX #4
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EFM32TG Data Sheet
Pin Definitions
QFN24 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
Analog
Timers
Communication
I2C0_SDA #6
I2C0_SCL #6
Other
22
IOVDD_5
Digital IO power supply 5.
CMU_CLK1 #2
LES_ALTEX6 #0
LES_ALTEX7 #0
ACMP0_O #0
23
PE12
PE13
TIM1_CC2 #1
24
GPIO_EM4WU5
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EFM32TG Data Sheet
Pin Definitions
5.1.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table
shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.
Table 5.2. Alternate functionality overview
Alternate
LOCATION
3
Functionality
ACMP0_CH0
ACMP0_CH1
ACMP0_O
0
PC0
PC1
PE13
PC14
PC15
PF2
1
2
PD6
PD7
4
5
6
Description
Analog comparator ACMP0, channel 0.
Analog comparator ACMP0, channel 1.
Analog comparator ACMP0, digital output.
Analog comparator ACMP1, channel 6.
Analog comparator ACMP1, channel 7.
Analog comparator ACMP1, digital output.
Bootloader RX.
ACMP1_CH6
ACMP1_CH7
ACMP1_O
BOOT_RX
PF1
BOOT_TX
PF0
Bootloader TX.
CMU_CLK0
CMU_CLK1
PD7
Clock Management Unit, clock output number 0.
Clock Management Unit, clock output number 1.
Debug-interface Serial Wire clock input.
PE12
DBG_SWCLK
DBG_SWDIO
DBG_SWO
PF0
PF1
PF2
PF0
Note that this function is enabled to pin out of reset,
and has a built-in pull down.
Debug-interface Serial Wire data input / output.
PF1
Note that this function is enabled to pin out of reset,
and has a built-in pull up.
Debug-interface Serial Wire viewer Output.
PC15
Note that this function is not enabled after reset, and
must be enabled by software to be used.
GPIO_EM4WU0 PA0
GPIO_EM4WU3 PF1
GPIO_EM4WU4 PF2
GPIO_EM4WU5 PE13
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
High Frequency Crystal negative pin. Also used as
external optional clock input pin.
HFXTAL_N
PB14
PB13
HFXTAL_P
I2C0_SCL
High Frequency Crystal positive pin.
I2C0 Serial Clock Line input / output.
I2C0 Serial Data input / output.
PD7
PD6
PC1
PC0
PF1
PF0
PE13
PE12
I2C0_SDA
PA0
PD6
PD7
PE12
LES_ALTEX0
LES_ALTEX1
LES_ALTEX6
LESENSE alternate exite output 0.
LESENSE alternate exite output 1.
LESENSE alternate exite output 6.
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EFM32TG Data Sheet
Pin Definitions
Alternate
LOCATION
3
Functionality
LES_ALTEX7
LES_CH0
0
1
2
4
5
6
Description
PE13
PC0
LESENSE alternate exite output 7.
LESENSE channel 0.
LES_CH1
PC1
LESENSE channel 1.
LES_CH14
LES_CH15
PC14
PC15
LESENSE channel 14.
LESENSE channel 15.
LETIM0_OUT0 PD6
LETIM0_OUT1 PD7
LEU0_RX
PB11
PF0
PF1
Low Energy Timer LETIM0, output channel 0.
Low Energy Timer LETIM0, output channel 1.
LEUART0 Receive input.
PB14
PB13
PF1
PF0
PA0
PF2
LEUART0 Transmit output. Also used as receive in-
put in half duplex communication.
LEU0_TX
Low Frequency Crystal (typically 32.768 kHz) nega-
tive pin. Also used as an optional external clock in-
put pin.
LFXTAL_N
LFXTAL_P
PB8
PB7
Low Frequency Crystal (typically 32.768 kHz) posi-
tive pin.
PCNT0_S0IN
PCNT0_S1IN
PRS_CH0
PRS_CH2
PRS_CH3
TIM0_CC0
TIM0_CC1
TIM0_CC2
TIM1_CC0
TIM1_CC1
TIM1_CC2
US1_CLK
US1_CS
PC0
PC1
PD6
PD7
Pulse Counter PCNT0 input number 0.
PC14
PA0
PC0
PC1
PA0
Pulse Counter PCNT0 input number 1.
Peripheral Reflex System PRS, channel 0.
Peripheral Reflex System PRS, channel 2.
Peripheral Reflex System PRS, channel 3.
Timer 0 Capture Compare input / output channel 0.
Timer 0 Capture Compare input / output channel 1.
Timer 0 Capture Compare input / output channel 2.
Timer 1 Capture Compare input / output channel 0.
Timer 1 Capture Compare input / output channel 1.
Timer 1 Capture Compare input / output channel 2.
USART1 clock input / output.
PA0
PA0
PC0
PC1
PD6
PD7
PF0
PF1
PF2
PB7
PB8
PB11
PC14
PC15 PE12
PB7
PF0
PF1
PB8
USART1 chip select input / output.
USART1 Asynchronous Receive.
US1_RX
US1_TX
PC1
PC0
PD6
PD7
USART1 Synchronous mode Master Input / Slave
Output (MISO).
USART1 Asynchronous Transmit.Also used as re-
ceive input in half duplex communication.
USART1 Synchronous mode Master Output / Slave
Input (MOSI).
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EFM32TG Data Sheet
Pin Definitions
5.1.3 GPIO Pinout Overview
The specific GPIO pins available in EFM32TG108 is shown in the following table. Each GPIO port is organized as 16-bit ports indicated
by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.
Table 5.3. GPIO Pinout
Port
Pin
15
Pin
14
Pin
13
Pin
12
Pin
11
Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
10
Port A
Port B
Port C
Port D
Port E
Port F
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PA0
-
PB14 PB13
PB11
PB8 PB7
PC15 PC14
-
-
-
-
-
-
-
-
-
-
-
PC1 PC0
-
-
-
-
-
-
PD7 PD6
-
-
-
-
PE13 PE12
-
-
-
-
-
-
PF2 PF1 PF0
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EFM32TG Data Sheet
Pin Definitions
5.2 EFM32TG110 (QFN24)
5.2.1 Pinout
The EFM32TG110 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location
number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the
*_ROUTE register in the module in question.
Figure 5.2. EFM32TG110 Pinout (top view, not to scale)
Table 5.4. Device Pinout
QFN24 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
Analog
Timers
Communication
Other
0
1
2
VSS
Ground.
LEU0_RX #4
I2C0_SDA #0
PRS_CH0 #0
PA0
TIM0_CC0 #0/1/4
GPIO_EM4WU0
IOVDD_0
Digital IO power supply 0.
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EFM32TG Data Sheet
Pin Definitions
QFN24 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
Analog
Timers
Communication
US0_TX #5
US1_TX #0
I2C0_SDA #4
US0_RX #5
US1_RX #0
I2C0_SCL #4
US0_TX #4
US1_CLK #0
US0_RX #4
US1_CS #0
Other
ACMP0_CH0
TIM0_CC1 #4
LES_CH0 #0
PRS_CH2 #0
3
PC0
DAC0_OUT0ALT #0/
OPAMP_OUT0ALT
ACMP0_CH1
PCNT0_S0IN #2
TIM0_CC2 #4
LES_CH1 #0
PRS_CH3 #0
4
5
PC1
PB7
DAC0_OUT0ALT #1/
OPAMP_OUT0ALT
PCNT0_S1IN #2
LFXTAL_P
LFXTAL_N
TIM1_CC0 #3
TIM1_CC1 #3
6
7
PB8
Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin
low during reset, and let the internal pull-up ensure that reset is released.
RESETn
DAC0_OUT0 /
OPAMP_OUT0
TIM1_CC2 #3
8
9
PB11
AVDD_2
PB13
LETIM0_OUT0 #1
Analog power supply 2.
US0_CLK #4/5
LEU0_TX #1
US0_CS #4/5
LEU0_RX #1
10
HFXTAL_P
HFXTAL_N
11
12
PB14
AVDD_0
Analog power supply 0.
ADC0_CH6
TIM1_CC0 #4
LETIM0_OUT0 #0
PCNT0_S0IN #3
TIM1_CC1 #4
US1_RX #2
LES_ALTEX0 #0
ACMP0_O #2
13
14
PD6
PD7
DAC0_P1/
I2C0_SDA #1
OPAMP_P1
ADC0_CH7
CMU_CLK0 #2
LES_ALTEX1 #0
ACMP1_O #2
US1_TX #2
DAC0_N1/
LETIM0_OUT1 #0
PCNT0_S1IN #3
I2C0_SCL #1
OPAMP_N1
15
16
VDD_DREG
DECOUPLE
Power supply for on-chip voltage regulator.
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required
at this pin.
ACMP1_CH6
TIM1_CC1 #0
17
18
PC14
PC15
DAC0_OUT1ALT #2/
OPAMP_OUT1ALT
ACMP1_CH7
US0_CS #3
LES_CH14 #0
PCNT0_S1IN #0
LES_CH15 #0
DBG_SWO #1
DAC0_OUT1ALT #3/
OPAMP_OUT1ALT
TIM1_CC2 #0
US0_CLK #3
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EFM32TG Data Sheet
Pin Definitions
QFN24 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
Analog
Timers
Communication
US1_CLK #2
LEU0_TX #3
I2C0_SDA #5
US1_CS #2
Other
TIM0_CC0 #5
DBG_SWCLK #0/1
BOOT_TX
19
20
PF0
LETIM0_OUT0 #2
DBG_SWDIO #0/1
GPIO_EM4WU3
BOOT_RX
TIM0_CC1 #5
PF1
LEU0_RX #3
I2C0_SCL #5
LETIM0_OUT1 #2
ACMP1_O #0
DBG_SWO #0
GPIO_EM4WU4
21
22
23
PF2
IOVDD_5
PE12
TIM0_CC2 #5
TIM1_CC2 #1
LEU0_TX #4
Digital IO power supply 5.
US0_RX #3
US0_CLK #0
I2C0_SDA #6
US0_TX #3
US0_CS #0
I2C0_SCL #6
CMU_CLK1 #2
LES_ALTEX6 #0
LES_ALTEX7 #0
ACMP0_O #0
24
PE13
GPIO_EM4WU5
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EFM32TG Data Sheet
Pin Definitions
5.2.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table
shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.
Table 5.5. Alternate functionality overview
Alternate
LOCATION
3
Functionality
ACMP0_CH0
ACMP0_CH1
ACMP0_O
0
1
2
PD6
PD7
4
5
6
Description
PC0
Analog comparator ACMP0, channel 0.
Analog comparator ACMP0, channel 1.
Analog comparator ACMP0, digital output.
Analog comparator ACMP1, channel 6.
Analog comparator ACMP1, channel 7.
Analog comparator ACMP1, digital output.
PC1
PE13
PC14
PC15
PF2
ACMP1_CH6
ACMP1_CH7
ACMP1_O
Analog to digital converter ADC0, input channel
number 6.
ADC0_CH6
ADC0_CH7
PD6
PD7
Analog to digital converter ADC0, input channel
number 7.
BOOT_RX
BOOT_TX
CMU_CLK0
CMU_CLK1
PF1
PF0
Bootloader RX.
Bootloader TX.
PD7
Clock Management Unit, clock output number 0.
Clock Management Unit, clock output number 1.
PE12
DAC0_N1/
OPAMP_N1
PD7
Operational Amplifier 1 external negative input.
DAC0_OUT0/
OPAMP_OUT0
Digital to Analog Converter DAC0_OUT0 /OPAMP
output channel number 0.
PB11
DAC0_OUT0AL
T/
Digital to Analog Converter DAC0_OUT0ALT /
OPAMP alternative output for channel 0.
PC0
PC1
OPAMP_OUT0
ALT
DAC0_OUT1AL
T/
Digital to Analog Converter DAC0_OUT1ALT /
OPAMP alternative output for channel 1.
PC14 PC15
OPAMP_OUT1
ALT
DAC0_P1/
OPAMP_P1
PD6
PF0
Operational Amplifier 1 external positive input.
Debug-interface Serial Wire clock input.
DBG_SWCLK
DBG_SWDIO
PF0
PF1
Note that this function is enabled to pin out of reset,
and has a built-in pull down.
Debug-interface Serial Wire data input / output.
PF1
Note that this function is enabled to pin out of reset,
and has a built-in pull up.
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EFM32TG Data Sheet
Pin Definitions
Alternate
LOCATION
3
Functionality
0
1
2
4
5
6
Description
Debug-interface Serial Wire viewer Output.
DBG_SWO
PF2
PC15
Note that this function is not enabled after reset, and
must be enabled by software to be used.
GPIO_EM4WU0 PA0
GPIO_EM4WU3 PF1
GPIO_EM4WU4 PF2
GPIO_EM4WU5 PE13
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
High Frequency Crystal negative pin. Also used as
external optional clock input pin.
HFXTAL_N
PB14
PB13
HFXTAL_P
I2C0_SCL
High Frequency Crystal positive pin.
I2C0 Serial Clock Line input / output.
I2C0 Serial Data input / output.
LESENSE alternate exite output 0.
LESENSE alternate exite output 1.
LESENSE alternate exite output 6.
LESENSE alternate exite output 7.
LESENSE channel 0.
PD7
PD6
PC1
PC0
PF1
PF0
PE13
PE12
I2C0_SDA
PA0
LES_ALTEX0
LES_ALTEX1
LES_ALTEX6
LES_ALTEX7
LES_CH0
PD6
PD7
PE12
PE13
PC0
LES_CH1
PC1
LESENSE channel 1.
LES_CH14
LES_CH15
PC14
PC15
LESENSE channel 14.
LESENSE channel 15.
LETIM0_OUT0 PD6
LETIM0_OUT1 PD7
LEU0_RX
PB11
PF0
PF1
Low Energy Timer LETIM0, output channel 0.
Low Energy Timer LETIM0, output channel 1.
LEUART0 Receive input.
PB14
PB13
PF1
PF0
PA0
PF2
LEUART0 Transmit output. Also used as receive in-
put in half duplex communication.
LEU0_TX
Low Frequency Crystal (typically 32.768 kHz) nega-
tive pin. Also used as an optional external clock in-
put pin.
LFXTAL_N
LFXTAL_P
PB8
PB7
Low Frequency Crystal (typically 32.768 kHz) posi-
tive pin.
PCNT0_S0IN
PCNT0_S1IN
PRS_CH0
PRS_CH2
PRS_CH3
TIM0_CC0
TIM0_CC1
TIM0_CC2
PC0
PC1
PD6
PD7
Pulse Counter PCNT0 input number 0.
PC14
PA0
PC0
PC1
PA0
Pulse Counter PCNT0 input number 1.
Peripheral Reflex System PRS, channel 0.
Peripheral Reflex System PRS, channel 2.
Peripheral Reflex System PRS, channel 3.
Timer 0 Capture Compare input / output channel 0.
Timer 0 Capture Compare input / output channel 1.
Timer 0 Capture Compare input / output channel 2.
PA0
PA0
PC0
PC1
PF0
PF1
PF2
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EFM32TG Data Sheet
Pin Definitions
Alternate
LOCATION
3
Functionality
TIM1_CC0
TIM1_CC1
TIM1_CC2
US0_CLK
US0_CS
0
1
2
4
5
6
Description
PB7
PB8
PB11
PD6
PD7
Timer 1 Capture Compare input / output channel 0.
Timer 1 Capture Compare input / output channel 1.
Timer 1 Capture Compare input / output channel 2.
USART0 clock input / output.
PC14
PC15 PE12
PE12
PC15 PB13
PC14 PB14
PB13
PB14
PE13
USART0 chip select input / output.
USART0 Asynchronous Receive.
US0_RX
US0_TX
PE12
PE13
PB8
PB7
PC1
PC0
USART0 Synchronous mode Master Input / Slave
Output (MISO).
USART0 Asynchronous Transmit.Also used as re-
ceive input in half duplex communication.
USART0 Synchronous mode Master Output / Slave
Input (MOSI).
US1_CLK
US1_CS
PB7
PB8
PF0
PF1
USART1 clock input / output.
USART1 chip select input / output.
USART1 Asynchronous Receive.
US1_RX
US1_TX
PC1
PC0
PD6
PD7
USART1 Synchronous mode Master Input / Slave
Output (MISO).
USART1 Asynchronous Transmit.Also used as re-
ceive input in half duplex communication.
USART1 Synchronous mode Master Output / Slave
Input (MOSI).
5.2.3 GPIO Pinout Overview
The specific GPIO pins available in EFM32TG110 is shown in the following table. Each GPIO port is organized as 16-bit ports indicated
by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.
Table 5.6. GPIO Pinout
Port
Pin
15
Pin
14
Pin
13
Pin
12
Pin
11
Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
10
Port A
Port B
Port C
Port D
Port E
Port F
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PA0
-
PB14 PB13
PB11
PB8 PB7
PC15 PC14
-
-
-
-
-
-
-
-
-
-
-
PC1 PC0
-
-
-
-
-
-
PD7 PD6
-
-
-
-
PE13 PE12
-
-
-
-
-
-
PF2 PF1 PF0
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EFM32TG Data Sheet
Pin Definitions
5.2.4 Opamp Pinout Overview
The specific opamp terminals available in EFM32TG110 is shown in the following figure.
PB11
OUT0ALT
+
PC0
OPA0
OUT0
PC1
-
+
OPA2
-
OUT2
PC14
PC15
PD6
PD7
OUT1ALT
OUT1
+
OPA1
-
Figure 5.3. Opamp Pinout
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EFM32TG Data Sheet
Pin Definitions
5.3 EFM32TG210 (QFN32)
5.3.1 Pinout
The EFM32TG210 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location
number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the
*_ROUTE register in the module in question.
Figure 5.4. EFM32TG210 Pinout (top view, not to scale)
Table 5.7. Device Pinout
QFN32 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
Analog
Timers
Communication
Other
0
VSS
Ground.
LEU0_RX #4
I2C0_SDA #0
PRS_CH0 #0
GPIO_EM4WU0
CMU_CLK1 #0
PRS_CH1 #0
1
PA0
PA1
TIM0_CC0 #0/1/4
TIM0_CC1 #0/1
2
I2C0_SCL #0
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EFM32TG Data Sheet
Pin Definitions
QFN32 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
PA2
Analog
Timers
Communication
Other
3
4
TIM0_CC2 #0/1
CMU_CLK0 #0
IOVDD_0
Digital IO power supply 0.
ACMP0_CH0
US0_TX #5
US1_TX #0
I2C0_SDA #4
US0_RX #5
US1_RX #0
I2C0_SCL #4
US0_TX #4
US1_CLK #0
US0_RX #4
US1_CS #0
TIM0_CC1 #4
LES_CH0 #0
PRS_CH2 #0
5
PC0
DAC0_OUT0ALT #0/
OPAMP_OUT0ALT
ACMP0_CH1
PCNT0_S0IN #2
TIM0_CC2 #4
LES_CH1 #0
PRS_CH3 #0
6
7
PC1
PB7
DAC0_OUT0ALT #1/
OPAMP_OUT0ALT
PCNT0_S1IN #2
LFXTAL_P
LFXTAL_N
TIM1_CC0 #3
TIM1_CC1 #3
8
9
PB8
Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin
low during reset, and let the internal pull-up ensure that reset is released.
RESETn
DAC0_OUT0/
OPAMP_OUT0
TIM1_CC2 #3
10
11
12
PB11
AVDD_2
PB13
LETIM0_OUT0 #1
Analog power supply 2.
US0_CLK #4/5
LEU0_TX #1
US0_CS #4/5
LEU0_RX #1
HFXTAL_P
HFXTAL_N
13
PB14
14
15
IOVDD_3
AVDD_0
Digital IO power supply 3.
Analog power supply 0.
ADC0_CH4
16
17
PD4
PD5
LEU0_TX #0
LEU0_RX #0
OPAMP_P2
ADC0_CH5
OPAMP_OUT2 #0
ADC0_CH6
TIM1_CC0 #4
LETIM0_OUT0 #0
PCNT0_S0IN #3
TIM1_CC1 #4
US1_RX #2
LES_ALTEX0 #0
ACMP0_O #2
18
19
PD6
PD7
DAC0_P1/
I2C0_SDA #1
OPAMP_P1
ADC0_CH7
CMU_CLK0 #2
LES_ALTEX1 #0
ACMP1_O #2
US1_TX #2
DAC0_N1/
LETIM0_OUT1 #0
PCNT0_S1IN #3
I2C0_SCL #1
OPAMP_N1
20
21
VDD_DREG
DECOUPLE
Power supply for on-chip voltage regulator.
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required
at this pin.
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EFM32TG Data Sheet
Pin Definitions
QFN32 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
Analog
Timers
Communication
Other
ACMP1_CH5
TIM1_CC0 #0
TIM1_CC2 #4
PCNT0_S0IN #0
22
23
24
25
26
27
PC13
DAC0_OUT1ALT #1/
OPAMP_OUT1ALT
ACMP1_CH6
LES_CH13 #0
TIM1_CC1 #0
PC14
PC15
PF0
DAC0_OUT1ALT #2/
OPAMP_OUT1ALT
ACMP1_CH7
US0_CS #3
LES_CH14 #0
PCNT0_S1IN #0
LES_CH15 #0
DBG_SWO #1
DAC0_OUT1ALT #3/
OPAMP_OUT1ALT
TIM1_CC2 #0
US0_CLK #3
US1_CLK #2
LEU0_TX #3
I2C0_SDA #5
US1_CS #2
TIM0_CC0 #5
DBG_SWCLK #0/1
LETIM0_OUT0 #2
TIM0_CC1 #5
DBG_SWDIO #0/1
GPIO_EM4WU3
PF1
LEU0_RX #3
I2C0_SCL #5
LETIM0_OUT1 #2
ACMP1_O #0
DBG_SWO #0
GPIO_EM4WU4
PF2
TIM0_CC2 #5
LEU0_TX #4
28
29
IOVDD_5
PE10
Digital IO power supply 5.
TIM1_CC0 #1
TIM1_CC1 #1
US0_TX #0
US0_RX #0
BOOT_TX
LES_ALTEX5 #0
BOOT_RX
30
PE11
US0_RX #3
US0_CLK #0
I2C0_SDA #6
US0_TX #3
US0_CS #0
I2C0_SCL #6
CMU_CLK1 #2
31
PE12
TIM1_CC2 #1
LES_ALTEX6 #0
LES_ALTEX7 #0
ACMP0_O #0
32
PE13
GPIO_EM4WU5
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EFM32TG Data Sheet
Pin Definitions
5.3.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table
shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.
Table 5.8. Alternate functionality overview
Alternate
LOCATION
3
Functionality
ACMP0_CH0
ACMP0_CH1
ACMP0_O
0
1
2
4
5
6
Description
PC0
Analog comparator ACMP0, channel 0.
Analog comparator ACMP0, channel 1.
Analog comparator ACMP0, digital output.
Analog comparator ACMP1, channel 5.
Analog comparator ACMP1, channel 6.
Analog comparator ACMP1, channel 7.
Analog comparator ACMP1, digital output.
PC1
PE13
PC13
PC14
PC15
PF2
PD6
ACMP1_CH5
ACMP1_CH6
ACMP1_CH7
ACMP1_O
PD7
Analog to digital converter ADC0, input channel
number 4.
ADC0_CH4
ADC0_CH5
ADC0_CH6
ADC0_CH7
PD4
PD5
PD6
PD7
Analog to digital converter ADC0, input channel
number 5.
Analog to digital converter ADC0, input channel
number 6.
Analog to digital converter ADC0, input channel
number 7.
BOOT_RX
BOOT_TX
CMU_CLK0
CMU_CLK1
PE11
PE10
PA2
Bootloader RX.
Bootloader TX.
PD7
Clock Management Unit, clock output number 0.
Clock Management Unit, clock output number 1.
PA1
PE12
DAC0_N1/
OPAMP_N1
PD7
Operational Amplifier 1 external negative input.
DAC0_OUT0/
OPAMP_OUT0
Digital to Analog Converter DAC0_OUT0 /OPAMP
output channel number 0.
PB11
DAC0_OUT0AL
T/
Digital to Analog Converter DAC0_OUT0ALT /
OPAMP alternative output for channel 0.
PC0
PC1
OPAMP_OUT0
ALT
DAC0_OUT1AL
T/
Digital to Analog Converter DAC0_OUT1ALT /
OPAMP alternative output for channel 1.
PC13 PC14 PC15
OPAMP_OUT1
ALT
OPAMP_OUT2 PD5
Operational Amplifier 2 output.
DAC0_P1/
PD6
Operational Amplifier 1 external positive input.
Operational Amplifier 2 external positive input.
OPAMP_P1
OPAMP_P2
PD4
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EFM32TG Data Sheet
Pin Definitions
Alternate
LOCATION
3
Functionality
0
1
2
4
5
6
Description
Debug-interface Serial Wire clock input.
DBG_SWCLK
DBG_SWDIO
DBG_SWO
PF0
PF0
Note that this function is enabled to pin out of reset,
and has a built-in pull down.
Debug-interface Serial Wire data input / output.
PF1
PF2
PF1
Note that this function is enabled to pin out of reset,
and has a built-in pull up.
Debug-interface Serial Wire viewer Output.
PC15
Note that this function is not enabled after reset, and
must be enabled by software to be used.
GPIO_EM4WU0 PA0
GPIO_EM4WU3 PF1
GPIO_EM4WU4 PF2
GPIO_EM4WU5 PE13
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
High Frequency Crystal negative pin. Also used as
external optional clock input pin.
HFXTAL_N
PB14
HFXTAL_P
I2C0_SCL
PB13
PA1
High Frequency Crystal positive pin.
I2C0 Serial Clock Line input / output.
I2C0 Serial Data input / output.
LESENSE alternate exite output 0.
LESENSE alternate exite output 1.
LESENSE alternate exite output 5.
LESENSE alternate exite output 6.
LESENSE alternate exite output 7.
LESENSE channel 0.
PD7
PD6
PC1
PC0
PF1
PF0
PE13
PE12
I2C0_SDA
PA0
LES_ALTEX0
LES_ALTEX1
LES_ALTEX5
LES_ALTEX6
LES_ALTEX7
LES_CH0
PD6
PD7
PE11
PE12
PE13
PC0
LES_CH1
PC1
LESENSE channel 1.
LES_CH13
LES_CH14
LES_CH15
PC13
PC14
PC15
LESENSE channel 13.
LESENSE channel 14.
LESENSE channel 15.
LETIM0_OUT0 PD6
LETIM0_OUT1 PD7
PB11
PF0
PF1
Low Energy Timer LETIM0, output channel 0.
Low Energy Timer LETIM0, output channel 1.
LEUART0 Receive input.
LEU0_RX
LEU0_TX
PD5
PD4
PB14
PB13
PF1
PF0
PA0
PF2
LEUART0 Transmit output. Also used as receive in-
put in half duplex communication.
Low Frequency Crystal (typically 32.768 kHz) nega-
tive pin. Also used as an optional external clock in-
put pin.
LFXTAL_N
PB8
Low Frequency Crystal (typically 32.768 kHz) posi-
tive pin.
LFXTAL_P
PB7
PCNT0_S0IN
PC13
PC0
PD6
Pulse Counter PCNT0 input number 0.
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EFM32TG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
PCNT0_S1IN
PRS_CH0
PRS_CH1
PRS_CH2
PRS_CH3
TIM0_CC0
TIM0_CC1
TIM0_CC2
TIM1_CC0
TIM1_CC1
TIM1_CC2
US0_CLK
US0_CS
0
PC14
PA0
PA1
PC0
PC1
PA0
PA1
PA2
1
2
3
4
5
6
Description
PC1
PD7
Pulse Counter PCNT0 input number 1.
Peripheral Reflex System PRS, channel 0.
Peripheral Reflex System PRS, channel 1.
Peripheral Reflex System PRS, channel 2.
Peripheral Reflex System PRS, channel 3.
Timer 0 Capture Compare input / output channel 0.
Timer 0 Capture Compare input / output channel 1.
Timer 0 Capture Compare input / output channel 2.
Timer 1 Capture Compare input / output channel 0.
Timer 1 Capture Compare input / output channel 1.
Timer 1 Capture Compare input / output channel 2.
USART0 clock input / output.
PA0
PA1
PA2
PA0
PC0
PC1
PD6
PD7
PC13
PF0
PF1
PF2
PC13 PE10
PC14 PE11
PC15 PE12
PE12
PB7
PB8
PB11
PC15 PB13
PC14 PB14
PB13
PB14
PE13
USART0 chip select input / output.
USART0 Asynchronous Receive.
US0_RX
US0_TX
PE11
PE10
PE12
PE13
PB8
PB7
PC1
PC0
USART0 Synchronous mode Master Input / Slave
Output (MISO).
USART0 Asynchronous Transmit.Also used as re-
ceive input in half duplex communication.
USART0 Synchronous mode Master Output / Slave
Input (MOSI).
US1_CLK
US1_CS
PB7
PB8
PF0
PF1
USART1 clock input / output.
USART1 chip select input / output.
USART1 Asynchronous Receive.
US1_RX
US1_TX
PC1
PC0
PD6
PD7
USART1 Synchronous mode Master Input / Slave
Output (MISO).
USART1 Asynchronous Transmit.Also used as re-
ceive input in half duplex communication.
USART1 Synchronous mode Master Output / Slave
Input (MOSI).
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EFM32TG Data Sheet
Pin Definitions
5.3.3 GPIO Pinout Overview
The specific GPIO pins available in EFM32TG210 is shown in the following table. Each GPIO port is organized as 16-bit ports indicated
by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.
Table 5.9. GPIO Pinout
Port
Pin
15
Pin
14
Pin
13
Pin
12
Pin
11
Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
10
Port A
Port B
Port C
Port D
Port E
Port F
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PA2 PA1 PA0
PB14 PB13
PB11
PB8 PB7
-
-
-
-
-
-
PC15 PC14 PC13
-
-
-
-
-
-
-
PC1 PC0
-
-
-
-
-
-
-
PD7 PD6 PD5 PD4
-
-
-
-
PE13 PE12 PE11 PE10
-
-
-
-
-
-
-
-
-
-
-
-
PF2 PF1 PF0
5.3.4 Opamp Pinout Overview
The specific opamp terminals available in EFM32TG210 is shown in the following figure.
PB11
OUT0ALT
+
PC0
PC1
OPA0
OUT0
-
+
PD4
OPA2
OUT2
-
PC13
PC14
PC15
PD6
PD7
OUT1ALT
OUT1
+
OPA1
-
PD5
Figure 5.5. Opamp Pinout
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EFM32TG Data Sheet
Pin Definitions
5.4 EFM32TG222 (TQFP48)
5.4.1 Pinout
The EFM32TG222 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location
number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the
*_ROUTE register in the module in question.
Figure 5.6. EFM32TG222 Pinout (top view, not to scale)
Table 5.10. Device Pinout
QFP48 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
Analog
Timers
Communication
LEU0_RX #4
Other
PRS_CH0 #0
GPIO_EM4WU0
CMU_CLK1 #0
PRS_CH1 #0
CMU_CLK0 #0
1
PA0
TIM0_CC0 #0/1/4
I2C0_SDA #0
2
3
PA1
PA2
TIM0_CC1 #0/1
TIM0_CC2 #0/1
I2C0_SCL #0
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EFM32TG Data Sheet
Pin Definitions
QFP48 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
IOVDD_0
VSS
Analog
Digital IO power supply 0.
Ground.
Timers
Communication
Other
4
5
ACMP0_CH0
US0_TX #5
US1_TX #0
I2C0_SDA #4
US0_RX #5
US1_RX #0
I2C0_SCL #4
TIM0_CC1 #4
LES_CH0 #0
PRS_CH2 #0
6
7
PC0
PC1
PC2
PC3
PC4
DAC0_OUT0ALT #0/
OPAMP_OUT0ALT
ACMP0_CH1
PCNT0_S0IN #2
TIM0_CC2 #4
LES_CH1 #0
PRS_CH3 #0
DAC0_OUT0ALT #1/
OPAMP_OUT0ALT
ACMP0_CH2
PCNT0_S1IN #2
8
DAC0_OUT0ALT #2/
OPAMP_OUT0ALT
ACMP0_CH3
LES_CH2 #0
LES_CH3 #0
LES_CH4 #0
9
DAC0_OUT0ALT #3/
OPAMP_OUT0ALT
ACMP0_CH4
10
DAC0_P0 /
LETIM0_OUT0 #3
OPAMP_P0
US0_TX #4
US1_CLK #0
US0_RX #4
US1_CS #0
11
12
PB7
PB8
LFXTAL_P
LFXTAL_N
TIM1_CC0 #3
TIM1_CC1 #3
13
14
15
PA8
PA9
PA10
Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin
low during reset, and let the internal pull-up ensure that reset is released.
16
17
RESETn
PB11
DAC0_OUT0/
TIM1_CC2 #3
OPAMP_OUT0
LETIM0_OUT0 #1
18
19
VSS
Ground.
AVDD_1
Analog power supply 1.
HFXTAL_P
US0_CLK #4/5
LEU0_TX #1
20
21
PB13
PB14
US0_CS #4/5
LEU0_RX #1
HFXTAL_N
22
23
IOVDD_3
AVDD_0
Digital IO power supply 3.
Analog power supply 0.
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EFM32TG Data Sheet
Pin Definitions
QFP48 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
Analog
ADC0_CH4
OPAMP_P2
ADC0_CH5
OPAMP_OUT2 #0
ADC0_CH6
DAC0_P1/
Timers
Communication
Other
24
25
PD4
LEU0_TX #0
PD5
PD6
LEU0_RX #0
TIM1_CC0 #4
LETIM0_OUT0 #0
PCNT0_S0IN #3
TIM1_CC1 #4
US1_RX #2
LES_ALTEX0 #0
ACMP0_O #2
26
27
I2C0_SDA #1
OPAMP_P1
ADC0_CH7
DAC0_N1/
CMU_CLK0 #2
LES_ALTEX1 #0
ACMP1_O #2
US1_TX #2
PD7
LETIM0_OUT1 #0
PCNT0_S1IN #3
I2C0_SCL #1
OPAMP_N1
28
29
30
VDD_DREG
DECOUPLE
PC8
Power supply for on-chip voltage regulator.
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required
at this pin.
ACMP1_CH0
US0_CS #2
LES_CH8 #0
LES_CH9 #0
31
PC9
ACMP1_CH1
US0_CLK #2
GPIO_EM4WU2
LES_CH10 #0
LES_CH11 #0
32
33
PC10
PC11
ACMP1_CH2
ACMP1_CH3
US0_RX #2
US0_TX #2
ACMP1_CH5
TIM1_CC0 #0
TIM1_CC2 #4
PCNT0_S0IN #0
34
35
36
37
38
39
PC13
PC14
PC15
PF0
DAC0_OUT1ALT #1/
OPAMP_OUT1ALT
ACMP1_CH6
LES_CH13 #0
LES_CH14 #0
TIM1_CC1 #0
DAC0_OUT1ALT #2/
OPAMP_OUT1ALT
ACMP1_CH7
US0_CS #3
PCNT0_S1IN #0
LES_CH15 #0
DBG_SWO #1
DAC0_OUT1ALT #3/
OPAMP_OUT1ALT
TIM1_CC2 #0
US0_CLK #3
US1_CLK #2
LEU0_TX #3
I2C0_SDA #5
US1_CS #2
TIM0_CC0 #5
DBG_SWCLK #0/1
LETIM0_OUT0 #2
TIM0_CC1 #5
DBG_SWDIO #0/1
GPIO_EM4WU3
PF1
LEU0_RX #3
I2C0_SCL #5
LETIM0_OUT1 #2
ACMP1_O #0
DBG_SWO #0
GPIO_EM4WU4
PF2
TIM0_CC2 #5
LEU0_TX #4
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EFM32TG Data Sheet
Pin Definitions
QFP48 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
PF3
Analog
Timers
Communication
Other
40
41
42
43
44
45
PRS_CH0 #1
PRS_CH1 #1
PRS_CH2 #1
PF4
PF5
IOVDD_5
VSS
Digital IO power supply 5.
Ground.
PE10
TIM1_CC0 #1
TIM1_CC1 #1
US0_TX #0
US0_RX #0
BOOT_TX
LES_ALTEX5 #0
BOOT_RX
46
PE11
PE12
US0_RX #3
US0_CLK #0
I2C0_SDA #6
US0_TX #3
US0_CS #0
I2C0_SCL #6
CMU_CLK1 #2
47
TIM1_CC2 #1
LES_ALTEX6 #0
LES_ALTEX7 #0
ACMP0_O #0
48
PE13
GPIO_EM4WU5
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EFM32TG Data Sheet
Pin Definitions
5.4.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table
shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.
Table 5.11. Alternate functionality overview
Alternate
LOCATION
3
Functionality
ACMP0_CH0
ACMP0_CH1
ACMP0_CH2
ACMP0_CH3
ACMP0_CH4
ACMP0_O
0
1
2
4
5
6
Description
PC0
Analog comparator ACMP0, channel 0.
Analog comparator ACMP0, channel 1.
Analog comparator ACMP0, channel 2.
Analog comparator ACMP0, channel 3.
Analog comparator ACMP0, channel 4.
Analog comparator ACMP0, digital output.
Analog comparator ACMP1, channel 0.
Analog comparator ACMP1, channel 1.
Analog comparator ACMP1, channel 2.
Analog comparator ACMP1, channel 3.
Analog comparator ACMP1, channel 5.
Analog comparator ACMP1, channel 6.
Analog comparator ACMP1, channel 7.
Analog comparator ACMP1, digital output.
PC1
PC2
PC3
PC4
PE13
PC8
PD6
ACMP1_CH0
ACMP1_CH1
ACMP1_CH2
ACMP1_CH3
ACMP1_CH5
ACMP1_CH6
ACMP1_CH7
ACMP1_O
PC9
PC10
PC11
PC13
PC14
PC15
PF2
PD7
Analog to digital converter ADC0, input channel
number 4.
ADC0_CH4
ADC0_CH5
ADC0_CH6
ADC0_CH7
PD4
PD5
PD6
PD7
Analog to digital converter ADC0, input channel
number 5.
Analog to digital converter ADC0, input channel
number 6.
Analog to digital converter ADC0, input channel
number 7.
BOOT_RX
BOOT_TX
CMU_CLK0
CMU_CLK1
PE11
PE10
PA2
Bootloader RX.
Bootloader TX.
PD7
Clock Management Unit, clock output number 0.
Clock Management Unit, clock output number 1.
PA1
PE12
DAC0_N1/
OPAMP_N1
PD7
Operational Amplifier 1 external negative input.
DAC0_OUT0/
OPAMP_OUT0
Digital to Analog Converter DAC0_OUT0 /OPAMP
output channel number 0.
PB11
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EFM32TG Data Sheet
Pin Definitions
Alternate
LOCATION
3
Functionality
0
1
2
4
5
6
Description
DAC0_OUT0AL
T/
Digital to Analog Converter DAC0_OUT0ALT /
OPAMP alternative output for channel 0.
PC0
PC1
PC2
PC3
OPAMP_OUT0
ALT
DAC0_OUT1AL
T/
Digital to Analog Converter DAC0_OUT1ALT /
OPAMP alternative output for channel 1.
PC13 PC14 PC15
OPAMP_OUT1
ALT
OPAMP_OUT2 PD5
Operational Amplifier 2 output.
DAC0_P0/
PC4
Operational Amplifier 0 external positive input.
OPAMP_P0
DAC0_P1/
PD6
Operational Amplifier 1 external positive input.
OPAMP_P1
OPAMP_P2
PD4
PF0
Operational Amplifier 2 external positive input.
Debug-interface Serial Wire clock input.
DBG_SWCLK
PF0
Note that this function is enabled to pin out of reset,
and has a built-in pull down.
Debug-interface Serial Wire data input / output.
DBG_SWDIO
DBG_SWO
PF1
PF2
PF1
Note that this function is enabled to pin out of reset,
and has a built-in pull up.
Debug-interface Serial Wire viewer Output.
PC15
Note that this function is not enabled after reset, and
must be enabled by software to be used.
GPIO_EM4WU0 PA0
GPIO_EM4WU2 PC9
GPIO_EM4WU3 PF1
GPIO_EM4WU4 PF2
GPIO_EM4WU5 PE13
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
High Frequency Crystal negative pin. Also used as
external optional clock input pin.
HFXTAL_N
PB14
HFXTAL_P
I2C0_SCL
PB13
PA1
High Frequency Crystal positive pin.
I2C0 Serial Clock Line input / output.
I2C0 Serial Data input / output.
LESENSE alternate exite output 0.
LESENSE alternate exite output 1.
LESENSE alternate exite output 5.
LESENSE alternate exite output 6.
LESENSE alternate exite output 7.
LESENSE channel 0.
PD7
PD6
PC1
PC0
PF1
PF0
PE13
PE12
I2C0_SDA
PA0
LES_ALTEX0
LES_ALTEX1
LES_ALTEX5
LES_ALTEX6
LES_ALTEX7
LES_CH0
PD6
PD7
PE11
PE12
PE13
PC0
PC1
PC2
LES_CH1
LESENSE channel 1.
LES_CH2
LESENSE channel 2.
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EFM32TG Data Sheet
Pin Definitions
Alternate
LOCATION
3
Functionality
LES_CH3
LES_CH4
LES_CH8
LES_CH9
LES_CH10
LES_CH11
LES_CH13
LES_CH14
LES_CH15
0
1
2
4
5
6
Description
LESENSE channel 3.
PC3
PC4
LESENSE channel 4.
LESENSE channel 8.
LESENSE channel 9.
LESENSE channel 10.
LESENSE channel 11.
LESENSE channel 13.
LESENSE channel 14.
LESENSE channel 15.
PC8
PC9
PC10
PC11
PC13
PC14
PC15
LETIM0_OUT0 PD6
LETIM0_OUT1 PD7
PB11
PF0
PF1
PC4
Low Energy Timer LETIM0, output channel 0.
Low Energy Timer LETIM0, output channel 1.
LEUART0 Receive input.
LEU0_RX
LEU0_TX
PD5
PD4
PB14
PB13
PF1
PF0
PA0
PF2
LEUART0 Transmit output. Also used as receive in-
put in half duplex communication.
Low Frequency Crystal (typically 32.768 kHz) nega-
tive pin. Also used as an optional external clock in-
put pin.
LFXTAL_N
LFXTAL_P
PB8
PB7
Low Frequency Crystal (typically 32.768 kHz) posi-
tive pin.
PCNT0_S0IN
PCNT0_S1IN
PRS_CH0
PRS_CH1
PRS_CH2
PRS_CH3
TIM0_CC0
TIM0_CC1
TIM0_CC2
TIM1_CC0
TIM1_CC1
TIM1_CC2
US0_CLK
US0_CS
PC13
PC14
PA0
PA1
PC0
PC1
PA0
PA1
PA2
PC0
PC1
PD6
PD7
Pulse Counter PCNT0 input number 0.
Pulse Counter PCNT0 input number 1.
PF3
PF4
PF5
Peripheral Reflex System PRS, channel 0.
Peripheral Reflex System PRS, channel 1.
Peripheral Reflex System PRS, channel 2.
Peripheral Reflex System PRS, channel 3.
Timer 0 Capture Compare input / output channel 0.
Timer 0 Capture Compare input / output channel 1.
Timer 0 Capture Compare input / output channel 2.
Timer 1 Capture Compare input / output channel 0.
Timer 1 Capture Compare input / output channel 1.
Timer 1 Capture Compare input / output channel 2.
USART0 clock input / output.
PA0
PA1
PA2
PA0
PC0
PC1
PD6
PD7
PC13
PF0
PF1
PF2
PC13 PE10
PC14 PE11
PC15 PE12
PE12
PB7
PB8
PB11
PC9
PC8
PC15 PB13
PC14 PB14
PB13
PB14
PE13
USART0 chip select input / output.
USART0 Asynchronous Receive.
US0_RX
PE11
PC10 PE12
PB8
PC1
USART0 Synchronous mode Master Input / Slave
Output (MISO).
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EFM32TG Data Sheet
Pin Definitions
Alternate
LOCATION
3
Functionality
0
1
2
4
5
6
Description
USART0 Asynchronous Transmit.Also used as re-
ceive input in half duplex communication.
US0_TX
PE10
PC11 PE13
PB7
PC0
USART0 Synchronous mode Master Output / Slave
Input (MOSI).
US1_CLK
US1_CS
PB7
PB8
PF0
PF1
USART1 clock input / output.
USART1 chip select input / output.
USART1 Asynchronous Receive.
US1_RX
US1_TX
PC1
PC0
PD6
PD7
USART1 Synchronous mode Master Input / Slave
Output (MISO).
USART1 Asynchronous Transmit.Also used as re-
ceive input in half duplex communication.
USART1 Synchronous mode Master Output / Slave
Input (MOSI).
5.4.3 GPIO Pinout Overview
The specific GPIO pins available in EFM32TG222 is shown in the following table. Each GPIO port is organized as 16-bit ports indicated
by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.
Table 5.12. GPIO Pinout
Port
Pin
15
Pin
14
Pin
13
Pin
12
Pin
11
Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
10
Port A
Port B
Port C
Port D
Port E
Port F
-
-
-
-
-
-
-
-
-
PA10 PA9 PA8
-
-
-
-
-
-
-
-
-
-
-
PA2 PA1 PA0
PB14 PB13
PB11
-
-
PB8 PB7
-
-
-
PC15 PC14 PC13
PC11 PC10 PC9 PC8
-
PC4 PC3 PC2 PC1 PC0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PD7 PD6 PD5 PD4
-
-
-
-
-
-
-
-
PE13 PE12 PE11 PE10
-
-
-
-
-
-
-
-
-
-
PF5 PF4 PF3 PF2 PF1 PF0
5.4.4 Opamp Pinout Overview
The specific opamp terminals available in EFM32TG222 is shown in the following figure.
PB11
OUT0ALT
OUT0
PC4
PD4
+
PC0
PC1
PC2
PC3
OPA0
-
+
OPA2
-
OUT2
PC13
PC14
PC15
PD6
PD7
OUT1ALT
OUT1
+
OPA1
-
PD5
Figure 5.7. Opamp Pinout
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EFM32TG Data Sheet
Pin Definitions
5.5 EFM32TG225 (BGA48)
5.5.1 Pinout
The EFM32TG225 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location
number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the
*_ROUTE register in the module in question.
Figure 5.8. EFM32TG225 Pinout (top view, not to scale)
Table 5.13. Device Pinout
BGA48 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
Analog
Timers
Communication
US0_TX #3
Other
LES_ALTEX7 #0
ACMP0_O #0
GPIO_EM4WU5
A1
PE13
US0_CS #0
I2C0_SCL #6
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EFM32TG Data Sheet
Pin Definitions
BGA48 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
Analog
Timers
Communication
US0_RX #3
Other
CMU_CLK1 #2
A2
PE12
TIM1_CC2 #1
US0_CLK #0
I2C0_SDA #6
LES_ALTEX6 #0
LES_ALTEX5 #0
BOOT_RX
A3
PE11
TIM1_CC1 #1
US0_RX #0
A4
A5
PF5
PF3
PRS_CH2 #1
PRS_CH0 #1
ACMP1_CH6
DAC0_OUT1ALT #2/
OPAMP_OUT1ALT
ACMP1_CH7
TIM1_CC1 #0
A6
A7
PC14
PC15
US0_CS #3
LES_CH14 #0
PCNT0_S1IN #0
LES_CH15 #0
DBG_SWO #1
DAC0_OUT1ALT #3/
OPAMP_OUT1ALT
TIM1_CC2 #0
US0_CLK #3
I2C0_SCL #0
CMU_CLK1 #0
PRS_CH1 #0
PRS_CH0 #0
GPIO_EM4WU0
BOOT_TX
B1
B2
PA1
PA0
TIM0_CC1 #0/1
LEU0_RX #4
I2C0_SDA #0
US0_TX #0
TIM0_CC0 #0/1/4
TIM1_CC0 #1
B3
B4
PE10
PF4
PRS_CH1 #1
ACMP1_O #0
DBG_SWO #0
GPIO_EM4WU4
LES_CH11 #0
B5
B6
B7
PF2
TIM0_CC2 #5
LEU0_TX #4
US0_TX #2
PC11
PC13
ACMP1_CH3
ACMP1_CH5
TIM1_CC0 #0
TIM1_CC2 #4
PCNT0_S0IN #0
DAC0_OUT1ALT #1/
OPAMP_OUT1ALT
ACMP0_CH0
LES_CH13 #0
US0_TX #5
US1_TX #0
I2C0_SDA #4
TIM0_CC1 #4
LES_CH0 #0
PRS_CH2 #0
C1
PC0
DAC0_OUT0ALT #0/
OPAMP_OUT0ALT
PCNT0_S0IN #2
C2
C3
C4
PA2
VSS
TIM0_CC2 #0/1
CMU_CLK0 #0
Ground.
IOVDD_5
Digital IO power supply 5.
US1_CS #2
LEU0_RX #3
I2C0_SCL #5
TIM0_CC1 #5
DBG_SWDIO #0/1
GPIO_EM4WU3
C5
PF1
LETIM0_OUT1 #2
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EFM32TG Data Sheet
Pin Definitions
BGA48 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
Analog
Timers
Communication
Other
LES_CH9 #0
GPIO_EM4WU2
LES_CH10 #0
C6
C7
PC9
ACMP1_CH1
US0_CLK #2
PC10
ACMP1_CH2
ACMP0_CH1
US0_RX #2
US0_RX #5
US1_RX #0
I2C0_SCL #4
TIM0_CC2 #4
LES_CH1 #0
PRS_CH3 #0
D1
PC1
DAC0_OUT0ALT #1/
OPAMP_OUT0ALT
ACMP0_CH3
PCNT0_S1IN #2
D2
D3
D5
PC3
IOVDD_0
PF0
DAC0_OUT0ALT #3/
OPAMP_OUT0ALT
Digital IO power supply 0.
LES_CH3 #0
US1_CLK #2
LEU0_TX #3
I2C0_SDA #5
US0_CS #2
TIM0_CC0 #5
DBG_SWCLK #0/1
LES_CH8 #0
LETIM0_OUT0 #2
D6
D7
PC8
ACMP1_CH0
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required
at this pin.
DECOUPLE
ACMP0_CH2
E1
E2
PC2
PC4
DAC0_OUT0ALT #2/
OPAMP_OUT0ALT
ACMP0_CH4
LES_CH2 #0
LES_CH4 #0
DAC0_P0/
LETIM0_OUT0 #3
OPAMP_P0
E3
E4
E5
PA8
VDD_DREG
AVSS_0
Power supply for on-chip voltage regulator.
Analog ground 0.
ADC0_CH7
DAC0_N1/
OPAMP_N1
ADC0_CH6
DAC0_P1/
OPAMP_P1
TIM1_CC1 #4
LETIM0_OUT1 #0
PCNT0_S1IN #3
TIM1_CC0 #4
CMU_CLK0 #2
LES_ALTEX1 #0
ACMP1_O #2
US1_TX #2
E6
PD7
I2C0_SCL #1
US1_RX #2
LES_ALTEX0 #0
ACMP0_O #2
E7
F1
PD6
PB7
LETIM0_OUT0 #0
PCNT0_S0IN #3
I2C0_SDA #1
US0_TX #4
LFXTAL_P
TIM1_CC0 #3
US1_CLK #0
F2
F3
PA9
Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin
low during reset, and let the internal pull-up ensure that reset is released.
RESETn
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EFM32TG Data Sheet
Pin Definitions
BGA48 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
IOVDD_3
AVDD_1
AVDD_0
Analog
Timers
Communication
Other
F4
F5
F6
Digital IO power supply 3.
Analog power supply 1.
Analog power supply 0.
ADC0_CH5
F7
PD5
LEU0_RX #0
OPAMP_OUT2 #0
US0_RX #4
US1_CS #0
G1
G2
G3
G4
G5
PB8
PA10
LFXTAL_N
TIM1_CC1 #3
DAC0_OUT0/
OPAMP_OUT0
TIM1_CC2 #3
PB11
LETIM0_OUT0 #1
AVSS_1
PB13
Analog ground 1.
US0_CLK #4/5
LEU0_TX #1
US0_CS #4/5
LEU0_RX #1
HFXTAL_P
HFXTAL_N
G6
G7
PB14
PD4
ADC0_CH4
OPAMP_P2
LEU0_TX #0
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EFM32TG Data Sheet
Pin Definitions
5.5.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table
shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.
Table 5.14. Alternate functionality overview
Alternate
LOCATION
3
Functionality
ACMP0_CH0
ACMP0_CH1
ACMP0_CH2
ACMP0_CH3
ACMP0_CH4
ACMP0_O
0
1
2
4
5
6
Description
PC0
Analog comparator ACMP0, channel 0.
Analog comparator ACMP0, channel 1.
Analog comparator ACMP0, channel 2.
Analog comparator ACMP0, channel 3.
Analog comparator ACMP0, channel 4.
Analog comparator ACMP0, digital output.
Analog comparator ACMP1, channel 0.
Analog comparator ACMP1, channel 1.
Analog comparator ACMP1, channel 2.
Analog comparator ACMP1, channel 3.
Analog comparator ACMP1, channel 5.
Analog comparator ACMP1, channel 6.
Analog comparator ACMP1, channel 7.
Analog comparator ACMP1, digital output.
PC1
PC2
PC3
PC4
PE13
PC8
PD6
ACMP1_CH0
ACMP1_CH1
ACMP1_CH2
ACMP1_CH3
ACMP1_CH5
ACMP1_CH6
ACMP1_CH7
ACMP1_O
PC9
PC10
PC11
PC13
PC14
PC15
PF2
PD7
Analog to digital converter ADC0, input channel
number 4.
ADC0_CH4
ADC0_CH5
ADC0_CH6
ADC0_CH7
PD4
PD5
PD6
PD7
Analog to digital converter ADC0, input channel
number 5.
Analog to digital converter ADC0, input channel
number 6.
Analog to digital converter ADC0, input channel
number 7.
BOOT_RX
BOOT_TX
CMU_CLK0
CMU_CLK1
PE11
PE10
PA2
Bootloader RX.
Bootloader TX.
PD7
Clock Management Unit, clock output number 0.
Clock Management Unit, clock output number 1.
PA1
PE12
DAC0_N1/
OPAMP_N1
PD7
Operational Amplifier 1 external negative input.
DAC0_OUT0/
OPAMP_OUT0
Digital to Analog Converter DAC0_OUT0 /OPAMP
output channel number 0.
PB11
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EFM32TG Data Sheet
Pin Definitions
Alternate
LOCATION
3
Functionality
0
1
2
4
5
6
Description
DAC0_OUT0AL
T/
Digital to Analog Converter DAC0_OUT0ALT /
OPAMP alternative output for channel 0.
PC0
PC1
PC2
PC3
OPAMP_OUT0
ALT
DAC0_OUT1AL
T/
Digital to Analog Converter DAC0_OUT1ALT /
OPAMP alternative output for channel 1.
PC13 PC14 PC15
OPAMP_OUT1
ALT
OPAMP_OUT2 PD5
Operational Amplifier 2 output.
DAC0_P0/
PC4
Operational Amplifier 0 external positive input.
OPAMP_P0
DAC0_P1/
PD6
Operational Amplifier 1 external positive input.
OPAMP_P1
OPAMP_P2
PD4
PF0
Operational Amplifier 2 external positive input.
Debug-interface Serial Wire clock input.
DBG_SWCLK
PF0
Note that this function is enabled to pin out of reset,
and has a built-in pull down.
Debug-interface Serial Wire data input / output.
DBG_SWDIO
DBG_SWO
PF1
PF2
PF1
Note that this function is enabled to pin out of reset,
and has a built-in pull up.
Debug-interface Serial Wire viewer Output.
PC15
Note that this function is not enabled after reset, and
must be enabled by software to be used.
GPIO_EM4WU0 PA0
GPIO_EM4WU2 PC9
GPIO_EM4WU3 PF1
GPIO_EM4WU4 PF2
GPIO_EM4WU5 PE13
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
High Frequency Crystal negative pin. Also used as
external optional clock input pin.
HFXTAL_N
PB14
HFXTAL_P
I2C0_SCL
PB13
PA1
High Frequency Crystal positive pin.
I2C0 Serial Clock Line input / output.
I2C0 Serial Data input / output.
LESENSE alternate exite output 0.
LESENSE alternate exite output 1.
LESENSE alternate exite output 5.
LESENSE alternate exite output 6.
LESENSE alternate exite output 7.
LESENSE channel 0.
PD7
PD6
PC1
PC0
PF1
PF0
PE13
PE12
I2C0_SDA
PA0
LES_ALTEX0
LES_ALTEX1
LES_ALTEX5
LES_ALTEX6
LES_ALTEX7
LES_CH0
PD6
PD7
PE11
PE12
PE13
PC0
PC1
PC2
LES_CH1
LESENSE channel 1.
LES_CH2
LESENSE channel 2.
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EFM32TG Data Sheet
Pin Definitions
Alternate
LOCATION
3
Functionality
LES_CH3
LES_CH4
LES_CH8
LES_CH9
LES_CH10
LES_CH11
LES_CH13
LES_CH14
LES_CH15
0
1
2
4
5
6
Description
LESENSE channel 3.
PC3
PC4
LESENSE channel 4.
LESENSE channel 8.
LESENSE channel 9.
LESENSE channel 10.
LESENSE channel 11.
LESENSE channel 13.
LESENSE channel 14.
LESENSE channel 15.
PC8
PC9
PC10
PC11
PC13
PC14
PC15
LETIM0_OUT0 PD6
LETIM0_OUT1 PD7
PB11
PF0
PF1
PC4
Low Energy Timer LETIM0, output channel 0.
Low Energy Timer LETIM0, output channel 1.
LEUART0 Receive input.
LEU0_RX
LEU0_TX
PD5
PD4
PB14
PB13
PF1
PF0
PA0
PF2
LEUART0 Transmit output. Also used as receive in-
put in half duplex communication.
Low Frequency Crystal (typically 32.768 kHz) nega-
tive pin. Also used as an optional external clock in-
put pin.
LFXTAL_N
LFXTAL_P
PB8
PB7
Low Frequency Crystal (typically 32.768 kHz) posi-
tive pin.
PCNT0_S0IN
PCNT0_S1IN
PRS_CH0
PRS_CH1
PRS_CH2
PRS_CH3
TIM0_CC0
TIM0_CC1
TIM0_CC2
TIM1_CC0
TIM1_CC1
TIM1_CC2
US0_CLK
US0_CS
PC13
PC14
PA0
PA1
PC0
PC1
PA0
PA1
PA2
PC0
PC1
PD6
PD7
Pulse Counter PCNT0 input number 0.
Pulse Counter PCNT0 input number 1.
PF3
PF4
PF5
Peripheral Reflex System PRS, channel 0.
Peripheral Reflex System PRS, channel 1.
Peripheral Reflex System PRS, channel 2.
Peripheral Reflex System PRS, channel 3.
Timer 0 Capture Compare input / output channel 0.
Timer 0 Capture Compare input / output channel 1.
Timer 0 Capture Compare input / output channel 2.
Timer 1 Capture Compare input / output channel 0.
Timer 1 Capture Compare input / output channel 1.
Timer 1 Capture Compare input / output channel 2.
USART0 clock input / output.
PA0
PA1
PA2
PA0
PC0
PC1
PD6
PD7
PC13
PF0
PF1
PF2
PC13 PE10
PC14 PE11
PC15 PE12
PE12
PB7
PB8
PB11
PC9
PC8
PC15 PB13
PC14 PB14
PB13
PB14
PE13
USART0 chip select input / output.
USART0 Asynchronous Receive.
US0_RX
PE11
PC10 PE12
PB8
PC1
USART0 Synchronous mode Master Input / Slave
Output (MISO).
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EFM32TG Data Sheet
Pin Definitions
Alternate
LOCATION
3
Functionality
0
1
2
4
5
6
Description
USART0 Asynchronous Transmit.Also used as re-
ceive input in half duplex communication.
US0_TX
PE10
PC11 PE13
PB7
PC0
USART0 Synchronous mode Master Output / Slave
Input (MOSI).
US1_CLK
US1_CS
PB7
PB8
PF0
PF1
USART1 clock input / output.
USART1 chip select input / output.
USART1 Asynchronous Receive.
US1_RX
US1_TX
PC1
PC0
PD6
PD7
USART1 Synchronous mode Master Input / Slave
Output (MISO).
USART1 Asynchronous Transmit.Also used as re-
ceive input in half duplex communication.
USART1 Synchronous mode Master Output / Slave
Input (MOSI).
5.5.3 GPIO Pinout Overview
The specific GPIO pins available in EFM32TG225 is shown in the following table. Each GPIO port is organized as 16-bit ports indicated
by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.
Table 5.15. GPIO Pinout
Port
Pin
15
Pin
14
Pin
13
Pin
12
Pin
11
Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
10
Port A
Port B
Port C
Port D
Port E
Port F
-
-
-
-
-
-
-
-
-
PA10 PA9 PA8
-
-
-
-
-
-
-
-
-
-
-
PA2 PA1 PA0
PB14 PB13
PB11
-
-
PB8 PB7
-
-
-
PC15 PC14 PC13
PC11 PC10 PC9 PC8
-
PC4 PC3 PC2 PC1 PC0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PD7 PD6 PD5 PD4
-
-
-
-
-
-
-
-
PE13 PE12 PE11 PE10
-
-
-
-
-
-
-
-
-
-
PF5 PF4 PF3 PF2 PF1 PF0
5.5.4 Opamp Pinout Overview
The specific opamp terminals available in EFM32TG225 is shown in the following figure.
PB11
OUT0ALT
OUT0
PC4
PD4
+
PC0
PC1
PC2
PC3
OPA0
-
+
OPA2
-
OUT2
PC13
PC14
PC15
PD6
PD7
OUT1ALT
OUT1
+
OPA1
-
PD5
Figure 5.9. Opamp Pinout
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EFM32TG Data Sheet
Pin Definitions
5.6 EFM32TG230 (QFN64)
5.6.1 Pinout
The EFM32TG230 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location
number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the
*_ROUTE register in the module in question.
Figure 5.10. EFM32TG230 Pinout (top view, not to scale)
Table 5.16. Device Pinout
QFN64 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
Analog
Timers
Communication
Other
0
VSS
Ground.
LEU0_RX #4
I2C0_SDA #0
PRS_CH0 #0
GPIO_EM4WU0
CMU_CLK1 #0
PRS_CH1 #0
1
PA0
PA1
TIM0_CC0 #0/1/4
TIM0_CC1 #0/1
2
I2C0_SCL #0
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EFM32TG Data Sheet
Pin Definitions
QFN64 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
PA2
Analog
Timers
Communication
Other
3
4
5
6
7
8
TIM0_CC2 #0/1
CMU_CLK0 #0
LES_ALTEX2 #0
LES_ALTEX3 #0
LES_ALTEX4 #0
GPIO_EM4WU1
PA3
PA4
PA5
PA6
IOVDD_0
Digital IO power supply 0.
ACMP0_CH0
US0_TX #5
US1_TX #0
I2C0_SDA #4
US0_RX #5
US1_RX #0
I2C0_SCL #4
TIM0_CC1 #4
LES_CH0 #0
PRS_CH2 #0
9
PC0
PC1
PC2
PC3
PC4
PC5
DAC0_OUT0ALT #0/
OPAMP_OUT0ALT
ACMP0_CH1
PCNT0_S0IN #2
TIM0_CC2 #4
LES_CH1 #0
PRS_CH3 #0
10
11
12
13
14
DAC0_OUT0ALT #1/
OPAMP_OUT0ALT
ACMP0_CH2
PCNT0_S1IN #2
DAC0_OUT0ALT #2/
OPAMP_OUT0ALT
ACMP0_CH3
LES_CH2 #0
LES_CH3 #0
LES_CH4 #0
LES_CH5 #0
DAC0_OUT0ALT #3/
OPAMP_OUT0ALT
ACMP0_CH4
DAC0_P0/
LETIM0_OUT0 #3
LETIM0_OUT1 #3
OPAMP_P0
ACMP0_CH5
DAC0_N0/
OPAMP_N0
US0_TX #4
US1_CLK #0
US0_RX #4
US1_CS #0
15
16
PB7
PB8
LFXTAL_P
LFXTAL_N
TIM1_CC0 #3
TIM1_CC1 #3
17
18
19
PA8
PA9
PA10
Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin
low during reset, and let the internal pull-up ensure that reset is released.
20
21
RESETn
PB11
DAC0_OUT0/
TIM1_CC2 #3
OPAMP_OUT0
LETIM0_OUT0 #1
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EFM32TG Data Sheet
Pin Definitions
QFN64 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
Analog
DAC0_OUT1/
Timers
Communication
Other
22
23
24
PB12
LETIM0_OUT1 #1
OPAMP_OUT1
AVDD_1
PB13
Analog power supply 1.
US0_CLK #4/5
LEU0_TX #1
US0_CS #4/5
LEU0_RX #1
HFXTAL_P
HFXTAL_N
25
PB14
26
27
IOVDD_3
AVDD_0
Digital IO power supply 3.
Analog power supply 0.
ADC0_CH0
DAC0_OUT0ALT #4/
OPAMP_OUT0ALT
OPAMP_OUT2 #1
ADC0_CH1
28
PD0
US1_TX #1
US1_RX #1
29
PD1
DAC0_OUT1ALT #4/
OPAMP_OUT1ALT
ADC0_CH2
TIM0_CC0 #3
30
31
PD2
PD3
TIM0_CC1 #3
TIM0_CC2 #3
US1_CLK #1
US1_CS #1
ADC0_CH3
OPAMP_N2
ADC0_CH4
32
33
PD4
PD5
LEU0_TX #0
LEU0_RX #0
OPAMP_P2
ADC0_CH5
OPAMP_OUT2 #0
ADC0_CH6
TIM1_CC0 #4
LETIM0_OUT0 #0
PCNT0_S0IN #3
TIM1_CC1 #4
US1_RX #2
LES_ALTEX0 #0
ACMP0_O #2
34
35
PD6
PD7
DAC0_P1/
I2C0_SDA #1
OPAMP_P1
ADC0_CH7
CMU_CLK0 #2
LES_ALTEX1 #0
ACMP1_O #2
CMU_CLK1 #1
LES_CH6 #0
US1_TX #2
DAC0_N1/
LETIM0_OUT1 #0
PCNT0_S1IN #3
I2C0_SCL #1
OPAMP_N1
36
37
38
39
PD8
PC6
ACMP0_CH6
ACMP0_CH7
I2C0_SDA #2
I2C0_SCL #2
PC7
LES_CH7 #0
VDD_DREG
Power supply for on-chip voltage regulator.
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required
at this pin.
40
41
DECOUPLE
PC8
ACMP1_CH0
US0_CS #2
LES_CH8 #0
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EFM32TG Data Sheet
Pin Definitions
QFN64 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
Analog
Timers
Communication
Other
LES_CH9 #0
GPIO_EM4WU2
LES_CH10 #0
LES_CH11 #0
42
PC9
ACMP1_CH1
US0_CLK #2
43
44
PC10
PC11
ACMP1_CH2
ACMP1_CH3
US0_RX #2
US0_TX #2
ACMP1_CH4
CMU_CLK0 #1
LES_CH12 #0
45
46
47
48
49
50
51
PC12
PC13
PC14
PC15
PF0
DAC0_OUT1ALT #0/
OPAMP_OUT1ALT
ACMP1_CH5
TIM1_CC0 #0
TIM1_CC2 #4
PCNT0_S0IN #0
DAC0_OUT1ALT #1/
OPAMP_OUT1ALT
ACMP1_CH6
LES_CH13 #0
LES_CH14 #0
TIM1_CC1 #0
DAC0_OUT1ALT #2/
OPAMP_OUT1ALT
ACMP1_CH7
US0_CS #3
PCNT0_S1IN #0
LES_CH15 #0
DBG_SWO #1
DAC0_OUT1ALT #3/
OPAMP_OUT1ALT
TIM1_CC2 #0
US0_CLK #3
US1_CLK #2
LEU0_TX #3
I2C0_SDA #5
US1_CS #2
TIM0_CC0 #5
DBG_SWCLK #0/1
LETIM0_OUT0 #2
TIM0_CC1 #5
DBG_SWDIO #0/1
GPIO_EM4WU3
PF1
LEU0_RX #3
I2C0_SCL #5
LETIM0_OUT1 #2
ACMP1_O #0
DBG_SWO #0
GPIO_EM4WU4
PRS_CH0 #1
PRS_CH1 #1
PRS_CH2 #1
PF2
TIM0_CC2 #5
LEU0_TX #4
52
53
54
55
56
57
58
PF3
PF4
PF5
IOVDD_5
PE8
Digital IO power supply 5.
PRS_CH3 #1
PE9
PE10
TIM1_CC0 #1
TIM1_CC1 #1
US0_TX #0
US0_RX #0
BOOT_TX
LES_ALTEX5 #0
BOOT_RX
59
PE11
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EFM32TG Data Sheet
Pin Definitions
QFN64 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
Analog
Timers
Communication
US0_RX #3
Other
CMU_CLK1 #2
60
61
PE12
TIM1_CC2 #1
US0_CLK #0
I2C0_SDA #6
US0_TX #3
LES_ALTEX6 #0
LES_ALTEX7 #0
ACMP0_O #0
PE13
US0_CS #0
I2C0_SCL #6
LEU0_TX #2
LEU0_RX #2
GPIO_EM4WU5
62
63
64
PE14
PE15
PA15
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EFM32TG Data Sheet
Pin Definitions
5.6.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table
shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.
Table 5.17. Alternate functionality overview
Alternate
LOCATION
3
Functionality
ACMP0_CH0
ACMP0_CH1
ACMP0_CH2
ACMP0_CH3
ACMP0_CH4
ACMP0_CH5
ACMP0_CH6
ACMP0_CH7
ACMP0_O
0
PC0
1
2
PD6
PD7
4
5
6
Description
Analog comparator ACMP0, channel 0.
Analog comparator ACMP0, channel 1.
Analog comparator ACMP0, channel 2.
Analog comparator ACMP0, channel 3.
Analog comparator ACMP0, channel 4.
Analog comparator ACMP0, channel 5.
Analog comparator ACMP0, channel 6.
Analog comparator ACMP0, channel 7.
Analog comparator ACMP0, digital output.
Analog comparator ACMP1, channel 0.
Analog comparator ACMP1, channel 1.
Analog comparator ACMP1, channel 2.
Analog comparator ACMP1, channel 3.
Analog comparator ACMP1, channel 4.
Analog comparator ACMP1, channel 5.
Analog comparator ACMP1, channel 6.
Analog comparator ACMP1, channel 7.
Analog comparator ACMP1, digital output.
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PE13
PC8
ACMP1_CH0
ACMP1_CH1
ACMP1_CH2
ACMP1_CH3
ACMP1_CH4
ACMP1_CH5
ACMP1_CH6
ACMP1_CH7
ACMP1_O
PC9
PC10
PC11
PC12
PC13
PC14
PC15
PF2
Analog to digital converter ADC0, input channel
number 0.
ADC0_CH0
ADC0_CH1
ADC0_CH2
ADC0_CH3
ADC0_CH4
ADC0_CH5
ADC0_CH6
PD0
PD1
PD2
PD3
PD4
PD5
PD6
Analog to digital converter ADC0, input channel
number 1.
Analog to digital converter ADC0, input channel
number 2.
Analog to digital converter ADC0, input channel
number 3.
Analog to digital converter ADC0, input channel
number 4.
Analog to digital converter ADC0, input channel
number 5.
Analog to digital converter ADC0, input channel
number 6.
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EFM32TG Data Sheet
Pin Definitions
Alternate
LOCATION
3
Functionality
0
1
2
4
5
6
Description
Analog to digital converter ADC0, input channel
number 7.
ADC0_CH7
PD7
BOOT_RX
BOOT_TX
CMU_CLK0
CMU_CLK1
PE11
PE10
PA2
Bootloader RX.
Bootloader TX.
PC12 PD7
PD8 PE12
Clock Management Unit, clock output number 0.
Clock Management Unit, clock output number 1.
PA1
DAC0_N0/
OPAMP_N0
PC5
Operational Amplifier 0 external negative input.
DAC0_N1/
OPAMP_N1
PD7
PD3
PB11
Operational Amplifier 1 external negative input.
Operational Amplifier 2 external negative input.
OPAMP_N2
DAC0_OUT0/
OPAMP_OUT0
Digital to Analog Converter DAC0_OUT0 /OPAMP
output channel number 0.
DAC0_OUT0AL
T/
Digital to Analog Converter DAC0_OUT0ALT /
OPAMP alternative output for channel 0.
PC0
PC1
PC2
PC3
PD0
OPAMP_OUT0
ALT
DAC0_OUT1/
OPAMP_OUT1
Digital to Analog Converter DAC0_OUT1 /OPAMP
output channel number 1.
PB12
DAC0_OUT1AL
T/
Digital to Analog Converter DAC0_OUT1ALT /
OPAMP alternative output for channel 1.
PC12 PC13 PC14 PC15 PD1
OPAMP_OUT1
ALT
OPAMP_OUT2 PD5
PD0
Operational Amplifier 2 output.
DAC0_P0/
PC4
Operational Amplifier 0 external positive input.
OPAMP_P0
DAC0_P1/
PD6
Operational Amplifier 1 external positive input.
OPAMP_P1
OPAMP_P2
PD4
PF0
Operational Amplifier 2 external positive input.
Debug-interface Serial Wire clock input.
DBG_SWCLK
PF0
Note that this function is enabled to pin out of reset,
and has a built-in pull down.
Debug-interface Serial Wire data input / output.
DBG_SWDIO
DBG_SWO
PF1
PF2
PF1
Note that this function is enabled to pin out of reset,
and has a built-in pull up.
Debug-interface Serial Wire viewer Output.
PC15
Note that this function is not enabled after reset, and
must be enabled by software to be used.
GPIO_EM4WU0 PA0
GPIO_EM4WU1 PA6
GPIO_EM4WU2 PC9
GPIO_EM4WU3 PF1
GPIO_EM4WU4 PF2
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
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EFM32TG Data Sheet
Pin Definitions
Alternate
LOCATION
3
Functionality
0
1
2
4
5
6
Description
GPIO_EM4WU5 PE13
Pin can be used to wake the system up from EM4
High Frequency Crystal negative pin. Also used as
external optional clock input pin.
HFXTAL_N
PB14
HFXTAL_P
I2C0_SCL
PB13
PA1
High Frequency Crystal positive pin.
I2C0 Serial Clock Line input / output.
I2C0 Serial Data input / output.
LESENSE alternate exite output 0.
LESENSE alternate exite output 1.
LESENSE alternate exite output 2.
LESENSE alternate exite output 3.
LESENSE alternate exite output 4.
LESENSE alternate exite output 5.
LESENSE alternate exite output 6.
LESENSE alternate exite output 7.
LESENSE channel 0.
PD7
PD6
PC7
PC6
PC1
PC0
PF1
PF0
PE13
PE12
I2C0_SDA
LES_ALTEX0
LES_ALTEX1
LES_ALTEX2
LES_ALTEX3
LES_ALTEX4
LES_ALTEX5
LES_ALTEX6
LES_ALTEX7
LES_CH0
PA0
PD6
PD7
PA3
PA4
PA5
PE11
PE12
PE13
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
LES_CH1
LESENSE channel 1.
LES_CH2
LESENSE channel 2.
LES_CH3
LESENSE channel 3.
LES_CH4
LESENSE channel 4.
LES_CH5
LESENSE channel 5.
LES_CH6
LESENSE channel 6.
LES_CH7
LESENSE channel 7.
LES_CH8
LESENSE channel 8.
LES_CH9
LESENSE channel 9.
LES_CH10
LES_CH11
LES_CH12
LES_CH13
LES_CH14
LES_CH15
LESENSE channel 10.
LESENSE channel 11.
LESENSE channel 12.
LESENSE channel 13.
LESENSE channel 14.
LESENSE channel 15.
LETIM0_OUT0 PD6
LETIM0_OUT1 PD7
PB11
PB12
PB14
PF0
PC4
PC5
PF1
Low Energy Timer LETIM0, output channel 0.
Low Energy Timer LETIM0, output channel 1.
LEUART0 Receive input.
PF1
LEU0_RX
LEU0_TX
PD5
PD4
PE15
PA0
PF2
LEUART0 Transmit output. Also used as receive in-
put in half duplex communication.
PB13
PE14
PF0
Low Frequency Crystal (typically 32.768 kHz) nega-
tive pin. Also used as an optional external clock in-
put pin.
LFXTAL_N
PB8
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EFM32TG Data Sheet
Pin Definitions
Alternate
LOCATION
3
Functionality
0
1
2
4
5
6
Description
Low Frequency Crystal (typically 32.768 kHz) posi-
tive pin.
LFXTAL_P
PB7
PCNT0_S0IN
PCNT0_S1IN
PRS_CH0
PRS_CH1
PRS_CH2
PRS_CH3
TIM0_CC0
TIM0_CC1
TIM0_CC2
TIM1_CC0
TIM1_CC1
TIM1_CC2
US0_CLK
US0_CS
PC13
PC14
PA0
PA1
PC0
PC1
PA0
PA1
PA2
PC0
PC1
PD6
PD7
Pulse Counter PCNT0 input number 0.
Pulse Counter PCNT0 input number 1.
PF3
PF4
PF5
PE8
PA0
PA1
PA2
Peripheral Reflex System PRS, channel 0.
Peripheral Reflex System PRS, channel 1.
Peripheral Reflex System PRS, channel 2.
Peripheral Reflex System PRS, channel 3.
Timer 0 Capture Compare input / output channel 0.
Timer 0 Capture Compare input / output channel 1.
Timer 0 Capture Compare input / output channel 2.
Timer 1 Capture Compare input / output channel 0.
Timer 1 Capture Compare input / output channel 1.
Timer 1 Capture Compare input / output channel 2.
USART0 clock input / output.
PD1
PD2
PD3
PB7
PB8
PB11
PA0
PC0
PC1
PD6
PD7
PC13
PF0
PF1
PF2
PC13 PE10
PC14 PE11
PC15 PE12
PE12
PC9
PC8
PC15 PB13
PC14 PB14
PB13
PB14
PE13
USART0 chip select input / output.
USART0 Asynchronous Receive.
US0_RX
US0_TX
PE11
PE10
PC10 PE12
PC11 PE13
PB8
PB7
PC1
PC0
USART0 Synchronous mode Master Input / Slave
Output (MISO).
USART0 Asynchronous Transmit.Also used as re-
ceive input in half duplex communication.
USART0 Synchronous mode Master Output / Slave
Input (MOSI).
US1_CLK
US1_CS
PB7
PB8
PD2
PD3
PF0
PF1
USART1 clock input / output.
USART1 chip select input / output.
USART1 Asynchronous Receive.
US1_RX
US1_TX
PC1
PC0
PD1
PD0
PD6
PD7
USART1 Synchronous mode Master Input / Slave
Output (MISO).
USART1 Asynchronous Transmit.Also used as re-
ceive input in half duplex communication.
USART1 Synchronous mode Master Output / Slave
Input (MOSI).
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EFM32TG Data Sheet
Pin Definitions
5.6.3 GPIO Pinout Overview
The specific GPIO pins available in EFM32TG230 is shown in the following table. Each GPIO port is organized as 16-bit ports indicated
by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.
Table 5.18. GPIO Pinout
Port
Pin
15
Pin
14
Pin
13
Pin
12
Pin
11
Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
10
Port A
Port B
Port C
Port D
Port E
Port F
PA15
-
-
-
-
-
PA10 PA9 PA8
-
PA6 PA5 PA4 PA3 PA2 PA1 PA0
PB14 PB13 PB12 PB11
-
-
PB8 PB7
-
-
-
-
-
-
-
PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
-
-
-
-
-
-
-
PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PF5 PF4 PF3 PF2 PF1 PF0
5.6.4 Opamp Pinout Overview
The specific opamp terminals available in EFM32TG230 is shown in the following figure.
PB11
PB12
PC0
OUT0ALT
OUT0
PC4
PC5
+
OPA0
-
PC1
PC2
PC3
+
PD4
PD3
PC12
PC13
PC14
PC15
PD0
OPA2
-
OUT2
PD6
PD7
OUT1ALT
OUT1
+
OPA1
-
PD1
PD5
Figure 5.11. Opamp Pinout
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EFM32TG Data Sheet
Pin Definitions
5.7 EFM32TG232 (TQFP64)
5.7.1 Pinout
The EFM32TG232 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location
number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the
*_ROUTE register in the module in question.
Figure 5.12. EFM32TG232 Pinout (top view, not to scale)
Table 5.19. Device Pinout
QFP64 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
Analog
Timers
Communication
LEU0_RX #4
Other
PRS_CH0 #0
GPIO_EM4WU0
CMU_CLK1 #0
PRS_CH1 #0
CMU_CLK0 #0
1
PA0
TIM0_CC0 #0/1/4
I2C0_SDA #0
2
3
PA1
PA2
TIM0_CC1 #0/1
TIM0_CC2 #0/1
I2C0_SCL #0
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EFM32TG Data Sheet
Pin Definitions
QFP64 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
PA3
Analog
Timers
Communication
Other
4
5
6
7
8
LES_ALTEX2 #0
LES_ALTEX3 #0
LES_ALTEX4 #0
PA4
PA5
IOVDD_0
VSS
Digital IO power supply 0.
Ground.
ACMP0_CH0
US0_TX #5
US1_TX #0
I2C0_SDA #4
US0_RX #5
US1_RX #0
I2C0_SCL #4
TIM0_CC1 #4
LES_CH0 #0
PRS_CH2 #0
9
PC0
PC1
PC2
PC3
PC4
PC5
DAC0_OUT0ALT #0/
OPAMP_OUT0ALT
ACMP0_CH1
PCNT0_S0IN #2
TIM0_CC2 #4
LES_CH1 #0
PRS_CH3 #0
10
11
12
13
14
DAC0_OUT0ALT #1/
OPAMP_OUT0ALT
ACMP0_CH2
PCNT0_S1IN #2
DAC0_OUT0ALT #2/
OPAMP_OUT0ALT
ACMP0_CH3
LES_CH2 #0
LES_CH3 #0
LES_CH4 #0
LES_CH5 #0
DAC0_OUT0ALT #3/
OPAMP_OUT0ALT
ACMP0_CH4
DAC0_P0/
LETIM0_OUT0 #3
LETIM0_OUT1 #3
OPAMP_P0
ACMP0_CH5
DAC0_N0/
OPAMP_N0
US0_TX #4
US1_CLK #0
US0_RX #4
US1_CS #0
15
16
PB7
PB8
LFXTAL_P
LFXTAL_N
TIM1_CC0 #3
TIM1_CC1 #3
17
18
19
PA8
PA9
PA10
Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin
low during reset, and let the internal pull-up ensure that reset is released.
20
21
RESETn
PB11
DAC0_OUT0/
TIM1_CC2 #3
OPAMP_OUT0
LETIM0_OUT0 #1
22
23
VSS
Ground.
Analog power supply 1.
AVDD_1
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EFM32TG Data Sheet
Pin Definitions
QFP64 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
Analog
Timers
Communication
US0_CLK #4/5
LEU0_TX #1
Other
24
25
PB13
HFXTAL_P
US0_CS #4/5
LEU0_RX #1
PB14
HFXTAL_N
26
27
IOVDD_3
AVDD_0
Digital IO power supply 3.
Analog power supply 0.
ADC0_CH0
DAC0_OUT0ALT #4/
OPAMP_OUT0ALT
OPAMP_OUT2 #1
ADC0_CH1
28
PD0
US1_TX #1
US1_RX #1
29
PD1
DAC0_OUT1ALT #4/
OPAMP_OUT1ALT
ADC0_CH2
TIM0_CC0 #3
30
31
PD2
PD3
TIM0_CC1 #3
TIM0_CC2 #3
US1_CLK #1
US1_CS #1
ADC0_CH3
OPAMP_N2
ADC0_CH4
32
33
PD4
PD5
LEU0_TX #0
LEU0_RX #0
OPAMP_P2
ADC0_CH5
OPAMP_OUT2 #0
ADC0_CH6
TIM1_CC0 #4
LETIM0_OUT0 #0
PCNT0_S0IN #3
TIM1_CC1 #4
US1_RX #2
LES_ALTEX0 #0
ACMP0_O #2
34
35
PD6
PD7
DAC0_P1/
I2C0_SDA #1
OPAMP_P1
ADC0_CH7
CMU_CLK0 #2
LES_ALTEX1 #0
ACMP1_O #2
CMU_CLK1 #1
LES_CH6 #0
US1_TX #2
DAC0_N1/
LETIM0_OUT1 #0
PCNT0_S1IN #3
I2C0_SCL #1
OPAMP_N1
36
37
38
39
PD8
PC6
ACMP0_CH6
ACMP0_CH7
I2C0_SDA #2
I2C0_SCL #2
PC7
LES_CH7 #0
VDD_DREG
Power supply for on-chip voltage regulator.
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required
at this pin.
40
41
DECOUPLE
PC8
ACMP1_CH0
ACMP1_CH1
ACMP1_CH2
US0_CS #2
US0_CLK #2
US0_RX #2
LES_CH8 #0
LES_CH9 #0
42
43
PC9
GPIO_EM4WU2
LES_CH10 #0
PC10
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EFM32TG Data Sheet
Pin Definitions
QFP64 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
Analog
Timers
Communication
Other
44
45
PC11
ACMP1_CH3
US0_TX #2
LES_CH11 #0
ACMP1_CH4
CMU_CLK0 #1
LES_CH12 #0
PC12
PC13
PC14
PC15
PF0
DAC0_OUT1ALT #0/
OPAMP_OUT1ALT
ACMP1_CH5
TIM1_CC0 #0
TIM1_CC2 #4
PCNT0_S0IN #0
46
47
48
49
50
51
DAC0_OUT1ALT #1/
OPAMP_OUT1ALT
ACMP1_CH6
LES_CH13 #0
LES_CH14 #0
TIM1_CC1 #0
DAC0_OUT1ALT #2/
OPAMP_OUT1ALT
ACMP1_CH7
US0_CS #3
PCNT0_S1IN #0
LES_CH15 #0
DBG_SWO #1
DAC0_OUT1ALT #3/
OPAMP_OUT1ALT
TIM1_CC2 #0
US0_CLK #3
US1_CLK #2
LEU0_TX #3
I2C0_SDA #5
US1_CS #2
TIM0_CC0 #5
DBG_SWCLK #0/1
LETIM0_OUT0 #2
TIM0_CC1 #5
DBG_SWDIO #0/1
GPIO_EM4WU3
PF1
LEU0_RX #3
I2C0_SCL #5
LETIM0_OUT1 #2
ACMP1_O #0
DBG_SWO #0
GPIO_EM4WU4
PRS_CH0 #1
PRS_CH1 #1
PRS_CH2 #1
PF2
TIM0_CC2 #5
LEU0_TX #4
52
53
54
55
56
57
58
59
PF3
PF4
PF5
IOVDD_5
VSS
Digital IO power supply 5.
Ground.
PE8
PRS_CH3 #1
PE9
PE10
TIM1_CC0 #1
TIM1_CC1 #1
US0_TX #0
US0_RX #0
BOOT_TX
LES_ALTEX5 #0
BOOT_RX
60
PE11
PE12
US0_RX #3
US0_CLK #0
I2C0_SDA #6
CMU_CLK1 #2
61
TIM1_CC2 #1
LES_ALTEX6 #0
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EFM32TG Data Sheet
Pin Definitions
QFP64 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
Analog
Timers
Communication
US0_TX #3
Other
LES_ALTEX7 #0
ACMP0_O #0
GPIO_EM4WU5
62
PE13
US0_CS #0
I2C0_SCL #6
LEU0_TX #2
LEU0_RX #2
63
64
PE14
PE15
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EFM32TG Data Sheet
Pin Definitions
5.7.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table
shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.
Table 5.20. Alternate functionality overview
Alternate
LOCATION
3
Functionality
ACMP0_CH0
ACMP0_CH1
ACMP0_CH2
ACMP0_CH3
ACMP0_CH4
ACMP0_CH5
ACMP0_CH6
ACMP0_CH7
ACMP0_O
0
PC0
1
2
PD6
PD7
4
5
6
Description
Analog comparator ACMP0, channel 0.
Analog comparator ACMP0, channel 1.
Analog comparator ACMP0, channel 2.
Analog comparator ACMP0, channel 3.
Analog comparator ACMP0, channel 4.
Analog comparator ACMP0, channel 5.
Analog comparator ACMP0, channel 6.
Analog comparator ACMP0, channel 7.
Analog comparator ACMP0, digital output.
Analog comparator ACMP1, channel 0.
Analog comparator ACMP1, channel 1.
Analog comparator ACMP1, channel 2.
Analog comparator ACMP1, channel 3.
Analog comparator ACMP1, channel 4.
Analog comparator ACMP1, channel 5.
Analog comparator ACMP1, channel 6.
Analog comparator ACMP1, channel 7.
Analog comparator ACMP1, digital output.
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PE13
PC8
ACMP1_CH0
ACMP1_CH1
ACMP1_CH2
ACMP1_CH3
ACMP1_CH4
ACMP1_CH5
ACMP1_CH6
ACMP1_CH7
ACMP1_O
PC9
PC10
PC11
PC12
PC13
PC14
PC15
PF2
Analog to digital converter ADC0, input channel
number 0.
ADC0_CH0
ADC0_CH1
ADC0_CH2
ADC0_CH3
ADC0_CH4
ADC0_CH5
ADC0_CH6
PD0
PD1
PD2
PD3
PD4
PD5
PD6
Analog to digital converter ADC0, input channel
number 1.
Analog to digital converter ADC0, input channel
number 2.
Analog to digital converter ADC0, input channel
number 3.
Analog to digital converter ADC0, input channel
number 4.
Analog to digital converter ADC0, input channel
number 5.
Analog to digital converter ADC0, input channel
number 6.
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EFM32TG Data Sheet
Pin Definitions
Alternate
LOCATION
3
Functionality
0
1
2
4
5
6
Description
Analog to digital converter ADC0, input channel
number 7.
ADC0_CH7
PD7
BOOT_RX
BOOT_TX
CMU_CLK0
CMU_CLK1
PE11
PE10
PA2
Bootloader RX.
Bootloader TX.
PC12 PD7
PD8 PE12
Clock Management Unit, clock output number 0.
Clock Management Unit, clock output number 1.
PA1
DAC0_N0/
OPAMP_N0
PC5
Operational Amplifier 0 external negative input.
DAC0_N1/
OPAMP_N1
PD7
PD3
PB11
Operational Amplifier 1 external negative input.
Operational Amplifier 2 external negative input.
OPAMP_N2
DAC0_OUT0/
OPAMP_OUT0
Digital to Analog Converter DAC0_OUT0 /OPAMP
output channel number 0.
DAC0_OUT0AL
T/
Digital to Analog Converter DAC0_OUT0ALT /
OPAMP alternative output for channel 0.
PC0
PC1
PC2
PC3
PD0
OPAMP_OUT0
ALT
DAC0_OUT1AL
T/
Digital to Analog Converter DAC0_OUT1ALT /
OPAMP alternative output for channel 1.
PC12 PC13 PC14 PC15 PD1
OPAMP_OUT1
ALT
OPAMP_OUT2 PD5
PD0
Operational Amplifier 2 output.
DAC0_P0/
PC4
Operational Amplifier 0 external positive input.
OPAMP_P0
DAC0_P1/
PD6
Operational Amplifier 1 external positive input.
OPAMP_P1
OPAMP_P2
PD4
PF0
Operational Amplifier 2 external positive input.
Debug-interface Serial Wire clock input.
DBG_SWCLK
PF0
Note that this function is enabled to pin out of reset,
and has a built-in pull down.
Debug-interface Serial Wire data input / output.
DBG_SWDIO
DBG_SWO
PF1
PF2
PF1
Note that this function is enabled to pin out of reset,
and has a built-in pull up.
Debug-interface Serial Wire viewer Output.
PC15
Note that this function is not enabled after reset, and
must be enabled by software to be used.
GPIO_EM4WU0 PA0
GPIO_EM4WU2 PC9
GPIO_EM4WU3 PF1
GPIO_EM4WU4 PF2
GPIO_EM4WU5 PE13
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
High Frequency Crystal negative pin. Also used as
external optional clock input pin.
HFXTAL_N
PB14
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EFM32TG Data Sheet
Pin Definitions
Alternate
LOCATION
3
Functionality
HFXTAL_P
I2C0_SCL
0
PB13
PA1
1
2
4
5
6
Description
High Frequency Crystal positive pin.
I2C0 Serial Clock Line input / output.
I2C0 Serial Data input / output.
LESENSE alternate exite output 0.
LESENSE alternate exite output 1.
LESENSE alternate exite output 2.
LESENSE alternate exite output 3.
LESENSE alternate exite output 4.
LESENSE alternate exite output 5.
LESENSE alternate exite output 6.
LESENSE alternate exite output 7.
LESENSE channel 0.
PD7
PD6
PC7
PC6
PC1
PC0
PF1
PF0
PE13
PE12
I2C0_SDA
LES_ALTEX0
LES_ALTEX1
LES_ALTEX2
LES_ALTEX3
LES_ALTEX4
LES_ALTEX5
LES_ALTEX6
LES_ALTEX7
LES_CH0
PA0
PD6
PD7
PA3
PA4
PA5
PE11
PE12
PE13
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
LES_CH1
LESENSE channel 1.
LES_CH2
LESENSE channel 2.
LES_CH3
LESENSE channel 3.
LES_CH4
LESENSE channel 4.
LES_CH5
LESENSE channel 5.
LES_CH6
LESENSE channel 6.
LES_CH7
LESENSE channel 7.
LES_CH8
LESENSE channel 8.
LES_CH9
LESENSE channel 9.
LES_CH10
LES_CH11
LES_CH12
LES_CH13
LES_CH14
LES_CH15
LESENSE channel 10.
LESENSE channel 11.
LESENSE channel 12.
LESENSE channel 13.
LESENSE channel 14.
LESENSE channel 15.
LETIM0_OUT0 PD6
LETIM0_OUT1 PD7
PB11
PF0
PC4
PC5
PF1
Low Energy Timer LETIM0, output channel 0.
Low Energy Timer LETIM0, output channel 1.
LEUART0 Receive input.
PF1
LEU0_RX
LEU0_TX
PD5
PD4
PB14
PB13
PE15
PA0
PF2
LEUART0 Transmit output. Also used as receive in-
put in half duplex communication.
PE14
PF0
Low Frequency Crystal (typically 32.768 kHz) nega-
tive pin. Also used as an optional external clock in-
put pin.
LFXTAL_N
PB8
Low Frequency Crystal (typically 32.768 kHz) posi-
tive pin.
LFXTAL_P
PB7
PCNT0_S0IN
PC13
PC0
PD6
Pulse Counter PCNT0 input number 0.
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EFM32TG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
PCNT0_S1IN
PRS_CH0
PRS_CH1
PRS_CH2
PRS_CH3
TIM0_CC0
TIM0_CC1
TIM0_CC2
TIM1_CC0
TIM1_CC1
TIM1_CC2
US0_CLK
US0_CS
0
PC14
PA0
PA1
PC0
PC1
PA0
PA1
PA2
1
2
3
4
5
6
Description
PC1
PD7
Pulse Counter PCNT0 input number 1.
PF3
PF4
PF5
PE8
PA0
PA1
PA2
Peripheral Reflex System PRS, channel 0.
Peripheral Reflex System PRS, channel 1.
Peripheral Reflex System PRS, channel 2.
Peripheral Reflex System PRS, channel 3.
Timer 0 Capture Compare input / output channel 0.
Timer 0 Capture Compare input / output channel 1.
Timer 0 Capture Compare input / output channel 2.
Timer 1 Capture Compare input / output channel 0.
Timer 1 Capture Compare input / output channel 1.
Timer 1 Capture Compare input / output channel 2.
USART0 clock input / output.
PD1
PD2
PD3
PB7
PB8
PB11
PA0
PC0
PC1
PD6
PD7
PC13
PF0
PF1
PF2
PC13 PE10
PC14 PE11
PC15 PE12
PE12
PC9
PC8
PC15 PB13
PC14 PB14
PB13
PB14
PE13
USART0 chip select input / output.
USART0 Asynchronous Receive.
US0_RX
US0_TX
PE11
PE10
PC10 PE12
PC11 PE13
PB8
PB7
PC1
PC0
USART0 Synchronous mode Master Input / Slave
Output (MISO).
USART0 Asynchronous Transmit.Also used as re-
ceive input in half duplex communication.
USART0 Synchronous mode Master Output / Slave
Input (MOSI).
US1_CLK
US1_CS
PB7
PB8
PD2
PD3
PF0
PF1
USART1 clock input / output.
USART1 chip select input / output.
USART1 Asynchronous Receive.
US1_RX
US1_TX
PC1
PC0
PD1
PD0
PD6
PD7
USART1 Synchronous mode Master Input / Slave
Output (MISO).
USART1 Asynchronous Transmit.Also used as re-
ceive input in half duplex communication.
USART1 Synchronous mode Master Output / Slave
Input (MOSI).
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EFM32TG Data Sheet
Pin Definitions
5.7.3 GPIO Pinout Overview
The specific GPIO pins available in EFM32TG232 is shown in the following table. Each GPIO port is organized as 16-bit ports indicated
by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.
Table 5.21. GPIO Pinout
Port
Pin
15
Pin
14
Pin
13
Pin
12
Pin
11
Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
10
Port A
Port B
Port C
Port D
Port E
Port F
-
-
-
-
-
-
-
PA10 PA9 PA8
-
-
-
PA5 PA4 PA3 PA2 PA1 PA0
PB14 PB13
PB11
-
-
PB8 PB7
-
-
-
-
-
-
PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
-
-
-
-
-
-
-
PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PF5 PF4 PF3 PF2 PF1 PF0
5.7.4 Opamp Pinout Overview
The specific opamp terminals available in EFM32TG232 is shown in the following figure.
PB11
PB12
PC0
OUT0ALT
OUT0
PC4
PC5
+
OPA0
-
PC1
PC2
PC3
+
PD4
PD3
PC12
PC13
PC14
PC15
PD0
OPA2
-
OUT2
PD6
PD7
OUT1ALT
OUT1
+
OPA1
-
PD1
PD5
Figure 5.13. Opamp Pinout
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EFM32TG Data Sheet
Pin Definitions
5.8 EFM32TG822 (TQFP48)
5.8.1 Pinout
The EFM32TG822 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location
number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the
*_ROUTE register in the module in question.
Figure 5.14. EFM32TG822 Pinout (top view, not to scale)
Table 5.22. Device Pinout
QFP48 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
Analog
Timers
Communication
LEU0_RX #4
Other
PRS_CH0 #0
GPIO_EM4WU0
CMU_CLK1 #0
PRS_CH1 #0
CMU_CLK0 #0
1
PA0
LCD_SEG13
TIM0_CC0 #0/1/4
I2C0_SDA #0
2
3
PA1
PA2
LCD_SEG14
LCD_SEG15
TIM0_CC1 #0/1
TIM0_CC2 #0/1
I2C0_SCL #0
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EFM32TG Data Sheet
Pin Definitions
QFP48 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
IOVDD_0
VSS
Analog
Digital IO power supply 0.
Ground.
Timers
Communication
Other
4
5
LCD_SEG20/
LCD_COM4
6
7
8
9
PB3
PB4
PB5
PB6
LCD_SEG21/
LCD_COM5
LCD_SEG22/
LCD_COM6
LCD_SEG23/
LCD_COM7
ACMP0_CH4
DAC0_P0/
10
PC4
LETIM0_OUT0 #3
LES_CH4 #0
OPAMP_P0
US0_TX #4
US1_CLK #0
US0_RX #4
US1_CS #0
11
12
PB7
PB8
LFXTAL_P
LFXTAL_N
TIM1_CC0 #3
TIM1_CC1 #3
13
14
15
PA12
PA13
PA14
LCD_BCAP_P
LCD_BCAP_N
LCD_BEXT
Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin
low during reset, and let the internal pull-up ensure that reset is released.
16
17
RESETn
PB11
DAC0_OUT0/
TIM1_CC2 #3
OPAMP_OUT0
LETIM0_OUT0 #1
18
19
VSS
Ground.
AVDD_1
Analog power supply 1.
US0_CLK #4/5
LEU0_TX #1
US0_CS #4/5
LEU0_RX #1
20
21
PB13
PB14
HFXTAL_P
HFXTAL_N
22
23
IOVDD_3
AVDD_0
Digital IO power supply 3.
Analog power supply 0.
ADC0_CH4
24
25
PD4
PD5
LEU0_TX #0
LEU0_RX #0
OPAMP_P2
ADC0_CH5
OPAMP_OUT2 #0
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EFM32TG Data Sheet
Pin Definitions
QFP48 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
Analog
Timers
Communication
Other
ADC0_CH6
DAC0_P1/
OPAMP_P1
ADC0_CH7
DAC0_N1/
OPAMP_N1
TIM1_CC0 #4
US1_RX #2
LES_ALTEX0 #0
ACMP0_O #2
26
27
PD6
LETIM0_OUT0 #0
PCNT0_S0IN #3
TIM1_CC1 #4
I2C0_SDA #1
CMU_CLK0 #2
LES_ALTEX1 #0
ACMP1_O #2
US1_TX #2
PD7
LETIM0_OUT1 #0
PCNT0_S1IN #3
I2C0_SCL #1
28
29
VDD_DREG
DECOUPLE
Power supply for on-chip voltage regulator.
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required
at this pin.
30
31
32
33
PE4
PE5
PE6
PE7
LCD_COM0
LCD_COM1
US0_CS #1
US0_CLK #1
US0_RX #1
US0_TX #1
LCD_COM2
LCD_COM3
ACMP1_CH5
TIM1_CC0 #0
TIM1_CC2 #4
PCNT0_S0IN #0
34
35
36
37
38
39
PC13
PC14
PC15
PF0
DAC0_OUT1ALT #1/
OPAMP_OUT1ALT
ACMP1_CH6
LES_CH13 #0
LES_CH14 #0
TIM1_CC1 #0
DAC0_OUT1ALT #2/
OPAMP_OUT1ALT
ACMP1_CH7
US0_CS #3
PCNT0_S1IN #0
LES_CH15 #0
DBG_SWO #1
DAC0_OUT1ALT #3/
OPAMP_OUT1ALT
TIM1_CC2 #0
US0_CLK #3
US1_CLK #2
LEU0_TX #3
I2C0_SDA #5
US1_CS #2
TIM0_CC0 #5
DBG_SWCLK #0/1
LETIM0_OUT0 #2
TIM0_CC1 #5
DBG_SWDIO #0/1
GPIO_EM4WU3
PF1
LEU0_RX #3
I2C0_SCL #5
LETIM0_OUT1 #2
ACMP1_O #0
DBG_SWO #0
GPIO_EM4WU4
PRS_CH0 #1
PRS_CH1 #1
PRS_CH2 #1
PF2
LCD_SEG0
TIM0_CC2 #5
LEU0_TX #4
40
41
42
43
44
PF3
PF4
LCD_SEG1
LCD_SEG2
PF5
LCD_SEG3
IOVDD_5
VSS
Digital IO power supply 5.
Ground.
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EFM32TG Data Sheet
Pin Definitions
QFP48 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
Analog
Timers
Communication
Other
BOOT_TX
45
PE10
LCD_SEG6
TIM1_CC0 #1
US0_TX #0
LES_ALTEX5 #0
BOOT_RX
46
PE11
PE12
LCD_SEG7
LCD_SEG8
TIM1_CC1 #1
TIM1_CC2 #1
US0_RX #0
US0_RX #3
US0_CLK #0
I2C0_SDA #6
US0_TX #3
US0_CS #0
I2C0_SCL #6
CMU_CLK1 #2
47
48
LES_ALTEX6 #0
LES_ALTEX7 #0
ACMP0_O #0
PE13
LCD_SEG9
GPIO_EM4WU5
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EFM32TG Data Sheet
Pin Definitions
5.8.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table
shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.
Table 5.23. Alternate functionality overview
Alternate
LOCATION
3
Functionality
ACMP0_CH4
ACMP0_O
0
1
2
4
5
6
Description
PC4
Analog comparator ACMP0, channel 4.
Analog comparator ACMP0, digital output.
Analog comparator ACMP1, channel 5.
Analog comparator ACMP1, channel 6.
Analog comparator ACMP1, channel 7.
Analog comparator ACMP1, digital output.
PE13
PC13
PC14
PC15
PF2
PD6
ACMP1_CH5
ACMP1_CH6
ACMP1_CH7
ACMP1_O
PD7
Analog to digital converter ADC0, input channel
number 4.
ADC0_CH4
ADC0_CH5
ADC0_CH6
ADC0_CH7
PD4
PD5
PD6
PD7
Analog to digital converter ADC0, input channel
number 5.
Analog to digital converter ADC0, input channel
number 6.
Analog to digital converter ADC0, input channel
number 7.
BOOT_RX
BOOT_TX
CMU_CLK0
CMU_CLK1
PE11
PE10
PA2
Bootloader RX.
Bootloader TX.
PD7
Clock Management Unit, clock output number 0.
Clock Management Unit, clock output number 1.
PA1
PE12
DAC0_N1/
OPAMP_N1
PD7
Operational Amplifier 1 external negative input.
DAC0_OUT0/
OPAMP_OUT0
Digital to Analog Converter DAC0_OUT0 /OPAMP
output channel number 0.
PB11
DAC0_OUT1AL
T/
Digital to Analog Converter DAC0_OUT1ALT /
OPAMP alternative output for channel 1.
PC13 PC14 PC15
OPAMP_OUT1
ALT
OPAMP_OUT2 PD5
Operational Amplifier 2 output.
DAC0_P0/
PC4
Operational Amplifier 0 external positive input.
OPAMP_P0
DAC0_P1/
PD6
Operational Amplifier 1 external positive input.
OPAMP_P1
OPAMP_P2
PD4
PF0
Operational Amplifier 2 external positive input.
Debug-interface Serial Wire clock input.
DBG_SWCLK
PF0
Note that this function is enabled to pin out of reset,
and has a built-in pull down.
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EFM32TG Data Sheet
Pin Definitions
Alternate
LOCATION
3
Functionality
0
1
2
4
5
6
Description
Debug-interface Serial Wire data input / output.
DBG_SWDIO
DBG_SWO
PF1
PF1
Note that this function is enabled to pin out of reset,
and has a built-in pull up.
Debug-interface Serial Wire viewer Output.
PF2
PC15
Note that this function is not enabled after reset, and
must be enabled by software to be used.
GPIO_EM4WU0 PA0
GPIO_EM4WU3 PF1
GPIO_EM4WU4 PF2
GPIO_EM4WU5 PE13
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
High Frequency Crystal negative pin. Also used as
external optional clock input pin.
HFXTAL_N
PB14
HFXTAL_P
I2C0_SCL
I2C0_SDA
PB13
PA1
PA0
High Frequency Crystal positive pin.
I2C0 Serial Clock Line input / output.
I2C0 Serial Data input / output.
PD7
PD6
PF1
PF0
PE13
PE12
LCD voltage booster (optional), boost capacitor,
negative pin. If using the LCD voltage booster, con-
nect a 22 nF capacitor between LCD_BCAP_N and
LCD_BCAP_P.
LCD_BCAP_N PA13
LCD_BCAP_P PA12
LCD voltage booster (optional), boost capacitor,
positive pin. If using the LCD voltage booster, con-
nect a 22 nF capacitor between LCD_BCAP_N and
LCD_BCAP_P.
LCD voltage booster (optional), boost output. If us-
ing the LCD voltage booster, connect a 1 uF capaci-
tor between this pin and VSS.
LCD_BEXT
PA14
An external LCD voltage may also be applied to this
pin if the booster is not enabled.
If AVDD is used directly as the LCD supply voltage,
this pin may be left unconnected or used as a GPIO.
LCD_COM0
LCD_COM1
LCD_COM2
LCD_COM3
PE4
PE5
PE6
PE7
LCD driver common line number 0.
LCD driver common line number 1.
LCD driver common line number 2.
LCD driver common line number 3.
LCD segment line 0. Segments 0, 1, 2 and 3 are
controlled by SEGEN0.
LCD_SEG0
LCD_SEG1
LCD_SEG2
LCD_SEG3
PF2
PF3
PF4
PF5
LCD segment line 1. Segments 0, 1, 2 and 3 are
controlled by SEGEN0.
LCD segment line 2. Segments 0, 1, 2 and 3 are
controlled by SEGEN0.
LCD segment line 3. Segments 0, 1, 2 and 3 are
controlled by SEGEN0.
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EFM32TG Data Sheet
Pin Definitions
Alternate
LOCATION
3
Functionality
0
1
2
4
5
6
Description
LCD segment line 6. Segments 4, 5, 6 and 7 are
controlled by SEGEN1.
LCD_SEG6
LCD_SEG7
LCD_SEG8
LCD_SEG9
LCD_SEG13
LCD_SEG14
LCD_SEG15
PE10
LCD segment line 7. Segments 4, 5, 6 and 7 are
controlled by SEGEN1.
PE11
PE12
PE13
PA0
LCD segment line 8. Segments 8, 9, 10 and 11 are
controlled by SEGEN2.
LCD segment line 9. Segments 8, 9, 10 and 11 are
controlled by SEGEN2.
LCD segment line 13. Segments 12, 13, 14 and 15
are controlled by SEGEN3.
LCD segment line 14. Segments 12, 13, 14 and 15
are controlled by SEGEN3.
PA1
LCD segment line 15. Segments 12, 13, 14 and 15
are controlled by SEGEN3.
PA2
LCD segment line 20. Segments 20, 21, 22 and 23
are controlled by SEGEN5. This pin may also be
used as LCD COM line 4
LCD_SEG20/
LCD_COM4
PB3
PB4
PB5
PB6
LCD segment line 21. Segments 20, 21, 22 and 23
are controlled by SEGEN5. This pin may also be
used as LCD COM line 5
LCD_SEG21/
LCD_COM5
LCD segment line 22. Segments 20, 21, 22 and 23
are controlled by SEGEN5. This pin may also be
used as LCD COM line 6
LCD_SEG22/
LCD_COM6
LCD segment line 23. Segments 20, 21, 22 and 23
are controlled by SEGEN5. This pin may also be
used as LCD COM line 7
LCD_SEG23/
LCD_COM7
LES_ALTEX0
LES_ALTEX1
LES_ALTEX5
LES_ALTEX6
LES_ALTEX7
LES_CH4
PD6
LESENSE alternate exite output 0.
LESENSE alternate exite output 1.
LESENSE alternate exite output 5.
LESENSE alternate exite output 6.
LESENSE alternate exite output 7.
LESENSE channel 4.
PD7
PE11
PE12
PE13
PC4
LES_CH13
PC13
PC14
PC15
LESENSE channel 13.
LES_CH14
LESENSE channel 14.
LES_CH15
LESENSE channel 15.
LETIM0_OUT0 PD6
LETIM0_OUT1 PD7
PB11
PF0
PF1
PC4
Low Energy Timer LETIM0, output channel 0.
Low Energy Timer LETIM0, output channel 1.
LEUART0 Receive input.
LEU0_RX
LEU0_TX
PD5
PD4
PB14
PB13
PF1
PF0
PA0
PF2
LEUART0 Transmit output. Also used as receive in-
put in half duplex communication.
Low Frequency Crystal (typically 32.768 kHz) nega-
tive pin. Also used as an optional external clock in-
put pin.
LFXTAL_N
PB8
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EFM32TG Data Sheet
Pin Definitions
Alternate
LOCATION
3
Functionality
0
1
2
4
5
6
Description
Low Frequency Crystal (typically 32.768 kHz) posi-
tive pin.
LFXTAL_P
PB7
PCNT0_S0IN
PCNT0_S1IN
PRS_CH0
PRS_CH1
PRS_CH2
TIM0_CC0
TIM0_CC1
TIM0_CC2
TIM1_CC0
TIM1_CC1
TIM1_CC2
US0_CLK
US0_CS
PC13
PC14
PA0
PD6
PD7
Pulse Counter PCNT0 input number 0.
Pulse Counter PCNT0 input number 1.
PF3
PF4
PF5
PA0
PA1
PA2
Peripheral Reflex System PRS, channel 0.
Peripheral Reflex System PRS, channel 1.
Peripheral Reflex System PRS, channel 2.
Timer 0 Capture Compare input / output channel 0.
Timer 0 Capture Compare input / output channel 1.
Timer 0 Capture Compare input / output channel 2.
Timer 1 Capture Compare input / output channel 0.
Timer 1 Capture Compare input / output channel 1.
Timer 1 Capture Compare input / output channel 2.
USART0 clock input / output.
PA1
PA0
PA1
PA2
PA0
PF0
PF1
PF2
PC13 PE10
PC14 PE11
PC15 PE12
PB7
PB8
PB11
PD6
PD7
PC13
PE12
PE13
PE5
PE4
PC15 PB13
PC14 PB14
PB13
PB14
USART0 chip select input / output.
USART0 Asynchronous Receive.
US0_RX
US0_TX
PE11
PE10
PE6
PE7
PE12
PE13
PB8
PB7
USART0 Synchronous mode Master Input / Slave
Output (MISO).
USART0 Asynchronous Transmit.Also used as re-
ceive input in half duplex communication.
USART0 Synchronous mode Master Output / Slave
Input (MOSI).
US1_CLK
US1_CS
PB7
PB8
PF0
PF1
USART1 clock input / output.
USART1 chip select input / output.
USART1 Asynchronous Receive.
US1_RX
US1_TX
PD6
PD7
USART1 Synchronous mode Master Input / Slave
Output (MISO).
USART1 Asynchronous Transmit.Also used as re-
ceive input in half duplex communication.
USART1 Synchronous mode Master Output / Slave
Input (MOSI).
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EFM32TG Data Sheet
Pin Definitions
5.8.3 GPIO Pinout Overview
The specific GPIO pins available in EFM32TG822 is shown in the following table. Each GPIO port is organized as 16-bit ports indicated
by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.
Table 5.24. GPIO Pinout
Port
Pin
15
Pin
14
Pin
13
Pin
12
Pin
11
Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
10
Port A
Port B
Port C
Port D
Port E
Port F
-
-
PA14 PA13 PA12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PA2 PA1 PA0
PB14 PB13
-
-
-
PB11
PB8 PB7 PB6 PB5 PB4 PB3
-
-
-
-
-
-
-
-
-
-
-
-
PC15 PC14 PC13
-
-
-
-
-
-
-
-
-
PC4
-
-
-
-
-
-
-
-
-
-
PD7 PD6 PD5 PD4
PE7 PE6 PE5 PE4
PE13 PE12 PE11 PE10
-
-
-
-
-
-
PF5 PF4 PF3 PF2 PF1 PF0
5.8.4 Opamp Pinout Overview
The specific opamp terminals available in EFM32TG822 is shown in the following figure.
PB11
OUT0ALT
OUT0
PC4
PD4
+
OPA0
-
+
OPA2
-
OUT2
PC13
PC14
PC15
PD6
PD7
OUT1ALT
OUT1
+
OPA1
-
PD5
Figure 5.15. Opamp Pinout
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EFM32TG Data Sheet
Pin Definitions
5.9 EFM32TG825 (BGA48)
5.9.1 Pinout
The EFM32TG825 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location
number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the
*_ROUTE register in the module in question.
Figure 5.16. EFM32TG825 Pinout (top view, not to scale)
Table 5.25. Device Pinout
BGA48 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
Analog
Timers
Communication
US0_TX #3
Other
LES_ALTEX7 #0
ACMP0_O #0
GPIO_EM4WU5
A1
PE13
LCD_SEG9
US0_CS #0
I2C0_SCL #6
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EFM32TG Data Sheet
Pin Definitions
BGA48 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
Analog
Timers
Communication
US0_RX #3
Other
CMU_CLK1 #2
A2
PE12
LCD_SEG8
TIM1_CC2 #1
US0_CLK #0
I2C0_SDA #6
LES_ALTEX6 #0
LES_ALTEX5 #0
BOOT_RX
A3
PE11
LCD_SEG7
TIM1_CC1 #1
US0_RX #0
A4
A5
PF5
PF3
LCD_SEG3
LCD_SEG1
PRS_CH2 #1
PRS_CH0 #1
ACMP1_CH6
TIM1_CC1 #0
A6
A7
PC14
PC15
DAC0_OUT1ALT #2/
OPAMP_OUT1ALT
ACMP1_CH7
US0_CS #3
LES_CH14 #0
PCNT0_S1IN #0
LES_CH15 #0
DBG_SWO #1
DAC0_OUT1ALT #3/
OPAMP_OUT1ALT
TIM1_CC2 #0
US0_CLK #3
I2C0_SCL #0
CMU_CLK1 #0
PRS_CH1 #0
PRS_CH0 #0
GPIO_EM4WU0
BOOT_TX
B1
B2
PA1
PA0
LCD_SEG14
LCD_SEG13
TIM0_CC1 #0/1
LEU0_RX #4
I2C0_SDA #0
US0_TX #0
TIM0_CC0 #0/1/4
TIM1_CC0 #1
B3
B4
PE10
PF4
LCD_SEG6
LCD_SEG2
PRS_CH1 #1
ACMP1_O #0
DBG_SWO #0
GPIO_EM4WU4
B5
B6
B7
PF2
PE7
LCD_SEG0
TIM0_CC2 #5
LEU0_TX #4
US0_TX #1
LCD_COM3
ACMP1_CH5
TIM1_CC0 #0
TIM1_CC2 #4
PCNT0_S0IN #0
PC13
DAC0_OUT1ALT #1/
OPAMP_OUT1ALT
LCD_SEG20/
LES_CH13 #0
CMU_CLK0 #0
C1
PB3
LCD_COM4
C2
C3
C4
PA2
VSS
LCD_SEG15
TIM0_CC2 #0/1
Ground.
IOVDD_5
Digital IO power supply 5.
US1_CS #2
LEU0_RX #3
I2C0_SCL #5
US0_CLK #1
US0_RX #1
TIM0_CC1 #5
DBG_SWDIO #0/1
GPIO_EM4WU3
C5
PF1
LETIM0_OUT1 #2
C6
C7
PE5
PE6
LCD_COM1
LCD_COM2
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EFM32TG Data Sheet
Pin Definitions
BGA48 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
Analog
LCD_SEG21/
Timers
Communication
Other
D1
PB4
LCD_COM5
LCD_SEG23/
D2
D3
PB6
LCD_COM7
IOVDD_0
Digital IO power supply 0.
US1_CLK #2
LEU0_TX #3
I2C0_SDA #5
US0_CS #1
TIM0_CC0 #5
D5
PF0
DBG_SWCLK #0/1
LETIM0_OUT0 #2
D6
D7
PE4
LCD_COM0
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required
at this pin.
DECOUPLE
LCD_SEG22/
LCD_COM6
ACMP0_CH4
E1
E2
PB5
PC4
DAC0_P0/
OPAMP_P0
LCD_BCAP_P
LETIM0_OUT0 #3
LES_CH4 #0
E3
E4
E5
PA12
VDD_DREG
AVSS_0
Power supply for on-chip voltage regulator.
Analog ground 0.
ADC0_CH7
DAC0_N1/
OPAMP_N1
ADC0_CH6
DAC0_P1/
OPAMP_P1
TIM1_CC1 #4
LETIM0_OUT1 #0
PCNT0_S1IN #3
TIM1_CC0 #4
CMU_CLK0 #2
LES_ALTEX1 #0
ACMP1_O #2
US1_TX #2
E6
PD7
I2C0_SCL #1
US1_RX #2
LES_ALTEX0 #0
ACMP0_O #2
E7
F1
PD6
PB7
LETIM0_OUT0 #0
PCNT0_S0IN #3
I2C0_SDA #1
US0_TX #4
LFXTAL_P
TIM1_CC0 #3
US1_CLK #0
F2
F3
PA13
LCD_BCAP_N
Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin
low during reset, and let the internal pull-up ensure that reset is released.
RESETn
F4
F5
F6
IOVDD_3
AVDD_1
AVDD_0
Digital IO power supply 3.
Analog power supply 1.
Analog power supply 0.
ADC0_CH5
F7
PD5
PB8
LEU0_RX #0
OPAMP_OUT2 #0
US0_RX #4
G1
LFXTAL_N
TIM1_CC1 #3
US1_CS #0
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EFM32TG Data Sheet
Pin Definitions
BGA48 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
Analog
LCD_BEXT
Timers
Communication
Other
G2
G3
G4
G5
PA14
DAC0_OUT0/
OPAMP_OUT0
Analog ground 1.
TIM1_CC2 #3
PB11
AVSS_1
PB13
LETIM0_OUT0 #1
US0_CLK #4/5
LEU0_TX #1
US0_CS #4/5
LEU0_RX #1
HFXTAL_P
HFXTAL_N
G6
G7
PB14
PD4
ADC0_CH4
OPAMP_P2
LEU0_TX #0
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EFM32TG Data Sheet
Pin Definitions
5.9.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table
shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.
Table 5.26. Alternate functionality overview
Alternate
LOCATION
3
Functionality
ACMP0_CH4
ACMP0_O
0
1
2
4
5
6
Description
PC4
Analog comparator ACMP0, channel 4.
Analog comparator ACMP0, digital output.
Analog comparator ACMP1, channel 5.
Analog comparator ACMP1, channel 6.
Analog comparator ACMP1, channel 7.
Analog comparator ACMP1, digital output.
PE13
PC13
PC14
PC15
PF2
PD6
ACMP1_CH5
ACMP1_CH6
ACMP1_CH7
ACMP1_O
PD7
Analog to digital converter ADC0, input channel
number 4.
ADC0_CH4
ADC0_CH5
ADC0_CH6
ADC0_CH7
PD4
PD5
PD6
PD7
Analog to digital converter ADC0, input channel
number 5.
Analog to digital converter ADC0, input channel
number 6.
Analog to digital converter ADC0, input channel
number 7.
BOOT_RX
BOOT_TX
CMU_CLK0
CMU_CLK1
PE11
PE10
PA2
Bootloader RX.
Bootloader TX.
PD7
Clock Management Unit, clock output number 0.
Clock Management Unit, clock output number 1.
PA1
PE12
DAC0_N1/
OPAMP_N1
PD7
Operational Amplifier 1 external negative input.
DAC0_OUT0/
OPAMP_OUT0
Digital to Analog Converter DAC0_OUT0 /OPAMP
output channel number 0.
PB11
DAC0_OUT1AL
T/
Digital to Analog Converter DAC0_OUT1ALT /
OPAMP alternative output for channel 1.
PC13 PC14 PC15
OPAMP_OUT1
ALT
OPAMP_OUT2 PD5
Operational Amplifier 2 output.
DAC0_P0/
PC4
Operational Amplifier 0 external positive input.
OPAMP_P0
DAC0_P1/
PD6
Operational Amplifier 1 external positive input.
OPAMP_P1
OPAMP_P2
PD4
PF0
Operational Amplifier 2 external positive input.
Debug-interface Serial Wire clock input.
DBG_SWCLK
PF0
Note that this function is enabled to pin out of reset,
and has a built-in pull down.
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EFM32TG Data Sheet
Pin Definitions
Alternate
LOCATION
3
Functionality
0
1
2
4
5
6
Description
Debug-interface Serial Wire data input / output.
DBG_SWDIO
DBG_SWO
PF1
PF1
Note that this function is enabled to pin out of reset,
and has a built-in pull up.
Debug-interface Serial Wire viewer Output.
PF2
PC15
Note that this function is not enabled after reset, and
must be enabled by software to be used.
GPIO_EM4WU0 PA0
GPIO_EM4WU3 PF1
GPIO_EM4WU4 PF2
GPIO_EM4WU5 PE13
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
High Frequency Crystal negative pin. Also used as
external optional clock input pin.
HFXTAL_N
PB14
HFXTAL_P
I2C0_SCL
I2C0_SDA
PB13
PA1
PA0
High Frequency Crystal positive pin.
I2C0 Serial Clock Line input / output.
I2C0 Serial Data input / output.
PD7
PD6
PF1
PF0
PE13
PE12
LCD voltage booster (optional), boost capacitor,
negative pin. If using the LCD voltage booster, con-
nect a 22 nF capacitor between LCD_BCAP_N and
LCD_BCAP_P.
LCD_BCAP_N PA13
LCD_BCAP_P PA12
LCD voltage booster (optional), boost capacitor,
positive pin. If using the LCD voltage booster, con-
nect a 22 nF capacitor between LCD_BCAP_N and
LCD_BCAP_P.
LCD voltage booster (optional), boost output. If us-
ing the LCD voltage booster, connect a 1 uF capaci-
tor between this pin and VSS.
LCD_BEXT
PA14
An external LCD voltage may also be applied to this
pin if the booster is not enabled.
If AVDD is used directly as the LCD supply voltage,
this pin may be left unconnected or used as a GPIO.
LCD_COM0
LCD_COM1
LCD_COM2
LCD_COM3
PE4
PE5
PE6
PE7
LCD driver common line number 0.
LCD driver common line number 1.
LCD driver common line number 2.
LCD driver common line number 3.
LCD segment line 0. Segments 0, 1, 2 and 3 are
controlled by SEGEN0.
LCD_SEG0
LCD_SEG1
LCD_SEG2
LCD_SEG3
PF2
PF3
PF4
PF5
LCD segment line 1. Segments 0, 1, 2 and 3 are
controlled by SEGEN0.
LCD segment line 2. Segments 0, 1, 2 and 3 are
controlled by SEGEN0.
LCD segment line 3. Segments 0, 1, 2 and 3 are
controlled by SEGEN0.
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EFM32TG Data Sheet
Pin Definitions
Alternate
LOCATION
3
Functionality
0
1
2
4
5
6
Description
LCD segment line 6. Segments 4, 5, 6 and 7 are
controlled by SEGEN1.
LCD_SEG6
LCD_SEG7
LCD_SEG8
LCD_SEG9
LCD_SEG13
LCD_SEG14
LCD_SEG15
PE10
LCD segment line 7. Segments 4, 5, 6 and 7 are
controlled by SEGEN1.
PE11
PE12
PE13
PA0
LCD segment line 8. Segments 8, 9, 10 and 11 are
controlled by SEGEN2.
LCD segment line 9. Segments 8, 9, 10 and 11 are
controlled by SEGEN2.
LCD segment line 13. Segments 12, 13, 14 and 15
are controlled by SEGEN3.
LCD segment line 14. Segments 12, 13, 14 and 15
are controlled by SEGEN3.
PA1
LCD segment line 15. Segments 12, 13, 14 and 15
are controlled by SEGEN3.
PA2
LCD segment line 20. Segments 20, 21, 22 and 23
are controlled by SEGEN5. This pin may also be
used as LCD COM line 4
LCD_SEG20/
LCD_COM4
PB3
PB4
PB5
PB6
LCD segment line 21. Segments 20, 21, 22 and 23
are controlled by SEGEN5. This pin may also be
used as LCD COM line 5
LCD_SEG21/
LCD_COM5
LCD segment line 22. Segments 20, 21, 22 and 23
are controlled by SEGEN5. This pin may also be
used as LCD COM line 6
LCD_SEG22/
LCD_COM6
LCD segment line 23. Segments 20, 21, 22 and 23
are controlled by SEGEN5. This pin may also be
used as LCD COM line 7
LCD_SEG23/
LCD_COM7
LES_ALTEX0
LES_ALTEX1
LES_ALTEX5
LES_ALTEX6
LES_ALTEX7
LES_CH4
PD6
LESENSE alternate exite output 0.
LESENSE alternate exite output 1.
LESENSE alternate exite output 5.
LESENSE alternate exite output 6.
LESENSE alternate exite output 7.
LESENSE channel 4.
PD7
PE11
PE12
PE13
PC4
LES_CH13
PC13
PC14
PC15
LESENSE channel 13.
LES_CH14
LESENSE channel 14.
LES_CH15
LESENSE channel 15.
LETIM0_OUT0 PD6
LETIM0_OUT1 PD7
PB11
PF0
PF1
PC4
Low Energy Timer LETIM0, output channel 0.
Low Energy Timer LETIM0, output channel 1.
LEUART0 Receive input.
LEU0_RX
LEU0_TX
PD5
PD4
PB14
PB13
PF1
PF0
PA0
PF2
LEUART0 Transmit output. Also used as receive in-
put in half duplex communication.
Low Frequency Crystal (typically 32.768 kHz) nega-
tive pin. Also used as an optional external clock in-
put pin.
LFXTAL_N
PB8
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EFM32TG Data Sheet
Pin Definitions
Alternate
LOCATION
3
Functionality
0
1
2
4
5
6
Description
Low Frequency Crystal (typically 32.768 kHz) posi-
tive pin.
LFXTAL_P
PB7
PCNT0_S0IN
PCNT0_S1IN
PRS_CH0
PRS_CH1
PRS_CH2
TIM0_CC0
TIM0_CC1
TIM0_CC2
TIM1_CC0
TIM1_CC1
TIM1_CC2
US0_CLK
US0_CS
PC13
PC14
PA0
PD6
PD7
Pulse Counter PCNT0 input number 0.
Pulse Counter PCNT0 input number 1.
PF3
PF4
PF5
PA0
PA1
PA2
Peripheral Reflex System PRS, channel 0.
Peripheral Reflex System PRS, channel 1.
Peripheral Reflex System PRS, channel 2.
Timer 0 Capture Compare input / output channel 0.
Timer 0 Capture Compare input / output channel 1.
Timer 0 Capture Compare input / output channel 2.
Timer 1 Capture Compare input / output channel 0.
Timer 1 Capture Compare input / output channel 1.
Timer 1 Capture Compare input / output channel 2.
USART0 clock input / output.
PA1
PA0
PA1
PA2
PA0
PF0
PF1
PF2
PC13 PE10
PC14 PE11
PC15 PE12
PB7
PB8
PB11
PD6
PD7
PC13
PE12
PE13
PE5
PE4
PC15 PB13
PC14 PB14
PB13
PB14
USART0 chip select input / output.
USART0 Asynchronous Receive.
US0_RX
US0_TX
PE11
PE10
PE6
PE7
PE12
PE13
PB8
PB7
USART0 Synchronous mode Master Input / Slave
Output (MISO).
USART0 Asynchronous Transmit.Also used as re-
ceive input in half duplex communication.
USART0 Synchronous mode Master Output / Slave
Input (MOSI).
US1_CLK
US1_CS
PB7
PB8
PF0
PF1
USART1 clock input / output.
USART1 chip select input / output.
USART1 Asynchronous Receive.
US1_RX
US1_TX
PD6
PD7
USART1 Synchronous mode Master Input / Slave
Output (MISO).
USART1 Asynchronous Transmit.Also used as re-
ceive input in half duplex communication.
USART1 Synchronous mode Master Output / Slave
Input (MOSI).
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EFM32TG Data Sheet
Pin Definitions
5.9.3 GPIO Pinout Overview
The specific GPIO pins available in EFM32TG825 is shown in the following table. Each GPIO port is organized as 16-bit ports indicated
by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.
Table 5.27. GPIO Pinout
Port
Pin
15
Pin
14
Pin
13
Pin
12
Pin
11
Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
10
Port A
Port B
Port C
Port D
Port E
Port F
-
-
PA14 PA13 PA12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PA2 PA1 PA0
PB14 PB13
-
-
-
PB11
PB8 PB7 PB6 PB5 PB4 PB3
-
-
-
-
-
-
-
-
-
-
-
-
PC15 PC14 PC13
-
-
-
-
-
-
-
-
-
PC4
-
-
-
-
-
-
-
-
-
-
PD7 PD6 PD5 PD4
PE7 PE6 PE5 PE4
PE13 PE12 PE11 PE10
-
-
-
-
-
-
PF5 PF4 PF3 PF2 PF1 PF0
5.9.4 Opamp Pinout Overview
The specific opamp terminals available in EFM32TG825 is shown in the following figure.
PB11
OUT0ALT
OUT0
PC4
PD4
+
OPA0
-
+
OPA2
-
OUT2
PC13
PC14
PC15
PD6
PD7
OUT1ALT
OUT1
+
OPA1
-
PD5
Figure 5.17. Opamp Pinout
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EFM32TG Data Sheet
Pin Definitions
5.10 EFM32TG840 (QFN64)
5.10.1 Pinout
The EFM32TG840 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location
number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the
*_ROUTE register in the module in question.
Figure 5.18. EFM32TG840 Pinout (top view, not to scale)
Table 5.28. Device Pinout
QFN64 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
Analog
Timers
Communication
LEU0_RX #4
Other
PRS_CH0 #0
GPIO_EM4WU0
CMU_CLK1 #0
PRS_CH1 #0
CMU_CLK0 #0
1
PA0
LCD_SEG13
TIM0_CC0 #0/1/4
I2C0_SDA #0
2
3
PA1
PA2
LCD_SEG14
LCD_SEG15
TIM0_CC1 #0/1
TIM0_CC2 #0/1
I2C0_SCL #0
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EFM32TG Data Sheet
Pin Definitions
QFN64 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
PA3
Analog
LCD_SEG16
LCD_SEG17
LCD_SEG18
LCD_SEG19
Digital IO power supply 0.
LCD_SEG20/
LCD_COM4
Timers
Communication
Other
4
5
6
7
8
LES_ALTEX2 #0
LES_ALTEX3 #0
LES_ALTEX4 #0
GPIO_EM4WU1
PA4
PA5
PA6
IOVDD_0
9
PB3
PB4
PB5
PB6
LCD_SEG21/
LCD_COM5
10
11
12
LCD_SEG22/
LCD_COM6
LCD_SEG23/
LCD_COM7
ACMP0_CH4
DAC0_P0/
13
14
PC4
PC5
LETIM0_OUT0 #3
LETIM0_OUT1 #3
LES_CH4 #0
LES_CH5 #0
OPAMP_P0
ACMP0_CH5
DAC0_N0/
OPAMP_N0
US0_TX #4
US1_CLK #0
US0_RX #4
US1_CS #0
15
16
PB7
PB8
LFXTAL_P
LFXTAL_N
TIM1_CC0 #3
TIM1_CC1 #3
17
18
19
PA12
PA13
PA14
LCD_BCAP_P
LCD_BCAP_N
LCD_BEXT
Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin
low during reset, and let the internal pull-up ensure that reset is released.
20
21
RESETn
PB11
DAC0_OUT0/
OPAMP_OUT0
TIM1_CC2 #3
LETIM0_OUT0 #1
DAC0_OUT1/
22
23
24
PB12
AVDD_1
PB13
LETIM0_OUT1 #1
OPAMP_OUT1
Analog power supply 1.
US0_CLK #4/5
LEU0_TX #1
HFXTAL_P
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EFM32TG Data Sheet
Pin Definitions
QFN64 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
Analog
Timers
Communication
US0_CS #4/5
LEU0_RX #1
Other
25
PB14
HFXTAL_N
26
27
IOVDD_3
AVDD_0
Digital IO power supply 3.
Analog power supply 0.
ADC0_CH0
DAC0_OUT0ALT #4/
OPAMP_OUT0ALT
OPAMP_OUT2 #1
ADC0_CH1
28
PD0
US1_TX #1
US1_RX #1
29
PD1
DAC0_OUT1ALT #4/
OPAMP_OUT1ALT
ADC0_CH2
TIM0_CC0 #3
30
31
PD2
PD3
TIM0_CC1 #3
TIM0_CC2 #3
US1_CLK #1
US1_CS #1
ADC0_CH3
OPAMP_N2
ADC0_CH4
32
33
PD4
PD5
LEU0_TX #0
LEU0_RX #0
OPAMP_P2
ADC0_CH5
OPAMP_OUT2 #0
ADC0_CH6
TIM1_CC0 #4
LETIM0_OUT0 #0
PCNT0_S0IN #3
TIM1_CC1 #4
US1_RX #2
LES_ALTEX0 #0
ACMP0_O #2
34
35
PD6
PD7
DAC0_P1/
I2C0_SDA #1
OPAMP_P1
ADC0_CH7
CMU_CLK0 #2
LES_ALTEX1 #0
ACMP1_O #2
CMU_CLK1 #1
LES_CH6 #0
US1_TX #2
DAC0_P1/
LETIM0_OUT1 #0
PCNT0_S1IN #3
I2C0_SCL #1
OPAMP_N1
36
37
38
39
PD8
PC6
ACMP0_CH6
ACMP0_CH7
I2C0_SDA #2
I2C0_SCL #2
PC7
LES_CH7 #0
VDD_DREG
Power supply for on-chip voltage regulator.
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required
at this pin.
40
DECOUPLE
41
42
43
44
PE4
PE5
PE6
PE7
LCD_COM0
LCD_COM1
LCD_COM2
LCD_COM3
US0_CS #1
US0_CLK #1
US0_RX #1
US0_TX #1
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EFM32TG Data Sheet
Pin Definitions
QFN64 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
Analog
Timers
Communication
Other
ACMP1_CH4
CMU_CLK0 #1
LES_CH12 #0
45
46
47
48
49
50
51
PC12
DAC0_OUT1ALT #0/
OPAMP_OUT1ALT
ACMP1_CH5
TIM1_CC0 #0
TIM1_CC2 #4
PCNT0_S0IN #0
PC13
PC14
PC15
PF0
DAC0_OUT1ALT #1/
OPAMP_OUT1ALT
ACMP1_CH6
LES_CH13 #0
LES_CH14 #0
TIM1_CC1 #0
DAC0_OUT1ALT #2/
OPAMP_OUT1ALT
ACMP1_CH7
US0_CS #3
PCNT0_S1IN #0
LES_CH15 #0
DBG_SWO #1
DAC0_OUT1ALT #3/
OPAMP_OUT1ALT
TIM1_CC2 #0
US0_CLK #3
US1_CLK #2
LEU0_TX #3
I2C0_SDA #5
US1_CS #2
TIM0_CC0 #5
DBG_SWCLK #0/1
LETIM0_OUT0 #2
TIM0_CC1 #5
DBG_SWDIO #0/1
GPIO_EM4WU3
PF1
LEU0_RX #3
I2C0_SCL #5
LETIM0_OUT1 #2
ACMP1_O #0
DBG_SWO #0
GPIO_EM4WU4
PRS_CH0 #1
PRS_CH1 #1
PRS_CH2 #1
PF2
LCD_SEG0
TIM0_CC2 #5
LEU0_TX #4
52
53
54
55
56
57
58
PF3
PF4
LCD_SEG1
LCD_SEG2
PF5
LCD_SEG3
IOVDD_5
PE8
Digital IO power supply 5.
LCD_SEG4
PRS_CH3 #1
PE9
LCD_SEG5
PE10
LCD_SEG6
TIM1_CC0 #1
TIM1_CC1 #1
US0_TX #0
US0_RX #0
BOOT_TX
LES_ALTEX5 #0
BOOT_RX
59
PE11
PE12
LCD_SEG7
LCD_SEG8
US0_RX #3
US0_CLK #0
I2C0_SDA #6
US0_TX #3
US0_CS #0
I2C0_SCL #6
CMU_CLK1 #2
60
TIM1_CC2 #1
LES_ALTEX6 #0
LES_ALTEX7 #0
ACMP0_O #0
61
PE13
LCD_SEG9
GPIO_EM4WU5
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EFM32TG Data Sheet
Pin Definitions
QFN64 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
PE14
Analog
Timers
Communication
LEU0_TX #2
Other
62
63
64
LCD_SEG10
LCD_SEG11
LCD_SEG12
PE15
LEU0_RX #2
PA15
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EFM32TG Data Sheet
Pin Definitions
5.10.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table
shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.
Table 5.29. Alternate functionality overview
Alternate
LOCATION
3
Functionality
ACMP0_CH4
ACMP0_CH5
ACMP0_CH6
ACMP0_CH7
ACMP0_O
0
1
2
PD6
PD7
4
5
6
Description
PC4
Analog comparator ACMP0, channel 4.
Analog comparator ACMP0, channel 5.
Analog comparator ACMP0, channel 6.
Analog comparator ACMP0, channel 7.
Analog comparator ACMP0, digital output.
Analog comparator ACMP1, channel 4.
Analog comparator ACMP1, channel 5.
Analog comparator ACMP1, channel 6.
Analog comparator ACMP1, channel 7.
Analog comparator ACMP1, digital output.
PC5
PC6
PC7
PE13
PC12
PC13
PC14
PC15
PF2
ACMP1_CH4
ACMP1_CH5
ACMP1_CH6
ACMP1_CH7
ACMP1_O
Analog to digital converter ADC0, input channel
number 0.
ADC0_CH0
ADC0_CH1
ADC0_CH2
ADC0_CH3
ADC0_CH4
ADC0_CH5
ADC0_CH6
ADC0_CH7
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
Analog to digital converter ADC0, input channel
number 1.
Analog to digital converter ADC0, input channel
number 2.
Analog to digital converter ADC0, input channel
number 3.
Analog to digital converter ADC0, input channel
number 4.
Analog to digital converter ADC0, input channel
number 5.
Analog to digital converter ADC0, input channel
number 6.
Analog to digital converter ADC0, input channel
number 7.
BOOT_RX
BOOT_TX
CMU_CLK0
CMU_CLK1
PE11
PE10
PA2
Bootloader RX.
Bootloader TX.
PC12 PD7
PD8 PE12
Clock Management Unit, clock output number 0.
Clock Management Unit, clock output number 1.
PA1
DAC0_N0/
OPAMP_N0
PC5
PD7
Operational Amplifier 0 external negative input.
Operational Amplifier 1 external negative input.
DAC0_N1/
OPAMP_N1
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EFM32TG Data Sheet
Pin Definitions
Alternate
LOCATION
3
Functionality
OPAMP_N2
0
1
2
4
5
6
Description
PD3
Operational Amplifier 2 external negative input.
DAC0_OUT0/
OPAMP_OUT0
Digital to Analog Converter DAC0_OUT0 /OPAMP
output channel number 0.
PB11
DAC0_OUT0AL
T/
Digital to Analog Converter DAC0_OUT0ALT /
OPAMP alternative output for channel 0.
PD0
OPAMP_OUT0
ALT
DAC0_OUT1/
OPAMP_OUT1
Digital to Analog Converter DAC0_OUT1 /OPAMP
output channel number 1.
PB12
DAC0_OUT1AL
T/
Digital to Analog Converter DAC0_OUT1ALT /
OPAMP alternative output for channel 1.
PC12 PC13 PC14 PC15 PD1
OPAMP_OUT1
ALT
OPAMP_OUT2 PD5
PD0
Operational Amplifier 2 output.
DAC0_P0/
PC4
Operational Amplifier 0 external positive input.
OPAMP_P0
DAC0_P1/
PD6
Operational Amplifier 1 external positive input.
OPAMP_P1
OPAMP_P2
PD4
PF0
Operational Amplifier 2 external positive input.
Debug-interface Serial Wire clock input.
DBG_SWCLK
PF0
Note that this function is enabled to pin out of reset,
and has a built-in pull down.
Debug-interface Serial Wire data input / output.
DBG_SWDIO
DBG_SWO
PF1
PF2
PF1
Note that this function is enabled to pin out of reset,
and has a built-in pull up.
Debug-interface Serial Wire viewer Output.
PC15
Note that this function is not enabled after reset, and
must be enabled by software to be used.
GPIO_EM4WU0 PA0
GPIO_EM4WU1 PA6
GPIO_EM4WU3 PF1
GPIO_EM4WU4 PF2
GPIO_EM4WU5 PE13
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
High Frequency Crystal negative pin. Also used as
external optional clock input pin.
HFXTAL_N
PB14
HFXTAL_P
I2C0_SCL
I2C0_SDA
PB13
PA1
PA0
High Frequency Crystal positive pin.
I2C0 Serial Clock Line input / output.
I2C0 Serial Data input / output.
PD7
PD6
PC7
PC6
PF1
PF0
PE13
PE12
LCD voltage booster (optional), boost capacitor,
negative pin. If using the LCD voltage booster, con-
nect a 22 nF capacitor between LCD_BCAP_N and
LCD_BCAP_P.
LCD_BCAP_N PA13
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EFM32TG Data Sheet
Pin Definitions
Alternate
LOCATION
3
Functionality
0
1
2
4
5
6
Description
LCD voltage booster (optional), boost capacitor,
positive pin. If using the LCD voltage booster, con-
nect a 22 nF capacitor between LCD_BCAP_N and
LCD_BCAP_P.
LCD_BCAP_P PA12
LCD voltage booster (optional), boost output. If us-
ing the LCD voltage booster, connect a 1 uF capaci-
tor between this pin and VSS.
LCD_BEXT
PA14
An external LCD voltage may also be applied to this
pin if the booster is not enabled.
If AVDD is used directly as the LCD supply voltage,
this pin may be left unconnected or used as a GPIO.
LCD_COM0
LCD_COM1
LCD_COM2
LCD_COM3
PE4
PE5
PE6
PE7
LCD driver common line number 0.
LCD driver common line number 1.
LCD driver common line number 2.
LCD driver common line number 3.
LCD segment line 0. Segments 0, 1, 2 and 3 are
controlled by SEGEN0.
LCD_SEG0
LCD_SEG1
LCD_SEG2
LCD_SEG3
LCD_SEG4
LCD_SEG5
LCD_SEG6
LCD_SEG7
LCD_SEG8
LCD_SEG9
LCD_SEG10
LCD_SEG11
LCD_SEG12
LCD_SEG13
LCD_SEG14
PF2
LCD segment line 1. Segments 0, 1, 2 and 3 are
controlled by SEGEN0.
PF3
LCD segment line 2. Segments 0, 1, 2 and 3 are
controlled by SEGEN0.
PF4
LCD segment line 3. Segments 0, 1, 2 and 3 are
controlled by SEGEN0.
PF5
LCD segment line 4. Segments 4, 5, 6 and 7 are
controlled by SEGEN1.
PE8
LCD segment line 5. Segments 4, 5, 6 and 7 are
controlled by SEGEN1.
PE9
LCD segment line 6. Segments 4, 5, 6 and 7 are
controlled by SEGEN1.
PE10
PE11
PE12
PE13
PE14
PE15
PA15
PA0
LCD segment line 7. Segments 4, 5, 6 and 7 are
controlled by SEGEN1.
LCD segment line 8. Segments 8, 9, 10 and 11 are
controlled by SEGEN2.
LCD segment line 9. Segments 8, 9, 10 and 11 are
controlled by SEGEN2.
LCD segment line 10. Segments 8, 9, 10 and 11 are
controlled by SEGEN2.
LCD segment line 11. Segments 8, 9, 10 and 11 are
controlled by SEGEN2.
LCD segment line 12. Segments 12, 13, 14 and 15
are controlled by SEGEN3.
LCD segment line 13. Segments 12, 13, 14 and 15
are controlled by SEGEN3.
LCD segment line 14. Segments 12, 13, 14 and 15
are controlled by SEGEN3.
PA1
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EFM32TG Data Sheet
Pin Definitions
Alternate
LOCATION
3
Functionality
0
1
2
4
5
6
Description
LCD segment line 15. Segments 12, 13, 14 and 15
are controlled by SEGEN3.
LCD_SEG15
LCD_SEG16
LCD_SEG17
LCD_SEG18
LCD_SEG19
PA2
LCD segment line 16. Segments 16, 17, 18 and 19
are controlled by SEGEN4.
PA3
PA4
PA5
PA6
LCD segment line 17. Segments 16, 17, 18 and 19
are controlled by SEGEN4.
LCD segment line 18. Segments 16, 17, 18 and 19
are controlled by SEGEN4.
LCD segment line 19. Segments 16, 17, 18 and 19
are controlled by SEGEN4.
LCD segment line 20. Segments 20, 21, 22 and 23
are controlled by SEGEN5. This pin may also be
used as LCD COM line 4
LCD_SEG20/
LCD_COM4
PB3
PB4
PB5
PB6
LCD segment line 21. Segments 20, 21, 22 and 23
are controlled by SEGEN5. This pin may also be
used as LCD COM line 5
LCD_SEG21/
LCD_COM5
LCD segment line 22. Segments 20, 21, 22 and 23
are controlled by SEGEN5. This pin may also be
used as LCD COM line 6
LCD_SEG22/
LCD_COM6
LCD segment line 23. Segments 20, 21, 22 and 23
are controlled by SEGEN5. This pin may also be
used as LCD COM line 7
LCD_SEG23/
LCD_COM7
LES_ALTEX0
LES_ALTEX1
LES_ALTEX2
LES_ALTEX3
LES_ALTEX4
LES_ALTEX5
LES_ALTEX6
LES_ALTEX7
LES_CH4
PD6
LESENSE alternate exite output 0.
LESENSE alternate exite output 1.
LESENSE alternate exite output 2.
LESENSE alternate exite output 3.
LESENSE alternate exite output 4.
LESENSE alternate exite output 5.
LESENSE alternate exite output 6.
LESENSE alternate exite output 7.
LESENSE channel 4.
PD7
PA3
PA4
PA5
PE11
PE12
PE13
PC4
LES_CH5
PC5
LESENSE channel 5.
LES_CH6
PC6
LESENSE channel 6.
LES_CH7
PC7
LESENSE channel 7.
LES_CH12
LES_CH13
LES_CH14
LES_CH15
PC12
PC13
PC14
PC15
LESENSE channel 12.
LESENSE channel 13.
LESENSE channel 14.
LESENSE channel 15.
LETIM0_OUT0 PD6
LETIM0_OUT1 PD7
PB11
PB12
PB14
PF0
PC4
PC5
Low Energy Timer LETIM0, output channel 0.
Low Energy Timer LETIM0, output channel 1.
LEUART0 Receive input.
PF1
LEU0_RX
PD5
PE15
PF1
PA0
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EFM32TG Data Sheet
Pin Definitions
Alternate
LOCATION
3
Functionality
0
1
2
4
5
6
Description
LEUART0 Transmit output. Also used as receive in-
put in half duplex communication.
LEU0_TX
LFXTAL_N
LFXTAL_P
PD4
PB13
PE14
PF0
PF2
Low Frequency Crystal (typically 32.768 kHz) nega-
tive pin. Also used as an optional external clock in-
put pin.
PB8
PB7
Low Frequency Crystal (typically 32.768 kHz) posi-
tive pin.
PCNT0_S0IN
PCNT0_S1IN
PRS_CH0
PRS_CH1
PRS_CH2
PRS_CH3
TIM0_CC0
TIM0_CC1
TIM0_CC2
TIM1_CC0
TIM1_CC1
TIM1_CC2
US0_CLK
US0_CS
PC13
PC14
PA0
PD6
PD7
Pulse Counter PCNT0 input number 0.
Pulse Counter PCNT0 input number 1.
PF3
PF4
PF5
PE8
PA0
PA1
PA2
Peripheral Reflex System PRS, channel 0.
Peripheral Reflex System PRS, channel 1.
Peripheral Reflex System PRS, channel 2.
Peripheral Reflex System PRS, channel 3.
Timer 0 Capture Compare input / output channel 0.
Timer 0 Capture Compare input / output channel 1.
Timer 0 Capture Compare input / output channel 2.
Timer 1 Capture Compare input / output channel 0.
Timer 1 Capture Compare input / output channel 1.
Timer 1 Capture Compare input / output channel 2.
USART0 clock input / output.
PA1
PA0
PA1
PA2
PD1
PD2
PD3
PB7
PB8
PB11
PA0
PF0
PF1
PF2
PC13 PE10
PC14 PE11
PC15 PE12
PD6
PD7
PC13
PE12
PE13
PE5
PE4
PC15 PB13
PC14 PB14
PB13
PB14
USART0 chip select input / output.
USART0 Asynchronous Receive.
US0_RX
US0_TX
PE11
PE10
PE6
PE7
PE12
PE13
PB8
PB7
USART0 Synchronous mode Master Input / Slave
Output (MISO).
USART0 Asynchronous Transmit.Also used as re-
ceive input in half duplex communication.
USART0 Synchronous mode Master Output / Slave
Input (MOSI).
US1_CLK
US1_CS
PB7
PB8
PD2
PD3
PF0
PF1
USART1 clock input / output.
USART1 chip select input / output.
USART1 Asynchronous Receive.
US1_RX
US1_TX
PD1
PD0
PD6
PD7
USART1 Synchronous mode Master Input / Slave
Output (MISO).
USART1 Asynchronous Transmit.Also used as re-
ceive input in half duplex communication.
USART1 Synchronous mode Master Output / Slave
Input (MOSI).
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EFM32TG Data Sheet
Pin Definitions
5.10.3 GPIO Pinout Overview
The specific GPIO pins available in EFM32TG840 is shown in the following table. Each GPIO port is organized as 16-bit ports indicated
by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.
Table 5.30. GPIO Pinout
Port
Pin
15
Pin
14
Pin
13
Pin
12
Pin
11
Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
10
Port A
Port B
Port C
Port D
Port E
Port F
PA15 PA14 PA13 PA12
-
-
-
-
-
-
-
-
-
-
-
PA6 PA5 PA4 PA3 PA2 PA1 PA0
-
PB14 PB13 PB12 PB11
PB8 PB7 PB6 PB5 PB4 PB3
PC7 PC6 PC5 PC4
-
-
-
-
-
-
PC15 PC14 PC13 PC12
-
-
-
-
-
-
-
-
PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PF5 PF4 PF3 PF2 PF1 PF0
5.10.4 Opamp Pinout Overview
The specific opamp terminals available in EFM32TG840 is shown in the following figure.
PB11
PB12
OUT0ALT
OUT0
PC4
PC5
+
OPA0
-
+
PD4
PD3
PC12
PC13
PC14
PC15
PD0
OPA2
-
OUT2
PD6
PD7
OUT1ALT
OUT1
+
OPA1
-
PD1
PD5
Figure 5.19. Opamp Pinout
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EFM32TG Data Sheet
Pin Definitions
5.11 EFM32TG842 (TQFP64)
5.11.1 Pinout
The EFM32TG842 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location
number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the
*_ROUTE register in the module in question.
Figure 5.20. EFM32TG842 Pinout (top view, not to scale)
Table 5.31. Device Pinout
QFP64 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
Analog
Timers
Communication
LEU0_RX #4
Other
PRS_CH0 #0
GPIO_EM4WU0
CMU_CLK1 #0
PRS_CH1 #0
CMU_CLK0 #0
1
PA0
LCD_SEG13
TIM0_CC0 #0/1/4
I2C0_SDA #0
2
3
PA1
PA2
LCD_SEG14
LCD_SEG15
TIM0_CC1 #0/1
TIM0_CC2 #0/1
I2C0_SCL #0
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EFM32TG Data Sheet
Pin Definitions
QFP64 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
PA3
Analog
LCD_SEG16
LCD_SEG17
LCD_SEG18
Digital IO power supply 0.
Ground.
Timers
Communication
Other
4
5
6
7
8
LES_ALTEX2 #0
LES_ALTEX3 #0
LES_ALTEX4 #0
PA4
PA5
IOVDD_0
VSS
LCD_SEG20/
LCD_COM4
LCD_SEG21/
LCD_COM5
LCD_SEG22/
LCD_COM6
LCD_SEG23/
LCD_COM7
ACMP0_CH4
DAC0_P0/
9
PB3
PB4
PB5
PB6
10
11
12
13
14
PC4
PC5
LETIM0_OUT0 #3
LETIM0_OUT1 #3
LES_CH4 #0
LES_CH5 #0
OPAMP_P0
ACMP0_CH5
DAC0_N1/
OPAMP_N0
US0_TX #4
US1_CLK #0
US0_RX #4
US1_CS #0
15
16
PB7
PB8
LFXTAL_P
LFXTAL_N
TIM1_CC0 #3
TIM1_CC1 #3
17
18
19
PA12
PA13
PA14
LCD_BCAP_P
LCD_BCAP_N
LCD_BEXT
Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin
low during reset, and let the internal pull-up ensure that reset is released.
20
21
RESETn
PB11
DAC0_OUT0/
TIM1_CC2 #3
OPAMP_OUT0
LETIM0_OUT0 #1
22
23
VSS
Ground.
AVDD_1
Analog power supply 1.
US0_CLK #4/5
LEU0_TX #1
US0_CS #4/5
LEU0_RX #1
24
25
PB13
PB14
HFXTAL_P
HFXTAL_N
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EFM32TG Data Sheet
Pin Definitions
QFP64 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
IOVDD_3
AVDD_0
Analog
Digital IO power supply 3.
Analog power supply 0.
ADC0_CH0
Timers
Communication
Other
26
27
DAC0_OUT0ALT #4/
OPAMP_OUT0ALT
OPAMP_OUT2 #1
ADC0_CH1
28
PD0
US1_TX #1
US1_RX #1
29
PD1
DAC0_OUT1ALT #4/
OPAMP_OUT1ALT
ADC0_CH2
TIM0_CC0 #3
30
31
PD2
PD3
TIM0_CC1 #3
TIM0_CC2 #3
US1_CLK #1
US1_CS #1
ADC0_CH3
OPAMP_N2
ADC0_CH4
32
33
PD4
PD5
LEU0_TX #0
LEU0_RX #0
OPAMP_P2
ADC0_CH5
OPAMP_OUT2 #0
ADC0_CH6
TIM1_CC0 #4
LETIM0_OUT0 #0
PCNT0_S0IN #3
TIM1_CC1 #4
US1_RX #2
LES_ALTEX0 #0
ACMP0_O #2
34
35
PD6
PD7
DAC0_P1/
I2C0_SDA #1
OPAMP_P1
ADC0_CH7
CMU_CLK0 #2
LES_ALTEX1 #0
ACMP1_O #2
CMU_CLK1 #1
LES_CH6 #0
US1_TX #2
DAC0_N1/
LETIM0_OUT1 #0
PCNT0_S1IN #3
I2C0_SCL #1
OPAMP_N1
36
37
38
39
PD8
PC6
ACMP0_CH6
ACMP0_CH7
I2C0_SDA #2
I2C0_SCL #2
PC7
LES_CH7 #0
VDD_DREG
Power supply for on-chip voltage regulator.
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required
at this pin.
40
DECOUPLE
41
42
43
44
PE4
PE5
PE6
PE7
LCD_COM0
LCD_COM1
US0_CS #1
US0_CLK #1
US0_RX #1
US0_TX #1
LCD_COM2
LCD_COM3
ACMP1_CH4
CMU_CLK0 #1
LES_CH12 #0
45
PC12
DAC0_OUT1ALT #0/
OPAMP_OUT1ALT
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EFM32TG Data Sheet
Pin Definitions
QFP64 Pin# and Name
Pin Alternate Functionality / Description
Pin #
Pin Name
Analog
Timers
Communication
Other
ACMP1_CH5
TIM1_CC0 #0
TIM1_CC2 #4
PCNT0_S0IN #0
46
47
48
49
50
51
PC13
DAC0_OUT1ALT #1/
OPAMP_OUT1ALT
ACMP1_CH6
LES_CH13 #0
TIM1_CC1 #0
PC14
PC15
PF0
DAC0_OUT1ALT #2/
OPAMP_OUT1ALT
ACMP1_CH7
US0_CS #3
LES_CH14 #0
PCNT0_S1IN #0
LES_CH15 #0
DBG_SWO #1
DAC0_OUT1ALT #3/
OPAMP_OUT1ALT
TIM1_CC2 #0
US0_CLK #3
US1_CLK #2
LEU0_TX #3
I2C0_SDA #5
US1_CS #2
TIM0_CC0 #5
DBG_SWCLK #0/1
LETIM0_OUT0 #2
TIM0_CC1 #5
DBG_SWDIO #0/1
GPIO_EM4WU3
PF1
LEU0_RX #3
I2C0_SCL #5
LETIM0_OUT1 #2
ACMP1_O #0
DBG_SWO #0
GPIO_EM4WU4
PRS_CH0 #1
PRS_CH1 #1
PRS_CH2 #1
PF2
LCD_SEG0
TIM0_CC2 #5
LEU0_TX #4
52
53
54
55
56
57
58
59
PF3
PF4
LCD_SEG1
LCD_SEG2
PF5
LCD_SEG3
IOVDD_5
VSS
Digital IO power supply 5.
Ground.
PE8
LCD_SEG4
PRS_CH3 #1
PE9
LCD_SEG5
PE10
LCD_SEG6
TIM1_CC0 #1
TIM1_CC1 #1
US0_TX #0
US0_RX #0
BOOT_TX
LES_ALTEX5 #0
BOOT_RX
60
PE11
PE12
LCD_SEG7
LCD_SEG8
US0_RX #3
US0_CLK #0
I2C0_SDA #6
US0_TX #3
CMU_CLK1 #2
61
TIM1_CC2 #1
LES_ALTEX6 #0
LES_ALTEX7 #0
ACMP0_O #0
62
PE13
LCD_SEG9
US0_CS #0
I2C0_SCL #6
LEU0_TX #2
LEU0_RX #2
GPIO_EM4WU5
63
64
PE14
PE15
LCD_SEG10
LCD_SEG11
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EFM32TG Data Sheet
Pin Definitions
5.11.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table
shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.
Table 5.32. Alternate functionality overview
Alternate
LOCATION
3
Functionality
ACMP0_CH4
ACMP0_CH5
ACMP0_CH6
ACMP0_CH7
ACMP0_O
0
1
2
PD6
PD7
4
5
6
Description
PC4
Analog comparator ACMP0, channel 4.
Analog comparator ACMP0, channel 5.
Analog comparator ACMP0, channel 6.
Analog comparator ACMP0, channel 7.
Analog comparator ACMP0, digital output.
Analog comparator ACMP1, channel 4.
Analog comparator ACMP1, channel 5.
Analog comparator ACMP1, channel 6.
Analog comparator ACMP1, channel 7.
Analog comparator ACMP1, digital output.
PC5
PC6
PC7
PE13
PC12
PC13
PC14
PC15
PF2
ACMP1_CH4
ACMP1_CH5
ACMP1_CH6
ACMP1_CH7
ACMP1_O
Analog to digital converter ADC0, input channel
number 0.
ADC0_CH0
ADC0_CH1
ADC0_CH2
ADC0_CH3
ADC0_CH4
ADC0_CH5
ADC0_CH6
ADC0_CH7
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
Analog to digital converter ADC0, input channel
number 1.
Analog to digital converter ADC0, input channel
number 2.
Analog to digital converter ADC0, input channel
number 3.
Analog to digital converter ADC0, input channel
number 4.
Analog to digital converter ADC0, input channel
number 5.
Analog to digital converter ADC0, input channel
number 6.
Analog to digital converter ADC0, input channel
number 7.
BOOT_RX
BOOT_TX
CMU_CLK0
CMU_CLK1
PE11
PE10
PA2
Bootloader RX.
Bootloader TX.
PC12 PD7
PD8 PE12
Clock Management Unit, clock output number 0.
Clock Management Unit, clock output number 1.
PA1
DAC0_N0/
OPAMP_N0
PC5
PD7
Operational Amplifier 0 external negative input.
Operational Amplifier 1 external negative input.
DAC0_N1/
OPAMP_N1
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EFM32TG Data Sheet
Pin Definitions
Alternate
LOCATION
3
Functionality
OPAMP_N2
0
1
2
4
5
6
Description
PD3
Operational Amplifier 2 external negative input.
DAC0_OUT0/
OPAMP_OUT0
Digital to Analog Converter DAC0_OUT0 /OPAMP
output channel number 0.
PB11
DAC0_OUT0AL
T/
Digital to Analog Converter DAC0_OUT0ALT /
OPAMP alternative output for channel 0.
PD0
OPAMP_OUT0
ALT
DAC0_OUT1AL
T/
Digital to Analog Converter DAC0_OUT1ALT /
OPAMP alternative output for channel 1.
PC12 PC13 PC14 PC15 PD1
OPAMP_OUT1
ALT
OPAMP_OUT2 PD5
PD0
Operational Amplifier 2 output.
DAC0_P0/
PC4
Operational Amplifier 0 external positive input.
OPAMP_P0
DAC0_P1/
PD6
Operational Amplifier 1 external positive input.
OPAMP_P1
OPAMP_P2
PD4
PF0
Operational Amplifier 2 external positive input.
Debug-interface Serial Wire clock input.
DBG_SWCLK
PF0
Note that this function is enabled to pin out of reset,
and has a built-in pull down.
Debug-interface Serial Wire data input / output.
DBG_SWDIO
DBG_SWO
PF1
PF2
PF1
Note that this function is enabled to pin out of reset,
and has a built-in pull up.
Debug-interface Serial Wire viewer Output.
PC15
Note that this function is not enabled after reset, and
must be enabled by software to be used.
GPIO_EM4WU0 PA0
GPIO_EM4WU3 PF1
GPIO_EM4WU4 PF2
GPIO_EM4WU5 PE13
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
High Frequency Crystal negative pin. Also used as
external optional clock input pin.
HFXTAL_N
PB14
HFXTAL_P
I2C0_SCL
I2C0_SDA
PB13
PA1
PA0
High Frequency Crystal positive pin.
I2C0 Serial Clock Line input / output.
I2C0 Serial Data input / output.
PD7
PD6
PC7
PC6
PF1
PF0
PE13
PE12
LCD voltage booster (optional), boost capacitor,
negative pin. If using the LCD voltage booster, con-
nect a 22 nF capacitor between LCD_BCAP_N and
LCD_BCAP_P.
LCD_BCAP_N PA13
LCD_BCAP_P PA12
LCD voltage booster (optional), boost capacitor,
positive pin. If using the LCD voltage booster, con-
nect a 22 nF capacitor between LCD_BCAP_N and
LCD_BCAP_P.
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Rev. 2.10 | 161
EFM32TG Data Sheet
Pin Definitions
Alternate
LOCATION
3
Functionality
0
1
2
4
5
6
Description
LCD voltage booster (optional), boost output. If us-
ing the LCD voltage booster, connect a 1 uF capaci-
tor between this pin and VSS.
LCD_BEXT
PA14
An external LCD voltage may also be applied to this
pin if the booster is not enabled.
If AVDD is used directly as the LCD supply voltage,
this pin may be left unconnected or used as a GPIO.
LCD_COM0
LCD_COM1
LCD_COM2
LCD_COM3
PE4
PE5
PE6
PE7
LCD driver common line number 0.
LCD driver common line number 1.
LCD driver common line number 2.
LCD driver common line number 3.
LCD segment line 0. Segments 0, 1, 2 and 3 are
controlled by SEGEN0.
LCD_SEG0
LCD_SEG1
LCD_SEG2
LCD_SEG3
LCD_SEG4
LCD_SEG5
LCD_SEG6
LCD_SEG7
LCD_SEG8
LCD_SEG9
LCD_SEG10
LCD_SEG11
LCD_SEG13
LCD_SEG14
LCD_SEG15
LCD_SEG16
LCD_SEG17
PF2
LCD segment line 1. Segments 0, 1, 2 and 3 are
controlled by SEGEN0.
PF3
LCD segment line 2. Segments 0, 1, 2 and 3 are
controlled by SEGEN0.
PF4
LCD segment line 3. Segments 0, 1, 2 and 3 are
controlled by SEGEN0.
PF5
LCD segment line 4. Segments 4, 5, 6 and 7 are
controlled by SEGEN1.
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PA0
PA1
PA2
PA3
PA4
LCD segment line 5. Segments 4, 5, 6 and 7 are
controlled by SEGEN1.
LCD segment line 6. Segments 4, 5, 6 and 7 are
controlled by SEGEN1.
LCD segment line 7. Segments 4, 5, 6 and 7 are
controlled by SEGEN1.
LCD segment line 8. Segments 8, 9, 10 and 11 are
controlled by SEGEN2.
LCD segment line 9. Segments 8, 9, 10 and 11 are
controlled by SEGEN2.
LCD segment line 10. Segments 8, 9, 10 and 11 are
controlled by SEGEN2.
LCD segment line 11. Segments 8, 9, 10 and 11 are
controlled by SEGEN2.
LCD segment line 13. Segments 12, 13, 14 and 15
are controlled by SEGEN3.
LCD segment line 14. Segments 12, 13, 14 and 15
are controlled by SEGEN3.
LCD segment line 15. Segments 12, 13, 14 and 15
are controlled by SEGEN3.
LCD segment line 16. Segments 16, 17, 18 and 19
are controlled by SEGEN4.
LCD segment line 17. Segments 16, 17, 18 and 19
are controlled by SEGEN4.
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EFM32TG Data Sheet
Pin Definitions
Alternate
LOCATION
3
Functionality
0
1
2
4
5
6
Description
LCD segment line 18. Segments 16, 17, 18 and 19
are controlled by SEGEN4.
LCD_SEG18
PA5
LCD segment line 20. Segments 20, 21, 22 and 23
are controlled by SEGEN5. This pin may also be
used as LCD COM line 4
LCD_SEG20/
LCD_COM4
PB3
PB4
PB5
PB6
LCD segment line 21. Segments 20, 21, 22 and 23
are controlled by SEGEN5. This pin may also be
used as LCD COM line 5
LCD_SEG21/
LCD_COM5
LCD segment line 22. Segments 20, 21, 22 and 23
are controlled by SEGEN5. This pin may also be
used as LCD COM line 6
LCD_SEG22/
LCD_COM6
LCD segment line 23. Segments 20, 21, 22 and 23
are controlled by SEGEN5. This pin may also be
used as LCD COM line 7
LCD_SEG23/
LCD_COM7
LES_ALTEX0
LES_ALTEX1
LES_ALTEX2
LES_ALTEX3
LES_ALTEX4
LES_ALTEX5
LES_ALTEX6
LES_ALTEX7
LES_CH4
PD6
LESENSE alternate exite output 0.
LESENSE alternate exite output 1.
LESENSE alternate exite output 2.
LESENSE alternate exite output 3.
LESENSE alternate exite output 4.
LESENSE alternate exite output 5.
LESENSE alternate exite output 6.
LESENSE alternate exite output 7.
LESENSE channel 4.
PD7
PA3
PA4
PA5
PE11
PE12
PE13
PC4
LES_CH5
PC5
LESENSE channel 5.
LES_CH6
PC6
LESENSE channel 6.
LES_CH7
PC7
LESENSE channel 7.
LES_CH12
LES_CH13
LES_CH14
LES_CH15
PC12
PC13
PC14
PC15
LESENSE channel 12.
LESENSE channel 13.
LESENSE channel 14.
LESENSE channel 15.
LETIM0_OUT0 PD6
LETIM0_OUT1 PD7
PB11
PF0
PC4
PC5
Low Energy Timer LETIM0, output channel 0.
Low Energy Timer LETIM0, output channel 1.
LEUART0 Receive input.
PF1
LEU0_RX
LEU0_TX
PD5
PD4
PB14
PB13
PE15
PF1
PF0
PA0
PF2
LEUART0 Transmit output. Also used as receive in-
put in half duplex communication.
PE14
Low Frequency Crystal (typically 32.768 kHz) nega-
tive pin. Also used as an optional external clock in-
put pin.
LFXTAL_N
PB8
Low Frequency Crystal (typically 32.768 kHz) posi-
tive pin.
LFXTAL_P
PB7
PCNT0_S0IN
PC13
PD6
Pulse Counter PCNT0 input number 0.
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EFM32TG Data Sheet
Pin Definitions
Alternate
LOCATION
Functionality
PCNT0_S1IN
PRS_CH0
PRS_CH1
PRS_CH2
PRS_CH3
TIM0_CC0
TIM0_CC1
TIM0_CC2
TIM1_CC0
TIM1_CC1
TIM1_CC2
US0_CLK
US0_CS
0
PC14
PA0
PA1
1
2
3
4
5
6
Description
PD7
Pulse Counter PCNT0 input number 1.
PF3
PF4
PF5
PE8
PA0
PA1
PA2
Peripheral Reflex System PRS, channel 0.
Peripheral Reflex System PRS, channel 1.
Peripheral Reflex System PRS, channel 2.
Peripheral Reflex System PRS, channel 3.
Timer 0 Capture Compare input / output channel 0.
Timer 0 Capture Compare input / output channel 1.
Timer 0 Capture Compare input / output channel 2.
Timer 1 Capture Compare input / output channel 0.
Timer 1 Capture Compare input / output channel 1.
Timer 1 Capture Compare input / output channel 2.
USART0 clock input / output.
PA0
PA1
PA2
PD1
PD2
PD3
PB7
PB8
PB11
PA0
PF0
PF1
PF2
PC13 PE10
PC14 PE11
PC15 PE12
PD6
PD7
PC13
PE12
PE13
PE5
PE4
PC15 PB13
PC14 PB14
PB13
PB14
USART0 chip select input / output.
USART0 Asynchronous Receive.
US0_RX
US0_TX
PE11
PE10
PE6
PE7
PE12
PE13
PB8
PB7
USART0 Synchronous mode Master Input / Slave
Output (MISO).
USART0 Asynchronous Transmit.Also used as re-
ceive input in half duplex communication.
USART0 Synchronous mode Master Output / Slave
Input (MOSI).
US1_CLK
US1_CS
PB7
PB8
PD2
PD3
PF0
PF1
USART1 clock input / output.
USART1 chip select input / output.
USART1 Asynchronous Receive.
US1_RX
US1_TX
PD1
PD0
PD6
PD7
USART1 Synchronous mode Master Input / Slave
Output (MISO).
USART1 Asynchronous Transmit.Also used as re-
ceive input in half duplex communication.
USART1 Synchronous mode Master Output / Slave
Input (MOSI).
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Rev. 2.10 | 164
EFM32TG Data Sheet
Pin Definitions
5.11.3 GPIO Pinout Overview
The specific GPIO pins available in EFM32TG842 is shown in the following table. Each GPIO port is organized as 16-bit ports indicated
by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.
Table 5.33. GPIO Pinout
Port
Pin
15
Pin
14
Pin
13
Pin
12
Pin
11
Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
10
Port A
Port B
Port C
Port D
Port E
Port F
-
-
PA14 PA13 PA12
PB14 PB13
-
-
-
-
-
-
-
-
-
-
-
-
PA5 PA4 PA3 PA2 PA1 PA0
-
PB11
PB8 PB7 PB6 PB5 PB4 PB3
PC7 PC6 PC5 PC4
-
-
-
-
-
-
PC15 PC14 PC13 PC12
-
-
-
-
-
-
-
-
PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PF5 PF4 PF3 PF2 PF1 PF0
5.11.4 Opamp Pinout Overview
The specific opamp terminals available in EFM32TG842 is shown in the following figure.
PB11
OUT0ALT
OUT0
PC4
PC5
+
OPA0
-
+
PD4
PD3
PC12
PC13
PC14
PC15
PD0
OPA2
-
OUT2
PD6
PD7
OUT1ALT
OUT1
+
OPA1
-
PD1
PD5
Figure 5.21. Opamp Pinout
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Rev. 2.10 | 165
EFM32TG Data Sheet
BGA48 Package Specifications
6. BGA48 Package Specifications
6.1 BGA48 Package Dimensions
0.1 C
A
B
(2X)
A1 BALL CORNER
4.00
A1 BALL CORNER
48X 0.3±0.05
7
6
5
4
3
2
1
A
B
C
D
E
F
0.15
0.05
C
C
A B
G
(0.50)
0.50
B
3.00
0.08 C
Figure 6.1. BGA48
Note:
1. The dimensions in parenthesis are reference.
2. Datum 'C' and seating plane are defined by the crown of the solder balls.
3. All dimensions are in millimeters.
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Rev. 2.10 | 166
EFM32TG Data Sheet
BGA48 Package Specifications
6.2 BGA48 PCB Layout
b
a
e
d
Figure 6.2. BGA48 PCB Land Pattern
Table 6.1. BGA48 PCB Land Pattern Dimensions (Dimensions in mm)
Symbol
Dim. (mm)
Symbol
Row name and column num-
ber
a
b
d
e
0.25
0.50
3.00
3.00
r1
rn
A
G
1
c1
cn
7
b
a
e
d
Figure 6.3. BGA48 PCB Solder Mask
Table 6.2. BGA48 PCB Solder Mask Dimensions (Dimensions in mm)
Symbol
Dim. (mm)
0.28
a
b
d
e
0.50
3.00
3.00
silabs.com | Building a more connected world.
Rev. 2.10 | 167
EFM32TG Data Sheet
BGA48 Package Specifications
b
a
e
d
Figure 6.4. BGA48 PCB Stencil Design
Table 6.3. BGA48 PCB Stencil Design Dimensions (Dimensions in mm)
Symbol
Dim. (mm)
0.25
a
b
d
e
0.50
3.00
3.00
Note:
1. The drawings are not to scale.
2. All dimensions are in millimeters.
3. All drawings are subject to change without notice.
4. The PCB Land Pattern drawing is in compliance with IPC-7351B.
5. Stencil thickness 0.125 mm.
6. For detailed pin-positioning, see Pin Definitions.
silabs.com | Building a more connected world.
Rev. 2.10 | 168
EFM32TG Data Sheet
BGA48 Package Specifications
6.3 BGA48 Package Marking
In the illustration below package fields and position are shown.
Figure 6.5. Example Chip Marking (Top View)
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Rev. 2.10 | 169
EFM32TG Data Sheet
QFN24 Package Specifications
7. QFN24 Package Specifications
7.1 QFN24 Package Dimensions
EXPOSED DIE
ATTACHED PAD
D
D2
B
0.1
C A B
A
PIN #1 CORNER
PIN #1 CORNER
19 20 21 22 23 24
18
17
16
15
14
13
1
2
3
4
5
6
12 11 10
9
8
7
24 X b
24 X L
bbb
ddd
C
A
B
e
M
G
ccc
C
eee
C
TERMINAL TIP
DETAIL G
VIEW ROTATED 90° CLOCKWISE
C
SEATING PLANE
e
EVEN / ODD TERMINAL SIDE
M
Figure 7.1. QFN24
Note:
1. Dimensioning & tolerancing confirm to ASME Y14.5M-1994.
2. All dimensions are in millimeters. Angles are in degrees.
3. Dimension 'b' applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from the terminal tip. Dimension L1
represents terminal full back from package edge up to 0.1 mm is acceptable.
4. Coplanarity applies to the exposed heat slug as well as the terminal.
5. Radius on terminal is optional.
Table 7.1. QFN (Dimensions in mm)
Symbol
Min
A
A1
0.80 0.00
0.85
0.90 0.05
A3
b
D
E
D2
E2
e
L
L1
aaa
bbb
ccc
ddd
eee
0.25
0.30
0.35
3.50 3.50
3.60 3.60
3.70 3.70
0.35 0.00
0.40
0.203
REF
5.00 5.00
BSC BSC
0.65
BSC
Nom
Max
—
0.10 0.10 0.10 0.05 0.08
0.45 0.10
The QFN24 package uses Nickel-Palladium-Gold preplated leadframe.
All EFM32 packages are RoHS compliant and free of Bromine (Br) and Antimony (Sb).
For additional Quality and Environmental information, please see: http://www.silabs.com/support/quality/pages/default.aspx.
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Rev. 2.10 | 170
EFM32TG Data Sheet
QFN24 Package Specifications
7.2 QFN24 PCB Layout
a
p8
p7
p1
p6
b
c
p9
g
e
p2
p5
p3
p4
f
d
Figure 7.2. QFN24 PCB Land Pattern
Table 7.2. QFN24 PCB Land Pattern Dimensions (Dimensions in mm)
Symbol
Dim. (mm)
0.80
Symbol
P1
Pin Number
Symbol
Pin Number
a
b
c
d
e
f
1
6
P8
24
0
-
0.30
P2
P9
0.65
P3
7
-
-
-
-
-
5.00
P4
12
13
18
19
-
5.00
P5
-
3.60
P6
-
g
3.60
P7
-
a
b
c
g
e
f
d
Figure 7.3. QFN24 PCB Solder Mask
Table 7.3. QFN24 PCB Solder Mask Dimensions (Dimensions in mm)
Symbol
Dim. (mm)
0.92
a
b
c
0.42
0.65
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EFM32TG Data Sheet
QFN24 Package Specifications
Symbol
Dim. (mm)
d
e
f
5.00
5.00
3.72
3.72
g
a
b
c
x
y
e
z
d
Figure 7.4. QFN24 PCB Stencil Design
Table 7.4. QFN24 PCB Stencil Design Dimensions (Dimensions in mm)
Symbol
Dim. (mm)
0.60
a
b
c
d
e
x
y
z
0.25
0.65
5.00
5.00
1.00
1.00
0.50
Note:
1. The drawings are not to scale.
2. All dimensions are in millimeters.
3. All drawings are subject to change without notice.
4. The PCB Land Pattern drawing is in compliance with IPC-7351B.
5. Stencil thickness 0.125 mm.
6. For detailed pin-positioning, see Pin Definitions.
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Rev. 2.10 | 172
EFM32TG Data Sheet
QFN24 Package Specifications
7.3 QFN24 Package Marking
In the illustration below package fields and position are shown.
Figure 7.5. Example Chip Marking (Top View)
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Rev. 2.10 | 173
EFM32TG Data Sheet
QFN32 Package Specifications
8. QFN32 Package Specifications
8.1 QFN32 Package Dimensions
D2
D
25
26
27
28
29
30
31
32
1
24
23
22
21
20
19
18
17
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
32xL
32xb
m
m
G
M
SEATING PLANE
DETAIL G
VIEW ROTATED 90° CLOCKWISE
e
EVEN / ODD TERMINL SIDE
M
Figure 8.1. QFN32
Note:
1. Dimensioning & tolerancing confirm to ASME Y14.5M-1994.
2. All dimensions are in millimeters. Angles are in degrees.
3. Dimension 'b' applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from the terminal tip. Dimension L1
represents terminal full back from package edge up to 0.1 mm is acceptable.
4. Coplanarity applies to the exposed heat slug as well as the terminal.
5. Radius on terminal is optional.
Table 8.1. QFN32 (Dimensions in mm)
Symbol
Min
A
A1
0.80 0.00
0.85
0.90 0.05
A3
b
D
E
D2
E2
e
L
L1
aaa
bbb
ccc
ddd
eee
0.25
0.30
0.35
4.30 4.30
4.40 4.40
4.50 4.50
0.35 0.00
0.40
0.203
REF
6.00 6.00
BSC BSC
0.65
BSC
Nom
Max
—
0.10 0.10 0.10 0.05 0.08
0.45 0.10
The QFN32 package uses Nickel-Palladium-Gold preplated leadframe.
All EFM32 packages are RoHS compliant and free of Bromine (Br) and Antimony (Sb).
For additional Quality and Environmental information, please see: http://www.silabs.com/support/quality/pages/default.aspx.
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Rev. 2.10 | 174
EFM32TG Data Sheet
QFN32 Package Specifications
8.2 QFN32 PCB Layout
a
p8
p7
p1
p6
b
c
p9
g
e
p2
p5
p3
p4
f
d
Figure 8.2. QFN32 PCB Land Pattern
Table 8.2. QFN32 PCB Land Pattern Dimensions (Dimensions in mm)
Symbol
Dim. (mm)
0.80
Symbol
P1
Pin Number
Symbol
P6
Pin Number
a
b
c
d
e
f
1
8
24
25
32
0
0.35
P2
P7
0.65
P3
9
P8
6.00
P4
16
17
P9
6.00
P5
4.40
g
4.40
a
b
c
g
e
f
d
Figure 8.3. QFN32 PCB Solder Mask
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Rev. 2.10 | 175
EFM32TG Data Sheet
QFN32 Package Specifications
Table 8.3. QFN32 PCB Solder Mask Dimensions (Dimensions in mm)
Symbol
Dim. (mm)
a
b
c
d
e
f
0.92
0.47
0.65
6.00
6.00
4.52
4.52
g
a
b
c
x
y
e
z
d
Figure 8.4. QFN32 PCB Stencil Design
Table 8.4. QFN32 PCB Stencil Design Dimensions (Dimensions in mm)
Symbol
Dim. (mm)
0.70
a
b
c
d
e
x
y
z
0.25
0.65
6.00
6.00
1.30
1.30
0.50
Note:
1. The drawings are not to scale.
2. All dimensions are in millimeters.
3. All drawings are subject to change without notice.
4. The PCB Land Pattern drawing is in compliance with IPC-7351B.
5. Stencil thickness 0.125 mm.
6. For detailed pin-positioning, see Pin Definitions.
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Rev. 2.10 | 176
EFM32TG Data Sheet
QFN32 Package Specifications
8.3 QFN32 Package Marking
In the illustration below package fields and position are shown.
Figure 8.5. Example Chip Marking (Top View)
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Rev. 2.10 | 177
EFM32TG Data Sheet
QFN64 Package Specifications
9. QFN64 Package Specifications
9.1 QFN64 Package Dimensions
49
64
48
1
33
16
32
17
m
m
Figure 9.1. QFN64
Note:
1. Dimensioning & tolerancing confirm to ASME Y14.5M-1994.
2. All dimensions are in millimeters. Angles are in degrees.
3. Dimension 'b' applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from the terminal tip. Dimension L1
represents terminal full back from package edge up to 0.1 mm is acceptable.
4. Coplanarity applies to the exposed heat slug as well as the terminal.
5. Radius on terminal is optional.
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EFM32TG Data Sheet
QFN64 Package Specifications
Table 9.1. QFN64 (Dimensions in mm)
Symbol
A
Min
0.80
0.00
Nom
0.85
Max
0.90
0.05
A1
A3
b
—
0.203 REF
0.25
0.20
0.30
D
9.00 BSC
9.00 BSC
7.20
E
D2
E2
e
7.10
7.10
7.30
7.30
7.20
0.50 BSC
0.45
L
0.40
0.00
0.50
0.10
L1
—
aaa
bbb
ccc
ddd
eee
0.10
0.10
0.10
0.05
0.08
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Rev. 2.10 | 179
EFM32TG Data Sheet
QFN64 Package Specifications
9.2 QFN64 PCB Layout
a
p8
p7
p1
p6
b
c
p9
g
e
p2
p5
p3
p4
f
d
Figure 9.2. QFN64 PCB Land Pattern
Table 9.2. QFN64 PCB Land Pattern Dimensions (Dimensions in mm)
Symbol
Dim. (mm)
0.85
Symbol
P1
Pin Number
Symbol
P8
Pin Number
a
b
c
d
e
f
1
64
0
0.30
P2
16
17
32
33
48
49
P9
0.50
P3
8.90
P4
8.90
P5
7.20
P6
g
7.20
P7
a
b
c
g
e
f
d
Figure 9.3. QFN64 PCB Solder Mask
Table 9.3. QFN64 PCB Solder Mask Dimensions (Dimensions in mm)
Symbol
Dim. (mm)
0.97
Symbol
Dim. (mm)
a
b
c
e
f
8.90
7.32
7.32
0.42
0.50
g
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Rev. 2.10 | 180
EFM32TG Data Sheet
QFN64 Package Specifications
Symbol
Dim. (mm)
Symbol
Dim. (mm)
d
8.90
-
-
a
b
c
x
y
e
z
d
Figure 9.4. QFN64 PCB Stencil Design
Table 9.4. QFN64 PCB Stencil Design Dimensions (Dimensions in mm)
Symbol
Dim. (mm)
0.75
Symbol
Dim. (mm)
8.90
a
b
c
d
e
x
y
z
0.22
2.70
0.50
2.70
8.90
0.80
Note:
1. The drawings are not to scale.
2. All dimensions are in millimeters.
3. All drawings are subject to change without notice.
4. The PCB Land Pattern drawing is in compliance with IPC-7351B.
5. Stencil thickness 0.125 mm.
6. For detailed pin-positioning, see Pin Definitions.
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Rev. 2.10 | 181
EFM32TG Data Sheet
QFN64 Package Specifications
9.3 QFN64 Package Marking
In the illustration below package fields and position are shown.
Figure 9.5. Example Chip Marking (Top View)
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Rev. 2.10 | 182
EFM32TG Data Sheet
TQFP48 Package Specifications
10. TQFP48 Package Specifications
10.1 TQFP48 Package Dimensions
Figure 10.1. TQFP48
Note:
1. Dimensions and tolerance per ASME Y14.5M-1994
2. Control dimension: Millimeter
3. Datum plane AB is located at bottom of lead and is coincident with the lead where the lead exists from the plastic body at the
bottom of the parting line.
4. Datums T, U and Z to be determined at datum plane AB.
5. Dimensions S and V to be determined at seating plane AC.
6. Dimensions A and B do not include mold protrusion. Allowable protrusion is 0.250 per side. Dimensions A and B do include mold
mismatch and are determined at datum AB.
7. Dimension D does not include dambar protrusion. Dambar protrusion shall not cause the D dimension to exceed 0.350.
8. Minimum solder plate thickness shall be 0.0076.
9. Exact shape of each corner is optional.
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Rev. 2.10 | 183
EFM32TG Data Sheet
TQFP48 Package Specifications
Table 10.1. QFP48 (Dimensions in mm)
DIM
A
MIN
—
NOM
MAX
—
DIM
M
MIN
—
NOM
12DEG REF
—
MAX
7.000 BSC
A1
B
—
3.500 BSC
—
N
0.090
—
0.160
—
—
7.000 BSC
—
P
0.250 BSC
—
B1
C
—
3.500 BSC
—
R
0.150
—
0.250
—
1.000
0.170
0.950
0.170
—
—
1.200
0.270
1.050
0.230
—
S
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 BSC
1.000 BSC
D
—
S1
V
—
—
E
—
—
—
F
—
V1
W
AA
—
—
G
H
0.500 BSC
—
—
0.050
0.090
0.500
0DEG
—
—
—
—
0.150
0.200
0.700
7DEG
—
—
J
K
L
The TQFP48 package is 7 by 7 mm in size and has a 0.5 mm pin pitch.
The TQFP48 package uses Nickel-Palladium-Gold preplated leadframe.
All EFM32 packages are RoHS compliant and free of Bromine (Br) and Antimony (Sb).
For additional Quality and Environmental information, please see: http://www.silabs.com/support/quality/pages/default.aspx.
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Rev. 2.10 | 184
EFM32TG Data Sheet
TQFP48 Package Specifications
10.2 TQFP48 PCB Layout
a
p8
p7
p6
p1
b
c
e
p2
p5
p3
p4
d
Figure 10.2. TQFP48 PCB Land Pattern
Table 10.2. TQFP48 PCB Land Pattern Dimensions (Dimensions in mm)
Symbol
Dim. (mm)
1.60
Symbol
P1
Pin Number
Symbol
P6
Pin Number
a
b
c
d
e
1
36
37
48
0.30
P2
12
13
24
25
P7
0.50
P3
P8
8.50
P4
8.50
P5
a
b
c
e
d
Figure 10.3. TQFP48 PCB Solder Mask
Table 10.3. TQFP48 PCB Solder Mask Dimensions (Dimensions in mm)
Symbol
Dim. (mm)
1.72
a
b
c
d
e
0.42
0.50
8.50
8.50
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Rev. 2.10 | 185
EFM32TG Data Sheet
TQFP48 Package Specifications
a
b
c
e
d
Figure 10.4. TQFP48 PCB Stencil Design
Table 10.4. TQFP48 PCB Stencil Design Dimensions (Dimensions in mm)
Symbol
Dim. (mm)
1.50
a
b
c
d
e
0.20
0.50
8.50
8.50
Note:
1. The drawings are not to scale.
2. All dimensions are in millimeters.
3. All drawings are subject to change without notice.
4. The PCB Land Pattern drawing is in compliance with IPC-7351B.
5. Stencil thickness 0.125 mm.
6. For detailed pin-positioning, see Pin Definitions.
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Rev. 2.10 | 186
EFM32TG Data Sheet
TQFP48 Package Specifications
10.3 TQFP48 Package Marking
In the illustration below package fields and position are shown.
Figure 10.5. Example Chip Marking (Top View)
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Rev. 2.10 | 187
EFM32TG Data Sheet
TQFP64 Package Specifications
11. TQFP64 Package Specifications
11.1 TQFP64 Package Dimensions
F
C
L
Figure 11.1. TQFP64
Note:
1. All dimensions & tolerancing confirm to ASME Y14.5M-1994.
2. The top package body size may be smaller than the bottom package body size.
3. Datum 'A,B', and 'B' to be determined at datum plane 'H'.
4. To be determined at seating place 'C'.
5. Dimension 'D1' and 'E1' do not include mold protrusions. Allowable protrusion is 0.25mm per side. 'D1' and 'E1' are maximum plas-
tic body size dimension including mold mismatch. Dimension 'D1' and 'E1' shall be determined at datum plane 'H'.
6. Detail of Pin 1 indicatifier are option all but must be located within the zone indicated.
7. Dimension 'b' does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maxi-
mum 'b' dimension by more than 0.08 mm. Dambar can not be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm.
8. Exact shape of each corner is optional.
9. These dimension apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.
10. All dimensions are in millimeters.
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Rev. 2.10 | 188
EFM32TG Data Sheet
TQFP64 Package Specifications
Table 11.1. QFP64 (Dimensions in mm)
DIM
A
MIN
—
NOM
1.10
—
MAX
1.20
0.15
1.05
0.27
0.23
0.20
0.16
DIM
L1
R1
R2
S
MIN
NOM
—
MAX
A1
A2
b
0.05
0.95
0.17
0.17
0.09
0.09
0.08
0.08
0.20
0°
—
—
0.20
—
1.00
0.22
0.20
—
—
—
b1
c
θ
3.5°
—
7°
θ1
θ2
θ3
0°
—
C1
D
—
11°
11°
12°
12°
13°
13°
12.0 BSC
D1
e
10.0 BSC
0.50 BSC
12.0 BSC
10.0 BSC
E
E1
L
0.45
0.60
0.75
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Rev. 2.10 | 189
EFM32TG Data Sheet
TQFP64 Package Specifications
11.2 TQFP64 PCB Layout
a
p8
p7
p6
p1
b
c
e
p2
p5
p3
p4
d
Figure 11.2. TQFP64 PCB Land Pattern
Table 11.2. TQFP64 PCB Land Pattern Dimensions (Dimensions in mm)
Symbol
Dim. (mm)
1.60
Symbol
P1
Pin Number
Symbol
P6
Pin Number
a
b
c
d
e
1
48
49
64
0.30
P2
16
17
32
33
P7
0.50
P3
P8
11.50
11.50
P4
P5
a
b
c
e
d
Figure 11.3. TQFP64 PCB Solder Mask
Table 11.3. TQFP64 PCB Solder Mask Dimensions (Dimensions in mm)
Symbol
Dim. (mm)
1.72
a
b
c
d
e
0.42
0.50
11.50
11.50
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Rev. 2.10 | 190
EFM32TG Data Sheet
TQFP64 Package Specifications
a
b
c
e
d
Figure 11.4. TQFP64 PCB Stencil Design
Table 11.4. TQFP64 PCB Stencil Design Dimensions (Dimensions in mm)
Symbol
Dim. (mm)
1.50
a
b
c
d
e
0.20
0.50
11.50
11.50
Note:
1. The drawings are not to scale.
2. All dimensions are in millimeters.
3. All drawings are subject to change without notice.
4. The PCB Land Pattern drawing is in compliance with IPC-7351B.
5. Stencil thickness 0.125 mm.
6. For detailed pin-positioning, see Pin Definitions.
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Rev. 2.10 | 191
EFM32TG Data Sheet
TQFP64 Package Specifications
11.3 TQFP64 Package Marking
In the illustration below package fields and position are shown.
Figure 11.5. Example Chip Marking (Top View)
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Rev. 2.10 | 192
EFM32TG Data Sheet
Chip Revision, Solder Information, Errata
12. Chip Revision, Solder Information, Errata
12.1 Chip Revision
The revision of a chip can be determined from the "Revision" field in the package marking.
12.2 Soldering Information
The latest IPC/JEDEC J-STD-020 recommendations for Pb-Free reflow soldering should be followed.
12.3 Errata
See the errata document for description and resolution of device errata. This document is available in Simplicity Studio and online at:
http://www.silabs.com/support/pages/document-library.aspx?p=MCUs--32-bit
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Rev. 2.10 | 193
EFM32TG Data Sheet
Revision History
13. Revision History
Revision 2.10
November, 2019
• 1. Feature List - Added SysTick.
• 2. Ordering Information - Updated for release of revision D devices.
• 4.2 Absolute Maximum Ratings - Removed footnote about storage temperature and added max sink/source current per I/O pin.
• 4.7 Flash – Added word write cycles between erase (WWCFLASH) specification.
• 4.10 Analog Digital Converter (ADC) - Updated ADC input impedance.
• 4.11 Digital Analog Converter (DAC) - Added max load current specification.
• 7.2 QFN24 PCB Layout - Corrected pin number for symbol P9.
• 8.2 QFN32 PCB Layout - Corrected pin number for symbol P9.
• 9.2 QFN64 PCB Layout - Corrected pin number for symbol P9.
Revision 2.00
August, 2018
• Consolidated all EFM32TG data sheets:
• EFM32TG108
• EFM32TG110
• EFM32TG210
• EFM32TG222
• EFM32TG225
• EFM32TG230
• EFM32TG232
• EFM32TG822
• EFM32TG825
• EFM32TG840
• EFM32TG842
• Added a Feature List section.
• 2. Ordering Information – Added ordering code decoder.
• 3.3 Memory Map – Separated the Memory Map into two figures – one for core and code space listing and one for peripheral listing.
• Environmental – Removed this section. Environmental specifications are available in the qualification report.
• Removed MSL information (Moisture Sensitivity Level). Instead, MSL information can be found in the Qual report that is available on
the Silicon Labs website.
• For QFN32 packages, corrected pin number for symbol P3.
• 6.1 BGA48 Package Dimensions – Removed statements regarding materials used.
• New formatting throughout.
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Rev. 2.10 | 194
EFM32TG Data Sheet
Revision History
Revision 1.40
March 6th, 2015
• This revision applies the following devices:
• EFM32TG108
• EFM32TG110
• EFM32TG210
• EFM32TG222
• EFM32TG225
• EFM32TG230
• EFM32TG232
• EFM32TG822
• EFM32TG825
• EFM32TG840
• EFM32TG842
• Updated Block Diagram.
• Updated Energy Modes current consumption.
• Updated Power Management section.
• Updated LFRCO and HFRCO sections.
• Added AUXHFRCO to block diagram and Electrical Characteristics.
• Corrected unit to kHz on LFRCO plots y-axis.
• For devices with ADC, updated ADC section and added clarification on conditions for INLADCand DNLADC parameters.
• For devices with DAC, updated ADC section and added clarification on conditions for INLDACand DNLDAC parameters.
• For devices with OPAMP, updated OPAMP section.
• For devices with ACMP, updated ACMP section and the response time graph.
• For devices with VCMP, updated VCMP section.
• For QFN24 and QFN32 packages, updated Package dimensions table.
• Updated Digital Peripherals section.
Revision 1.30
July 2nd, 2014
• This revision applies the following devices:
• EFM32TG108
• EFM32TG110
• EFM32TG210
• EFM32TG222
• EFM32TG225
• EFM32TG230
• EFM32TG232
• EFM32TG822
• EFM32TG825
• EFM32TG840
• EFM32TG842
• Updated current consumption.
• Updated transition between energy modes.
• Updated power management data.
• Updated GPIO data.
• Updated LFXO, HFXO, HFRCO and ULFRCO data.
• Updated LFRCO and HFRCO plots.
• Updated ACMP data.
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Rev. 2.10 | 195
EFM32TG Data Sheet
Revision History
Revision 1.21
November 21st, 2013
• This revision applies the following devices:
• EFM32TG108
• EFM32TG110
• EFM32TG210
• EFM32TG222
• EFM32TG225
• EFM32TG230
• EFM32TG232
• EFM32TG822
• EFM32TG825
• EFM32TG840
• EFM32TG842
• Updated figures.
• Updated errata-link.
• Updated chip marking.
• Added link to Environmental and Quality information.
• For devices with DAC, re-added missing DAC-data.
Revision 1.20
September 30th, 2013
• This revision applies the following devices:
• EFM32TG108
• EFM32TG110
• EFM32TG210
• EFM32TG222
• EFM32TG225
• EFM32TG230
• EFM32TG232
• EFM32TG822
• EFM32TG825
• EFM32TG840
• EFM32TG842
• Added I2C characterization data.
• For devices with DAC, corrected the DAC and OPAMP2 pin sharing information in the Alternate Functionality Pinout section.
• Corrected GPIO operating voltage from 1.8 V to 1.85 V.
• For devices with ADC, corrected the ADC gain and offset measurement reference voltage from 2.25 to 2.5V.
• For devices with ADC, corrected the ADC resolution from 12, 10 and 6 bit to 12, 8 and 6 bit.
• For QFP48 devices, updated the Max VESDCDM value to 750 V.
• Document changed status from "Preliminary".
• Updated Environmental information.
• Updated trademark, disclaimer and contact information.
• Other minor corrections.
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Rev. 2.10 | 196
EFM32TG Data Sheet
Revision History
Revision 1.10
June 28th, 2013
• This revision applies the following devices:
• EFM32TG108
• EFM32TG110
• EFM32TG210
• EFM32TG222
• EFM32TG225
• EFM32TG230
• EFM32TG232
• EFM32TG822
• EFM32TG825
• EFM32TG840
• EFM32TG842
• For BGA packages, updated PCB Land Pattern, PCB Solder Mask and PCB Stencil Design figures.
• Updated power requirements in the Power Management section.
• Removed minimum load capacitance figure and table. Added reference to application note.
• Other minor corrections.
Revision 1.00
September 11th, 2012
• This revision applies the following devices:
• EFM32TG108
• EFM32TG110
• EFM32TG210
• EFM32TG222
• EFM32TG225
• EFM32TG230
• EFM32TG232
• EFM32TG822
• EFM32TG825
• EFM32TG840
• EFM32TG842
• Updated the HFRCO 1 MHz band typical value to 1.2 MHz.
• Updated the HFRCO 7 MHz band typical value to 6.6 MHz.
• Added GPIO_EM4WU3, GPIO_EM4WU4 and GPIO_EM4WU5 pins and removed GPIO_EM4WU1 in the Alternate functionality
overview table.
• Other minor corrections.
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Rev. 2.10 | 197
EFM32TG Data Sheet
Revision History
Revision 0.96
May 4th, 2012
• This revision applies the following devices:
• EFM32TG108
• EFM32TG110
• EFM32TG210
• EFM32TG222
• EFM32TG225
• EFM32TG230
• EFM32TG232
• EFM32TG822
• EFM32TG825
• EFM32TG840
• EFM32TG842
• For BGA48 packages, added PCB land pattern, Stencil design and solder mask.
• For BGA48 packages, corrected PCB footprint figures and tables.
Revision 0.95
February 27th, 2012
• This revision applies the following devices:
• EFM32TG108
• EFM32TG110
• EFM32TG210
• EFM32TG222
• EFM32TG225
• EFM32TG230
• EFM32TG232
• EFM32TG822
• EFM32TG825
• EFM32TG840
• EFM32TG842
• For BGA48 packages, initial preliminary release.
• For BGA48 packages, corrected operating voltage from 1.8 V to 1.85 V.
• For BGA48 packages, added rising POR level and corrected Thermometer output gradient in Electrical Characteristics section.
• For BGA48 packages, updated Minimum Load Capacitance (CLFXOL) Requirement For Safe Crystal Startup.
• For BGA48 packages, added Gain error drift and Offset error drift to ADC table.
• For devices with OPAMP in BGA48 packages, added Opamp pinout overview.
• For BGA48 packages, added reference to errata document.
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Rev. 2.10 | 198
EFM32TG Data Sheet
Revision History
Revision 0.92
July 22nd, 2011
• This revision applies the following devices:
• EFM32TG108
• EFM32TG110
• EFM32TG210
• EFM32TG222
• EFM32TG225
• EFM32TG230
• EFM32TG232
• EFM32TG822
• EFM32TG825
• EFM32TG840
• EFM32TG842
• Updated current consumption numbers from latest device characterization data.
• For devices with OPAMP, updated OPAMP electrical characteristics.
• For devices with ADC, made ADC plots render properly in Adobe Reader.
• For EFM32TG822, corrected number of DAC channels available.
• For EFM32TG232, corrected number of DAC channels available.
• For EFM32TG842, corrected number of DAC channels available.
• For EFM32TG230, corrected number of DAC channels available.
Revision 0.91
February 4th, 2011
• This revision applies the following devices:
• EFM32TG108
• EFM32TG110
• EFM32TG210
• EFM32TG230
• EFM32TG840
• Corrected max DAC sampling rate.
• Increased max storage temperature.
• Added data for <150°C and <70°C on Flash data retention.
• Changed latch-up sensitivity test description.
• Added IO leakage current.
• Added Flash current consumption.
• Updated HFRCO data.
• Updated LFRCO data.
• For devices with ADC, added graph for ADC Absolute Offset over temperature.
• For devices with ADC, added graph for ADC Temperature sensor readout.
• For devices with OPAMP, updated OPAMP electrical characteristics.
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Rev. 2.10 | 199
EFM32TG Data Sheet
Revision History
Revision 0.90
December 1st, 2010
• This revision applies the following devices:
• EFM32TG108
• EFM32TG110
• EFM32TG210
• EFM32TG230
• EFM32TG840
• New peripherals added to pinout, including LESENSE and OpAmps.
April 14th, 2011
• This revision applies the following devices:
• EFM32TG222
• EFM32TG232
• EFM32TG822
• Initial preliminary release.
June 30th, 2011
• This revision applies the following devices:
• EFM32TG842
• Initial preliminary release.
Revision 0.70
August 16th, 2010
• This revision applies the following devices:
• EFM32TG110
• Added pinout.
Revision 0.60
June 8th, 2010
• This revision applies the following devices:
• EFM32TG230
• Corrected pinout.
Revision 0.50
May 25th, 2010
• This revision applies the following devices:
• EFM32TG108
• EFM32TG110
• EFM32TG210
• EFM32TG230
• EFM32TG840
• Block diagram update.
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Rev. 2.10 | 200
EFM32TG Data Sheet
Revision History
Revision 0.40
March 26th, 2010
• This revision applies the following devices:
• EFM32TG108
• EFM32TG110
• EFM32TG210
• EFM32TG230
• EFM32TG840
• Initial preliminary release.
silabs.com | Building a more connected world.
Rev. 2.10 | 201
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wireless tools, documentation,
software, source code libraries &
more. Available for Windows,
Mac and Linux!
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Disclaimer
Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or
intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"
parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes
without further notice to the product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information.
Without prior notification, Silicon Labs may update product firmware during the manufacturing process for security or reliability reasons. Such changes will not alter the specifications or the
performance of the product. Silicon Labs shall have no liability for the consequences of use of the information supplied in this document. This document does not imply or expressly grant
any license to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any FDA Class III devices, applications for which FDA premarket
approval is required or Life Support Systems without the specific written consent of Silicon Labs. A "Life Support System" is any product or system intended to support or sustain life and/or
health, which, if it fails, can be reasonably expected to result in significant personal injury or death. Silicon Labs products are not designed or authorized for military applications. Silicon
Labs products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering
such weapons. Silicon Labs disclaims all express and implied warranties and shall not be responsible or liable for any injuries or damages related to use of a Silicon Labs product in such
unauthorized applications.
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Silicon Laboratories Inc.® , Silicon Laboratories®, Silicon Labs®, SiLabs® and the Silicon Labs logo®, Bluegiga®, Bluegiga Logo®, ClockBuilder®, CMEMS®, DSPLL®, EFM®,
EFM32®, EFR, Ember®, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZRadio®, EZRadioPRO®,
Gecko®, Gecko OS, Gecko OS Studio, ISOmodem®, Precision32®, ProSLIC®, Simplicity Studio®, SiPHY®, Telegesis, the Telegesis Logo®, USBXpress® , Zentri, the Zentri logo and Zentri
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