EFM32WG360F64G-A-CSP81

...the world's most energy friendly microcontrollers

EFM32WG360 DATASHEET

F256/F128/F64

• ARM Cortex-M4 CPU platform

• Communication interfaces

• High Performance 32-bit processor @ up to 48 MHz

• DSP instruction support and floating-point unit

• Memory Protection Unit

• Flexible Energy Management System

• 20 nA @ 3 V Shutoff Mode

• 3× Universal Synchronous/Asynchronous Receiv-

er/Transmitter

• UART/SPI/SmartCard (ISO 7816)/IrDA/I2S

• 2× Universal Asynchronous Receiver/Transmitter

• 2× Low Energy UART

• Autonomous operation with DMA in Deep Sleep

Mode

• 0.4 µA @ 3 V Shutoff Mode with RTC

• 0.65 µA @ 3 V Stop Mode, including Power-on Reset, Brown-out

Detector, RAM and CPU retention

• 0.95 µA @ 3 V Deep Sleep Mode, including RTC with 32.768 kHz

oscillator, Power-on Reset, Brown-out Detector, RAM and CPU

retention

• 2× I²C Interface with SMBus support

• Address recognition in Stop Mode

• Universal Serial Bus (USB) with Host & OTG support

• Fully USB 2.0 compliant

• 63 µA/MHz @ 3 V Sleep Mode

• 225 µA/MHz @ 3 V Run Mode, with code executed from flash

• 256/128/64 KB Flash

• 32 KB RAM

• 65 General Purpose I/O pins

• On-chip PHY and embedded 5V to 3.3V regulator

• Ultra low power precision analog peripherals

• 12-bit 1 Msamples/s Analog to Digital Converter

• 8 single ended channels/4 differential channels

• On-chip temperature sensor

• Configurable push-pull, open-drain, pull-up/down, input filter, drive

strength

• 12-bit 500 ksamples/s Digital to Analog Converter

• 2× Analog Comparator

• Configurable peripheral I/O locations

• 16 asynchronous external interrupts

• Output state retention and wake-up from Shutoff Mode

• 12 Channel DMA Controller

• Capacitive sensing with up to 16 inputs

• 3× Operational Amplifier

• 6.1 MHz GBW, Rail-to-rail, Programmable Gain

• Supply Voltage Comparator

• 12 Channel Peripheral Reflex System (PRS) for autonomous in-

ter-peripheral signaling

• Hardware AES with 128/256-bit keys in 54/75 cycles

• Timers/Counters

• Low Energy Sensor Interface (LESENSE)

• Autonomous sensor monitoring in Deep Sleep Mode

• Wide range of sensors supported, including LC sen-

sors and capacitive buttons

• 4× 16-bit Timer/Counter

• 4×3 Compare/Capture/PWM channels

• Dead-Time Insertion on TIMER0

• Ultra efficient Power-on Reset and Brown-Out Detec-

tor

• Debug Interface

• 16-bit Low Energy Timer

• 1× 24-bit Real-Time Counter and 1× 32-bit Real-Time Counter

• 3× 16/8-bit Pulse Counter

• Watchdog Timer with dedicated RC oscillator @ 50 nA

• Backup Power Domain

• RTC and retention registers in a separate power domain, avail-

able in all energy modes

• 2-pin Serial Wire Debug interface

• 1-pin Serial Wire Viewer

• Embedded Trace Module v3.5 (ETM)

• Pre-Programmed USB/UART Bootloader

• Temperature range -40 to 85 ºC

• Single power supply 1.98 to 3.8 V

• CSP81 package

• Operation from backup battery when main power drains out

32-bit ARM Cortex-M0+, Cortex-M3 and Cortex-M4 microcontrollers for:

• Energy, gas, water and smart metering

• Health and fitness applications

• Smart accessories

• Alarm and security systems

• Industrial and home automation

...the world's most energy friendly microcontrollers

1 Ordering Information

Table 1.1 (p. 2) shows the available EFM32WG360 devices.

Table 1.1. Ordering Information

Ordering Code

Flash (kB) RAM (kB)

Max

Speed

(MHz)

Supply

Voltage

(V)

Temperature

(ºC)

Package

EFM32WG360F64G-A-CSP81

EFM32WG360F128G-A-CSP81

EFM32WG360F256G-A-CSP81

64

32

48

1.98 - 3.8

-40 - 85

CSP81

128

256

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2 System Summary

2.1 System Introduction

The EFM32 MCUs are the world’s most energy friendly microcontrollers. With a unique combination of

the powerful 32-bit ARM Cortex-M4, with DSP instruction support and floating-point unit, innovative low

energy techniques, short wake-up time from energy saving modes, and a wide selection of peripherals,

the EFM32WG microcontroller is well suited for any battery operated application as well as other systems

requiring high performance and low-energy consumption. This section gives a short introduction to each

of the modules in general terms and also shows a summary of the configuration for the EFM32WG360

devices. For a complete feature set and in-depth information on the modules, the reader is referred to

the EFM32WG Reference Manual.

A block diagram of the EFM32WG360 is shown in Figure 2.1 (p. 3) .

Figure 2.1. Block Diagram

WG360F64/ 128/ 256

Core and Memory

Clock Management

Energy Management

Aux High Freq.

RC

Oscillator

High Freq.

RC

Oscillator

Voltage

Comparator

Voltage

Regulator

Memory

Protection

Unit

ARM Cortex™M4 processor

with DSP extensions and FPU

Low Freq.

RC

Oscillator

High Freq.

Crystal

Oscillator

Brown- out

Detector

Power- on

Reset

Flash

Debug

Interface

w/ ETM

DMA

Controller

RAM

Back- up

Power

Domain

Program

Memory

Low Freq.

Crystal

Oscillator

Ultra Low Freq.

RC

Oscillator

32- bit bus

Peripheral Reflex System

Serial Interfaces

I/ O Ports

Timers and Triggers

Analog Interfaces

Security

Timer/

Counter

LESENSE

Hardware

AES

USART

UART

ADC

Low Energy

Timer

Real Time

Counter

Low

Energy

UART™

General

Purpose

I/ O

External

Interrupts

Operational

Amplifier

I²C

DAC

Pulse

Counter

Watchdog

Timer

Reset

Wakeup

Analog

Comparator

Back- up

RTC

USB

2.1.1 ARM Cortex-M4 Core

The ARM Cortex-M4 includes a 32-bit RISC processor, with DSP instruction support and floating-point

unit, which can achieve as much as 1.25 Dhrystone MIPS/MHz. A Memory Protection Unit with support

for up to 8 memory segments is included, as well as a Wake-up Interrupt Controller handling interrupts

triggered while the CPU is asleep. The EFM32 implementation of the Cortex-M4 is described in detail

in ARM Cortex-M4 Devices Generic User Guide.

2.1.2 Debug Interface (DBG)

This device includes hardware debug support through a 2-pin serial-wire debug interface and an Embed-

ded Trace Module (ETM) for data/instruction tracing. In addition there is also a 1-wire Serial Wire Viewer

pin which can be used to output profiling information, data trace and software-generated messages.

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2.1.3 Memory System Controller (MSC)

The Memory System Controller (MSC) is the program memory unit of the EFM32WG microcontroller.

The flash memory is readable and writable from both the Cortex-M4 and DMA. The flash memory is

divided into two blocks; the main block and the information block. Program code is normally written to

the main block. Additionally, the information block is available for special user data and flash lock bits.

There is also a read-only page in the information block containing system and device calibration data.

Read and write operations are supported in the energy modes EM0 and EM1.

2.1.4 Direct Memory Access Controller (DMA)

The Direct Memory Access (DMA) controller performs memory operations independently of the CPU.

This has the benefit of reducing the energy consumption and the workload of the CPU, and enables

the system to stay in low energy modes when moving for instance data from the USART to RAM or

from the External Bus Interface to a PWM-generating timer. The DMA controller uses the PL230 µDMA

controller licensed from ARM.

2.1.5 Reset Management Unit (RMU)

The RMU is responsible for handling the reset functionality of the EFM32WG.

2.1.6 Energy Management Unit (EMU)

The Energy Management Unit (EMU) manage all the low energy modes (EM) in EFM32WG microcon-

trollers. Each energy mode manages if the CPU and the various peripherals are available. The EMU

can also be used to turn off the power to unused SRAM blocks.

2.1.7 Clock Management Unit (CMU)

The Clock Management Unit (CMU) is responsible for controlling the oscillators and clocks on-board the

EFM32WG. The CMU provides the capability to turn on and off the clock on an individual basis to all

peripheral modules in addition to enable/disable and configure the available oscillators. The high degree

of flexibility enables software to minimize energy consumption in any specific application by not wasting

power on peripherals and oscillators that are inactive.

2.1.8 Watchdog (WDOG)

The purpose of the watchdog timer is to generate a reset in case of a system failure, to increase appli-

cation reliability. The failure may e.g. be caused by an external event, such as an ESD pulse, or by a

software failure.

2.1.9 Peripheral Reflex System (PRS)

The Peripheral Reflex System (PRS) system is a network which lets the different peripheral module

communicate directly with each other without involving the CPU. Peripheral modules which send out

Reflex signals are called producers. The PRS routes these reflex signals to consumer peripherals which

apply actions depending on the data received. The format for the Reflex signals is not given, but edge

triggers and other functionality can be applied by the PRS.

2.1.10 Universal Serial Bus Controller (USB)

The USB is a full-speed USB 2.0 compliant OTG host/device controller. The USB can be used in Device,

On-the-go (OTG) Dual Role Device or Host-only configuration. In OTG mode the USB supports both

Host Negotiation Protocol (HNP) and Session Request Protocol (SRP). The device supports both full-

speed (12MBit/s) and low speed (1.5MBit/s) operation. The USB device includes an internal dedicated

Descriptor-Based Scatter/Garther DMA and supports up to 6 OUT endpoints and 6 IN endpoints, in

addition to endpoint 0. The on-chip PHY includes all OTG features, except for the voltage booster for

supplying 5V to VBUS when operating as host.

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2.1.11 Inter-Integrated Circuit Interface (I2C)

The I²C module provides an interface between the MCU and a serial I²C-bus. It is capable of acting as

both a master and a slave, and supports multi-master buses. Both standard-mode, fast-mode and fast-

mode plus speeds are supported, allowing transmission rates all the way from 10 kbit/s up to 1 Mbit/s.

Slave arbitration and timeouts are also provided to allow implementation of an SMBus compliant system.

The interface provided to software by the I²C module, allows both fine-grained control of the transmission

process and close to automatic transfers. Automatic recognition of slave addresses is provided in all

energy modes.

2.1.12 Universal Synchronous/Asynchronous Receiver/Transmitter (US-

ART)

The Universal Synchronous Asynchronous serial Receiver and Transmitter (USART) is a very flexible

serial I/O module. It supports full duplex asynchronous UART communication as well as RS-485, SPI,

MicroWire and 3-wire. It can also interface with ISO7816 SmartCards, IrDA and I2S devices.

2.1.13 Pre-Programmed USB/UART Bootloader

The bootloader presented in application note AN0042 is pre-programmed in the device at factory. The

bootloader enables users to program the EFM32 through a UART or a USB CDC class virtual UART

without the need for a debugger. The autobaud feature, interface and commands are described further

in the application note.

2.1.14 Universal Asynchronous Receiver/Transmitter (UART)

The Universal Asynchronous serial Receiver and Transmitter (UART) is a very flexible serial I/O module.

It supports full- and half-duplex asynchronous UART communication.

2.1.15 Low Energy Universal Asynchronous Receiver/Transmitter

(LEUART)

The unique LEUART^TM, the Low Energy UART, is a UART that allows two-way UART communication on

a strict power budget. Only a 32.768 kHz clock is needed to allow UART communication up to 9600 baud/

s. The LEUART includes all necessary hardware support to make asynchronous serial communication

possible with minimum of software intervention and energy consumption.

2.1.16 Timer/Counter (TIMER)

The 16-bit general purpose Timer has 3 compare/capture channels for input capture and compare/Pulse-

Width Modulation (PWM) output. TIMER0 also includes a Dead-Time Insertion module suitable for motor

control applications.

2.1.17 Real Time Counter (RTC)

The Real Time Counter (RTC) contains a 24-bit counter and is clocked either by a 32.768 kHz crystal

oscillator, or a 32.768 kHz RC oscillator. In addition to energy modes EM0 and EM1, the RTC is also

available in EM2. This makes it ideal for keeping track of time since the RTC is enabled in EM2 where

most of the device is powered down.

2.1.18 Backup Real Time Counter (BURTC)

The Backup Real Time Counter (BURTC) contains a 32-bit counter and is clocked either by a 32.768 kHz

crystal oscillator, a 32.768 kHz RC oscillator or a 1 kHz ULFRCO. The BURTC is available in all Energy

Modes and it can also run in backup mode, making it operational even if the main power should drain out.

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2.1.19 Low Energy Timer (LETIMER)

The unique LETIMER^TM, the Low Energy Timer, is a 16-bit timer that is available in energy mode EM2

in addition to EM1 and EM0. Because of this, it can be used for timing and output generation when most

of the device is powered down, allowing simple tasks to be performed while the power consumption of

the system is kept at an absolute minimum. The LETIMER can be used to output a variety of waveforms

with minimal software intervention. It is also connected to the Real Time Counter (RTC), and can be

configured to start counting on compare matches from the RTC.

2.1.20 Pulse Counter (PCNT)

The Pulse Counter (PCNT) can be used for counting pulses on a single input or to decode quadrature

encoded inputs. It runs off either the internal LFACLK or the PCNTn_S0IN pin as external clock source.

The module may operate in energy mode EM0 - EM3.

2.1.21 Analog Comparator (ACMP)

The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indi-

cating which input voltage is higher. Inputs can either be one of the selectable internal references or from

external pins. Response time and thereby also the current consumption can be configured by altering

the current supply to the comparator.

2.1.22 Voltage Comparator (VCMP)

The Voltage Supply Comparator is used to monitor the supply voltage from software. An interrupt can

be generated when the supply falls below or rises above a programmable threshold. Response time and

thereby also the current consumption can be configured by altering the current supply to the comparator.

2.1.23 Analog to Digital Converter (ADC)

The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits

at up to one million samples per second. The integrated input mux can select inputs from 8 external

pins and 6 internal signals.

2.1.24 Digital to Analog Converter (DAC)

The Digital to Analog Converter (DAC) can convert a digital value to an analog output voltage. The DAC

is fully differential rail-to-rail, with 12-bit resolution. It has two single ended output buffers which can be

combined into one differential output. The DAC may be used for a number of different applications such

as sensor interfaces or sound output.

2.1.25 Operational Amplifier (OPAMP)

The EFM32WG360 features 3 Operational Amplifiers. The Operational Amplifier is a versatile general

purpose amplifier with rail-to-rail differential input and rail-to-rail single ended output. The input can be set

to pin, DAC or OPAMP, whereas the output can be pin, OPAMP or ADC. The current is programmable

and the OPAMP has various internal configurations such as unity gain, programmable gain using internal

resistors etc.

2.1.26 Low Energy Sensor Interface (LESENSE)

The Low Energy Sensor Interface (LESENSE^TM), is a highly configurable sensor interface with support

for up to 16 individually configurable sensors. By controlling the analog comparators and DAC, LESENSE

is capable of supporting a wide range of sensors and measurement schemes, and can for instance mea-

sure LC sensors, resistive sensors and capacitive sensors. LESENSE also includes a programmable

FSM which enables simple processing of measurement results without CPU intervention. LESENSE is

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available in energy mode EM2, in addition to EM0 and EM1, making it ideal for sensor monitoring in

applications with a strict energy budget.

2.1.27 Backup Power Domain

The backup power domain is a separate power domain containing a Backup Real Time Counter, BURTC,

and a set of retention registers, available in all energy modes. This power domain can be configured to

automatically change power source to a backup battery when the main power drains out. The backup

power domain enables the EFM32WG360 to keep track of time and retain data, even if the main power

source should drain out.

2.1.28 Advanced Encryption Standard Accelerator (AES)

The AES accelerator performs AES encryption and decryption with 128-bit or 256-bit keys. Encrypting or

decrypting one 128-bit data block takes 52 HFCORECLK cycles with 128-bit keys and 75 HFCORECLK

cycles with 256-bit keys. The AES module is an AHB slave which enables efficient access to the data

and key registers. All write accesses to the AES module must be 32-bit operations, i.e. 8- or 16-bit

operations are not supported.

2.1.29 General Purpose Input/Output (GPIO)

In the EFM32WG360, there are 65 General Purpose Input/Output (GPIO) pins, which are divided into

ports with up to 16 pins each. These pins can individually be configured as either an output or input. More

advanced configurations like open-drain, filtering and drive strength can also be configured individually

for the pins. The GPIO pins can also be overridden by peripheral pin connections, like Timer PWM

outputs or USART communication, which can be routed to several locations on the device. The GPIO

supports up to 16 asynchronous external pin interrupts, which enables interrupts from any pin on the

device. Also, the input value of a pin can be routed through the Peripheral Reflex System to other

peripherals.

2.2 Configuration Summary

The features of the EFM32WG360 is a subset of the feature set described in the EFM32WG Reference

Manual. Table 2.1 (p. 7) describes device specific implementation of the features.

Table 2.1. Configuration Summary

Module

Cortex-M4

DBG

Configuration

Pin Connections

Full configuration

NA

DBG_SWCLK, DBG_SWDIO,

DBG_SWO

MSC

DMA

RMU

EMU

CMU

WDOG

PRS

Full configuration

NA

CMU_OUT0, CMU_OUT1

NA

USB

USB_VBUS, USB_VBUSEN,

USB_VREGI, USB_VREGO, USB_DM,

USB_DMPU, USB_DP, USB_ID

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Module

I2C0

Configuration

Pin Connections

Full configuration

I2C0_SDA, I2C0_SCL

I2C1_SDA, I2C1_SCL

US0_TX, US0_RX. US0_CLK, US0_CS

US1_TX, US1_RX, US1_CLK, US1_CS

US2_TX, US2_RX, US2_CLK, US2_CS

U0_TX, U0_RX

I2C1

Full configuration

USART0

USART1

USART2

UART0

UART1

LEUART0

LEUART1

TIMER0

TIMER1

TIMER2

TIMER3

RTC

Full configuration with IrDA

Full configuration with I2S

Full configuration

U1_TX, U1_RX

Full configuration

LEU0_TX, LEU0_RX

LEU1_TX, LEU1_RX

TIM0_CC[2:0], TIM0_CDTI[2:0]

TIM1_CC[2:0]

Full configuration

Full configuration with DTI

Full configuration

TIM2_CC[2:0]

Full configuration

TIM3_CC[2:0]

Full configuration

NA

BURTC

LETIMER0

PCNT0

PCNT1

PCNT2

ACMP0

ACMP1

VCMP

Full configuration

NA

Full configuration

LET0_O[1:0]

Full configuration, 16-bit count register PCNT0_S[1:0]

Full configuration, 8-bit count register

Full configuration

PCNT1_S[1:0]

PCNT2_S[1:0]

ACMP0_CH[7:0], ACMP0_O

ACMP1_CH[7:0], ACMP1_O

NA

Full configuration

ADC0

Full configuration

ADC0_CH[7:0]

DAC0

Full configuration

DAC0_OUT[1:0], DAC0_OUTxALT

OPAMP

Full configuration

Outputs: OPAMP_OUTx,

OPAMP_OUTxALT, Inputs:

OPAMP_Px, OPAMP_Nx

AES

Full configuration

65 pins

NA

GPIO

Available pins are shown in

Table 4.3 (p. 62)

2.3 Memory Map

The EFM32WG360 memory map is shown in Figure 2.2 (p. 9), with RAM and Flash sizes for the

largest memory configuration.

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Figure 2.2. EFM32WG360 Memory Map with largest RAM and Flash sizes

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3 Electrical Characteristics

3.1 Test Conditions

3.1.1 Typical Values

The typical data are based on T_AMB=25°C and V_DD=3.0 V, as defined in Table 3.2 (p. 10), by simu-

lation and/or technology characterisation unless otherwise specified.

3.1.2 Minimum and Maximum Values

The minimum and maximum values represent the worst conditions of ambient temperature, supply volt-

age and frequencies, as defined in Table 3.2 (p. 10), by simulation and/or technology characterisa-

tion unless otherwise specified.

3.2 Absolute Maximum Ratings

The absolute maximum ratings are stress ratings, and functional operation under such conditions are

not guaranteed. Stress beyond the limits specified in Table 3.1 (p. 10) may affect the device reliability

or cause permanent damage to the device. Functional operating conditions are given in Table 3.2 (p.

10) .

Table 3.1. Absolute Maximum Ratings

Symbol

Parameter

Condition

Min

Typ

Max

Unit

150¹°C

T_STG

Storage tempera-

ture range

-40

T_S

Maximum soldering Latest IPC/JEDEC J-STD-020

260 °C

temperature

Standard

V_DDMAX

External main sup-

ply voltage

0

3.8

V

V_IOPIN

Voltage on any I/O

-0.3

V_DD+0.3

¹Based on programmed devices tested for 10000 hours at 150ºC. Storage temperature affects retention of preprogrammed cal-

ibration values stored in flash. Please refer to the Flash section in the Electrical Characteristics for information on flash data re-

tention for different temperatures.

3.3 General Operating Conditions

3.3.1 General Operating Conditions

Table 3.2. General Operating Conditions

Symbol

T_AMB

V_DDOP

f_APB

Parameter

Min

Typ

Max

Unit

85 °C

3.8

Ambient temperature range

Operating supply voltage

Internal APB clock frequency

Internal AHB clock frequency

-40

1.98

V

48 MHz

f_AHB

3.3.2 Environmental

WLCSP devices can be handled and soldered using industry standard surface mount assembly tech-

niques. However, because WLCSP devices are essentially a piece of silicon and are not encapsulated

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in plastic, they are susceptible to mechanical damage and may be sensitive to light. When WLCSPs

must be used in an environment exposed to light, it may be necessary to cover the top and sides with

an opaque material.

3.4 Current Consumption

Table 3.3. Current Consumption

Symbol

Parameter

Condition

Min

Typ

Max

Unit

48 MHz HFXO, all peripheral

clocks disabled, V_DD= 3.0 V,

T_AMB=25°C

225

226

227

228

229

230

231

232

233

238

271

275

63

236 µA/

MHz

48 MHz HFXO, all peripheral

clocks disabled, V_DD= 3.0 V,

T_AMB=85°C

µA/

MHz

28 MHz HFRCO, all peripher-

al clocks disabled, V_DD= 3.0 V,

T_AMB=25°C

238 µA/

MHz

28 MHz HFRCO, all peripher-

al clocks disabled, V_DD= 3.0 V,

T_AMB=85°C

µA/

MHz

21 MHz HFRCO, all peripher-

al clocks disabled, V_DD= 3.0 V,

T_AMB=25°C

240 µA/

MHz

21 MHz HFRCO, all peripher-

al clocks disabled, V_DD= 3.0 V,

T_AMB=85°C

µA/

MHz

EM0 current. No

prescaling. Running

prime number cal-

culation code from

Flash. (Production

test condition = 14

MHz)

14 MHz HFRCO, all peripher-

al clocks disabled, V_DD= 3.0 V,

T_AMB=25°C

243 µA/

MHz

I_EM0

14 MHz HFRCO, all peripher-

al clocks disabled, V_DD= 3.0 V,

T_AMB=85°C

µA/

MHz

11 MHz HFRCO, all peripher-

al clocks disabled, V_DD= 3.0 V,

T_AMB=25°C

245 µA/

MHz

11 MHz HFRCO, all peripher-

al clocks disabled, V_DD= 3.0 V,

T_AMB=85°C

µA/

MHz

6.6 MHz HFRCO, all peripher-

al clocks disabled, V_DD= 3.0 V,

T_AMB=25°C

250 µA/

MHz

6.6 MHz HFRCO, all peripher-

al clocks disabled, V_DD= 3.0 V,

T_AMB=85°C

µA/

MHz

1.2 MHz HFRCO, all peripher-

al clocks disabled, V_DD= 3.0 V,

T_AMB=25°C

286 µA/

MHz

1.2 MHz HFRCO, all peripher-

al clocks disabled, V_DD= 3.0 V,

T_AMB=85°C

µA/

MHz

48 MHz HFXO, all peripheral

clocks disabled, V_DD= 3.0 V,

T_AMB=25°C

75 µA/

MHz

EM1 current (Pro-

duction test condi-

tion = 14 MHz)

I_EM1

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Symbol

Parameter

Condition

Min

Typ

Max

Unit

48 MHz HFXO, all peripheral

clocks disabled, V_DD= 3.0 V,

T_AMB=85°C

65

64

76 µA/

MHz

28 MHz HFRCO, all peripher-

al clocks disabled, V_DD= 3.0 V,

T_AMB=25°C

75 µA/

MHz

28 MHz HFRCO, all peripher-

al clocks disabled, V_DD= 3.0 V,

T_AMB=85°C

65

77 µA/

MHz

21 MHz HFRCO, all peripher-

al clocks disabled, V_DD= 3.0 V,

T_AMB=25°C

65

76 µA/

MHz

21 MHz HFRCO, all peripher-

al clocks disabled, V_DD= 3.0 V,

T_AMB=85°C

66

78 µA/

MHz

14 MHz HFRCO, all peripher-

al clocks disabled, V_DD= 3.0 V,

T_AMB=25°C

67

79 µA/

MHz

14 MHz HFRCO, all peripher-

al clocks disabled, V_DD= 3.0 V,

T_AMB=85°C

68

82 µA/

MHz

11 MHz HFRCO, all peripher-

al clocks disabled, V_DD= 3.0 V,

T_AMB=25°C

68

81 µA/

MHz

11 MHz HFRCO, all peripher-

al clocks disabled, V_DD= 3.0 V,

T_AMB=85°C

70

83 µA/

MHz

6.6 MHz HFRCO, all peripher-

al clocks disabled, V_DD= 3.0 V,

T_AMB=25°C

74

87 µA/

MHz

6.6 MHz HFRCO, all peripher-

al clocks disabled, V_DD= 3.0 V,

T_AMB=85°C

76

89 µA/

MHz

1.2 MHz HFRCO. all peripher-

al clocks disabled, V_DD= 3.0 V,

T_AMB=25°C

106

112

0.95¹

120 µA/

MHz

1.2 MHz HFRCO. all peripher-

al clocks disabled, V_DD= 3.0 V,

T_AMB=85°C

129 µA/

MHz

EM2 current with RTC

prescaled to 1 Hz, 32.768

kHz LFRCO, V_DD= 3.0 V,

T_AMB=25°C

1.7¹µA

I_EM2

EM2 current

EM2 current with RTC

prescaled to 1 Hz, 32.768

kHz LFRCO, V_DD= 3.0 V,

T_AMB=85°C

3.0¹

4.0¹µA

V_DD= 3.0 V, T_AMB=25°C

V_DD= 3.0 V, T_AMB=85°C

V_DD= 3.0 V, T_AMB=25°C

V_DD= 3.0 V, T_AMB=85°C

0.65

2.65

0.02

0.44

1.3 µA

4.0 µA

I_EM3

EM3 current

EM4 current

0.055 µA

0.9 µA

I_EM4

¹Using backup RTC.

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3.4.1 EM1 Current Consumption

Figure 3.1. EM1 Current consumption with all peripheral clocks disabled and HFXO running at

48 MHz

3.15

3.10

3.05

3.00

2.95

2.90

3.15

3.10

3.05

3.00

2.95

2.90

2.0V

2.2V

2.4V

2.6V

2.8V

3.0V

3.2V

3.4V

3.6V

3.8V

- 40°C

- 15°C

5°C

25°C

45°C

65°C

85°C

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

–40

–15

5

25

45

65

85

Vdd [V]

Temperature [°C]

Figure 3.2. EM1 Current consumption with all peripheral clocks disabled and HFRCO running

at 28 MHz

1.85

1.80

1.75

1.70

1.65

1.60

1.85

1.80

1.75

1.70

1.65

1.60

2.0V

2.2V

2.4V

2.6V

2.8V

3.0V

3.2V

3.4V

3.6V

3.8V

- 40°C

- 15°C

5°C

25°C

45°C

65°C

85°C

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

–40

–15

5

25

45

65

85

Vdd [V]

Temperature [°C]

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Figure 3.3. EM1 Current consumption with all peripheral clocks disabled and HFRCO running

at 21 MHz

1.42

1.40

1.38

1.36

1.34

1.32

1.30

1.28

1.26

1.24

1.42

1.40

1.38

1.36

1.34

1.32

1.30

1.28

1.26

1.24

2.0V

2.2V

2.4V

2.6V

2.8V

3.0V

3.2V

3.4V

3.6V

3.8V

- 40°C

- 15°C

5°C

25°C

45°C

65°C

85°C

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

–40

–15

5

25

45

65

85

Vdd [V]

Temperature [°C]

Figure 3.4. EM1 Current consumption with all peripheral clocks disabled and HFRCO running

at 14 MHz

0.98

0.96

0.94

0.92

0.90

0.88

0.86

0.98

0.96

0.94

0.92

0.90

0.88

0.86

2.0V

2.2V

2.4V

2.6V

2.8V

3.0V

3.2V

3.4V

3.6V

3.8V

- 40°C

- 15°C

5°C

25°C

45°C

65°C

85°C

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

–40

–15

5

25

45

65

85

Vdd [V]

Temperature [°C]

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Figure 3.5. EM1 Current consumption with all peripheral clocks disabled and HFRCO running

at 11 MHz

0.78

0.76

0.74

0.72

0.70

0.78

0.76

0.74

0.72

0.70

2.0V

2.2V

2.4V

2.6V

2.8V

3.0V

3.2V

3.4V

3.6V

3.8V

- 40°C

- 15°C

5°C

25°C

45°C

65°C

85°C

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

–40

–15

5

25

45

65

85

Vdd [V]

Temperature [°C]

Figure 3.6. EM1 Current consumption with all peripheral clocks disabled and HFRCO running

at 6.6 MHz

0.52

0.51

0.50

0.49

0.48

0.47

0.46

0.45

0.52

0.51

0.50

0.49

0.48

0.47

0.46

0.45

2.0V

2.2V

2.4V

2.6V

2.8V

3.0V

3.2V

3.4V

3.6V

3.8V

- 40°C

- 15°C

5°C

25°C

45°C

65°C

85°C

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

–40

–15

5

25

45

65

85

Vdd [V]

Temperature [°C]

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Figure 3.7. EM1 Current consumption with all peripheral clocks disabled and HFRCO running

at 1.2 MHz

0.138

0.136

0.134

0.132

0.130

0.128

0.126

0.124

0.122

0.160

0.155

0.150

0.145

0.140

0.135

0.130

0.125

0.120

0.115

- 40°C

- 15°C

5°C

2.0V

2.2V

2.4V

2.6V

2.8V

3.0V

3.2V

3.4V

3.6V

3.8V

25°C

45°C

65°C

85°C

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

–40

–15

5

25

45

65

85

Vdd [V]

Temperature [°C]

3.4.2 EM2 Current Consumption

Figure 3.8. EM2 current consumption. RTC¹prescaled to 1kHz, 32.768 kHz LFRCO.

3.5

3.0

2.5

2.0

1.5

1.0

0.5

3.5

3.0

2.5

2.0

1.5

1.0

0.5

- 40.0°C

- 15.0°C

5.0°C

Vdd= 2.0V

Vdd= 2.2V

Vdd= 2.4V

Vdd= 2.6V

Vdd= 2.8V

Vdd= 3.0V

Vdd= 3.2V

Vdd= 3.4V

Vdd= 3.6V

Vdd= 3.8V

25.0°C

45.0°C

65.0°C

85.0°C

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

–40

–20

0

20

40

60

80

Vdd [V]

Temperature [°C]

¹Using backup RTC.

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3.4.3 EM3 Current Consumption

Figure 3.9. EM3 current consumption.

3.0

- 40.0°C

Vdd= 2.0V

- 15.0°C

5.0°C

Vdd= 2.2V

Vdd= 2.4V

2.5

2.0

1.5

1.0

0.5

0.0

2.5

25.0°C

45.0°C

65.0°C

85.0°C

Vdd= 2.6V

Vdd= 2.8V

Vdd= 3.0V

2.0

Vdd= 3.2V

Vdd= 3.4V

Vdd= 3.6V

1.5

1.0

0.5

0.0

Vdd= 3.8V

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

–40

–20

0

20

40

60

80

Vdd [V]

Temperature [°C]

3.4.4 EM4 Current Consumption

Figure 3.10. EM4 current consumption.

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

- 40.0°C

Vdd= 2.0V

Vdd= 2.2V

Vdd= 2.4V

Vdd= 2.6V

Vdd= 2.8V

Vdd= 3.0V

Vdd= 3.2V

Vdd= 3.4V

Vdd= 3.6V

Vdd= 3.8V

- 15.0°C

0.6

0.5

0.4

0.3

0.2

0.1

0.0

5.0°C

25.0°C

45.0°C

65.0°C

85.0°C

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

–40

–20

0

20

40

60

80

Vdd [V]

Temperature [°C]

3.5 Transition between Energy Modes

The transition times are measured from the trigger to the first clock edge in the CPU.

Table 3.4. Energy Modes Transitions

Symbol

Parameter

Min

Typ

Max

Unit

t_EM10

Transition time from EM1 to EM0

0

HF-

CORE-

CLK

cycles

t_EM20

t_EM30

t_EM40

Transition time from EM2 to EM0

Transition time from EM3 to EM0

Transition time from EM4 to EM0

2

µs

163

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3.6 Power Management

The EFM32WG requires the AVDD_x, VDD_DREG and IOVDD_x pins to be connected together (with

optional filter) at the PCB level. For practical schematic recommendations, please see the application

note, "AN0002 EFM32 Hardware Design Considerations".

Table 3.5. Power Management

Symbol

Parameter

Condition

Min

Typ

Max

Unit

V_BODextthr-

BOD threshold on

falling external sup-

ply voltage

1.74

1.96

1.98

V

V_BODextthr+

BOD threshold on

rising external sup-

ply voltage

1.85

V

V_PORthr+

Power-on Reset

(POR) threshold on

rising external sup-

ply voltage

t_RESET

Delay from reset

is released until

program execution

starts

Applies to Power-on Reset,

Brown-out Reset and pin reset.

163

µs

C_DECOUPLE

C_{USB_VREGO}

C_{USB_VREGI}

Voltage regulator

decoupling capaci-

tor.

X5R capacitor recommended.

Apply between DECOUPLE pin

and GROUND

1

µF

USB voltage regu-

lator out decoupling Apply between USB_VREGO

capacitor. pin and GROUND

X5R capacitor recommended.

USB voltage regula- X5R capacitor recommended.

tor in decoupling ca- Apply between USB_VREGI

4.7

pacitor.

pin and GROUND

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3.7 Flash

Table 3.6. Flash

Symbol

Parameter

Condition

Min

Typ

Max

Unit

EC_FLASH

Flash erase cycles

before failure

20000

cycles

T_AMB<150°C

10000

10

h

RET_FLASH

Flash data retention T_AMB<85°C

T_AMB<70°C

years

µs

20

t_{W_PROG}

Word (32-bit) pro-

gramming time

20

t_PERASE

t_DERASE

I_ERASE

I_WRITE

Page erase time

Device erase time

Erase current

20

40

20.4

40.8

20.8 ms

41.6 ms

7¹mA

Write current

V_FLASH

Supply voltage dur-

ing flash erase and

write

1.98

3.8

V

¹Measured at 25°C

3.8 General Purpose Input Output

Table 3.7. GPIO

Symbol

V_IOIL

Parameter

Condition

Min

Typ

Max

0.30V_DD

Unit

V

Input low voltage

Input high voltage

V_IOIH

0.70V_DD

V

Sourcing 0.1 mA, V_DD=1.98 V,

GPIO_Px_CTRL DRIVEMODE

= LOWEST

0.80V_DD

0.90V_DD

0.85V_DD

0.90V_DD

V

Sourcing 0.1 mA, V_DD=3.0 V,

GPIO_Px_CTRL DRIVEMODE

= LOWEST

V

Sourcing 1 mA, V_DD=1.98 V,

GPIO_Px_CTRL DRIVEMODE

= LOW

Output high volt-

age (Production test

condition = 3.0V,

DRIVEMODE =

STANDARD)

Sourcing 1 mA, V_DD=3.0 V,

GPIO_Px_CTRL DRIVEMODE

= LOW

V_IOOH

Sourcing 6 mA, V_DD=1.98 V,

GPIO_Px_CTRL DRIVEMODE

= STANDARD

0.75V_DD

0.85V_DD

0.60V_DD

Sourcing 6 mA, V_DD=3.0 V,

GPIO_Px_CTRL DRIVEMODE

= STANDARD

Sourcing 20 mA, V_DD=1.98 V,

GPIO_Px_CTRL DRIVEMODE

= HIGH

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Symbol

Parameter

Condition

Min

0.80V_DD

Typ

Max

Unit

Sourcing 20 mA, V_DD=3.0 V,

GPIO_Px_CTRL DRIVEMODE

= HIGH

V

Sinking 0.1 mA, V_DD=1.98 V,

GPIO_Px_CTRL DRIVEMODE

= LOWEST

0.20V_DD

0.10V_DD

0.05V_DD

V

Sinking 0.1 mA, V_DD=3.0 V,

GPIO_Px_CTRL DRIVEMODE

= LOWEST

Sinking 1 mA, V_DD=1.98 V,

GPIO_Px_CTRL DRIVEMODE

= LOW

Sinking 1 mA, V_DD=3.0 V,

GPIO_Px_CTRL DRIVEMODE

= LOW

Output low voltage

(Production test

condition = 3.0V,

DRIVEMODE =

STANDARD)

V_IOOL

Sinking 6 mA, V_DD=1.98 V,

GPIO_Px_CTRL DRIVEMODE

= STANDARD

0.30V_DD

Sinking 6 mA, V_DD=3.0 V,

GPIO_Px_CTRL DRIVEMODE

= STANDARD

0.20V_DD

0.35V_DD

0.25V_DD

Sinking 20 mA, V_DD=1.98 V,

GPIO_Px_CTRL DRIVEMODE

= HIGH

Sinking 20 mA, V_DD=3.0 V,

GPIO_Px_CTRL DRIVEMODE

= HIGH

I_IOLEAK

Input leakage cur-

rent

High Impedance IO connected

to GROUND or Vdd

±0.1

40

±100 nA

R_PU

I/O pin pull-up resis-

tor

kOhm

Ohm

R_PD

I/O pin pull-down re-

sistor

40

R_IOESD

Internal ESD series

resistor

200

t_IOGLITCH

Pulse width of puls-

es to be removed

by the glitch sup-

pression filter

10

50 ns

GPIO_Px_CTRL DRIVEMODE

= LOWEST and load capaci-

tance C_L=12.5-25pF.

20+0.1C_L

0.10V_DD

250 ns

V

t_IOOF

Output fall time

GPIO_Px_CTRL DRIVEMODE

= LOW and load capacitance

C_L=350-600pF

V_IOHYST

I/O pin hysteresis

V_DD= 1.98 - 3.8 V

(V_IOTHR+- V_IOTHR-

)

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Figure 3.11. Typical Low-Level Output Current, 2V Supply Voltage

0.20

0.15

0.10

0.05

0.00

5

4

3

2

1

- 40°C

25°C

85°C

- 40°C

25°C

85°C

0

0.0

0.5

1.0

1.5

2.0

0.0

0.5

1.0

1.5

2.0

Low- Level Output Voltage [V]

GPIO_Px_CTRL DRIVEMODE = LOWEST

GPIO_Px_CTRL DRIVEMODE = LOW

20

45

40

35

30

25

20

15

10

5

15

10

5

- 40°C

25°C

- 40°C

25°C

85°C

0

0.0

0

0.5

1.0

1.5

2.0

0.0

0.5

1.0

1.5

2.0

Low- Level Output Voltage [V]

GPIO_Px_CTRL DRIVEMODE = STANDARD

GPIO_Px_CTRL DRIVEMODE = HIGH

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Figure 3.12. Typical High-Level Output Current, 2V Supply Voltage

0.00

–0.05

–0.10

–0.15

–0.20

0.0

–0.5

–1.0

–1.5

–2.0

–2.5

- 40°C

25°C

85°C

- 40°C

25°C

85°C

0.0

0.5

1.0

1.5

2.0

0.0

0.5

1.0

1.5

2.0

High- Level Output Voltage [V]

GPIO_Px_CTRL DRIVEMODE = LOWEST

GPIO_Px_CTRL DRIVEMODE = LOW

0

- 40°C

25°C

85°C

25°C

85°C

–10

–20

–30

–40

–50

–5

–10

–15

–20

0.0

0.5

1.0

1.5

2.0

0.0

0.5

1.0

1.5

2.0

High- Level Output Voltage [V]

GPIO_Px_CTRL DRIVEMODE = STANDARD

GPIO_Px_CTRL DRIVEMODE = HIGH

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Figure 3.13. Typical Low-Level Output Current, 3V Supply Voltage

0.5

0.4

0.3

0.2

0.1

0.0

10

8

6

4

2

- 40°C

25°C

85°C

- 40°C

25°C

85°C

0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

Low- Level Output Voltage [V]

GPIO_Px_CTRL DRIVEMODE = LOWEST

GPIO_Px_CTRL DRIVEMODE = LOW

40

35

30

25

20

15

10

50

40

30

20

10

0

5

- 40°C

25°C

85°C

25°C

85°C

0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

Low- Level Output Voltage [V]

GPIO_Px_CTRL DRIVEMODE = STANDARD

GPIO_Px_CTRL DRIVEMODE = HIGH

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Figure 3.14. Typical High-Level Output Current, 3V Supply Voltage

0.0

–0.1

–0.2

–0.3

–0.4

–0.5

0

- 40°C

25°C

85°C

- 40°C

25°C

85°C

–1

–2

–3

–4

–5

–6

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

High- Level Output Voltage [V]

GPIO_Px_CTRL DRIVEMODE = LOWEST

GPIO_Px_CTRL DRIVEMODE = LOW

0

- 40°C

25°C

85°C

25°C

85°C

–10

–20

–30

–40

–50

–10

–20

–30

–40

–50

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

High- Level Output Voltage [V]

GPIO_Px_CTRL DRIVEMODE = STANDARD

GPIO_Px_CTRL DRIVEMODE = HIGH

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Figure 3.15. Typical Low-Level Output Current, 3.8V Supply Voltage

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

14

12

10

8

6

4

2

- 40°C

25°C

85°C

- 40°C

25°C

85°C

0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

Low- Level Output Voltage [V]

GPIO_Px_CTRL DRIVEMODE = LOWEST

GPIO_Px_CTRL DRIVEMODE = LOW

50

40

30

20

10

50

40

30

20

10

0

- 40°C

25°C

- 40°C

25°C

85°C

0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

Low- Level Output Voltage [V]

GPIO_Px_CTRL DRIVEMODE = STANDARD

GPIO_Px_CTRL DRIVEMODE = HIGH

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Figure 3.16. Typical High-Level Output Current, 3.8V Supply Voltage

0.0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

–0.7

–0.8

0

- 40°C

25°C

85°C

- 40°C

25°C

85°C

–1

–2

–3

–4

–5

–6

–7

–8

–9

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

High- Level Output Voltage [V]

GPIO_Px_CTRL DRIVEMODE = LOWEST

GPIO_Px_CTRL DRIVEMODE = LOW

0

- 40°C

25°C

85°C

25°C

85°C

–10

–20

–30

–40

–50

–10

–20

–30

–40

–50

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

High- Level Output Voltage [V]

GPIO_Px_CTRL DRIVEMODE = STANDARD

GPIO_Px_CTRL DRIVEMODE = HIGH

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3.9 Oscillators

3.9.1 LFXO

Table 3.8. LFXO

Symbol

Parameter

Condition

Min

Typ

Max

Unit

f_LFXO

Supported nominal

crystal frequency

32.768

30

kHz

ESR_LFXO

Supported crystal

equivalent series re-

sistance (ESR)

120 kOhm

C_LFXOL

Supported crystal

external load range

X¹

25 pF

nA

I_LFXO

Current consump-

tion for core and

buffer after startup.

ESR=30 kOhm, C_L=10 pF,

LFXOBOOST in CMU_CTRL is

1

190

400

t_LFXO

Start- up time.

ESR=30 kOhm, C_L=10 pF,

40% - 60% duty cycle has

been reached, LFXOBOOST in

CMU_CTRL is 1

ms

¹See Minimum Load Capacitance (C_LFXOL) Requirement For Safe Crystal Startup in energyAware Designer in Simplicity Studio

For safe startup of a given crystal, the energyAware Designer in Simplicity Studio contains a tool to help

users configure both load capacitance and software settings for using the LFXO. For details regarding

the crystal configuration, the reader is referred to application note "AN0016 EFM32 Oscillator Design

Consideration".

3.9.2 HFXO

Table 3.9. HFXO

Symbol

Parameter

Condition

Min

Typ

Max

Unit

f_HFXO

Supported nominal

crystal Frequency

4

48 MHz

Crystal frequency 48 MHz

50 Ohm

60 Ohm

1500 Ohm

mS

Supported crystal

ESR_HFXO

equivalent series re- Crystal frequency 32 MHz

30

sistance (ESR)

Crystal frequency 4 MHz

400

g_mHFXO

The transconduc-

tance of the HFXO

input transistor at

crystal startup

HFXOBOOST in CMU_CTRL

equals 0b11

20

5

C_HFXOL

Supported crystal

external load range

25 pF

µA

4 MHz: ESR=400 Ohm,

C_L=20 pF, HFXOBOOST in

CMU_CTRL equals 0b11

85

165

400

Current consump-

tion for HFXO after

startup

I_HFXO

32 MHz: ESR=30 Ohm,

C_L=10 pF, HFXOBOOST in

CMU_CTRL equals 0b11

µA

µs

t_HFXO

Startup time

32 MHz: ESR=30 Ohm,

C_L=10 pF, HFXOBOOST in

CMU_CTRL equals 0b11

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3.9.3 LFRCO

Table 3.10. LFRCO

Symbol

Parameter

Condition

Min

Typ

Max

Unit

f_LFRCO

Oscillation frequen-

cy , V_DD= 3.0 V,

T_AMB=25°C

31.29

32.768

150

34.28 kHz

t_LFRCO

Startup time not in-

cluding software

calibration

µs

I_LFRCO

Current consump-

tion

300

1.5

nA

%

TUNESTEP_L-Frequency step

for LSB change in

FRCO

TUNING value

Figure 3.17. Calibrated LFRCO Frequency vs Temperature and Supply Voltage

42

40

38

36

34

32

30

42

40

38

36

34

32

30

- 40°C

25°C

85°C

2.0 V

3.0 V

3.8 V

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

–40

–15

5

25

45

65

85

Vdd [V]

Temperature [°C]

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3.9.4 HFRCO

Table 3.11. HFRCO

Symbol

Parameter

Condition

Min

Typ

Max

Unit

28 MHz frequency band

21 MHz frequency band

14 MHz frequency band

11 MHz frequency band

7 MHz frequency band

1 MHz frequency band

f_HFRCO= 14 MHz

28.0

21.0

14.0

11.0

6.60

1.20

0.6

MHz

Cycles

Oscillation frequen-

cy, V_DD= 3.0 V,

T_AMB=25°C

f_HFRCO

t_{HFRCO_settling}Settling time after

start-up

f_HFRCO= 28 MHz

f_HFRCO= 21 MHz

f_HFRCO= 14 MHz

f_HFRCO= 11 MHz

f_HFRCO= 6.6 MHz

f_HFRCO= 1.2 MHz

165

134

106

94

215 µA

175 µA

140 µA

125 µA

105 µA

40 µA

%

Current consump-

tion

I_HFRCO

77

25

TUNESTEP_H-Frequency step

0.3¹

for LSB change in

FRCO

TUNING value

¹The TUNING field in the CMU_HFRCOCTRL register may be used to adjust the HFRCO frequency. There is enough adjustment

range to ensure that the frequency bands above 7 MHz will always have some overlap across supply voltage and temperature. By

using a stable frequency reference such as the LFXO or HFXO, a firmware calibration routine can vary the TUNING bits and the

frequency band to maintain the HFRCO frequency at any arbitrary value between 7 MHz and 28 MHz across operating conditions.

Figure 3.18. Calibrated HFRCO 1 MHz Band Frequency vs Supply Voltage and Temperature

1.45

1.40

1.35

1.30

1.25

1.20

1.15

1.10

1.05

1.45

1.40

1.35

1.30

1.25

1.20

1.15

1.10

1.05

- 40°C

25°C

85°C

2.0 V

3.0 V

3.8 V

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

–40

–15

5

25

45

65

85

Vdd [V]

Temperature [°C]

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Figure 3.19. Calibrated HFRCO 7 MHz Band Frequency vs Supply Voltage and Temperature

6.70

6.65

6.60

6.55

6.50

6.45

6.40

6.35

6.30

6.70

6.65

6.60

6.55

6.50

6.45

6.40

6.35

6.30

- 40°C

25°C

85°C

2.0 V

3.0 V

3.8 V

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

–40

–15

5

25

45

65

85

Vdd [V]

Temperature [°C]

Figure 3.20. Calibrated HFRCO 11 MHz Band Frequency vs Supply Voltage and Temperature

11.2

11.1

11.0

10.9

10.8

10.7

10.6

11.2

11.1

11.0

10.9

10.8

10.7

10.6

- 40°C

25°C

85°C

2.0 V

3.0 V

3.8 V

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

–40

–15

5

25

45

65

85

Vdd [V]

Temperature [°C]

Figure 3.21. Calibrated HFRCO 14 MHz Band Frequency vs Supply Voltage and Temperature

14.2

14.1

14.0

13.9

13.8

13.7

13.6

13.5

13.4

14.2

14.1

14.0

13.9

13.8

13.7

13.6

13.5

13.4

- 40°C

25°C

85°C

2.0 V

3.0 V

3.8 V

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

–40

–15

5

25

45

65

85

Vdd [V]

Temperature [°C]

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Figure 3.22. Calibrated HFRCO 21 MHz Band Frequency vs Supply Voltage and Temperature

21.2

21.0

20.8

20.6

20.4

20.2

21.2

21.0

20.8

20.6

20.4

20.2

- 40°C

25°C

85°C

2.0 V

3.0 V

3.8 V

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

–40

–15

5

25

45

65

85

Vdd [V]

Temperature [°C]

Figure 3.23. Calibrated HFRCO 28 MHz Band Frequency vs Supply Voltage and Temperature

28.2

28.0

27.8

27.6

27.4

27.2

27.0

26.8

28.4

28.2

28.0

27.8

27.6

27.4

27.2

27.0

26.8

- 40°C

25°C

85°C

2.0 V

3.0 V

3.8 V

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

–40

–15

5

25

45

65

85

Vdd [V]

Temperature [°C]

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3.9.5 AUXHFRCO

Table 3.12. AUXHFRCO

Symbol

Parameter

Condition

Min

Typ

Max

Unit

28 MHz frequency band

21 MHz frequency band

14 MHz frequency band

11 MHz frequency band

7 MHz frequency band

1 MHz frequency band

f_AUXHFRCO= 14 MHz

28.0

21.0

14.0

11.0

6.60

1.20

0.6

MHz

Cycles

Oscillation frequen-

cy, V_DD= 3.0 V,

T_AMB=25°C

f_AUXHFRCO

t_{AUXHFRCO_settling}Settling time after

start-up

TUNESTEP_AUX-Frequency step

0.3¹

%

for LSB change in

HFRCO

TUNING value

¹The TUNING field in the CMU_AUXHFRCOCTRL register may be used to adjust the AUXHFRCO frequency. There is enough

adjustment range to ensure that the frequency bands above 7 MHz will always have some overlap across supply voltage and

temperature. By using a stable frequency reference such as the LFXO or HFXO, a firmware calibration routine can vary the

TUNING bits and the frequency band to maintain the AUXHFRCO frequency at any arbitrary value between 7 MHz and 28 MHz

across operating conditions.

3.9.6 ULFRCO

Table 3.13. ULFRCO

Symbol

Parameter

Condition

Min

Typ

Max

Unit

f_ULFRCO

Oscillation frequen- 25°C, 3V

cy

0.7

1.75 kHz

TC_ULFRCO

Temperature coeffi-

cient

0.05

%/°C

%/V

VC_ULFRCO

Supply voltage co-

efficient

-18.2

3.10 Analog Digital Converter (ADC)

Table 3.14. ADC

Symbol

Parameter

Condition

Single ended

Differential

Min

Typ

Max

Unit

0

-V_REF/2

1.25

V_REF

V_REF/2

V_DD

V

V_ADCIN

Input voltage range

V_ADCREFIN

Input range of exter-

nal reference volt-

age, single ended

and differential

V_{ADCREFIN_CH7}Input range of ex-

ternal negative ref-

erence voltage on

See V_ADCREFIN

0

V_DD- 1.1

V

channel 7

V_{ADCREFIN_CH6}Input range of ex-

ternal positive ref-

See V_ADCREFIN

0.625

V_DD

erence voltage on

channel 6

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Symbol

Parameter

Condition

Min

Typ

Max

Unit

V_ADCCMIN

Common mode in-

put range

0

V_DD

V

I_ADCIN

Input current

2pF sampling capacitors

<100

65

nA

dB

CMRR_ADC

Analog input com-

mon mode rejection

ratio

1 MSamples/s, 12 bit, external

reference

351

67

µA

10 kSamples/s 12 bit, internal

1.25 V reference, WARMUP-

MODE in ADCn_CTRL set to

0b00

Average active cur-

rent

10 kSamples/s 12 bit, internal

1.25 V reference, WARMUP-

MODE in ADCn_CTRL set to

0b01

63

64

µA

I_ADC

10 kSamples/s 12 bit, internal

1.25 V reference, WARMUP-

MODE in ADCn_CTRL set to

0b10

I_ADCREF

Current consump-

tion of internal volt-

age reference

Internal voltage reference

65

2

C_ADCIN

R_ADCIN

R_ADCFILT

Input capacitance

pF

Input ON resistance

1

MOhm

kOhm

Input RC filter resis-

tance

10

C_ADCFILT

Input RC filter/de-

coupling capaci-

tance

250

fF

f_ADCCLK

ADC Clock Fre-

quency

13 MHz

6 bit

7

11

13

1

ADC-

CLK

Cycles

8 bit

ADC-

CLK

Cycles

t_ADCCONV

Conversion time

Acquisition time

12 bit

ADC-

CLK

Cycles

t_ADCACQ

Programmable

256 ADC-

CLK

Cycles

t_ADCACQVDD3

Required acquisi-

tion time for VDD/3

reference

2

µs

Startup time of ref-

erence generator

and ADC core in

NORMAL mode

5

µs

t_ADCSTART

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Symbol

Parameter

Condition

Min

Typ

Max

Unit

Startup time of ref-

erence generator

and ADC core in

KEEPADCWARM

mode

1

µs

1 MSamples/s, 12 bit, single

ended, internal 1.25V refer-

ence

59

dB

1 MSamples/s, 12 bit, single

ended, internal 2.5V reference

63

65

60

65

54

67

69

62

dB

1 MSamples/s, 12 bit, single

ended, V_DDreference

1 MSamples/s, 12 bit, differen-

tial, internal 1.25V reference

1 MSamples/s, 12 bit, differen-

tial, internal 2.5V reference

1 MSamples/s, 12 bit, differen-

tial, 5V reference

1 MSamples/s, 12 bit, differen-

tial, V_DDreference

1 MSamples/s, 12 bit, differen-

tial, 2xV_DDreference

Signal to Noise Ra-

tio (SNR)

SNR_ADC

200 kSamples/s, 12 bit, sin-

gle ended, internal 1.25V refer-

ence

200 kSamples/s, 12 bit, single

ended, internal 2.5V reference

63

67

63

66

70

58

dB

200 kSamples/s, 12 bit, single

ended, V_DDreference

200 kSamples/s, 12 bit, differ-

ential, internal 1.25V reference

200 kSamples/s, 12 bit, differ-

ential, internal 2.5V reference

200 kSamples/s, 12 bit, differ-

ential, 5V reference

200 kSamples/s, 12 bit, differ-

ential, V_DDreference

63

200 kSamples/s, 12 bit, differ-

ential, 2xV_DDreference

1 MSamples/s, 12 bit, single

ended, internal 1.25V refer-

ence

1 MSamples/s, 12 bit, single

ended, internal 2.5V reference

62

64

60

dB

SIgnal-to-Noise

And Distortion-ratio

(SINAD)

SINAD_ADC

1 MSamples/s, 12 bit, single

ended, V_DDreference

1 MSamples/s, 12 bit, differen-

tial, internal 1.25V reference

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Symbol

Parameter

Condition

Min

Typ

Max

Unit

1 MSamples/s, 12 bit, differen-

tial, internal 2.5V reference

64

54

66

68

61

dB

1 MSamples/s, 12 bit, differen-

tial, 5V reference

dB

1 MSamples/s, 12 bit, differen-

tial, V_DDreference

1 MSamples/s, 12 bit, differen-

tial, 2xV_DDreference

200 kSamples/s, 12 bit, sin-

gle ended, internal 1.25V refer-

ence

200 kSamples/s, 12 bit, single

ended, internal 2.5V reference

65

66

63

66

69

64

dB

dBc

200 kSamples/s, 12 bit, single

ended, V_DDreference

200 kSamples/s, 12 bit, differ-

ential, internal 1.25V reference

200 kSamples/s, 12 bit, differ-

ential, internal 2.5V reference

200 kSamples/s, 12 bit, differ-

ential, 5V reference

200 kSamples/s, 12 bit, differ-

ential, V_DDreference

62

200 kSamples/s, 12 bit, differ-

ential, 2xV_DDreference

1 MSamples/s, 12 bit, single

ended, internal 1.25V refer-

ence

1 MSamples/s, 12 bit, single

ended, internal 2.5V reference

76

73

66

77

76

75

69

75

dBc

1 MSamples/s, 12 bit, single

ended, V_DDreference

1 MSamples/s, 12 bit, differen-

tial, internal 1.25V reference

1 MSamples/s, 12 bit, differen-

tial, internal 2.5V reference

Spurious-Free Dy-

namic Range (SF-

DR)

1 MSamples/s, 12 bit, differen-

tial, V_DDreference

SFDR_ADC

1 MSamples/s, 12 bit, differen-

tial, 2xV_DDreference

1 MSamples/s, 12 bit, differen-

tial, 5V reference

200 kSamples/s, 12 bit, sin-

gle ended, internal 1.25V refer-

ence

200 kSamples/s, 12 bit, single

ended, internal 2.5V reference

75

76

dBc

200 kSamples/s, 12 bit, single

ended, V_DDreference

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Symbol

Parameter

Condition

Min

Typ

Max

Unit

200 kSamples/s, 12 bit, differ-

ential, internal 1.25V reference

79

78

79

dBc

200 kSamples/s, 12 bit, differ-

ential, internal 2.5V reference

dBc

200 kSamples/s, 12 bit, differ-

ential, 5V reference

200 kSamples/s, 12 bit, differ-

ential, V_DDreference

68

200 kSamples/s, 12 bit, differ-

ential, 2xV_DDreference

After calibration, single ended

After calibration, differential

-3.5

0.3

3

mV

V_ADCOFFSET

Offset voltage

mV

-1.92

-6.3

mV/°C

Thermometer out-

put gradient

ADC

Codes/

°C

TGRAD_ADCTH

DNL_ADC

INL_ADC

Differential non-lin-

earity (DNL)

-1

±0.7

±1.2

4

LSB

Integral non-linear-

ity (INL), End point

method

±3 LSB

MC_ADC

No missing codes

11.999¹

12

0.01²

0.2²

bits

1.25V reference

2.5V reference

1.25V reference

2.5V reference

0.033³%/°C

0.03³%/°C

0.7³LSB/°C

0.62³LSB/°C

GAIN_ED

Gain error drift

OFFSET_ED

Offset error drift

0.2²

¹On the average every ADC will have one missing code, most likely to appear around 2048 +/- n*512 where n can be a value in

the set {-3, -2, -1, 1, 2, 3}. There will be no missing code around 2048, and in spite of the missing code the ADC will be monotonic

at all times so that a response to a slowly increasing input will always be a slowly increasing output. Around the one code that is

missing, the neighbour codes will look wider in the DNL plot. The spectra will show spurs on the level of -78dBc for a full scale

input for chips that have the missing code issue.

²Typical numbers given by abs(Mean) / (85 - 25).

³Max number given by (abs(Mean) + 3x stddev) / (85 - 25).

The integral non-linearity (INL) and differential non-linearity parameters are explained in Figure 3.24 (p.

37) and Figure 3.25 (p. 37) , respectively.

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Figure 3.24. Integral Non-Linearity (INL)

Digital ouput code

INL= |[(V_D- V_SS)/ V_LSBIDEAL] - D| where 0 < D < 2^N- 1

4095

4094

4093

4092

Actual ADC

tranfer function

before offset and

gain correction

Actual ADC

tranfer function

after offset and

gain correction

INL Error

(End Point INL)

Ideal transfer

curve

3

2

1

0

V_OFFSET

Analog Input

Figure 3.25. Differential Non-Linearity (DNL)

Digital

ouput

DNL= |[(V_{D+ 1}- V_D)/ V_LSBIDEAL] - 1| where 0 < D < 2^N- 2

code

4095

4094

4093

4092

Full Scale Range

Example: Adjacent

input value V_{D+ 1}

corrresponds to digital

output code D+ 1

Actual transfer

function with one

missing code.

Example: Input value

V_Dcorrresponds to

digital output code D

Code width = 2 LSB

DNL= 1 LSB

Ideal transfer

curve

0.5

LSB

Ideal spacing

between two

adjacent codes

V_LSBIDEAL= 1 LSB

5

4

3

2

1

0

Ideal 50%

Transition Point

Ideal Code Center

Analog Input

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3.10.1 Typical performance

Figure 3.26. ADC Frequency Spectrum, Vdd = 3V, Temp = 25°C

1.25V Reference

2XVDDVSS Reference

VDD Reference

2.5V Reference

5VDIFF Reference

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Figure 3.27. ADC Integral Linearity Error vs Code, Vdd = 3V, Temp = 25°C

1.25V Reference

2.5V Reference

2XVDDVSS Reference

5VDIFF Reference

VDD Reference

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Figure 3.28. ADC Differential Linearity Error vs Code, Vdd = 3V, Temp = 25°C

1.25V Reference

2.5V Reference

2XVDDVSS Reference

5VDIFF Reference

VDD Reference

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Figure 3.29. ADC Absolute Offset, Common Mode = Vdd /2

5

4

3

2

1

0

2.0

1.5

Vref= 1V25

VRef= 1V25

Vref= 2V5

VRef= 2V5

Vref= 2XVDDVSS

Vref= 5VDIFF

Vref= VDD

VRef= 2XVDDVSS

VRef= 5VDIFF

VRef= VDD

1.0

0.5

–1

0.0

–2

–3

–4

–0.5

–1.0

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

–40

–15

5

25

45

65

85

Vdd (V)

Temp (C)

Offset vs Supply Voltage, Temp = 25°C

Offset vs Temperature, Vdd = 3V

Figure 3.30. ADC Dynamic Performance vs Temperature for all ADC References, Vdd = 3V

71

70

69

68

67

66

65

64

63

79.4

79.2

79.0

78.8

78.6

78.4

78.2

78.0

2XVDDV

Vdd

1V25

Vdd

2V5

5VDIFF

2V5

2XVDDV

5VDIFF

1V25

–40

–15

5

25

45

65

85

–40

–15

5

25

45

65

85

Temperature [°C]

Signal to Noise Ratio (SNR)

Spurious-Free Dynamic Range (SFDR)

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Figure 3.31. ADC Temperature sensor readout

2600

2500

2400

2300

2200

2100

Vdd= 2.0

Vdd= 3.0

Vdd= 3.8

–40

–25 –15 –5

5

15 25 35 45 55 65 75 85

Temperature [°C]

3.11 Digital Analog Converter (DAC)

Table 3.15. DAC

Symbol

V_DACOUT

V_DACCM

Parameter

Condition

Min

Typ

Max

Unit

VDD voltage reference, single

ended

0

-V_DD

0

V_DD

V

Output voltage

range

VDD voltage reference, differ-

ential

V

Output common

mode voltage range

500 kSamples/s, 12 bit

400¹

200¹

17¹

µA

Active current in-

cluding references

for 2 channels

I_DAC

100 kSamples/s, 12 bit

1 kSamples/s 12 bit NORMAL

SR_DAC

Sample rate

500 ksam-

ples/s

Continuous Mode

Sample/Hold Mode

Sample/Off Mode

1000 kHz

250 kHz

DAC clock frequen-

cy

f_DAC

CYC_DACCONVClock cyckles per

conversion

2

t_DACCONV

Conversion time

Settling time

2

µs

dB

t_DACSETTLE

5

500 kSamples/s, 12 bit, sin-

gle ended, internal 1.25V refer-

ence

58

Signal to Noise Ra-

tio (SNR)

500 kSamples/s, 12 bit, single

ended, internal 2.5V reference

59

58

dB

SNR_DAC

500 kSamples/s, 12 bit, differ-

ential, internal 1.25V reference

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Symbol

Parameter

Condition

Min

Typ

Max

Unit

500 kSamples/s, 12 bit, differ-

ential, internal 2.5V reference

58

59

57

dB

500 kSamples/s, 12 bit, differ-

ential, V_DDreference

dB

500 kSamples/s, 12 bit, sin-

gle ended, internal 1.25V refer-

ence

500 kSamples/s, 12 bit, single

ended, internal 2.5V reference

54

56

53

55

62

dB

dBc

Signal to Noise-

SNDR_DAC

pulse Distortion Ra- 500 kSamples/s, 12 bit, differ-

tio (SNDR)

ential, internal 1.25V reference

500 kSamples/s, 12 bit, differ-

ential, internal 2.5V reference

500 kSamples/s, 12 bit, differ-

ential, V_DDreference

500 kSamples/s, 12 bit, sin-

gle ended, internal 1.25V refer-

ence

500 kSamples/s, 12 bit, single

ended, internal 2.5V reference

56

61

55

60

dBc

Spurious-Free

Dynamic

Range(SFDR)

SFDR_DAC

500 kSamples/s, 12 bit, differ-

ential, internal 1.25V reference

500 kSamples/s, 12 bit, differ-

ential, internal 2.5V reference

500 kSamples/s, 12 bit, differ-

ential, V_DDreference

After calibration, single ended

After calibration, differential

2

mV

LSB

V_DACOFFSET

DNL_DAC

INL_DAC

Offset voltage

Differential non-lin-

earity

±1

Integral non-lineari-

ty

±5

12

LSB

bits

MC_DAC

No missing codes

¹Measured with a static input code and no loading on the output.

3.12 Operational Amplifier (OPAMP)

The electrical characteristics for the Operational Amplifiers are based on simulations.

Table 3.16. OPAMP

Symbol

Parameter

Condition

Min

Typ

Max

Unit

(OPA2)BIASPROG=0xF,

(OPA2)HALFBIAS=0x0, Unity

Gain

370

95

460 µA

I_OPAMP

Active Current

(OPA2)BIASPROG=0x7,

(OPA2)HALFBIAS=0x1, Unity

Gain

135 µA

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Symbol

Parameter

Condition

Min

Typ

Max

Unit

25 µA

(OPA2)BIASPROG=0x0,

(OPA2)HALFBIAS=0x1, Unity

Gain

13

(OPA2)BIASPROG=0xF,

(OPA2)HALFBIAS=0x0

101

98

dB

(OPA2)BIASPROG=0x7,

(OPA2)HALFBIAS=0x1

dB

G_OL

Open Loop Gain

(OPA2)BIASPROG=0x0,

(OPA2)HALFBIAS=0x1

91

dB

(OPA2)BIASPROG=0xF,

(OPA2)HALFBIAS=0x0

6.1

1.8

0.25

64

MHz

°

Gain Bandwidth

Product

(OPA2)BIASPROG=0x7,

(OPA2)HALFBIAS=0x1

GBW_OPAMP

(OPA2)BIASPROG=0x0,

(OPA2)HALFBIAS=0x1

(OPA2)BIASPROG=0xF,

(OPA2)HALFBIAS=0x0, C_L=75

pF

(OPA2)BIASPROG=0x7,

(OPA2)HALFBIAS=0x1, C_L=75

pF

58

°

PM_OPAMP

Phase Margin

(OPA2)BIASPROG=0x0,

(OPA2)HALFBIAS=0x1, C_L=75

pF

R_INPUT

R_LOAD

Input Resistance

Load Resistance

DC Load Current

100

Mohm

Ohm

200

I_{LOAD_DC}

11 mA

OPAxHCMDIS=0

OPAxHCMDIS=1

V_SS

V_DD

V

V_INPUT

Input Voltage

V_DD-1.2

V_DD

V

V_OUTPUT

Output Voltage

V

Unity Gain, V_SS<V_in<V_DD

OPAxHCMDIS=0

,

0

1

mV

V_OFFSET

Input Offset Voltage

Unity Gain, V_SS<V_in<_DD-1.2,

OPAxHCMDIS=1

mV

V_{OFFSET_DRIFT}Input Offset Voltage

Drift

0.02 mV/°C

V/µs

(OPA2)BIASPROG=0xF,

(OPA2)HALFBIAS=0x0

3.2

0.8

0.1

101

(OPA2)BIASPROG=0x7,

(OPA2)HALFBIAS=0x1

V/µs

SR_OPAMP

Slew Rate

(OPA2)BIASPROG=0x0,

(OPA2)HALFBIAS=0x1

V/µs

V_out=1V, RESSEL=0,

0.1 Hz<f<10 kHz, OPAx-

HCMDIS=0

µV_RMS

N_OPAMP

Voltage Noise

V_out=1V, RESSEL=0,

0.1 Hz<f<10 kHz, OPAx-

HCMDIS=1

141

µV_RMS

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Symbol

Parameter

Condition

Min

Typ

Max

Unit

V_out=1V, RESSEL=0, 0.1

Hz<f<1 MHz, OPAxHCMDIS=0

196

229

µV_RMS

V_out=1V, RESSEL=0, 0.1

Hz<f<1 MHz, OPAxHCMDIS=1

µV_RMS

RESSEL=7, 0.1 Hz<f<10 kHz,

OPAxHCMDIS=0

1230

2130

1630

2590

RESSEL=7, 0.1 Hz<f<10 kHz,

OPAxHCMDIS=1

RESSEL=7, 0.1 Hz<f<1 MHz,

OPAxHCMDIS=0

RESSEL=7, 0.1 Hz<f<1 MHz,

OPAxHCMDIS=1

Figure 3.32. OPAMP Common Mode Rejection Ratio

Figure 3.33. OPAMP Positive Power Supply Rejection Ratio

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Figure 3.34. OPAMP Negative Power Supply Rejection Ratio

Figure 3.35. OPAMP Voltage Noise Spectral Density (Unity Gain) V_out=1V

Figure 3.36. OPAMP Voltage Noise Spectral Density (Non-Unity Gain)

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3.13 Analog Comparator (ACMP)

Table 3.17. ACMP

Symbol

V_ACMPIN

V_ACMPCM

Parameter

Condition

Min

Typ

Max

Unit

V

Input voltage range

0

V_DD

ACMP Common

V

Mode voltage range

BIASPROG=0b0000, FULL-

BIAS=0 and HALFBIAS=1 in

ACMPn_CTRL register

0.1

2.87

195

0

0.4 µA

15 µA

520 µA

µA

BIASPROG=0b1111, FULL-

BIAS=0 and HALFBIAS=0 in

ACMPn_CTRL register

I_ACMP

Active current

BIASPROG=0b1111, FULL-

BIAS=1 and HALFBIAS=0 in

ACMPn_CTRL register

Internal voltage reference off.

Using external voltage refer-

ence

Current consump-

tion of internal volt-

age reference

I_ACMPREF

Internal voltage reference

5

0

µA

V_ACMPOFFSETOffset voltage

BIASPROG= 0b1010, FULL-

BIAS=0 and HALFBIAS=0 in

ACMPn_CTRL register

-12

12 mV

V_ACMPHYST

ACMP hysteresis

Programmable

17

39

mV

CSRESSEL=0b00 in

ACMPn_INPUTSEL

kOhm

CSRESSEL=0b01 in

ACMPn_INPUTSEL

71

104

136

kOhm

Capacitive Sense

Internal Resistance

R_CSRES

CSRESSEL=0b10 in

ACMPn_INPUTSEL

CSRESSEL=0b11 in

ACMPn_INPUTSEL

t_ACMPSTART

Startup time

10 µs

The total ACMP current is the sum of the contributions from the ACMP and its internal voltage reference

as given in Equation 3.1 (p. 47) . I_ACMPREFis zero if an external voltage reference is used.

Total ACMP Active Current

I_ACMPTOTAL= I_ACMP+ I_ACMPREF

(3.1)

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Figure 3.37. ACMP Characteristics, Vdd = 3V, Temp = 25°C, FULLBIAS = 0, HALFBIAS = 1

2.5

2.0

1.5

1.0

0.5

0.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

HYSTSEL= 0.0

HYSTSEL= 2.0

HYSTSEL= 4.0

HYSTSEL= 6.0

0

4

8

12

0

2

4

6

8

10

12

14

ACMP_CTRL_BIASPROG

Current consumption, HYSTSEL = 4

Response time

100

80

60

40

20

0

BIASPROG= 0.0

BIASPROG= 4.0

BIASPROG= 8.0

BIASPROG= 12.0

0

1

2

3

4

5

6

7

ACMP_CTRL_HYSTSEL

Hysteresis

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3.14 Voltage Comparator (VCMP)

Table 3.18. VCMP

Symbol

V_VCMPIN

V_VCMPCM

Parameter

Condition

Min

Typ

Max

Unit

V

Input voltage range

V_DD

VCMP Common

V

Mode voltage range

BIASPROG=0b0000 and

HALFBIAS=1 in VCMPn_CTRL

register

0.3

22

10

0.6 µA

I_VCMP

Active current

BIASPROG=0b1111 and

HALFBIAS=0 in VCMPn_CTRL

register. LPREF=0.

35 µA

µs

t_VCMPREF

Startup time refer-

ence generator

NORMAL

Single ended

Differential

10

61

mV

V_VCMPOFFSETOffset voltage

V_VCMPHYST

t_VCMPSTART

VCMP hysteresis

Startup time

210 mV

10 µs

The V_DDtrigger level can be configured by setting the TRIGLEVEL field of the VCMP_CTRL register in

accordance with the following equation:

VCMP Trigger Level as a Function of Level Setting

V_{DD Trigger Level}=1.667V+0.034 ×TRIGLEVEL

(3.2)

3.15 I2C

Table 3.19. I2C Standard-mode (Sm)

Symbol

f_SCL

Parameter

Min

Typ

Max

Unit

SCL clock frequency

0

4.7

4.0

250

8

100¹kHz

t_LOW

SCL clock low time

µs

t_HIGH

SCL clock high time

µs

t_SU,DAT

t_HD,DAT

t_SU,STA

t_HD,STA

t_SU,STO

t_BUF

SDA set-up time

ns

SDA hold time

3450^2,3ns

Repeated START condition set-up time

(Repeated) START condition hold time

STOP condition set-up time

4.7

4.0

4.7

µs

Bus free time between a STOP and a START condi-

tion

¹For the minimum HFPERCLK frequency required in Standard-mode, see the I2C chapter in the EFM32WG Reference Manual.

²The maximum SDA hold time (t_HD,DAT) needs to be met only when the device does not stretch the low time of SCL (t_LOW).

³When transmitting data, this number is guaranteed only when I2Cn_CLKDIV < ((3450*10^-9[s] * f_HFPERCLK[Hz]) - 4).

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Table 3.20. I2C Fast-mode (Fm)

Symbol

f_SCL

Parameter

Min

Typ

Max

Unit

SCL clock frequency

0

1.3

0.6

100

8

400¹kHz

t_LOW

SCL clock low time

µs

t_HIGH

SCL clock high time

µs

t_SU,DAT

t_HD,DAT

t_SU,STA

t_HD,STA

t_SU,STO

t_BUF

SDA set-up time

ns

SDA hold time

900^2,3ns

Repeated START condition set-up time

(Repeated) START condition hold time

STOP condition set-up time

0.6

1.3

µs

Bus free time between a STOP and a START condi-

tion

¹For the minimum HFPERCLK frequency required in Fast-mode, see the I2C chapter in the EFM32WG Reference Manual.

²The maximum SDA hold time (t_HD,DAT) needs to be met only when the device does not stretch the low time of SCL (t_LOW).

³When transmitting data, this number is guaranteed only when I2Cn_CLKDIV < ((900*10^-9[s] * f_HFPERCLK[Hz]) - 4).

Table 3.21. I2C Fast-mode Plus (Fm+)

Symbol

f_SCL

Parameter

Min

Typ

Max

Unit

SCL clock frequency

0

0.5

1000¹kHz

t_LOW

SCL clock low time

µs

ns

µs

t_HIGH

SCL clock high time

0.26

50

t_SU,DAT

t_HD,DAT

t_SU,STA

t_HD,STA

t_SU,STO

t_BUF

SDA set-up time

SDA hold time

8

Repeated START condition set-up time

(Repeated) START condition hold time

STOP condition set-up time

0.26

0.5

Bus free time between a STOP and a START condi-

tion

¹For the minimum HFPERCLK frequency required in Fast-mode Plus, see the I2C chapter in the EFM32WG Reference Manual.

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3.16 USART SPI

Figure 3.38. SPI Master Timing

t_{CS_MO}

CS

t_{SCKL_MO}

SCLK

CLKPOL = 0

t_SCLK

SCLK

CLKPOL = 1

MOSI

MISO

t_{SU_MI}

t_{H_MI}

Table 3.22. SPI Master Timing

Symbol

Parameter

Condition

Min

2 * t_HFPER-

Typ

Max

Unit

1 2

t_SCLK

SCLK period

ns

CLK

1 2

t_{CS_MO}

CS to MOSI

-2.00

2.00 ns

1 2

t_{SCLK_MO}

SCLK to MOSI

MISO setup time

MISO hold time

-1.00

36.00

-6.00

3.00 ns

1 2

t_{SU_MI}

IOVDD = 3.0 V

ns

1 2

t_{H_MI}

¹Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0)

²Measurement done at 10% and 90% of V_DD(figure shows 50% of V_DD

)

Table 3.23. SPI Master Timing with SSSEARLY and SMSDELAY

Symbol

Parameter

Condition

Min

2 * t_HFPER-

Typ

Max

Unit

1 2

t_SCLK

SCLK period

ns

CLK

12

t_{CS_MO}

CS to MOSI

-2.00

2.00 ns

3.00 ns

ns

12

t_{SCLK_MO}

SCLK to MOSI

MISO setup time

MISO hold time

-1.00

-32.00

63.00

12

t_{SU_MI}

IOVDD = 3.0 V

12

t_{H_MI}

ns

¹Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0)

²Measurement done at 10% and 90% of V_DD(figure shows 50% of _VDD

)

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Figure 3.39. SPI Slave Timing

t_{CS_ACT_MI}

CS

t_{CS_DIS_MI}

SCLK

CLKPOL = 0

t_{SCLK_HI}

t_{SCLK_LO}

SCLK

t_{SU_MO}

CLKPOL = 1

t_SCLK

t_{H_MO}

MOSI

MISO

t_{SCLK_MI}

Table 3.24. SPI Slave Timing

Symbol

Parameter

Min

Typ

Max

Unit

1 2

t_{SCLK_sl}

t_{SCLK_hi}

t_{SCLK_lo}

SCKL period

6 * t_HFPER-

ns

CLK

1 2

SCLK high period

SCLK low period

3 * t_HFPER-

ns

CLK

3 * t_HFPER-

CLK

1 2

t_{CS_ACT_MI}

CS active to MISO

CS disable to MISO

MOSI setup time

MOSI hold time

5.00

35.00 ns

1 2

t_{CS_DIS_MI}

35.00 ns

1 2

t_{SU_MO}

ns

1 2

t_{H_MO}

2 + 2 * t_HF-

PERCLK

1 2

t_{SCLK_MI}

SCLK to MISO

7 + t_HFPER-

42 + 2 * ns

t_HFPERCLK

CLK

¹Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0)

²Measurement done at 10% and 90% of V_DD(figure shows 50% of V_DD

)

Table 3.25. SPI Slave Timing with SSSEARLY and SMSDELAY

Symbol

Parameter

Min

6 * t_HFPER-

Typ

Max

Unit

12

t_{SCLK_sl}

t_{SCLK_hi}

t_{SCLK_lo}

SCKL period

ns

CLK

12

SCLK high period

SCLK low period

3 * t_HFPER-

CLK

3 * t_HFPER-

CLK

12

t_{CS_ACT_MI}

CS active to MISO

CS disable to MISO

MOSI setup time

MOSI hold time

5.00

35.00 ns

ns

12

t_{CS_DIS_MI}

12

t_{SU_MO}

12

t_{H_MO}

2 + 2 * t_HF-

ns

PERCLK

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Symbol

Parameter

Min

-264 + t_HF-

Typ

Max

Unit

12

t_{SCLK_MI}

SCLK to MISO

-234 + 2 * ns

t_HFPERCLK

PERCLK

¹Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0)

²Measurement done at 10% and 90% of V_DD(figure shows 50% of _VDD

)

3.17 Digital Peripherals

Table 3.26. Digital Peripherals

Symbol

Parameter

Condition

Min

Typ

Max

Unit

I_USART

USART current

USART idle current, clock en-

abled

4.0

3.8

µA/

MHz

I_UART

UART current

LEUART current

I2C current

UART idle current, clock en-

abled

µA/

MHz

I_LEUART

LEUART idle current, clock en-

abled

194.0

7.6

nA

I_I2C

I2C idle current, clock enabled

µA/

MHz

I_TIMER

I_LETIMER

I_PCNT

TIMER current

LETIMER current

PCNT current

TIMER_0 idle current, clock

enabled

6.5

µA/

MHz

LETIMER idle current, clock

enabled

85.8

91.4

nA

PCNT idle current, clock en-

abled

I_RTC

I_AES

RTC current

AES current

RTC idle current, clock enabled

AES idle current, clock enabled

54.6

1.8

µA/

MHz

I_GPIO

I_PRS

I_DMA

GPIO current

PRS current

DMA current

GPIO idle current, clock en-

abled

3.4

3.9

µA/

MHz

PRS idle current

µA/

MHz

Clock enable

10.9

µA/

MHz

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4 Pinout and Package

Note

Please refer to the application note "AN0002 EFM32 Hardware Design Considerations" for

guidelines on designing Printed Circuit Boards (PCB's) for the EFM32WG360.

4.1 Pinout

The EFM32WG360 pinout is shown in Figure 4.1 (p. 54) and Table 4.1 (p. 54). Alternate locations

are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/").

Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module

in question.

Figure 4.1. EFM32WG360 Pinout (top view, not to scale)

Table 4.1. Device Pinout

CSP81 Pin#

and Name

Pin Alternate Functionality / Description

Pin Name

Analog

Timers

Communication

Other

U1_TX #1

USB_DM

A1

PF10

U1_RX #1

USB_DP

A2

A3

PF11

PF2

TIM0_CC2 #5

54

LEU0_TX #4

ACMP1_O #0

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CSP81 Pin#

and Name

Pin Alternate Functionality / Description

Pin Name

Analog

Timers

Communication

Other

DBG_SWO #0

GPIO_EM4WU4

A4

A5

A6

VSS

IOVDD_5

PE9

Ground

Digital IO power supply 5.

PCNT2_S1IN #1

TIM1_CC1 #1

LES_ALTEX5 #0

BOOT_RX

A7

A8

PE11

PE12

US0_RX #0

US0_RX #3

US0_CLK #0

I2C0_SDA #6

CMU_CLK1 #2

LES_ALTEX6 #0

TIM1_CC2 #1

TIM3_CC2 #0

A9

B1

B2

PA15

USB_VREGI

USB_VBUS

USB 5.0 V VBUS input.

ACMP1_CH7

DAC0_OUT1ALT #3/

OPAMP_OUT1ALT

TIM0_CDTI2 #1/3

TIM1_CC2 #0

US0_CLK #3

U0_RX #3

LES_CH15 #0

DBG_SWO #1

B3

B4

PC15

PF1

US1_CS #2

LEU0_RX #3

I2C0_SCL #5

TIM0_CC1 #5

LETIM0_OUT1 #2

DBG_SWDIO #0/1/2/3

GPIO_EM4WU3

B5

B6

PF5

PE8

TIM0_CDTI2 #2/5

PCNT2_S0IN #1

USB_VBUSEN #0

PRS_CH2 #1

PRS_CH3 #1

US0_TX #3

US0_CS #0

I2C0_SCL #6

LES_ALTEX7 #0

ACMP0_O #0

GPIO_EM4WU5

B7

B8

PE13

PA0

LEU0_RX #4

I2C0_SDA #0

PRS_CH0 #0

GPIO_EM4WU0

TIM0_CC0 #0/1/4

TIM0_CC2 #0/1

CMU_CLK0 #0

ETM_TD0 #3

B9

C1

PA2

USB_VREGO

TIM0_CDTI0 #1/3

TIM1_CC0 #0

TIM1_CC2 #4

ACMP1_CH5

DAC0_OUT1ALT #1/

OPAMP_OUT1ALT

C2

PC13

U1_RX #0

LES_CH13 #0

PCNT0_S0IN #0

ACMP1_CH6

DAC0_OUT1ALT #2/

OPAMP_OUT1ALT

TIM0_CDTI1 #1/3

TIM1_CC1 #0

PCNT0_S1IN #0

US0_CS #3

U0_TX #3

C3

C4

PC14

PF0

LES_CH14 #0

US1_CLK #2

LEU0_TX #3

I2C0_SDA #5

TIM0_CC0 #5

LETIM0_OUT0 #2

DBG_SWCLK #0/1/2/3

C5

C6

C7

PF12

PE10

PE14

USB_ID

TIM1_CC0 #1

TIM3_CC0 #0

US0_TX #0

LEU0_TX #2

BOOT_TX

CMU_CLK1 #0

PRS_CH1 #0

C8

C9

PA1

PA3

TIM0_CC1 #0/1

I2C0_SCL #0

U0_TX #2

LES_ALTEX2 #0

ETM_TD1 #3

TIM0_CDTI0 #0

TIM2_CC2 #2

D1

D2

PC10

PC11

ACMP1_CH2

ACMP1_CH3

US0_RX #2

US0_TX #2

LES_CH10 #0

LES_CH11 #0

ACMP1_CH4

DAC0_OUT1ALT #0/

OPAMP_OUT1ALT

CMU_CLK0 #1

LES_CH12 #0

D3

PC12

U1_TX #0

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CSP81 Pin#

and Name

Pin Alternate Functionality / Description

Pin Name

Analog

Timers

Communication

Other

LES_CH9 #0

GPIO_EM4WU2

D4

D5

D6

PC9

PC8

PA4

ACMP1_CH1

ACMP1_CH0

TIM2_CC1 #2

TIM2_CC0 #2

TIM0_CDTI1 #0

US0_CLK #2

US0_CS #2

U0_RX #2

LES_CH8 #0

LES_ALTEX3 #0

ETM_TD2 #3

LES_ALTEX4 #0

ETM_TD3 #3

D7

D8

PA5

PA6

TIM0_CDTI2 #0

LEU1_TX #1

LEU1_RX #1

ETM_TCLK #3

GPIO_EM4WU1

D9

E1

E2

E3

IOVDD_0

PE4

Digital IO power supply 0.

US0_CS #1

US0_CLK #1

U1_RX #3

PE5

PE3

BU_STAT

ACMP1_O #1

LEU1_RX #0

I2C0_SCL #2

LES_CH7 #0

ETM_TD0 #2

E4

PC7

ACMP0_CH7

E5

E6

E7

E8

E9

F1

F2

PE15

PB5

TIM3_CC1 #0

LEU0_RX #2

US2_CLK #1

US2_TX #1

US2_RX #1

PB3

PCNT1_S0IN #1

PCNT1_S1IN #1

PB4

VSS

Ground

DEC_0

PE2

Decouple output for on-chip voltage regulator.

BU_VOUT

TIM3_CC2 #1

U1_TX #3

ACMP0_O #1

LEU1_TX #0

I2C0_SDA #2

LES_CH6 #0

ETM_TCLK #2

F3

F4

PC6

PD7

ACMP0_CH6

CMU_CLK0 #2

LES_ALTEX1 #0

ACMP1_O #2

ADC0_CH7

DAC0_N1 /

OPAMP_N1

TIM1_CC1 #4

LETIM0_OUT1 #0

PCNT0_S1IN #3

US1_TX #2

I2C0_SCL #1

ETM_TCLK #0

ADC0_CH0

DAC0_OUT0ALT #4/

OPAMP_OUT0ALT

OPAMP_OUT2 #1

F5

PD0

PCNT2_S0IN #0

US1_TX #1

F6

F7

PA8

PC2

TIM2_CC0 #0

ACMP0_CH2

DAC0_OUT0ALT #2/

OPAMP_OUT0ALT

TIM0_CDTI0 #4

US2_TX #0

LES_CH2 #0

ACMP0_CH0

DAC0_OUT0ALT #0/

OPAMP_OUT0ALT

US0_TX #5

US1_TX #0

I2C0_SDA #4

TIM0_CC1 #4

PCNT0_S0IN #2

LES_CH0 #0

PRS_CH2 #0

F8

PC0

F9

G1

G2

PB6

US2_CS #1

VDD_DREG

VSS_DREG

Power supply for on-chip voltage regulator.

Ground for on-chip voltage regulator.

ADC0_CH4

OPAMP_P2

G3

G4

PD4

PD3

LEU0_TX #0

US1_CS #1

ETM_TD2 #0/2

ETM_TD1 #0/2

ADC0_CH3

OPAMP_N2

TIM0_CC2 #3

DAC0_OUT1 /

OPAMP_OUT1

G5

G6

PB12

PB11

LETIM0_OUT1 #1

TIM1_CC2 #3

I2C1_SCL #1

I2C1_SDA #1

DAC0_OUT0 /

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CSP81 Pin#

and Name

Pin Alternate Functionality / Description

Pin Name

Analog

Timers

Communication

Other

OPAMP_OUT0

LETIM0_OUT0 #1

TIM2_CC1 #0

G7

G8

PA9

PC4

ACMP0_CH4

DAC0_P0 /

OPAMP_P0

TIM0_CDTI2 #4

LETIM0_OUT0 #3

PCNT1_S0IN #0

US2_CLK #0

I2C1_SDA #0

LES_CH4 #0

ACMP0_CH1

DAC0_OUT0ALT #1/

OPAMP_OUT0ALT

US0_RX #5

US1_RX #0

I2C0_SCL #4

TIM0_CC2 #4

PCNT0_S1IN #2

LES_CH1 #0

PRS_CH3 #0

G9

H1

H2

PC1

PD8

PD6

BU_VIN

CMU_CLK1 #1

ADC0_CH6

DAC0_P1 /

OPAMP_P1

TIM1_CC0 #4

LETIM0_OUT0 #0

PCNT0_S0IN #3

LES_ALTEX0 #0

ACMP0_O #2

ETM_TD0 #0

US1_RX #2

I2C0_SDA #1

USB_DMPU #0

US1_CLK #1

H3

PD2

ADC0_CH2

TIM0_CC1 #3

DBG_SWO #3

H4

H5

H6

H7

VSS

Ground

AVSS_0

AVDD_0

PA10

Analog ground 0.

Analog power supply 0.

TIM2_CC2 #0

ACMP0_CH5

DAC0_N0 /

OPAMP_N0

LETIM0_OUT1 #3

PCNT1_S1IN #0

US2_CS #0

I2C1_SCL #0

H8

PC5

LES_CH5 #0

ACMP0_CH3

H9

J1

J2

PC3

PD5

PD1

DAC0_OUT0ALT #3/

OPAMP_OUT0ALT

TIM0_CDTI1 #4

US2_RX #0

LEU0_RX #0

US1_RX #1

LES_CH3 #0

ETM_TD3 #0/2

DBG_SWO #2

ADC0_CH5

OPAMP_OUT2 #0

ADC0_CH1

DAC0_OUT1ALT #4/

OPAMP_OUT1ALT

TIM0_CC0 #3

PCNT2_S1IN #0

J3

J4

IOVDD_3

PB14

Digital IO power supply 3.

HFXTAL_N

US0_CS #4/5

LEU0_RX #1

US0_CLK #4/5

LEU0_TX #1

J5

J6

PB13

HFXTAL_P

AVDD_1

Analog power supply 1.

Reset input, active low.

J7

RESETn

To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up

ensure that reset is released.

US0_RX #4

US1_CS #0

J8

J9

PB8

PB7

LFXTAL_N

LFXTAL_P

TIM1_CC1 #3

TIM1_CC0 #3

US0_TX #4

US1_CLK #0

4.2 Alternate Functionality Pinout

A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in

Table 4.2 (p. 58). The table shows the name of the alternate functionality in the first column, followed

by columns showing the possible LOCATION bitfield settings.

Note

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Some functionality, such as analog interfaces, do not have alternate settings or a LOCA-

TION bitfield. In these cases, the pinout is shown in the column corresponding to LOCA-

TION 0.

Table 4.2. Alternate functionality overview

Alternate

LOCATION

Functionality

ACMP0_CH0

ACMP0_CH1

ACMP0_CH2

ACMP0_CH3

ACMP0_CH4

ACMP0_CH5

ACMP0_CH6

ACMP0_CH7

ACMP0_O

0

1

2

PD6

PD7

3

4

5

6

Description

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

PE13

PC8

PC9

PC10

PC11

PC12

PC13

PC14

PC15

PF2

Analog comparator ACMP0, channel 0.

Analog comparator ACMP0, channel 1.

Analog comparator ACMP0, channel 2.

Analog comparator ACMP0, channel 3.

Analog comparator ACMP0, channel 4.

Analog comparator ACMP0, channel 5.

Analog comparator ACMP0, channel 6.

Analog comparator ACMP0, channel 7.

Analog comparator ACMP0, digital output.

Analog comparator ACMP1, channel 0.

Analog comparator ACMP1, channel 1.

Analog comparator ACMP1, channel 2.

Analog comparator ACMP1, channel 3.

Analog comparator ACMP1, channel 4.

Analog comparator ACMP1, channel 5.

Analog comparator ACMP1, channel 6.

Analog comparator ACMP1, channel 7.

Analog comparator ACMP1, digital output.

Analog to digital converter ADC0, input channel number 0.

Analog to digital converter ADC0, input channel number 1.

Analog to digital converter ADC0, input channel number 2.

Analog to digital converter ADC0, input channel number 3.

Analog to digital converter ADC0, input channel number 4.

Analog to digital converter ADC0, input channel number 5.

Analog to digital converter ADC0, input channel number 6.

Analog to digital converter ADC0, input channel number 7.

Bootloader RX

PE2

ACMP1_CH0

ACMP1_CH1

ACMP1_CH2

ACMP1_CH3

ACMP1_CH4

ACMP1_CH5

ACMP1_CH6

ACMP1_CH7

ACMP1_O

PE3

ADC0_CH0

ADC0_CH1

ADC0_CH2

ADC0_CH3

ADC0_CH4

ADC0_CH5

ADC0_CH6

ADC0_CH7

BOOT_RX

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PD7

PE11

PE10

BOOT_TX

Bootloader TX

Backup Power Domain status, whether or not the system

is in backup mode

BU_STAT

PE3

BU_VIN

PD8

PE2

PA2

PA1

Battery input for Backup Power Domain

BU_VOUT

CMU_CLK0

CMU_CLK1

Power output for Backup Power Domain

Clock Management Unit, clock output number 0.

Clock Management Unit, clock output number 1.

PC12

PD8

PD7

PE12

DAC0_N0 /

OPAMP_N0

PC5

PD7

Operational Amplifier 0 external negative input.

Operational Amplifier 1 external negative input.

DAC0_N1 /

OPAMP_N1

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Alternate

LOCATION

Functionality

0

1

2

3

4

5

6

Description

OPAMP_N2

PD3

Operational Amplifier 2 external negative input.

DAC0_OUT0 /

OPAMP_OUT0

Digital to Analog Converter DAC0_OUT0 /

OPAMP output channel number 0.

PB11

DAC0_OUT0ALT /

OPAMP_OUT0ALT

Digital to Analog Converter DAC0_OUT0ALT /

OPAMP alternative output for channel 0.

PC0

PC1

PC2

PC3

PD0

DAC0_OUT1 /

OPAMP_OUT1

Digital to Analog Converter DAC0_OUT1 /

OPAMP output channel number 1.

PB12

DAC0_OUT1ALT /

OPAMP_OUT1ALT

Digital to Analog Converter DAC0_OUT1ALT /

OPAMP alternative output for channel 1.

PC12

PD5

PC4

PC13

PD0

PC14

PC15

PD1

OPAMP_OUT2

Operational Amplifier 2 output.

DAC0_P0 /

OPAMP_P0

Operational Amplifier 0 external positive input.

DAC0_P1 /

OPAMP_P1

PD6

PD4

Operational Amplifier 1 external positive input.

OPAMP_P2

Operational Amplifier 2 external positive input.

Debug-interface Serial Wire clock input.

DBG_SWCLK

PF0

PF1

PF2

PF0

PF1

PD1

PF0

PF1

PD2

Note that this function is enabled to pin out of reset, and

has a built-in pull down.

Debug-interface Serial Wire data input / output.

DBG_SWDIO

DBG_SWO

PF1

Note that this function is enabled to pin out of reset, and

has a built-in pull up.

Debug-interface Serial Wire viewer Output.

PC15

Note that this function is not enabled after reset, and must

be enabled by software to be used.

ETM_TCLK

PD7

PD6

PD3

PD4

PD5

PA0

PA6

PC9

PF1

PF2

PE13

PC6

PC7

PD3

PD4

PD5

PA6

PA2

PA3

PA4

PA5

Embedded Trace Module ETM clock .

ETM_TD0

Embedded Trace Module ETM data 0.

ETM_TD1

Embedded Trace Module ETM data 1.

ETM_TD2

Embedded Trace Module ETM data 2.

ETM_TD3

Embedded Trace Module ETM data 3.

GPIO_EM4WU0

GPIO_EM4WU1

GPIO_EM4WU2

GPIO_EM4WU3

GPIO_EM4WU4

GPIO_EM4WU5

Pin can be used to wake the system up from EM4

High Frequency Crystal negative pin. Also used as exter-

nal optional clock input pin.

HFXTAL_N

PB14

HFXTAL_P

I2C0_SCL

PB13

PA1

PA0

PC5

PC4

PD6

PD7

PA3

PA4

PA5

High Frequency Crystal positive pin.

I2C0 Serial Clock Line input / output.

I2C0 Serial Data input / output.

PD7

PC7

PC6

PC1

PC0

PF1

PF0

PE13

PE12

I2C0_SDA

PD6

I2C1_SCL

PB12

PB11

I2C1 Serial Clock Line input / output.

I2C1 Serial Data input / output.

I2C1_SDA

LES_ALTEX0

LES_ALTEX1

LES_ALTEX2

LES_ALTEX3

LES_ALTEX4

LESENSE alternate exite output 0.

LESENSE alternate exite output 1.

LESENSE alternate exite output 2.

LESENSE alternate exite output 3.

LESENSE alternate exite output 4.

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Alternate

LOCATION

Functionality

LES_ALTEX5

LES_ALTEX6

LES_ALTEX7

LES_CH0

0

1

2

3

4

5

6

Description

LESENSE alternate exite output 5.

LESENSE alternate exite output 6.

LESENSE alternate exite output 7.

LESENSE channel 0.

PE11

PE12

PE13

PC0

LES_CH1

PC1

LESENSE channel 1.

LES_CH2

PC2

LESENSE channel 2.

LES_CH3

PC3

LESENSE channel 3.

LES_CH4

PC4

LESENSE channel 4.

LES_CH5

PC5

LESENSE channel 5.

LES_CH6

PC6

LESENSE channel 6.

LES_CH7

PC7

LESENSE channel 7.

LES_CH8

PC8

LESENSE channel 8.

LES_CH9

PC9

LESENSE channel 9.

LES_CH10

LES_CH11

LES_CH12

LES_CH13

LES_CH14

LES_CH15

LETIM0_OUT0

LETIM0_OUT1

LEU0_RX

PC10

PC11

PC12

PC13

PC14

PC15

PD6

LESENSE channel 10.

LESENSE channel 11.

LESENSE channel 12.

LESENSE channel 13.

LESENSE channel 14.

LESENSE channel 15.

PB11

PB12

PB14

PF0

PC4

PC5

PF1

Low Energy Timer LETIM0, output channel 0.

Low Energy Timer LETIM0, output channel 1.

LEUART0 Receive input.

PD7

PF1

PD5

PE15

PA0

LEUART0 Transmit output. Also used as receive input in

half duplex communication.

LEU0_TX

LEU1_RX

LEU1_TX

PD4

PC7

PC6

PB13

PA6

PA5

PE14

PF0

PF2

LEUART1 Receive input.

LEUART1 Transmit output. Also used as receive input in

half duplex communication.

Low Frequency Crystal (typically 32.768 kHz) negative

pin. Also used as an optional external clock input pin.

LFXTAL_N

PB8

LFXTAL_P

PCNT0_S0IN

PCNT0_S1IN

PCNT1_S0IN

PCNT1_S1IN

PCNT2_S0IN

PCNT2_S1IN

PRS_CH0

PB7

PC13

PC14

PC4

PC5

PD0

PD1

PA0

PA1

PC0

PC1

PA0

PA1

PA2

Low Frequency Crystal (typically 32.768 kHz) positive pin.

Pulse Counter PCNT0 input number 0.

PC0

PC1

PD6

PD7

Pulse Counter PCNT0 input number 1.

PB3

PB4

PE8

PE9

Pulse Counter PCNT1 input number 0.

Pulse Counter PCNT1 input number 1.

Pulse Counter PCNT2 input number 0.

Pulse Counter PCNT2 input number 1.

Peripheral Reflex System PRS, channel 0.

Peripheral Reflex System PRS, channel 1.

Peripheral Reflex System PRS, channel 2.

Peripheral Reflex System PRS, channel 3.

Timer 0 Capture Compare input / output channel 0.

Timer 0 Capture Compare input / output channel 1.

Timer 0 Capture Compare input / output channel 2.

PRS_CH1

PRS_CH2

PF5

PE8

PA0

PA1

PA2

PRS_CH3

TIM0_CC0

TIM0_CC1

TIM0_CC2

PD1

PD2

PD3

PA0

PC0

PC1

PF0

PF1

PF2

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Alternate

LOCATION

Functionality

TIM0_CDTI0

TIM0_CDTI1

TIM0_CDTI2

TIM1_CC0

TIM1_CC1

TIM1_CC2

TIM2_CC0

TIM2_CC1

TIM2_CC2

TIM3_CC0

TIM3_CC1

TIM3_CC2

U0_RX

0

1

PC13

PC14

PC15

PE10

PE11

PE12

2

3

4

5

6

Description

PA3

PC13

PC14

PC15

PB7

PC2

Timer 0 Complimentary Deat Time Insertion channel 0.

Timer 0 Complimentary Deat Time Insertion channel 1.

Timer 0 Complimentary Deat Time Insertion channel 2.

Timer 1 Capture Compare input / output channel 0.

Timer 1 Capture Compare input / output channel 1.

Timer 1 Capture Compare input / output channel 2.

Timer 2 Capture Compare input / output channel 0.

Timer 2 Capture Compare input / output channel 1.

Timer 2 Capture Compare input / output channel 2.

Timer 3 Capture Compare input / output channel 0.

Timer 3 Capture Compare input / output channel 1.

Timer 3 Capture Compare input / output channel 2.

UART0 Receive input.

PA4

PC3

PC4

PD6

PD7

PC13

PA5

PF5

PC13

PC14

PC15

PA8

PB8

PB11

PC8

PC9

PC10

PA9

PA10

PE14

PE15

PA15

PE2

PA4

PA3

PC15

PC14

PE3

UART0 Transmit output. Also used as receive input in half

duplex communication.

U0_TX

U1_RX

U1_TX

PC13

PC12

PF11

PF10

UART1 Receive input.

UART1 Transmit output. Also used as receive input in half

duplex communication.

PE2

US0_CLK

US0_CS

PE12

PE13

PE5

PE4

PC9

PC8

PC15

PC14

PB13

PB14

PB13

PB14

USART0 clock input / output.

USART0 chip select input / output.

USART0 Asynchronous Receive.

US0_RX

US0_TX

PE11

PE10

PC10

PC11

PE12

PE13

PB8

PB7

PC1

PC0

USART0 Synchronous mode Master Input / Slave Output

(MISO).

USART0 Asynchronous Transmit.Also used as receive in-

put in half duplex communication.

USART0 Synchronous mode Master Output / Slave Input

(MOSI).

US1_CLK

US1_CS

PB7

PB8

PD2

PD3

PF0

PF1

USART1 clock input / output.

USART1 chip select input / output.

USART1 Asynchronous Receive.

US1_RX

US1_TX

PC1

PC0

PD1

PD0

PD6

PD7

USART1 Synchronous mode Master Input / Slave Output

(MISO).

USART1 Asynchronous Transmit.Also used as receive in-

put in half duplex communication.

USART1 Synchronous mode Master Output / Slave Input

(MOSI).

US2_CLK

US2_CS

PC4

PC5

PB5

PB6

USART2 clock input / output.

USART2 chip select input / output.

USART2 Asynchronous Receive.

US2_RX

US2_TX

PC3

PC2

PB4

PB3

USART2 Synchronous mode Master Input / Slave Output

(MISO).

USART2 Asynchronous Transmit.Also used as receive in-

put in half duplex communication.

USART2 Synchronous mode Master Output / Slave Input

(MOSI).

USB_DM

PF10

PD2

USB D- pin.

USB_DMPU

USB D- Pullup control.

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Alternate

LOCATION

Functionality

USB_DP

0

1

2

3

4

5

6

Description

PF11

PF12

USB D+ pin.

USB_ID

USB ID pin. Used in OTG mode.

USB 5 V VBUS input.

USB_VBUS

USB_VBUSEN

USB_VREGI

USB_VBUS

PF5

USB 5 V VBUS enable.

USB_VREGI

USB Input to internal 3.3 V regulator

USB Decoupling for internal 3.3 V USB regulator and reg-

ulator output

USB_VREGO

4.3 GPIO Pinout Overview

The specific GPIO pins available in EFM32WG360 is shown in Table 4.3 (p. 62). Each GPIO port is

organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated

by a number from 15 down to 0.

Table 4.3. GPIO Pinout

Port

Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin

0

15

PA15

-

14

13

12

11

10

PA10

-

9

PA9

-

8

7

6

PA6

PB6

PC6

PD6

-

5

4

3

2

1

PA1

-

Port A

Port B

Port C

Port D

Port E

Port F

-

PA8

PB8

PC8

PD8

PE8

-

PA5

PB5

PC5

PD5

PE5

PF5

PA4

PB4

PC4

PD4

PE4

-

PA3

PB3

PC3

PD3

PE3

-

PA2

-

PA0

-

PB14 PB13 PB12 PB11

PB7

PC7

PD7

-

PC15 PC14 PC13 PC12 PC11 PC10

PC9

-

PC2

PD2

PE2

PF2

PC1

PD1

-

PC0

PD0

-

PE15 PE14 PE13 PE12 PE11 PE10

PF12 PF11 PF10

PE9

-

PF1

PF0

4.4 Opamp Pinout Overview

The specific opamp terminals available in EFM32WG360 is shown in Figure 4.2 (p. 62) .

Figure 4.2. Opamp Pinout

PB11

PB12

PC0

OUT0ALT

OUT0

PC4

PC5

+

OPA0

-

PC1

PC2

PC3

+

PD4

PD3

PC12

PC13

PC14

PC15

PD0

OPA2

-

OUT2

PD6

PD7

OUT1ALT

OUT1

+

OPA1

-

PD1

PD5

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4.5 CSP81 Package

Figure 4.3. CSP81

Note:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. Primary datum “C” and seating plane are defined by the spherical crowns of the solder balls.

4. Dimension “b” is measured at the maximum solder bump diameter, parallel to primary datum “C”.

5. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body

Components.

Table 4.4. CSP81 (Dimensions in mm)

Symbol

Min

A

A1

A2

b

S

D

E

e

D1

E1

n

aaa bbb ccc ddd

eee

0.491 0.17 0.036 0.23 0.3075

4.355 4.275 0.40 3.20 3.20

BSC. BSC. BSC. BSC. BSC.

Nom

Max

0.55

-

0.31

81

0.05 0.10 0.075 0.15 0.05

0.609 0.23 0.044 0.29 0.3125

All EFM32 packages are RoHS compliant and free of Bromine (Br) and Antimony (Sb).

For additional Quality and Environmental information, please see:

http://www.silabs.com/support/quality/pages/default.aspx

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5 PCB Layout and Soldering

5.1 Recommended PCB Layout

Figure 5.1. CSP81 PCB Land Pattern

Table 5.1. CSP81 PCB Land Pattern Dimensions (Dimensions in mm)

Symbol

X

Dim. (mm)

0.20

3.20

0.40

C1

C2

E1

E2

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Figure 5.2. CSP81 PCB Solder Mask

Table 5.2. CSP81 PCB Solder Mask Dimensions (Dimensions in mm)

Symbol

X

Dim. (mm)

0.26

3.20

0.40

C1

C2

E1

E2

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Figure 5.3. CSP81 PCB Stencil Design

Table 5.3. CSP81 PCB Stencil Design Dimensions (Dimensions in mm)

Symbol

X

Dim. (mm)

0.20

3.20

0.40

C1

C2

E1

E2

1. The drawings are not to scale.

2. All dimensions are in millimeters.

3. All drawings are subject to change without notice.

4. The PCB Land Pattern drawing is in compliance with IPC-7351B.

5. Stencil thickness 0.125 mm.

6. For detailed pin-positioning, see Figure 4.3 (p. 63) .

5.2 Soldering Information

The latest IPC/JEDEC J-STD-020 recommendations for Pb-Free reflow soldering should be followed.

The packages have a Moisture Sensitivity Level rating of 3, please see the latest IPC/JEDEC J-STD-033

standard for MSL description and level 3 bake conditions.

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6 Chip Marking, Revision and Errata

6.1 Chip Marking

In the illustration below package fields and position are shown.

Figure 6.1. Example Chip Marking (top view)

6.2 Revision

The revision of a chip can be determined from the "Revision" field in Figure 6.1 (p. 67) .

6.3 Errata

Please see the errata document for EFM32WG360 for description and resolution of device erratas. This

document is available in Simplicity Studio and online at:

http://www.silabs.com/support/pages/document-library.aspx?p=MCUs--32-bit

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7 Revision History

7.1 Revision 1.00

October 15th, 2014

Initial release.

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A Disclaimer and Trademarks

A.1 Disclaimer

Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation

of all peripherals and modules available for system and software implementers using or intending to use

the Silicon Laboratories products. Characterization data, available modules and peripherals, memory

sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and

do vary in different applications. Application examples described herein are for illustrative purposes only.

Silicon Laboratories reserves the right to make changes without further notice and limitation to product

information, specifications, and descriptions herein, and does not give warranties as to the accuracy

or completeness of the included information. Silicon Laboratories shall have no liability for the conse-

quences of use of the information supplied herein. This document does not imply or express copyright

licenses granted hereunder to design or fabricate any integrated circuits. The products must not be

used within any Life Support System without the specific written consent of Silicon Laboratories. A "Life

Support System" is any product or system intended to support or sustain life and/or health, which, if it

fails, can be reasonably expected to result in significant personal injury or death. Silicon Laboratories

products are generally not intended for military applications. Silicon Laboratories products shall under no

circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological

or chemical weapons, or missiles capable of delivering such weapons.

A.2 Trademark Information

Silicon Laboratories Inc., Silicon Laboratories, Silicon Labs, SiLabs and the Silicon Labs logo, CMEMS®,

EFM, EFM32, EFR, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most ener-

gy friendly microcontrollers", Ember®, EZLink®, EZMac®, EZRadio®, EZRadioPRO®, DSPLL®, ISO-

modem®, Precision32®, ProSLIC®, SiPHY®, USBXpress® and others are trademarks or registered

trademarks of Silicon Laboratories Inc. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or reg-

istered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited. All other products

or brand names mentioned herein are trademarks of their respective holders.

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B Contact Information

Silicon Laboratories Inc.

400 West Cesar Chavez

Austin, TX 78701

Please visit the Silicon Labs Technical Support web page:

http://www.silabs.com/support/pages/contacttechnicalsupport.aspx

and register to submit a technical support request.

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Table of Contents

1. Ordering Information .................................................................................................................................. 2

2. System Summary ...................................................................................................................................... 3

2.1. System Introduction ......................................................................................................................... 3

2.2. Configuration Summary .................................................................................................................... 7

2.3. Memory Map ................................................................................................................................. 8

3. Electrical Characteristics ........................................................................................................................... 10

3.1. Test Conditions ............................................................................................................................. 10

3.2. Absolute Maximum Ratings ............................................................................................................. 10

3.3. General Operating Conditions .......................................................................................................... 10

3.4. Current Consumption ..................................................................................................................... 11

3.5. Transition between Energy Modes .................................................................................................... 17

3.6. Power Management ....................................................................................................................... 18

3.7. Flash .......................................................................................................................................... 19

3.8. General Purpose Input Output ......................................................................................................... 19

3.9. Oscillators .................................................................................................................................... 27

3.10. Analog Digital Converter (ADC) ...................................................................................................... 32

3.11. Digital Analog Converter (DAC) ...................................................................................................... 42

3.12. Operational Amplifier (OPAMP) ...................................................................................................... 43

3.13. Analog Comparator (ACMP) .......................................................................................................... 47

3.14. Voltage Comparator (VCMP) ......................................................................................................... 49

3.15. I2C ........................................................................................................................................... 49

3.16. USART SPI ................................................................................................................................ 51

3.17. Digital Peripherals ....................................................................................................................... 53

4. Pinout and Package ................................................................................................................................. 54

4.1. Pinout ......................................................................................................................................... 54

4.2. Alternate Functionality Pinout .......................................................................................................... 57

4.3. GPIO Pinout Overview ................................................................................................................... 62

4.4. Opamp Pinout Overview ................................................................................................................. 62

4.5. CSP81 Package ........................................................................................................................... 63

5. PCB Layout and Soldering ........................................................................................................................ 64

5.1. Recommended PCB Layout ............................................................................................................ 64

5.2. Soldering Information ..................................................................................................................... 66

6. Chip Marking, Revision and Errata .............................................................................................................. 67

6.1. Chip Marking ................................................................................................................................ 67

6.2. Revision ...................................................................................................................................... 67

6.3. Errata ......................................................................................................................................... 67

7. Revision History ...................................................................................................................................... 68

7.1. Revision 1.00 ............................................................................................................................... 68

A. Disclaimer and Trademarks ....................................................................................................................... 69

A.1. Disclaimer ................................................................................................................................... 69

A.2. Trademark Information ................................................................................................................... 69

B. Contact Information ................................................................................................................................. 70

B.1. ................................................................................................................................................. 70

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List of Figures

2.1. Block Diagram ....................................................................................................................................... 3

2.2. EFM32WG360 Memory Map with largest RAM and Flash sizes ....................................................................... 9

3.1. EM1 Current consumption with all peripheral clocks disabled and HFXO running at 48 MHz ................................ 13

3.2. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 28 MHz .............................. 13

3.3. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 21 MHz .............................. 14

3.4. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 14 MHz .............................. 14

3.5. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 11 MHz .............................. 15

3.6. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 6.6 MHz ............................. 15

3.7. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 1.2 MHz ............................. 16

3.8. EM2 current consumption. RTC prescaled to 1kHz, 32.768 kHz LFRCO. ......................................................... 16

3.9. EM3 current consumption. ..................................................................................................................... 17

3.10. EM4 current consumption. ................................................................................................................... 17

3.11. Typical Low-Level Output Current, 2V Supply Voltage ................................................................................ 21

3.12. Typical High-Level Output Current, 2V Supply Voltage ................................................................................ 22

3.13. Typical Low-Level Output Current, 3V Supply Voltage ................................................................................ 23

3.14. Typical High-Level Output Current, 3V Supply Voltage ................................................................................ 24

3.15. Typical Low-Level Output Current, 3.8V Supply Voltage .............................................................................. 25

3.16. Typical High-Level Output Current, 3.8V Supply Voltage ............................................................................. 26

3.17. Calibrated LFRCO Frequency vs Temperature and Supply Voltage .............................................................. 28

3.18. Calibrated HFRCO 1 MHz Band Frequency vs Supply Voltage and Temperature ............................................ 29

3.19. Calibrated HFRCO 7 MHz Band Frequency vs Supply Voltage and Temperature ............................................ 30

3.20. Calibrated HFRCO 11 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 30

3.21. Calibrated HFRCO 14 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 30

3.22. Calibrated HFRCO 21 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 31

3.23. Calibrated HFRCO 28 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 31

3.24. Integral Non-Linearity (INL) ................................................................................................................... 37

3.25. Differential Non-Linearity (DNL) .............................................................................................................. 37

3.26. ADC Frequency Spectrum, Vdd = 3V, Temp = 25°C ................................................................................. 38

3.27. ADC Integral Linearity Error vs Code, Vdd = 3V, Temp = 25°C ................................................................... 39

3.28. ADC Differential Linearity Error vs Code, Vdd = 3V, Temp = 25°C ............................................................... 40

3.29. ADC Absolute Offset, Common Mode = Vdd /2 ........................................................................................ 41

3.30. ADC Dynamic Performance vs Temperature for all ADC References, Vdd = 3V .............................................. 41

3.31. ADC Temperature sensor readout ......................................................................................................... 42

3.32. OPAMP Common Mode Rejection Ratio ................................................................................................. 45

3.33. OPAMP Positive Power Supply Rejection Ratio ........................................................................................ 45

3.34. OPAMP Negative Power Supply Rejection Ratio ...................................................................................... 46

3.35. OPAMP Voltage Noise Spectral Density (Unity Gain) V_out=1V ..................................................................... 46

3.36. OPAMP Voltage Noise Spectral Density (Non-Unity Gain) .......................................................................... 46

3.37. ACMP Characteristics, Vdd = 3V, Temp = 25°C, FULLBIAS = 0, HALFBIAS = 1 ............................................. 48

3.38. SPI Master Timing ............................................................................................................................... 51

3.39. SPI Slave Timing ................................................................................................................................ 52

4.1. EFM32WG360 Pinout (top view, not to scale) ............................................................................................. 54

4.2. Opamp Pinout ...................................................................................................................................... 62

4.3. CSP81 ................................................................................................................................................ 63

5.1. CSP81 PCB Land Pattern ...................................................................................................................... 64

5.2. CSP81 PCB Solder Mask ....................................................................................................................... 65

5.3. CSP81 PCB Stencil Design .................................................................................................................... 66

6.1. Example Chip Marking (top view) ............................................................................................................. 67

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List of Tables

1.1. Ordering Information ................................................................................................................................ 2

2.1. Configuration Summary ............................................................................................................................ 7

3.1. Absolute Maximum Ratings ..................................................................................................................... 10

3.2. General Operating Conditions .................................................................................................................. 10

3.3. Current Consumption ............................................................................................................................. 11

3.4. Energy Modes Transitions ...................................................................................................................... 17

3.5. Power Management ............................................................................................................................... 18

3.6. Flash .................................................................................................................................................. 19

3.7. GPIO .................................................................................................................................................. 19

3.8. LFXO .................................................................................................................................................. 27

3.9. HFXO ................................................................................................................................................. 27

3.10. LFRCO .............................................................................................................................................. 28

3.11. HFRCO ............................................................................................................................................. 29

3.12. AUXHFRCO ....................................................................................................................................... 32

3.13. ULFRCO ............................................................................................................................................ 32

3.14. ADC .................................................................................................................................................. 32

3.15. DAC .................................................................................................................................................. 42

3.16. OPAMP ............................................................................................................................................. 43

3.17. ACMP ............................................................................................................................................... 47

3.18. VCMP ............................................................................................................................................... 49

3.19. I2C Standard-mode (Sm) ...................................................................................................................... 49

3.20. I2C Fast-mode (Fm) ............................................................................................................................ 50

3.21. I2C Fast-mode Plus (Fm+) .................................................................................................................... 50

3.22. SPI Master Timing ............................................................................................................................... 51

3.23. SPI Master Timing with SSSEARLY and SMSDELAY ................................................................................. 51

3.24. SPI Slave Timing ................................................................................................................................ 52

3.25. SPI Slave Timing with SSSEARLY and SMSDELAY .................................................................................. 52

3.26. Digital Peripherals ............................................................................................................................... 53

4.1. Device Pinout ....................................................................................................................................... 54

4.2. Alternate functionality overview ................................................................................................................ 58

4.3. GPIO Pinout ........................................................................................................................................ 62

4.4. CSP81 (Dimensions in mm) .................................................................................................................... 63

5.1. CSP81 PCB Land Pattern Dimensions (Dimensions in mm) .......................................................................... 64

5.2. CSP81 PCB Solder Mask Dimensions (Dimensions in mm) ........................................................................... 65

5.3. CSP81 PCB Stencil Design Dimensions (Dimensions in mm) ........................................................................ 66

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List of Equations

3.1. Total ACMP Active Current ..................................................................................................................... 47

3.2. VCMP Trigger Level as a Function of Level Setting ..................................................................................... 49

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型号：	EFM32WG360F64G-A-CSP81
厂家：	SILICON
描述：	Operation from backup battery when main power drains out 时钟外围集成电路
文件：	总75页 (文件大小：1768K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

EFM32WG360F64G-A-CSP81 [SILICON]

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