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EFM8BB22F16G-C-QFN28 [SILICON]

Microcontroller, 8-Bit, FLASH, 50MHz, CMOS, QFN-28;
EFM8BB22F16G-C-QFN28
型号： EFM8BB22F16G-C-QFN28
厂家： SILICON    SILICON
描述：

Microcontroller, 8-Bit, FLASH, 50MHz, CMOS, QFN-28

时钟 微控制器 外围集成电路
文件： 总59页 (文件大小：1109K)
中文：  中文翻译
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EFM8 Busy Bee Family  
EFM8BB2 Data Sheet  
The EFM8BB2, part of the Busy Bee family of MCUs, is a multi-  
purpose line of 8-bit microcontrollers with a comprehensive feature  
set in small packages.  
KEY FEATURES  
• Pipelined 8-bit C8051 core with 50 MHz  
maximum operating frequency  
These devices offer high-value by integrating advanced analog and enhanced high-  
speed communication peripherals into small packages, making them ideal for space-con-  
strained applications. With an efficient 8051 core, enhanced pulse-width modulation, and  
precision analog, the EFM8BB2 family is also optimal for embedded applications.  
• Up to 22 multifunction, 5 V tolerant I/O  
pins  
• One 12-bit Analog to Digital converter  
(ADC)  
• Two Low-current analog comparators with  
build-in DAC as reference input  
EFM8BB2 applications include the following:  
• Medical equipment  
• Motor control  
• Integrated temperature sensor  
• Lighting systems  
• Consumer electronics  
• 3-channel PWM / PCA with special  
hardware kill/safe state capability  
• High-speed communication hub  
• Sensor controllers  
• Five 16-bit timers  
• Two UARTs, SPI, SMBus/I2C master/  
slave and I2C slave  
• Priority crossbar for flexible pin mapping  
Core / Memory  
Clock Management  
Energy Management  
High Frequency  
49 MHz RC  
Oscillator  
CIP-51 8051 Core  
(50 MHz)  
External CMOS  
Oscillator  
Internal LDO  
Power-On Reset  
Regulator  
Flash Program  
Memory  
High Frequency  
24.5 MHz RC  
Oscillator  
RAM Memory  
(2304 bytes)  
Debug Interface  
with C2  
Low Frequency  
RC Oscillator  
Brown-Out  
Detector  
5 V-to 3.3 V LDO  
Regulator  
(16 KB)  
8-bit SFR bus  
Serial Interfaces  
I/O Ports  
Timers and Triggers  
Analog Interfaces  
Security  
16-bit CRC  
External  
Interrupts  
Timer  
Comparator 0  
2 x UART  
SPI  
Pin Reset  
PCA/PWM  
0/1/2  
ADC  
Internal  
Voltage  
Reference  
High-Speed  
I2C Slave  
Watchdog  
Timer 3/4  
Timer  
General  
Purpose I/O  
I2C / SMBus  
Comparator 1  
Pin Wakeup  
Lowest power mode with peripheral operational:  
Normal Idle Suspend  
Snooze  
Shutdown  
silabs.com | Building a more connected world.  
Rev. 1.4  
EFM8BB2 Data Sheet  
Feature List  
1. Feature List  
The EFM8BB2 highlighted features are listed below.  
• Core:  
• Timers/Counters and PWM:  
• Pipelined CIP-51 Core  
• 3-channel Programmable Counter Array (PCA) supporting  
PWM, capture/compare, and frequency output modes  
• Fully compatible with standard 8051 instruction set  
• 70% of instructions execute in 1-2 clock cycles  
• 50 MHz maximum operating frequency  
• Memory:  
• 5 x 16-bit general-purpose timers  
• Independent watchdog timer, clocked from the low frequen-  
cy oscillator  
• Communications and Digital Peripherals:  
• 2 x UART, up to 3 Mbaud  
• Up to 16 KB flash memory, in-system re-programmable  
from firmware, including 1 KB of 64-byte sectors and 15  
KB of 512-byte sectors.  
• SPI™ Master / Slave, up to 12 Mbps  
• SMBus™/I2C™ Master / Slave, up to 400 kbps  
• Up to 2304 bytes RAM (including 256 bytes standard 8051  
RAM and 2048 bytes on-chip XRAM)  
I2C High-Speed Slave, up to 3.4 Mbps  
•
• Power:  
• 16-bit CRC unit, supporting automatic CRC of flash at 256-  
byte boundaries  
• 5 V-input LDO regulator  
• Internal LDO regulator for CPU core voltage  
• Power-on reset circuit and brownout detectors  
• I/O: Up to 22 total multifunction I/O pins:  
• All pins 5 V tolerant under bias  
• Analog:  
• 12-Bit Analog-to-Digital Converter (ADC)  
• 2 x Low-current analog comparators with adjustable refer-  
ence  
• Flexible peripheral crossbar for peripheral routing  
• 5 mA source, 12.5 mA sink allows direct drive of LEDs  
• Clock Sources:  
• On-Chip, Non-Intrusive Debugging  
• Full memory and register inspection  
• Four hardware breakpoints, single-stepping  
• Pre-loaded UART bootloader  
• Internal 49 MHz oscillator with accuracy of ±1.5%  
• Internal 24.5 MHz oscillator with ±2% accuracy  
• Internal 80 kHz low-frequency oscillator  
• External CMOS clock option  
• Temperature range -40 to 85 ºC or -40 to 125 ºC  
• Automotive grade available (requires PPAP)  
• Single power supply of 2.2 to 3.6 V or 3.0 to 5.25 V  
• QFN28, QSOP24, and QFN20 packages  
With on-chip power-on reset, voltage supply monitor, watchdog timer, and clock oscillator, the EFM8BB2 devices are truly standalone  
system-on-a-chip solutions. The flash memory is reprogrammable in-circuit, providing nonvolatile data storage and allowing field up-  
grades of the firmware. The on-chip debugging interface (C2) allows non-intrusive (uses no on-chip resources), full speed, in-circuit  
debugging using the production MCU installed in the final application. This debug logic supports inspection and modification of memory  
and registers, setting breakpoints, single stepping, and run and halt commands. All analog and digital peripherals are fully functional  
while debugging. Each device is specified for 2.2 to 3.6 V operation (or up to 5.25 V with the 5 V regulator option). Both the G-grade  
and I-grade devices are available in 28-pin QFN, 20-pin QFN, or 24-pin QSOP packages, and A-grade devices are available in 28-pin  
QFN or 20-pin QFN packages. All package options are lead-free and RoHS compliant.  
silabs.com | Building a more connected world.  
Rev. 1.4 | 2  
 
EFM8BB2 Data Sheet  
Ordering Information  
2. Ordering Information  
EFM8 BB2 2 F 16 G – A – QFN28 R  
Tape and Reel (Optional)  
Package Type  
Revision  
Temperature Grade G (-40 to +85), I (-40 to +125), A (-40 to +125, Automotive Grade)  
Flash Memory Size – 16 KB  
Memory Type (Flash)  
Family Feature Set  
Busy Bee 2 Family  
Silicon Labs EFM8 Product Line  
Figure 2.1. EFM8BB2 Part Numbering  
All EFM8B2 family members have the following features:  
• CIP-51 Core running up to 50 MHz  
• Three Internal Oscillators (49 MHz, 24.5 MHz and 80 kHz)  
• SMBus  
• I2C Slave  
• SPI  
• 2 UARTs  
• 3-Channel Programmable Counter Array (PWM, Clock Generation, Capture/Compare)  
• 5 16-bit Timers  
• 2 Analog Comparators  
• 12-bit Analog-to-Digital Converter with integrated multiplexer, voltage reference, and temperature sensor  
• 16-bit CRC Unit  
• AEC-Q100 qualified  
• Pre-loaded UART bootloader  
In addition to these features, each part number in the EFM8BB2 family has a set of features that vary across the product line. The  
product selection guide shows the features available on each family member.  
Table 2.1. Product Selection Guide  
EFM8BB22F16G-C-QFN28  
EFM8BB21F16G-C-QSOP24  
EFM8BB21F16G-C-QFN20  
EFM8BB22F16I-C-QFN28  
16  
16  
16  
16  
2304  
2304  
2304  
2304  
22  
21  
16  
22  
20  
20  
15  
20  
10  
10  
10  
10  
12  
12  
7
Yes  
Yes  
Yes  
Yes  
Yes  
—
-40 to +85 ºC  
-40 to +85 ºC  
-40 to +85 ºC  
-40 to +125 ºC  
QFN28  
QSOP24  
QFN20  
QFN28  
—
12  
Yes  
silabs.com | Building a more connected world.  
Rev. 1.4 | 3  
 
EFM8BB2 Data Sheet  
Ordering Information  
EFM8BB21F16I-C-QSOP24  
EFM8BB21F16I-C-QFN20  
EFM8BB22F16A-C-QFN28  
EFM8BB21F16A-C-QFN20  
16  
16  
16  
16  
2304  
2304  
2304  
2304  
21  
16  
22  
16  
20  
15  
20  
15  
10  
10  
10  
10  
12  
7
Yes  
Yes  
Yes  
Yes  
—
—
-40 to +125 ºC  
QSOP24  
QFN20  
QFN28  
QFN20  
-40 to +125 ºC  
-40 to +125 ºC  
-40 to +125 ºC  
12  
7
Yes  
—
The A-grade (i.e. EFM8BB21F16A-C-QFN20) devices receive full automotive quality production status, including AEC-Q100 qualifica-  
tion, registration with International Material Data System (IMDS), and Part Production Approval Process (PPAP) documentation. PPAP  
documentation is available at www.silabs.com with a registered and NDA approved user account.  
silabs.com | Building a more connected world.  
Rev. 1.4 | 4  
Table of Contents  
1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
3. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
3.2 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
3.3 I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
3.4 Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
3.5 Counters/Timers and PWM . . . . . . . . . . . . . . . . . . . . . . . . . 9  
3.6 Communications and Other Digital Peripherals . . . . . . . . . . . . . . . . . . .10  
3.7 Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12  
3.8 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13  
3.9 Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13  
3.10 Bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14  
4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
4.1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .16  
4.1.1 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . .16  
4.1.2 Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . .17  
4.1.3 Reset and Supply Monitor. . . . . . . . . . . . . . . . . . . . . . . .20  
4.1.4 Flash Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . .20  
4.1.5 Power Management Timing . . . . . . . . . . . . . . . . . . . . . . .21  
4.1.6 Internal Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . .21  
4.1.7 External Clock Input. . . . . . . . . . . . . . . . . . . . . . . . . .22  
4.1.8 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23  
4.1.9 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . .24  
4.1.10 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . .25  
4.1.11 1.8 V Internal LDO Voltage Regulator . . . . . . . . . . . . . . . . . . .25  
4.1.12 5 V Voltage Regulator. . . . . . . . . . . . . . . . . . . . . . . . .25  
4.1.13 Comparators. . . . . . . . . . . . . . . . . . . . . . . . . . . .26  
4.1.14 Port I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27  
4.2 Thermal Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .27  
4.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . .28  
4.4 Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . .29  
5. Typical Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . 33  
5.1 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33  
5.2 Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34  
5.3 Other Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . .34  
6. Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35  
6.1 EFM8BB2x-QFN28 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . .35  
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Rev. 1.4 | 5  
6.2 EFM8BB2x-QSOP24 Pin Definitions . . . . . . . . . . . . . . . . . . . . . .39  
6.3 EFM8BB2x-QFN20 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . .42  
7. QFN28 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . . 45  
7.1 QFN28 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . .45  
7.2 QFN28 PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . .47  
7.3 QFN28 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . .48  
8. QSOP24 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . 49  
8.1 QSOP24 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . .49  
8.2 QSOP24 PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . .51  
8.3 QSOP24 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . .52  
9. QFN20 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . . 53  
9.1 QFN20 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . .53  
9.2 QFN20 PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . .55  
9.3 QFN20 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . .56  
10. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57  
10.1 Revision 1.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57  
10.2 Revision 1.31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57  
10.3 Revision 1.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57  
10.4 Revision 1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57  
10.5 Revision 1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57  
10.6 Revision 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58  
10.7 Revision 0.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58  
10.8 Revision 0.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58  
silabs.com | Building a more connected world.  
Rev. 1.4 | 6  
EFM8BB2 Data Sheet  
System Overview  
3. System Overview  
3.1 Introduction  
Port I/O Configuration  
Digital Peripherals  
Debug / Programming  
Hardware  
C2D  
C2CK/RSTb  
Reset  
CIP-51 8051 Controller  
Core  
UART0  
Power-On  
Reset  
UART1  
16 KB ISP Flash  
Program Memory  
Timers 0,  
1, 2, 3, 4  
Port 0  
Drivers  
P0.n  
Supply  
Monitor  
Priority  
Crossbar  
Decoder  
3-ch PCA  
I2C Slave  
256 Byte SRAM  
2048 Byte XRAM  
VDD  
Power  
Net  
Port 1  
Drivers  
I2C /  
SMBus  
P1.n  
P2.n  
P3.n  
Voltage  
Regulators  
VREGIN  
GND  
SPI  
CRC  
Port 2  
Drivers  
SYSCLK  
Independent  
Watchdog Timer  
SFR  
Bus  
Crossbar Control  
Port 3  
Drivers  
Analog Peripherals  
System Clock  
Configuration  
Internal  
Reference  
49 MHz 1.5%  
Oscillator  
VDD  
VREF  
24.5 MHz 2%  
Oscillator  
VDD  
12/10 bit  
ADC  
Temp  
Sensor  
Low-Freq.  
Oscillator  
CMOS Oscillator  
Input  
+
EXTCLK  
+
-
2 Comparators  
Figure 3.1. Detailed EFM8BB2 Block Diagram  
This section describes the EFM8BB2 family at a high level. For more information on each module including register definitions, see the  
EFM8BB2 Reference Manual.  
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Rev. 1.4 | 7  
 
 
EFM8BB2 Data Sheet  
System Overview  
3.2 Power  
All internal circuitry draws power from the VDD supply pin. External I/O pins are powered from the VIO supply voltage (or VDD on devi-  
ces without a separate VIO connection), while most of the internal circuitry is supplied by an on-chip LDO regulator. Control over the  
device power can be achieved by enabling/disabling individual peripherals as needed. Each analog peripheral can be disabled when  
not in use and placed in low power mode. Digital peripherals, such as timers and serial buses, have their clocks gated off and draw little  
power when they are not in use.  
Table 3.1. Power Modes  
Power Mode  
Normal  
Details  
Mode Entry  
Wake-Up Sources  
—
Core and all peripherals clocked and fully operational  
—
Idle  
• Core halted  
Set IDLE bit in PCON0  
Any interrupt  
• All peripherals clocked and fully operational  
• Code resumes execution on wake event  
Suspend  
• Core and peripheral clocks halted  
1. Switch SYSCLK to  
HFOSC0  
• Timer 4 Event  
• HFOSC0 and HFOSC1 oscillators stopped  
• Regulators in normal bias mode for fast wake  
• Timer 3 and 4 may clock from LFOSC0  
• Code resumes execution on wake event  
• SPI0 Activity  
2. Set SUSPEND bit in  
PCON1  
• I2C0 Slave Activity  
• Port Match Event  
• Comparator 0 Falling  
Edge  
Stop  
• All internal power nets shut down  
• 5 V regulator remains active (if enabled)  
• Internal 1.8 V LDO on  
1. Clear STOPCF bit in  
REG0CN  
Any reset source  
2. Set STOP bit in  
PCON0  
• Pins retain state  
• Exit on any reset source  
Snooze  
• Core and peripheral clocks halted  
1. Switch SYSCLK to  
HFOSC0  
• Timer 4 Event  
• HFOSC0 and HFOSC1 oscillators stopped  
• SPI0 Activity  
2. Set SNOOZE bit in  
PCON1  
• Regulators in low bias current mode for energy sav-  
ings  
• I2C0 Slave Activity  
• Port Match Event  
• Timer 3 and 4 may clock from LFOSC0  
• Code resumes execution on wake event  
• Comparator 0 Falling  
Edge  
Shutdown  
• All internal power nets shut down  
• 5 V regulator remains active (if enabled)  
• Internal 1.8 V LDO off to save energy  
• Pins retain state  
1. Set STOPCF bit in  
REG0CN  
• RSTb pin reset  
• Power-on reset  
2. Set STOP bit in  
PCON0  
• Exit on pin or power-on reset  
3.3 I/O  
Digital and analog resources are externally available on the device’s multi-purpose I/O pins. Port pins P0.0-P2.3 can be defined as gen-  
eral-purpose I/O (GPIO), assigned to one of the internal digital resources through the crossbar or dedicated channels, or assigned to an  
analog function. Port pins P3.0 and P3.1 can be used as GPIO. Additionally, the C2 Interface Data signal (C2D) is shared with P3.0.  
The port control block offers the following features:  
• Up to 22 multi-functions I/O pins, supporting digital and analog functions.  
• Flexible priority crossbar decoder for digital peripheral assignment.  
• Two drive strength settings for each port.  
• Two direct-pin interrupt sources with dedicated interrupt vectors (INT0 and INT1).  
• Up to 20 direct-pin interrupt sources with shared interrupt vector (Port Match).  
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Rev. 1.4 | 8  
 
 
EFM8BB2 Data Sheet  
System Overview  
3.4 Clocking  
The CPU core and peripheral subsystem may be clocked by both internal and external oscillator resources. By default, the system  
clock comes up running from the 24.5 MHz oscillator divided by 8.  
The clock control system offers the following features:  
• Provides clock to core and peripherals.  
• 24.5 MHz internal oscillator (HFOSC0), accurate to ±2% over supply and temperature corners.  
• 49 MHz internal oscillator (HFOSC1), accurate to ±1.5% over supply and temperature corners.  
• 80 kHz low-frequency oscillator (LFOSC0).  
• External CMOS clock input (EXTCLK).  
• Clock divider with eight settings for flexible clock scaling:  
• Divide the selected clock source by 1, 2, 4, 8, 16, 32, 64, or 128.  
• HFOSC0 and HFOSC1 include 1.5x pre-scalers for further flexibility.  
3.5 Counters/Timers and PWM  
Programmable Counter Array (PCA0)  
The programmable counter array (PCA) provides multiple channels of enhanced timer and PWM functionality while requiring less CPU  
intervention than standard counter/timers. The PCA consists of a dedicated 16-bit counter/timer and one 16-bit capture/compare mod-  
ule for each channel. The counter/timer is driven by a programmable timebase that has flexible external and internal clocking options.  
Each capture/compare module may be configured to operate independently in one of five modes: Edge-Triggered Capture, Software  
Timer, High-Speed Output, Frequency Output, or Pulse-Width Modulated (PWM) Output. Each capture/compare module has its own  
associated I/O line (CEXn) which is routed through the crossbar to port I/O when enabled.  
• 16-bit time base  
• Programmable clock divisor and clock source selection  
• Up to three independently-configurable channels  
• 8, 9, 10, 11 and 16-bit PWM modes (center or edge-aligned operation)  
• Output polarity control  
• Frequency output mode  
• Capture on rising, falling or any edge  
• Compare function for arbitrary waveform generation  
• Software timer (internal compare) mode  
• Can accept hardware “kill” signal from comparator 0  
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Rev. 1.4 | 9  
 
 
EFM8BB2 Data Sheet  
System Overview  
Timers (Timer 0, Timer 1, Timer 2, Timer 3, and Timer 4)  
Several counter/timers are included in the device: two are 16-bit counter/timers compatible with those found in the standard 8051, and  
the rest are 16-bit auto-reload timers for timing peripherals or for general purpose use. These timers can be used to measure time inter-  
vals, count external events and generate periodic interrupt requests. Timer 0 and Timer 1 are nearly identical and have four primary  
modes of operation. The other timers offer both 16-bit and split 8-bit timer functionality with auto-reload and capture capabilities.  
Timer 0 and Timer 1 include the following features:  
• Standard 8051 timers, supporting backwards-compatibility with firmware and hardware.  
• Clock sources include SYSCLK, SYSCLK divided by 12, 4, or 48, the External Clock divided by 8, or an external pin.  
• 8-bit auto-reload counter/timer mode  
• 13-bit counter/timer mode  
• 16-bit counter/timer mode  
• Dual 8-bit counter/timer mode (Timer 0)  
Timer 2, Timer 3 and Timer 4 are 16-bit timers including the following features:  
• Clock sources for all timers include SYSCLK, SYSCLK divided by 12, or the External Clock divided by 8.  
• LFOSC0 divided by 8 may be used to clock Timer 3 and Timer 4 in active or suspend/snooze power modes.  
• Timer 4 is a low-power wake source, and can be chained together with Timer 3  
• 16-bit auto-reload timer mode  
• Dual 8-bit auto-reload timer mode  
• External pin capture  
• LFOSC0 capture  
• Comparator 0 capture  
Watchdog Timer (WDT0)  
The device includes a programmable watchdog timer (WDT) running off the low-frequency oscillator. A WDT overflow forces the MCU  
into the reset state. To prevent the reset, the WDT must be restarted by application software before overflow. If the system experiences  
a software or hardware malfunction preventing the software from restarting the WDT, the WDT overflows and causes a reset. Following  
a reset, the WDT is automatically enabled and running with the default maximum time interval. If needed, the WDT can be disabled by  
system software or locked on to prevent accidental disabling. Once locked, the WDT cannot be disabled until the next system reset.  
The state of the RST pin is unaffected by this reset.  
The Watchdog Timer has the following features:  
• Programmable timeout interval  
• Runs from the low-frequency oscillator  
• Lock-out feature to prevent any modification until a system reset  
3.6 Communications and Other Digital Peripherals  
Universal Asynchronous Receiver/Transmitter (UART0)  
UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support  
allows a wide range of clock sources to generate standard baud rates. Received data buffering allows UART0 to start reception of a  
second incoming data byte before software has finished reading the previous data byte.  
The UART module provides the following features:  
• Asynchronous transmissions and receptions.  
• Baud rates up to SYSCLK/2 (transmit) or SYSCLK/8 (receive).  
• 8- or 9-bit data.  
• Automatic start and stop generation.  
• Single-byte FIFO on transmit and receive.  
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EFM8BB2 Data Sheet  
System Overview  
Universal Asynchronous Receiver/Transmitter (UART1)  
UART1 is an asynchronous, full duplex serial port offering a variety of data formatting options. A dedicated baud rate generator with a  
16-bit timer and selectable prescaler is included, which can generate a wide range of baud rates. A received data FIFO allows UART1  
to receive multiple bytes before data is lost and an overflow occurs.  
UART1 provides the following features:  
• Asynchronous transmissions and receptions.  
• Dedicated baud rate generator supports baud rates up to SYSCLK/2 (transmit) or SYSCLK/8 (receive).  
• 5, 6, 7, 8, or 9 bit data.  
• Automatic start and stop generation.  
• Automatic parity generation and checking.  
• Four byte FIFO on transmit and receive.  
• Auto-baud detection.  
• LIN break and sync field detection.  
• CTS / RTS hardware flow control.  
Serial Peripheral Interface (SPI0)  
The serial peripheral interface (SPI) module provides access to a flexible, full-duplex synchronous serial bus. The SPI can operate as a  
master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and slaves on a single SPI bus. The slave-select  
(NSS) signal can be configured as an input to select the SPI in slave mode, or to disable master mode operation in a multi-master  
environment, avoiding contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can also be  
configured as a firmware-controlled chip-select output in master mode, or disabled to reduce the number of pins required. Additional  
general purpose port I/O pins can be used to select multiple slave devices in master mode.  
• Supports 3- or 4-wire master or slave modes.  
• Supports external clock frequencies up to 12 Mbps in master or slave mode.  
• Support for all clock phase and polarity modes.  
• 8-bit programmable clock rate (master).  
• Programmable receive timeout (slave).  
• Four byte FIFO on transmit and receive.  
• Can operate in suspend or snooze modes and wake the CPU on reception of a byte.  
• Support for multiple masters on the same data lines.  
System Management Bus / I2C (SMB0)  
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specifica-  
tion, version 1.1, and compatible with the I2C serial bus.  
The SMBus module includes the following features:  
• Standard (up to 100 kbps) and Fast (400 kbps) transfer speeds  
• Support for master, slave, and multi-master modes  
• Hardware synchronization and arbitration for multi-master mode  
• Clock low extending (clock stretching) to interface with faster masters  
• Hardware support for 7-bit slave and general call address recognition  
• Firmware support for 10-bit slave address decoding  
• Ability to inhibit all slave states  
• Programmable data setup/hold times  
• Transmit and receive FIFOs (one byte) to help increase throughput in faster applications  
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EFM8BB2 Data Sheet  
System Overview  
I2C Slave (I2CSLAVE0)  
The I2C Slave interface is a 2-wire, bidirectional serial bus that is compatible with the I2C Bus Specification 3.0. It is capable of transfer-  
ring in high-speed mode (HS-mode) at speeds of up to 3.4 Mbps. Firmware can write to the I2C interface, and the I2C interface can  
autonomously control the serial transfer of data. The interface also supports clock stretching for cases where the core may be tempora-  
rily prohibited from transmitting a byte or processing a received byte during an I2C transaction. This module operates only as an I2C  
slave device.  
The I2C module includes the following features:  
• Standard (up to 100 kbps), Fast (400 kbps), Fast Plus (1 Mbps), and High-speed (3.4 Mbps) transfer speeds  
• Support for slave mode only  
• Clock low extending (clock stretching) to interface with faster masters  
• Hardware support for 7-bit slave address recognition  
• Transmit and receive FIFOs (two bytes) to help increase throughput in faster applications  
16-bit CRC (CRC0)  
The cyclic redundancy check (CRC) module performs a CRC using a 16-bit polynomial. CRC0 accepts a stream of 8-bit data and posts  
the 16-bit result to an internal register. In addition to using the CRC block for data manipulation, hardware can automatically CRC the  
flash contents of the device.  
The CRC module is designed to provide hardware calculations for flash memory verification and communications protocols. The CRC  
module supports the standard CCITT-16 16-bit polynomial (0x1021), and includes the following features:  
• Support for CCITT-16 polynomial  
• Byte-level bit reversal  
• Automatic CRC of flash contents on one or more 256-byte blocks  
• Initial seed selection of 0x0000 or 0xFFFF  
3.7 Analog  
12-Bit Analog-to-Digital Converter (ADC0)  
The ADC is a successive-approximation-register (SAR) ADC with 12-, 10-, and 8-bit modes, integrated track-and hold and a program-  
mable window detector. The ADC is fully configurable under software control via several registers. The ADC may be configured to  
measure different signals using the analog multiplexer. The voltage reference for the ADC is selectable between internal and external  
reference sources.  
• Up to 20 external inputs.  
• Single-ended 12-bit and 10-bit modes.  
• Supports an output update rate of 200 ksps samples per second in 12-bit mode or 800 ksps samples per second in 10-bit mode.  
• Operation in low power modes at lower conversion speeds.  
• Asynchronous hardware conversion trigger, selectable between software, external I/O and internal timer sources.  
• Output data window comparator allows automatic range checking.  
• Support for burst mode, which produces one set of accumulated data per conversion-start trigger with programmable power-on set-  
tling and tracking time.  
• Conversion complete and window compare interrupts supported.  
• Flexible output data formatting.  
• Includes an internal fast-settling reference with two levels (1.65 V and 2.4 V) and support for external reference and signal ground.  
• Integrated temperature sensor.  
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EFM8BB2 Data Sheet  
System Overview  
Low Current Comparators (CMP0, CMP1)  
Analog comparators are used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is higher.  
External input connections to device I/O pins and internal connections are available through separate multiplexers on the positive and  
negative inputs. Hysteresis, response time, and current consumption may be programmed to suit the specific needs of the application.  
The comparator includes the following features:  
• Up to 10 (CMP0) or 12 (CMP1) external positive inputs  
• Up to 10 (CMP0) or 12 (CMP1) external negative inputs  
• Additional input options:  
• Internal connection to LDO output  
• Direct connection to GND  
• Direct connection to VDD  
• Dedicated 6-bit reference DAC  
• Synchronous and asynchronous outputs can be routed to pins via crossbar  
• Programmable hysteresis between 0 and ±20 mV  
• Programmable response time  
• Interrupts generated on rising, falling, or both edges  
• PWM output kill feature  
3.8 Reset Sources  
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur:  
• The core halts program execution.  
• Module registers are initialized to their defined reset values unless the bits reset only with a power-on reset.  
• External port pins are forced to a known state.  
• Interrupts and timers are disabled.  
All registers are reset to the predefined values noted in the register descriptions unless the bits only reset with a power-on reset. The  
contents of RAM are unaffected during a reset; any previously stored data is preserved as long as power is not lost. The Port I/O latch-  
es are reset to 1 in open-drain mode. Weak pullups are enabled during and after the reset. For Supply Monitor and power-on resets,  
the RSTb pin is driven low until the device exits the reset state. On exit from the reset state, the program counter (PC) is reset, and the  
system clock defaults to an internal oscillator. The Watchdog Timer is enabled, and program execution begins at location 0x0000.  
Reset sources on the device include the following:  
• Power-on reset  
• External reset pin  
• Comparator reset  
• Software-triggered reset  
• Supply monitor reset (monitors VDD supply)  
• Watchdog timer reset  
• Missing clock detector reset  
• Flash error reset  
3.9 Debugging  
The EFM8BB2 devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow flash programming and in-system debug-  
ging with the production part installed in the end application. The C2 interface uses a clock signal (C2CK) and a bi-directional C2 data  
signal (C2D) to transfer information between the device and a host system. See the C2 Interface Specification for details on the C2  
protocol.  
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EFM8BB2 Data Sheet  
System Overview  
3.10 Bootloader  
All devices come pre-programmed with a UART bootloader. This bootloader resides in the code security page and last page of code  
flash; it can be erased if it is not needed.  
The byte before the Lock Byte is the Bootloader Signature Byte. Setting this byte to a value of 0xA5 indicates the presence of the boot-  
loader in the system. Any other value in this location indicates that the bootloader is not present in flash.  
When a bootloader is present, the device will jump to the bootloader vector after any reset, allowing the bootloader to run. The boot-  
loader then determines if the device should stay in bootload mode or jump to the reset vector located at 0x0000. When the bootloader  
is not present, the device will jump to the reset vector of 0x0000 after any reset.  
More information about the bootloader protocol and usage can be found in AN945: EFM8 Factory Bootloader User Guide. Application  
notes can be found on the Silicon Labs website (www.silabs.com/8bit-appnotes) or within Simplicity Studio by using the [Application  
Notes] tile.  
0xFFFF  
Read-Only  
0xFFC0  
0xFFBF  
Reserved  
0xFC00  
Lock Byte  
0xFBFF  
Bootloader Signature Byte  
0xFBFE  
Code Security Page  
64 Bytes  
0xFBC0  
Bootloader Vector  
0xFBBF  
Nonvolatile Data  
0xF800  
0xF7FF  
Reserved  
0x4000  
0x3FFF  
16 KB Code  
(32 x 512 Byte pages)  
0x0000  
Reset Vector  
Figure 3.2. Flash Memory Map with Bootloader—16 KB Devices  
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EFM8BB2 Data Sheet  
System Overview  
Table 3.2. Summary of Pins for Bootloader Communication  
Bootloader  
UART  
Pins for Bootload Communication  
TX – P0.4  
RX – P0.5  
Table 3.3. Summary of Pins for Bootload Mode Entry  
Device Package  
QFN28  
Pin for Bootload Mode Entry  
P3.0 / C2D  
QSOP24  
P3.0 / C2D  
QFN20  
P2.0 / C2D  
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Rev. 1.4 | 15  
EFM8BB2 Data Sheet  
Electrical Characteristics  
4. Electrical Characteristics  
4.1 Electrical Characteristics  
All electrical parameters in all tables are specified under the conditions listed in Table 4.1 Recommended Operating Conditions on page  
16, unless stated otherwise.  
4.1.1 Recommended Operating Conditions  
Table 4.1. Recommended Operating Conditions  
Parameter  
Symbol  
Test Condition  
Min  
2.2  
3.0  
Typ  
—
Max  
3.6  
Unit  
V
Operating Supply Voltage on VDD VDD  
Operating Supply Voltage on VRE- VREGIN  
GIN  
—
5.25  
V
System Clock Frequency  
fSYSCLK  
TA  
0
—
—
—
50  
85  
MHz  
°C  
Operating Ambient Temperature  
G-grade devices  
I-grade or A-grade devices  
-40  
-40  
125  
°C  
Note:  
1. All voltages with respect to GND.  
2. GPIO levels are undefined whenever VDD is less than 1 V.  
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EFM8BB2 Data Sheet  
Electrical Characteristics  
4.1.2 Power Consumption  
Table 4.2. Power Consumption  
Test Condition  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
Digital Core Supply Current (G-grade devices, -40 °C to +85 °C)  
FSYSCLK = 49 MHz (HFOSC1)2  
FSYSCLK = 24.5 MHz (HFOSC0)2  
FSYSCLK = 1.53 MHz (HFOSC0)2  
FSYSCLK = 80 kHz3  
Normal Mode-Full speed with code IDD  
executing from flash  
—
—
—
—
—
—
—
—
9.4  
4.5  
10.1  
5.2  
mA  
mA  
μA  
600  
145  
6.3  
900  
410  
6.8  
μA  
FSYSCLK = 49 MHz (HFOSC1)2  
FSYSCLK = 24.5 MHz (HFOSC0)2  
FSYSCLK = 1.53 MHz (HFOSC0)2  
Idle Mode-Core halted with periph- IDD  
erals running  
mA  
mA  
μA  
2.9  
3.3  
440  
130  
750  
420  
FSYSCLK = 80 kHz3  
LFO Running  
μA  
Suspend Mode-Core halted and  
high frequency clocks stopped,  
Supply monitor off.  
IDD  
—
—
125  
120  
400  
390  
μA  
μA  
LFO Stopped  
Snooze Mode-Core halted and IDD  
high frequency clocks stopped.  
Regulator in low-power state, Sup-  
ply monitor off.  
LFO Running  
LFO Stopped  
—
—
25  
20  
300  
290  
μA  
μA  
Stop Mode—Core halted and all  
clocks stopped,Internal LDO On,  
Supply monitor off.  
IDD  
—
—
120  
0.2  
390  
3
μA  
μA  
Shutdown Mode—Core halted and IDD  
all clocks stopped,Internal LDO  
Off, Supply monitor off.  
Digital Core Supply Current (I-grade or A-grade devices, -40 °C to +125 °C)  
FSYSCLK = 49 MHz (HFOSC1)2  
FSYSCLK = 24.5 MHz (HFOSC0)2  
FSYSCLK = 1.53 MHz (HFOSC0)2  
FSYSCLK = 80 kHz3  
Normal Mode-Full speed with code IDD  
executing from flash  
—
—
—
—
—
—
—
—
9.4  
4.5  
10.9  
5.6  
mA  
mA  
μA  
600  
145  
6.3  
1555  
1070  
7.4  
μA  
FSYSCLK = 49 MHz (HFOSC1)2  
FSYSCLK = 24.5 MHz (HFOSC0)2  
FSYSCLK = 1.53 MHz (HFOSC0)2  
Idle Mode-Core halted with periph- IDD  
erals running  
mA  
mA  
μA  
2.9  
3.9  
440  
130  
1400  
1050  
FSYSCLK = 80 kHz3  
LFO Running  
μA  
Suspend Mode-Core halted and  
high frequency clocks stopped,  
Supply monitor off.  
IDD  
—
—
125  
120  
1050  
1045  
μA  
μA  
LFO Stopped  
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EFM8BB2 Data Sheet  
Electrical Characteristics  
Parameter  
Symbol  
Test Condition  
LFO Running  
LFO Stopped  
Min  
—
Typ  
25  
Max  
950  
940  
Unit  
μA  
Snooze Mode-Core halted and IDD  
high frequency clocks stopped.  
Regulator in low-power state, Sup-  
ply monitor off.  
—
20  
μA  
Stop Mode—Core halted and all  
clocks stopped,Internal LDO On,  
Supply monitor off.  
IDD  
—
—
120  
0.2  
1045  
15  
μA  
μA  
Shutdown Mode—Core halted and IDD  
all clocks stopped,Internal LDO  
Off, Supply monitor off.  
Analog Peripheral Supply Currents (-40 °C to +125 °C)  
High-Frequency Oscillator 0  
High-Frequency Oscillator 1  
Low-Frequency Oscillator  
IHFOSC0  
IHFOSC1  
ILFOSC  
IADC  
Operating at 24.5 MHz,  
TA = 25 °C  
—
—
—
—
105  
865  
4
—
940  
—
μA  
μA  
μA  
μA  
Operating at 49 MHz,  
TA = 25 °C  
Operating at 80 kHz,  
TA = 25 °C  
ADC0 Always-on4  
800 ksps, 10-bit conversions or  
200 ksps, 12-bit conversions  
Normal bias settings  
VDD = 3.0 V  
820  
1200  
250 ksps, 10-bit conversions or  
62.5 ksps 12-bit conversions  
Low power bias settings  
VDD = 3.0 V  
—
405  
580  
μA  
ADC0 Burst Mode, 10-bit single  
conversions, external reference  
IADC  
IADC  
IADC  
200 ksps, VDD = 3.0 V  
100 ksps, VDD = 3.0 V  
10 ksps, VDD = 3.0 V  
200 ksps, VDD = 3.0 V  
100 ksps, VDD = 3.0 V  
10 ksps, VDD = 3.0 V  
100 ksps, VDD = 3.0 V  
50 ksps, VDD = 3.0 V  
10 ksps, VDD = 3.0 V  
—
—
—
—
—
—
—
—
—
370  
185  
20  
—
—
—
—
—
—
—
—
—
μA  
μA  
μA  
μA  
μA  
μA  
μA  
μA  
μA  
ADC0 Burst Mode, 10-bit single  
conversions, internal reference,  
Low power bias settings  
485  
245  
25  
ADC0 Burst Mode, 12-bit single  
conversions, external reference  
505  
255  
50  
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EFM8BB2 Data Sheet  
Electrical Characteristics  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
ADC0 Burst Mode, 12-bit single  
conversions, internal reference  
IADC  
100 ksps, VDD = 3.0 V,  
—
950  
—
μA  
Normal bias  
50 ksps, VDD = 3.0 V,  
—
—
415  
80  
—
—
μA  
μA  
Low power bias  
10 ksps, VDD = 3.0 V,  
Low power bias  
Internal ADC0 Reference, Always- IVREFFS  
on5  
Normal Power Mode  
Low Power Mode  
—
—
—
—
—
—
—
—
680  
160  
70  
790  
210  
120  
—
μA  
μA  
μA  
μA  
μA  
μA  
μA  
μA  
Temperature Sensor  
ITSENSE  
ICMP  
Comparator 0 (CMP0, CMP1)  
CPMD = 11  
CPMD = 10  
CPMD = 01  
CPMD = 00  
0.5  
3
—
8.5  
22.5  
1.2  
—
—
Comparator Reference6  
Voltage Supply Monitor (VMON0)  
5V Regulator  
ICPREF  
IVMON  
IVREG  
—
—
—
15  
20  
μA  
μA  
Normal Mode  
245  
340  
(SUSEN = 0, BIASENB = 0)  
Suspend Mode  
—
—
—
60  
2.5  
2.5  
100  
10  
μA  
μA  
nA  
(SUSEN = 1, BIASENB = 0)  
Bias Disabled  
(BIASENB = 1)  
Disabled  
—
(BIASENB = 1, REG1ENB = 1)  
Note:  
1. Currents are additive. For example, where IDD is specified and the mode is not mutually exclusive, enabling the functions increa-  
ses supply current by the specified amount.  
2. Includes supply current from internal LDO regulator, supply monitor, and High Frequency Oscillator.  
3. Includes supply current from internal LDO regulator, supply monitor, and Low Frequency Oscillator.  
4. ADC0 always-on power excludes internal reference supply current.  
5. The internal reference is enabled as-needed when operating the ADC in burst mode to save power.  
6. This value is the current sourced from the pin or supply selected as the full-scale reference to the comparator DAC.  
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EFM8BB2 Data Sheet  
Electrical Characteristics  
4.1.3 Reset and Supply Monitor  
Table 4.3. Reset and Supply Monitor  
Test Condition  
Parameter  
Symbol  
Min  
1.95  
—
Typ  
2.05  
1.2  
—
Max  
2.15  
—
Unit  
V
VDD Supply Monitor Threshold  
VVDDM  
Power-On Reset (POR) Threshold VPOR  
Rising Voltage on VDD  
Falling Voltage on VDD  
Time to VDD > 2.2 V  
V
0.75  
10  
1.36  
—
V
VDD Ramp Time  
tRMP  
tPOR  
—
μs  
ms  
μs  
Reset Delay from POR  
Relative to VDD > VPOR  
3
10  
31  
Reset Delay from non-POR source tRST  
RST Low Time to Generate Reset tRSTL  
Time between release of reset  
source and code execution  
—
50  
—
15  
—
—
—
μs  
Missing Clock Detector Response tMCD  
Time (final rising edge to reset)  
FSYSCLK >1 MHz  
0.625  
1.2  
ms  
Missing Clock Detector Trigger  
Frequency  
FMCD  
—
—
7.5  
2
13.5  
—
kHz  
μs  
VDD Supply Monitor Turn-On Time tMON  
4.1.4 Flash Memory  
Table 4.4. Flash Memory  
Parameter  
Write Time1 ,2  
Symbol  
Test Condition  
One Byte,  
Min  
Typ  
Max  
Units  
tWRITE  
tERASE  
VPROG  
19  
20  
21  
μs  
FSYSCLK = 24.5 MHz  
One Page,  
Erase Time1 ,2  
5.2  
5.35  
5.5  
ms  
FSYSCLK = 24.5 MHz  
VDD Voltage During Programming3  
Endurance (Write/Erase Cycles)  
CRC Calculation Time  
2.2  
—
3.6  
V
NWE  
tCRC  
20k  
—
100k  
5.5  
—
—
Cycles  
µs  
One 256-Byte Block  
SYSCLK = 49 MHz  
Note:  
1. Does not include sequencing time before and after the write/erase operation, which may be multiple SYSCLK cycles.  
2. The internal High-Frequency Oscillator 0 has a programmable output frequency, which is factory programmed to 24.5 MHz. If  
user firmware adjusts the oscillator speed, it must be between 22 and 25 MHz during any flash write or erase operation. It is  
recommended to write the HFO0CAL register back to its reset value when writing or erasing flash.  
3. Flash can be safely programmed at any voltage above the supply monitor threshold (VVDDM).  
4. Data Retention Information is published in the Quarterly Quality and Reliability Report.  
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EFM8BB2 Data Sheet  
Electrical Characteristics  
4.1.5 Power Management Timing  
Table 4.5. Power Management Timing  
Test Condition  
Parameter  
Symbol  
Min  
2
Typ  
—
Max  
3
Units  
SYSCLKs  
ns  
Idle Mode Wake-up Time  
Suspend Mode Wake-up Time  
tIDLEWK  
tSUS-  
SYSCLK = HFOSC0  
CLKDIV = 0x00  
—
170  
—
PENDWK  
Snooze Mode Wake-up Time  
tSLEEPWK SYSCLK = HFOSC0  
CLKDIV = 0x00  
—
12  
—
µs  
4.1.6 Internal Oscillators  
Table 4.6. Internal Oscillators  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
High Frequency Oscillator 0 (24.5 MHz)  
Oscillator Frequency  
fHFOSC0  
Full Temperature and Supply  
Range  
24  
—
24.5  
0.5  
25  
—
MHz  
%/V  
Power Supply Sensitivity  
PSSHFOS TA = 25 °C  
C0  
Temperature Sensitivity  
TSHFOSC0 VDD = 3.0 V  
—
40  
—
ppm/°C  
High Frequency Oscillator 1 (49 MHz)  
Oscillator Frequency  
fHFOSC1  
Full Temperature and Supply  
Range  
48.25  
—
49  
49.75  
—
MHz  
%/V  
Power Supply Sensitivity  
PSSHFOS TA = 25 °C  
0.02  
C1  
Temperature Sensitivity  
TSHFOSC1 VDD = 3.0 V  
—
45  
80  
—
ppm/°C  
kHz  
Low Frequency Oscillator (80 kHz)  
Oscillator Frequency  
fLFOSC  
Full Temperature and Supply  
Range  
75  
85  
Power Supply Sensitivity  
Temperature Sensitivity  
PSSLFOSC TA = 25 °C  
TSLFOSC VDD = 3.0 V  
—
—
0.05  
65  
—
—
%/V  
ppm/°C  
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Rev. 1.4 | 21  
 
 
EFM8BB2 Data Sheet  
Electrical Characteristics  
4.1.7 External Clock Input  
Table 4.7. External Clock Input  
Test Condition  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
External Input CMOS Clock  
Frequency (at EXTCLK pin)  
fCMOS  
0
—
50  
MHz  
External Input CMOS Clock High  
Time  
tCMOSH  
9
9
—
—
—
—
ns  
ns  
External Input CMOS Clock Low  
Time  
tCMOSL  
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EFM8BB2 Data Sheet  
Electrical Characteristics  
4.1.8 ADC  
Table 4.8. ADC  
Test Condition  
Parameter  
Symbol  
Min  
Typ  
12  
10  
—
—
—
—
—
—
—
—
Max  
Unit  
Bits  
Bits  
ksps  
ksps  
ksps  
ksps  
ns  
Resolution  
Nbits  
12 Bit Mode  
10 Bit Mode  
Throughput Rate  
(High Speed Mode)  
Throughput Rate  
(Low Power Mode)  
Tracking Time  
fS  
12 Bit Mode  
—
—
200  
800  
62.5  
250  
—
10 Bit Mode  
fS  
12 Bit Mode  
—
10 Bit Mode  
—
tTRK  
High Speed Mode  
Low Power Mode  
230  
450  
1.2  
—
—
ns  
Power-On Time  
tPWR  
fSAR  
—
μs  
SAR Clock Frequency  
High Speed Mode,  
Reference is 2.4 V internal  
High Speed Mode,  
Reference is not 2.4 V internal  
Low Power Mode  
6.25  
MHz  
—
—
—
12.5  
4
MHz  
—
MHz  
μs  
Conversion Time  
tCNV  
10-Bit Conversion,  
SAR Clock = 12.25 MHz,  
System Clock = 24.5 MHz.  
Gain = 1  
1.1  
Sample/Hold Capacitor  
CSAR  
—
—
—
—
1
5
2.5  
20  
550  
—
—
—
pF  
pF  
pF  
Ω
Gain = 0.5  
Input Pin Capacitance  
Input Mux Impedance  
Voltage Reference Range  
CIN  
—
RMUX  
VREF  
VIN  
—
VDD  
VREF  
2xVREF  
—
V
Input Voltage Range1  
Gain = 1  
0
—
V
Gain = 0.5  
0
—
V
Power Supply Rejection Ratio  
DC Performance  
PSRRADC  
INL  
—
70  
dB  
Integral Nonlinearity  
12 Bit Mode  
—
—
-1  
—
-3  
-2  
—
±1  
±0.2  
±0.7  
±0.2  
0
±2.3  
±0.6  
1.9  
±0.6  
3
LSB  
LSB  
10 Bit Mode  
Differential Nonlinearity (Guaran-  
teed Monotonic)  
DNL  
12 Bit Mode  
LSB  
10 Bit Mode  
LSB  
Offset Error  
EOFF  
12 Bit Mode, VREF = 1.65 V  
10 Bit Mode, VREF = 1.65 V  
LSB  
0
2
LSB  
Offset Temperature Coefficient  
TCOFF  
0.004  
—
LSB/°C  
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EFM8BB2 Data Sheet  
Electrical Characteristics  
Parameter  
Symbol  
Test Condition  
12 Bit Mode  
10 Bit Mode  
Min  
—
Typ  
Max  
±0.1  
Unit  
%
Slope Error  
EM  
±0.02  
±0.06  
—
±0.24  
%
Dynamic Performance 10 kHz Sine Wave Input 1 dB below full scale, Max throughput, using AGND pin  
Signal-to-Noise  
SNR  
12 Bit Mode  
10 Bit Mode  
12 Bit Mode  
10 Bit Mode  
12 Bit Mode  
10 Bit Mode  
12 Bit Mode  
10 Bit Mode  
61  
53  
61  
53  
—
—
—
—
66  
60  
66  
60  
71  
70  
-79  
-70  
—
—
—
—
—
—
—
—
dB  
dB  
dB  
dB  
dB  
dB  
dB  
dB  
Signal-to-Noise Plus Distortion  
SNDR  
THD  
Total Harmonic Distortion (Up to  
5th Harmonic)  
Spurious-Free Dynamic Range  
SFDR  
Note:  
1. Absolute input pin voltage is limited by the VDD supply.  
4.1.9 Voltage Reference  
Table 4.9. Voltage Reference  
Parameter  
Internal Fast Settling Reference  
Output Voltage  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
VREFFS  
1.65 V Setting  
1.62  
2.35  
1.65  
2.4  
1.68  
2.45  
V
V
2.4 V Setting, VDD > 2.6 V  
(Full Temperature and Supply  
Range)  
Temperature Coefficient  
Turn-on Time  
TCREFFS  
tREFFS  
—
—
—
50  
—
—
1.5  
—
ppm/°C  
μs  
Power Supply Rejection  
PSRRREF  
400  
ppm/V  
FS  
External Reference  
Input Current  
IEXTREF  
Sample Rate = 800 ksps; VREF =  
3.0 V  
—
8
—
μA  
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EFM8BB2 Data Sheet  
Electrical Characteristics  
4.1.10 Temperature Sensor  
Table 4.10. Temperature Sensor  
Parameter  
Symbol  
VOFF  
Test Condition  
TA = 0 °C  
Min  
—
Typ  
757  
17  
Max  
—
Unit  
mV  
mV  
Offset  
Offset Error1  
Slope  
EOFF  
TA = 0 °C  
—
—
M
—
—
2.85  
70  
—
—
mV/°C  
μV/°  
Slope Error1  
Linearity  
EM  
—
—
0.5  
1.8  
—
—
°C  
μs  
Turn-on Time  
Note:  
1. Represents one standard deviation from the mean.  
4.1.11 1.8 V Internal LDO Voltage Regulator  
Table 4.11. 1.8V Internal LDO Voltage Regulator  
Parameter  
Output Voltage  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
VOUT_1.8V  
1.78  
1.85  
1.92  
V
4.1.12 5 V Voltage Regulator  
Table 4.12. 5V Voltage Regulator  
Test Condition  
Parameter  
Input Voltage Range1  
Output Voltage on VDD2  
Symbol  
Min  
Typ  
Max  
Unit  
VREGIN  
3.0  
—
5.25  
V
VREGOUT Output Current = 1 to 100 mA  
3.1  
—
3.3  
3.6  
—
V
V
Regulation range (VREGIN ≥ 4.1  
V)  
Output Current = 1 to 100 mA  
Dropout range (VREGIN < 4.1 V)  
IREGOUT  
VREGIN –  
VDROPOUT  
Output Current2  
Dropout Voltage  
Note:  
—
—
—
—
100  
0.8  
mA  
V
VDROPOUT Output Current = 100 mA  
1. Input range to meet the Output Voltage on VDD specification. If the 5V voltage regulator is not used, VREGIN should be tied to  
VDD.  
2. Output current is total regulator output, including any current required by the device.  
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EFM8BB2 Data Sheet  
Electrical Characteristics  
4.1.13 Comparators  
Table 4.13. Comparators  
Parameter  
Symbol  
Test Condition  
+100 mV Differential, VCM = 1.65 V  
-100 mV Differential, VCM = 1.65 V  
+100 mV Differential, VCM = 1.65 V  
-100 mV Differential, VCM = 1.65 V  
CPHYP = 00  
Min  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-0.25  
—
Typ  
110  
160  
1.2  
4.5  
0.4  
8
Max  
—
Unit  
ns  
Response Time, CPMD = 00  
(Highest Speed)  
tRESP0  
—
ns  
Response Time, CPMD = 11 (Low- tRESP3  
est Power)  
—
μs  
—
μs  
Positive Hysteresis  
HYSCP+  
HYSCP-  
HYSCP+  
HYSCP-  
—
mV  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
V
CPHYP = 01  
—
Mode 0 (CPMD = 00)  
CPHYP = 10  
16  
32  
-0.4  
-8  
—
CPHYP = 11  
—
Negative Hysteresis  
Mode 0 (CPMD = 00)  
CPHYN = 00  
—
CPHYN = 01  
—
CPHYN = 10  
-16  
-32  
1.5  
4
—
CPHYN = 11  
—
Positive Hysteresis  
CPHYP = 00  
—
CPHYP = 01  
—
Mode 3 (CPMD = 11)  
CPHYP = 10  
8
—
CPHYP = 11  
16  
-1.5  
-4  
—
Negative Hysteresis  
Mode 3 (CPMD = 11)  
CPHYN = 00  
—
CPHYN = 01  
—
CPHYN = 10  
-8  
—
CPHYN = 11  
-16  
—
—
Input Range (CP+ or CP-)  
Input Pin Capacitance  
VIN  
VDD+0.25  
—
CCP  
7.5  
6
pF  
Internal Reference DAC Resolution Nbits  
bits  
dB  
Common-Mode Rejection Ratio  
Power Supply Rejection Ratio  
Input Offset Voltage  
CMRRCP  
—
—
70  
72  
0
—
—
10  
—
PSRRCP  
VOFF  
dB  
TA = 25 °C  
-10  
—
mV  
μV/°  
Input Offset Tempco  
TCOFF  
3.5  
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EFM8BB2 Data Sheet  
Electrical Characteristics  
4.1.14 Port I/O  
Table 4.14. Port I/O  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
—
Max  
Unit  
V
Output High Voltage (High Drive)1  
Output Low Voltage (High Drive)1  
Output High Voltage (Low Drive)1  
VOH  
IOH = -7 mA, VDD ≥ 3.0 V  
VDD - 0.7  
—
—
IOH = -3.3 mA, 2.2 V ≤ VDD < 3.0 V VDD x 0.8  
—
V
VOL  
IOL = 13.5 mA, VDD ≥ 3.0 V  
IOL = 7 mA, 2.2 V ≤ VDD < 3.0 V  
IOH = -4.75 mA, VDD ≥ 3.0 V  
—
—
0.6  
V
—
—
VDD x 0.2  
—
V
VOH  
VDD - 0.7  
VDD x 0.8  
—
V
IOH = -2.25 mA, 2.2 V ≤ VDD < 3.0  
V
—
—
V
Output Low Voltage (Low Drive)1  
VOL  
IOL = 6.5 mA, VDD ≥ 3.0 V  
—
—
—
—
—
—
7
0.6  
VDD x 0.2  
—
V
V
IOL = 3.5 mA, 2.2 V ≤ VDD < 3.0 V  
Input High Voltage  
Input Low Voltage  
Pin Capacitance  
Weak Pull-Up Current  
(VIN = 0 V)  
VIH  
VIL  
CIO  
IPU  
VDD - 0.6  
—
V
0.6  
V
—
—
pF  
μA  
VDD = 3.6  
-30  
-20  
-10  
Input Leakage (Pullups off or Ana- ILK  
log)  
GND < VIN < VDD  
-1.1  
0
—
5
1.1  
μA  
μA  
Input Leakage Current with VIN  
above VDD  
ILK  
VDD < VIN < VDD+2.0 V  
150  
Note:  
1. See Figure 4.6 Typical VOH Curves on page 32 and Figure 4.7 Typical VOL Curves on page 32 for more information.  
4.2 Thermal Conditions  
Table 4.15. Thermal Conditions  
Parameter  
Symbol  
Test Condition  
QFN-20 Packages  
Min  
─
Typ  
60  
Max  
─
Unit  
°C/W  
°C/W  
°C/W  
°C/W  
Thermal Resistance (Junction to  
Ambient)  
θJA  
QFN-28 Packages  
QSOP-24 Packages  
QFN-20 Packages  
─
26  
─
─
65  
─
Thermal Resistance (Junction to  
Case)  
θJC  
─
28.86  
─
Note:  
1. Thermal resistance assumes a multi-layer PCB with any exposed pad soldered to a PCB pad.  
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EFM8BB2 Data Sheet  
Electrical Characteristics  
4.3 Absolute Maximum Ratings  
Stresses above those listed in Table 4.16 Absolute Maximum Ratings on page 28 may cause permanent damage to the device. This  
is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation  
listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. For  
more information on the available quality and reliability data, see the Quality and Reliability Monitor Report at http://www.silabs.com/  
support/quality/pages/default.aspx.  
Table 4.16. Absolute Maximum Ratings  
Parameter  
Ambient Temperature Under Bias  
Storage Temperature  
Symbol  
TBIAS  
TSTG  
VDD  
Test Condition  
Min  
-55  
Max  
125  
Unit  
°C  
°C  
V
-65  
150  
Voltage on VDD  
GND-0.3  
GND-0.3  
GND-0.3  
GND-0.3  
─
4.2  
Voltage on VREGIN  
VREGIN  
VIN  
5.8  
V
Voltage on I/O pins or RSTb  
VDD > 3.3 V  
VDD < 3.3 V  
5.8  
V
VDD+2.5  
200  
V
Total Current Sunk into Supply Pin  
IVDD  
IGND  
mA  
mA  
Total Current Sourced out of Ground  
Pin  
200  
─
Current Sourced or Sunk by any I/O  
Pin or RSTb  
IIO  
TJ  
-100  
100  
mA  
Operating Junction Temperature  
TA = -40 °C to 85 °C  
–40  
-40  
105  
130  
°C  
°C  
TA = -40 °C to 125 °C (I-grade or A-  
grade parts only)  
Note:  
1. Exposure to maximum rating conditions for extended periods may affect device reliability.  
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EFM8BB2 Data Sheet  
Electrical Characteristics  
4.4 Typical Performance Curves  
Figure 4.1. Typical Operating Supply Current using HFOSC0  
Figure 4.2. Typical Operating Supply Current using HFOSC1  
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EFM8BB2 Data Sheet  
Electrical Characteristics  
Figure 4.3. Typical Operating Supply Current using LFOSC  
Figure 4.4. Typical ADC0 and Internal Reference Supply Current in Burst Mode  
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EFM8BB2 Data Sheet  
Electrical Characteristics  
Figure 4.5. Typical ADC0 Supply Current in Normal (always-on) Mode  
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EFM8BB2 Data Sheet  
Electrical Characteristics  
Figure 4.6. Typical VOH Curves  
Figure 4.7. Typical VOL Curves  
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EFM8BB2 Data Sheet  
Typical Connection Diagrams  
5. Typical Connection Diagrams  
5.1 Power  
Figure 5.1 Connection Diagram with Voltage Regulator Used on page 33 shows a typical connection diagram for the power pins of  
the EFM8BB2 devices when the 5 V-to-3.3 V regulator is in use.  
EFM8BB2 Device  
2.7-5.25 V (in)  
Voltage  
Regulator  
VREGIN  
VDD  
3.3 V (out)  
4.7 µF and 0.1 µF bypass  
capacitors required for  
each power pin placed as  
close to the pins as  
possible.  
GND  
Figure 5.1. Connection Diagram with Voltage Regulator Used  
Figure 5.2 Connection Diagram with Voltage Regulator Not Used on page 33 shows a typical connection diagram for the power pins  
of the EFM8BB2 devices when the internal 5 V-to-3.3 V regulator is not used.  
EFM8BB2 Device  
2.2-3.6 V (in)  
Voltage  
Regulator  
VREGIN  
VDD  
4.7 µF and 0.1 µF bypass  
capacitors required for  
each power pin placed as  
close to the pins as  
possible.  
GND  
Figure 5.2. Connection Diagram with Voltage Regulator Not Used  
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EFM8BB2 Data Sheet  
Typical Connection Diagrams  
5.2 Debug  
The diagram below shows a typical connection diagram for the debug connections pins. The pin sharing resistors are only required if  
the functionality on the C2D (a GPIO pin) and the C2CK (RSTb) is routed to external circuitry. For example, if the RSTb pin is connec-  
ted to an external switch with debouncing filter or if the GPIO sharing with the C2D pin is connected to an external circuit, the pin shar-  
ing resistors and connections to the debug adapter must be placed on the hardware. Otherwise, these components and connections  
can be omitted.  
For more information on debug connections, see the example schematics and information available in AN124: Pin Sharing Techniques  
for the C2 Interface. Application notes can be found on the Silicon Labs website (http://www.silabs.com/8bit-appnotes) or in Simplicity  
Studio.  
VDD  
External  
System  
EFM8BB2 Device  
1 k  
C2CK  
1 k  
1 k  
1 k  
(if pin sharing)  
(if pin sharing)  
C2D  
1 k  
GND  
Debug Adapter  
Figure 5.3. Debug Connection Diagram  
5.3 Other Connections  
Other components or connections may be required to meet the system-level requirements. Application note, "AN203: 8-bit MCU Printed  
Circuit Board Design Notes", contains detailed information on these connections. Application Notes can be accessed on the Silicon  
Labs website (www.silabs.com/8bit-appnotes).  
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EFM8BB2 Data Sheet  
Pin Definitions  
6. Pin Definitions  
6.1 EFM8BB2x-QFN28 Pin Definitions  
1
2
3
4
5
6
7
21  
20  
19  
18  
17  
16  
15  
P0.1  
P0.0  
P1.1  
P1.2  
P1.3  
P1.4  
P1.5  
P1.6  
P1.7  
GND  
28 pin QFN  
N/C  
(Top View)  
N/C  
VDD  
GND  
VREGIN  
Figure 6.1. EFM8BB2x-QFN28 Pinout  
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EFM8BB2 Data Sheet  
Pin Definitions  
Table 6.1. Pin Definitions for EFM8BB2x-QFN28  
Pin  
Pin Name  
Description  
Crossbar Capability  
Additional Digital  
Analog Functions  
Functions  
Number  
1
P0.1  
Multifunction I/O  
Multifunction I/O  
Yes  
P0MAT.1  
INT0.1  
ADC0.1  
CMP0P.1  
CMP0N.1  
AGND  
INT1.1  
2
P0.0  
Yes  
P0MAT.0  
INT0.0  
ADC0.0  
CMP0P.0  
CMP0N.0  
VREF  
INT1.0  
3
4
5
6
GND  
N/C  
Ground  
No Connection  
N/C  
No Connection  
VDD  
Supply Power Input /  
5V Regulator Output  
5V Regulator Input  
Multifunction I/O  
Active-low Reset /  
C2 Debug Clock  
Multifunction I/O /  
C2 Debug Data  
Multifunction I/O  
7
8
9
VREGIN  
P3.1  
RST /  
C2CK  
P3.0 /  
C2D  
10  
11  
P2.3  
Yes  
Yes  
Yes  
Yes  
Yes  
P2MAT.3  
P2MAT.2  
P2MAT.1  
P2MAT.0  
P1MAT.7  
ADC0.23  
CP1P.12  
CP1N.12  
ADC0.22  
CP1P.11  
CP1N.11  
ADC0.21  
CP1P.10  
CP1N.10  
ADC0.20  
CP1P.9  
12  
13  
14  
15  
P2.2  
P2.1  
P2.0  
P1.7  
Multifunction I/O  
Multifunction I/O  
Multifunction I/O  
Multifunction I/O  
CP1N.9  
ADC0.15  
CP1P.7  
CP1N.7  
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EFM8BB2 Data Sheet  
Pin Definitions  
Pin  
Pin Name  
Description  
Crossbar Capability  
Additional Digital  
Functions  
Analog Functions  
Number  
16  
P1.6  
Multifunction I/O  
Yes  
P1MAT.6  
ADC0.14  
CP1P.6  
I2C0_SCL  
CP1N.6  
ADC0.13  
CP1P.5  
17  
18  
19  
20  
21  
P1.5  
P1.4  
P1.3  
P1.2  
P1.1  
Multifunction I/O  
Multifunction I/O  
Multifunction I/O  
Multifunction I/O  
Multifunction I/O  
Yes  
Yes  
Yes  
Yes  
Yes  
P1MAT.5  
I2C0_SDA  
CP1N.5  
ADC0.12  
CP1P.4  
P1MAT.4  
P1MAT.3  
P1MAT.2  
P1MAT.1  
CP1N.4  
ADC0.11  
CP1P.3  
CP1N.3  
ADC0.10  
CP1P.2  
CP1N.2  
ADC0.9  
CP1P.1  
CP1N.1  
CMP0P.10  
CMP0N.10  
ADC0.8  
CP1P.0  
22  
P1.0  
Multifunction I/O  
Yes  
P1MAT.0  
CP1N.0  
CMP0P.9  
CMP0N.9  
ADC0.7  
CMP0P.7  
CMP0N.7  
ADC0.6  
CMP0P.6  
CMP0N.6  
23  
24  
P0.7  
P0.6  
Multifunction I/O  
Multifunction I/O  
Yes  
Yes  
P0MAT.7  
INT0.7  
INT1.7  
P0MAT.6  
CNVSTR  
INT0.6  
INT1.6  
25  
P0.5  
Multifunction I/O  
Yes  
P0MAT.5  
INT0.5  
ADC0.5  
CMP0P.5  
CMP0N.5  
INT1.5  
UART0_RX  
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EFM8BB2 Data Sheet  
Pin Definitions  
Pin  
Pin Name  
Description  
Crossbar Capability  
Additional Digital  
Functions  
Analog Functions  
Number  
26  
P0.4  
Multifunction I/O  
Yes  
P0MAT.4  
INT0.4  
ADC0.4  
CMP0P.4  
CMP0N.4  
INT1.4  
UART0_TX  
P0MAT.3  
EXTCLK  
INT0.3  
27  
P0.3  
Multifunction I/O  
Yes  
Yes  
ADC0.3  
CMP0P.3  
CMP0N.3  
INT1.3  
28  
P0.2  
GND  
Multifunction I/O  
Ground  
P0MAT.2  
INT0.2  
ADC0.2  
CMP0P.2  
CMP0N.2  
INT1.2  
Center  
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EFM8BB2 Data Sheet  
Pin Definitions  
6.2 EFM8BB2x-QSOP24 Pin Definitions  
1
2
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
P0.3  
P0.2  
P0.1  
P0.0  
GND  
P0.4  
P0.5  
P0.6  
P0.7  
P1.0  
P1.1  
P1.2  
P1.3  
P1.4  
P1.5  
3
4
5
6
24 pin QSOP  
VDD  
(Top View)  
7
RSTb / C2CK  
8
P3.0 / C2D  
P2.3  
9
10  
11  
12  
P2.2  
P2.1  
P1.6  
P1.7  
P2.0  
Figure 6.2. EFM8BB2x-QSOP24 Pinout  
Table 6.2. Pin Definitions for EFM8BB2x-QSOP24  
Pin  
Pin Name  
Description  
Crossbar Capability  
Additional Digital  
Functions  
Analog Functions  
Number  
1
P0.3  
Multifunction I/O  
Yes  
P0MAT.3  
EXTCLK  
INT0.3  
ADC0.3  
CMP0P.3  
CMP0N.3  
INT1.3  
2
P0.2  
Multifunction I/O  
Yes  
P0MAT.2  
INT0.2  
ADC0.2  
CMP0P.2  
CMP0N.2  
INT1.2  
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EFM8BB2 Data Sheet  
Pin Definitions  
Pin  
Pin Name  
Description  
Crossbar Capability  
Additional Digital  
Functions  
Analog Functions  
Number  
3
P0.1  
Multifunction I/O  
Yes  
P0MAT.1  
INT0.1  
ADC0.1  
CMP0P.1  
CMP0N.1  
AGND  
INT1.1  
4
P0.0  
Multifunction I/O  
Yes  
P0MAT.0  
INT0.0  
ADC0.0  
CMP0P.0  
CMP0N.0  
VREF  
INT1.0  
5
6
7
GND  
VDD  
Ground  
Supply Power Input  
Active-low Reset /  
C2 Debug Clock  
Multifunction I/O /  
C2 Debug Data  
Multifunction I/O  
RSTb /  
C2CK  
P3.0 /  
C2D  
8
9
P2.3  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
P2MAT.3  
P2MAT.2  
P2MAT.1  
P2MAT.0  
P1MAT.7  
ADC0.23  
CMP1P.12  
CMP1N.12  
ADC0.22  
CMP1P.11  
CMP1N.11  
ADC0.21  
CMP1P.10  
CMP1N.10  
ADC0.20  
CMP1P.9  
CMP1N.9  
ADC0.15  
CMP1P.7  
CMP1N.7  
ADC0.14  
CMP1P.6  
CMP1N.6  
ADC0.13  
CMP1P.5  
CMP1N.5  
10  
11  
12  
13  
14  
15  
P2.2  
P2.1  
P2.0  
P1.7  
P1.6  
P1.5  
Multifunction I/O  
Multifunction I/O  
Multifunction I/O  
Multifunction I/O  
Multifunction I/O  
Multifunction I/O  
P1MAT.6  
I2C0_SCL  
P1MAT.5  
I2C0_SDA  
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EFM8BB2 Data Sheet  
Pin Definitions  
Pin  
Pin Name  
Description  
Crossbar Capability  
Additional Digital  
Functions  
Analog Functions  
Number  
16  
P1.4  
Multifunction I/O  
Yes  
P1MAT.4  
P1MAT.3  
P1MAT.2  
P1MAT.1  
ADC0.12  
CMP1P.4  
CMP1N.4  
ADC0.11  
CMP1P.3  
CMP1N.3  
ADC0.10  
CMP1P.2  
CMP1N.2  
ADC0.9  
17  
18  
19  
P1.3  
P1.2  
P1.1  
Multifunction I/O  
Multifunction I/O  
Multifunction I/O  
Yes  
Yes  
Yes  
CMP1P.1  
CMP1N.1  
CMP0P.10  
CMP0N.10  
ADC0.8  
20  
P1.0  
Multifunction I/O  
Yes  
P1MAT.0  
CMP1P.0  
CMP1N.0  
CMP0P.9  
CMP0N.9  
ADC0.7  
21  
22  
P0.7  
P0.6  
Multifunction I/O  
Multifunction I/O  
Yes  
Yes  
P0MAT.7  
INT0.7  
CMP0P.7  
CMP0N.7  
ADC0.6  
INT1.7  
P0MAT.6  
CNVSTR  
INT0.6  
CMP0P.6  
CMP0N.6  
INT1.6  
23  
24  
P0.5  
P0.4  
Multifunction I/O  
Multifunction I/O  
Yes  
Yes  
P0MAT.5  
INT0.5  
ADC0.5  
CMP0P.5  
CMP0N.5  
INT1.5  
UART0_RX  
P0MAT.4  
INT0.4  
ADC0.4  
CMP0P.4  
CMP0N.4  
INT1.4  
UART0_TX  
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EFM8BB2 Data Sheet  
Pin Definitions  
6.3 EFM8BB2x-QFN20 Pin Definitions  
1
16  
P0.1  
P0.0  
P0.6  
P0.7  
P1.0  
P1.1  
GND  
P1.2  
2
3
4
5
15  
14  
13  
12  
GND  
20 pin QFN  
(Top View)  
VDD  
GND  
RSTb / C2CK  
P2.0 / C2D  
6
11  
Figure 6.3. EFM8BB2x-QFN20 Pinout  
Table 6.3. Pin Definitions for EFM8BB2x-QFN20  
Pin  
Pin Name  
Description  
Crossbar Capability  
Additional Digital  
Analog Functions  
Functions  
Number  
1
P0.1  
Multifunction I/O  
Multifunction I/O  
Yes  
P0MAT.1  
INT0.1  
ADC0.1  
CMP0P.1  
CMP0N.1  
AGND  
INT1.1  
2
P0.0  
Yes  
P0MAT.0  
INT0.0  
ADC0.0  
CMP0P.0  
CMP0N.0  
VREF  
INT1.0  
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EFM8BB2 Data Sheet  
Pin Definitions  
Pin  
Pin Name  
Description  
Crossbar Capability  
Additional Digital  
Functions  
Analog Functions  
Number  
3
4
5
GND  
VDD  
Ground  
Supply Power Input  
Active-low Reset /  
C2 Debug Clock  
Multifunction I/O /  
C2 Debug Data  
Multifunction I/O  
RSTb /  
C2CK  
P2.0 /  
C2D  
6
7
Yes  
Yes  
P1.6  
P1MAT.6  
P1MAT.5  
P1MAT.4  
ADC0.14  
CMP1P.6  
CMP1N.6  
ADC0.13  
CMP1P.5  
CMP1N.5  
ADC0.12  
CMP1P.4  
CMP1N.4  
ADC0.11  
CMP1P.3  
CMP1N.3  
ADC0.10  
CMP1P.2  
CMP1N.2  
8
P1.5  
P1.4  
P1.3  
P1.2  
Multifunction I/O  
Multifunction I/O  
Multifunction I/O  
Multifunction I/O  
Yes  
Yes  
Yes  
Yes  
9
10  
11  
P1MAT.3  
I2C0_SCL  
P1MAT.2  
I2C0_SDA  
12  
13  
GND  
P1.1  
Ground  
Multifunction I/O  
Yes  
Yes  
Yes  
P1MAT.1  
ADC0.9  
CMP1P.1  
CMP1N.1  
CMP0P.10  
CMP0N.10  
ADC0.8  
14  
P1.0  
Multifunction I/O  
P1MAT.0  
CMP1P.0  
CMP1N.0  
CMP0P.9  
CMP0N.9  
ADC0.7  
15  
P0.7  
Multifunction I/O  
P0MAT.7  
INT0.7  
CMP0P.7  
CMP0N.7  
INT1.7  
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EFM8BB2 Data Sheet  
Pin Definitions  
Pin  
Pin Name  
Description  
Crossbar Capability  
Additional Digital  
Functions  
Analog Functions  
Number  
16  
P0.6  
Multifunction I/O  
Yes  
P0MAT.6  
CNVSTR  
INT0.6  
ADC0.6  
CMP0P.6  
CMP0N.6  
INT1.6  
17  
18  
19  
P0.5  
P0.4  
P0.3  
Multifunction I/O  
Multifunction I/O  
Multifunction I/O  
Yes  
Yes  
Yes  
Yes  
P0MAT.5  
INT0.5  
ADC0.5  
CMP0P.5  
CMP0N.5  
INT1.5  
UART0_RX  
P0MAT.4  
INT0.4  
ADC0.4  
CMP0P.4  
CMP0N.4  
INT1.4  
UART0_TX  
P0MAT.3  
EXTCLK  
INT0.3  
ADC0.3  
CMP0P.3  
CMP0N.3  
INT1.3  
20  
P0.2  
GND  
Multifunction I/O  
Ground  
P0MAT.2  
INT0.2  
ADC0.2  
CMP0P.2  
CMP0N.2  
INT1.2  
Center  
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EFM8BB2 Data Sheet  
QFN28 Package Specifications  
7. QFN28 Package Specifications  
7.1 QFN28 Package Dimensions  
Figure 7.1. QFN28 Package Drawing  
Table 7.1. QFN28 Package Dimensions  
Dimension  
Min  
0.70  
0.00  
Typ  
0.75  
Max  
0.80  
0.05  
A
A1  
A3  
b
—
0.20 REF  
0.25  
0.20  
3.15  
0.30  
3.35  
D
5.00 BSC  
3.25  
D2  
e
0.50 BSC  
5.00 BSC  
3.25  
E
E2  
L
3.15  
0.45  
3.35  
0.65  
0.55  
aaa  
bbb  
ddd  
0.10  
0.10  
0.05  
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EFM8BB2 Data Sheet  
QFN28 Package Specifications  
Dimension  
eee  
Min  
Typ  
Max  
0.08  
Note:  
1. All dimensions shown are in millimeters (mm) unless otherwise noted.  
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.  
3. This drawing conforms to JEDEC Solid State Outline MO-220.  
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.  
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EFM8BB2 Data Sheet  
QFN28 Package Specifications  
7.2 QFN28 PCB Land Pattern  
X1  
C0.35  
E
X2  
C1  
Figure 7.2. QFN28 PCB Land Pattern Drawing  
Table 7.2. QFN28 PCB Land Pattern Dimensions  
Dimension  
Min  
Max  
C1  
C2  
E
4.80  
4.80  
0.50  
0.30  
3.35  
0.95  
3.35  
X1  
X2  
Y1  
Y2  
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EFM8BB2 Data Sheet  
QFN28 Package Specifications  
Dimension  
Note:  
Min  
Max  
1. All dimensions shown are in millimeters (mm) unless otherwise noted.  
2. This Land Pattern Design is based on the IPC-7351 guidelines.  
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm  
minimum, all the way around the pad.  
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.  
5. The stencil thickness should be 0.125 mm (5 mils).  
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.  
7. A 2 x 2 array of 1.2 mm square openings on a 1.5 mm pitch should be used for the center pad.  
8. A No-Clean, Type-3 solder paste is recommended.  
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.  
7.3 QFN28 Package Marking  
EFM8  
PPPPPPPP  
TTTTTT  
YYWW #  
Figure 7.3. QFN28 Package Marking  
The package marking consists of:  
• PPPPPPPP – The part number designation.  
• TTTTTT – A trace or manufacturing code.  
• YY – The last 2 digits of the assembly year.  
• WW – The 2-digit workweek when the device was assembled.  
• # – The device revision (A, B, etc.).  
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EFM8BB2 Data Sheet  
QSOP24 Package Specifications  
8. QSOP24 Package Specifications  
8.1 QSOP24 Package Dimensions  
Figure 8.1. QSOP24 Package Drawing  
Table 8.1. QSOP24 Package Dimensions  
Dimension  
Min  
—
Typ  
—
Max  
1.75  
0.25  
0.30  
0.25  
A
A1  
b
0.10  
0.20  
0.10  
—
—
c
—
D
E
8.65 BSC  
6.00 BSC  
3.90 BSC  
0.635 BSC  
—
E1  
e
L
0.40  
1.27  
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EFM8BB2 Data Sheet  
QSOP24 Package Specifications  
Dimension  
theta  
aaa  
Min  
Typ  
—
Max  
0º  
8º  
0.20  
0.18  
0.10  
0.10  
bbb  
ccc  
ddd  
Note:  
1. All dimensions shown are in millimeters (mm) unless otherwise noted.  
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.  
3. This drawing conforms to JEDEC outline MO-137, variation AE.  
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.  
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EFM8BB2 Data Sheet  
QSOP24 Package Specifications  
8.2 QSOP24 PCB Land Pattern  
Figure 8.2. QSOP24 PCB Land Pattern Drawing  
Table 8.2. QSOP24 PCB Land Pattern Dimensions  
Dimension  
Min  
Max  
C
5.20  
5.30  
E
0.635 BSC  
X
0.30  
0.40  
1.60  
Y
1.50  
Note:  
1. All dimensions shown are in millimeters (mm) unless otherwise noted.  
2. This land pattern design is based on the IPC-7351 guidelines.  
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm  
minimum, all the way around the pad.  
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.  
5. The stencil thickness should be 0.125 mm (5 mils).  
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.  
7. A No-Clean, Type-3 solder paste is recommended.  
8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.  
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EFM8BB2 Data Sheet  
QSOP24 Package Specifications  
8.3 QSOP24 Package Marking  
EFM8  
PPPPPPPP #  
TTTTTTYYWW  
Figure 8.3. QSOP24 Package Marking  
The package marking consists of:  
• PPPPPPPP – The part number designation.  
• TTTTTT – A trace or manufacturing code.  
• YY – The last 2 digits of the assembly year.  
• WW – The 2-digit workweek when the device was assembled.  
• # – The device revision (A, B, etc.).  
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EFM8BB2 Data Sheet  
QFN20 Package Specifications  
9. QFN20 Package Specifications  
9.1 QFN20 Package Dimensions  
Figure 9.1. QFN20 Package Drawing  
Table 9.1. QFN20 Package Dimensions  
Dimension  
Min  
0.70  
0.00  
Typ  
0.75  
Max  
0.80  
0.05  
A
A1  
A3  
b
0.02  
0.20 REF  
0.25  
0.18  
0.25  
0.30  
0.35  
c
0.30  
D
3.00 BSC  
1.70  
D2  
e
1.6  
1.80  
0.50 BSC  
3.00 BSC  
E
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EFM8BB2 Data Sheet  
QFN20 Package Specifications  
Dimension  
Min  
Typ  
1.70  
Max  
E2  
f
1.60  
1.80  
2.50 BSC  
0.40  
L
0.30  
0.09  
0.50  
0.15  
K
0.25 REF  
0.125  
0.15  
R
aaa  
bbb  
ccc  
ddd  
eee  
fff  
0.10  
0.10  
0.05  
0.08  
0.10  
Note:  
1. All dimensions shown are in millimeters (mm) unless otherwise noted.  
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.  
3. The drawing complies with JEDEC MO-220.  
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.  
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EFM8BB2 Data Sheet  
QFN20 Package Specifications  
9.2 QFN20 PCB Land Pattern  
Figure 9.2. QFN20 PCB Land Pattern Drawing  
Table 9.2. QFN20 PCB Land Pattern Dimensions  
Dimension  
Min  
3.10  
3.10  
2.50  
2.50  
0.50  
0.30  
0.25  
1.80  
0.90  
0.25  
1.80  
Max  
C1  
C2  
C3  
C4  
E
X1  
X2  
X3  
Y1  
Y2  
Y3  
0.35  
0.35  
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EFM8BB2 Data Sheet  
QFN20 Package Specifications  
Dimension  
Note:  
Min  
Max  
1. All dimensions shown are in millimeters (mm) unless otherwise noted.  
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.  
3. This Land Pattern Design is based on the IPC-7351 guidelines.  
4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm  
minimum, all the way around the pad.  
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.  
6. The stencil thickness should be 0.125 mm (5 mils).  
7. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.  
8. A 2 x 2 array of 0.75 mm openings on a 0.95 mm pitch should be used for the center pad to assure proper paste volume.  
9. A No-Clean, Type-3 solder paste is recommended.  
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.  
9.3 QFN20 Package Marking  
PPPP  
PPPP  
TTTTTT  
YYWW #  
Figure 9.3. QFN20 Package Marking  
The package marking consists of:  
• PPPPPPPP – The part number designation.  
• TTTTTT – A trace or manufacturing code.  
• YY – The last 2 digits of the assembly year.  
• WW – The 2-digit workweek when the device was assembled.  
• # – The device revision (A, B, etc.).  
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EFM8BB2 Data Sheet  
Revision History  
10. Revision History  
10.1 Revision 1.4  
March 13, 2017  
Updated the language in 1. Feature List to clarify the package offerings for each of the different temperature grades.  
Added bootloader pinout information to 3.10 Bootloader.  
Corrected the application note number for AN124: Pin Sharing Techniques for the C2 Interface in 5.2 Debug. Added  
CRC Calculation Time to 4.1.4 Flash Memory.  
10.2 Revision 1.31  
November 7, 2016  
Updated typical and maximum specifications in 4.1.2 Power Consumption.  
Added 4.1.11 1.8 V Internal LDO Voltage Regulator.  
10.3 Revision 1.3  
August 11, 2016  
Added A-grade parts.  
Added Thermal Resistance (Junction to Case) for QFN20 packages to 4.2 Thermal Conditions.  
Added a note to Table 4.2 Power Consumption on page 17 providing more information about the Comparator Reference specification.  
Added a note linking to the Typical VOH and VOL Performance graphs in 4.1.14 Port I/O.  
Specified the sizes of the SMBus and I2CSLAVE transmit and receive FIFOs.  
Added a note to 3.1 Introduction referencing the Reference Manual.  
10.4 Revision 1.2  
February 10, 2016  
Updated Figure 5.3 Debug Connection Diagram on page 34 to move the pull-up resistor on C2D / RSTb to after the series resistor  
instead of before.  
Added a reference to AN945: EFM8 Factory Bootloader User Guide in 3.10 Bootloader.  
Added I-grade parts.  
Adjusted and added maximum specifications in 4.1.2 Power Consumption for G-grade devices and added a note on which high fre-  
quency oscillator is used for the specification.  
Adjusted the Total Current Sunk into Supply Pin and Total Current Sourced out of Ground Pin specifications in 4.3 Absolute Maximum  
Ratings.  
10.5 Revision 1.1  
December 16, 2015  
Updated 3.2 Power to properly reflect that a comparator falling edge wakes the device from Suspend and Snooze.  
Added Note 2 to Table 4.1 Recommended Operating Conditions on page 16.  
Added 5.2 Debug.  
silabs.com | Building a more connected world.  
Rev. 1.4 | 57  
 
 
 
 
 
 
EFM8BB2 Data Sheet  
Revision History  
10.6 Revision 1.0  
Updated any TBD numbers in and adjusted various specifications.  
Updated VOH and VOL graphs in Figure 4.6 Typical VOH Curves on page 32 and Figure 4.7 Typical VOL Curves on page 32 and upda-  
ted the VOH and VOL specifications in Table 4.14 Port I/O on page 27.  
Added more information to 3.10 Bootloader.  
Updated part numbers to Revision C.  
10.7 Revision 0.3  
Updated QFN20 packaging and landing diagram dimensions.  
Updated QFN28 D and E minimum value.  
Updated some characterization TBD values.  
Updated the 5 V-to-3.3 V regulator Electrical Characteristics table.  
Added Stop mode to the Power Modes table in 3.2 Power.  
10.8 Revision 0.2  
Initial release.  
silabs.com | Building a more connected world.  
Rev. 1.4 | 58  
 
 
 
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more. Available for Windows,  
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Disclaimer  
Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or  
intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"  
parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes  
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