EFM8BB31F32G-A-QFN32 [SILICON]
The EFM8BB3 device family are fully integrated, mixed-signal system-on-a-chip MCUs. Highlighted features are listed below;
| 型号： | EFM8BB31F32G-A-QFN32 |
| 厂家： | 
SILICON |
| 描述： | The EFM8BB3 device family are fully integrated, mixed-signal system-on-a-chip MCUs. Highlighted features are listed below |
| 文件： | 总70页 (文件大小：1114K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EFM8 Busy Bee Family
EFM8BB3 Data Sheet
The EFM8BB3, part of the Busy Bee family of MCUs, is a per-
formance line of 8-bit microcontrollers with a comprehensive ana-
log and digital feature set in small packages.
KEY FEATURES
• Pipelined 8-bit 8051 MCU Core with
50 MHz operating frequency
These devices offer state-of-the-art performance by integrating 12-bit ADC, internal
temperature sensor, and up to two 12-bit DACs into small packages, making them ideal
for general purpose applications. With an efficient, pipelined 8051 core with maximum
operating frequency at 50 MHz, various communication interfaces, and four channels
of configurable logic, the EFM8BB3 family is optimal for many embedded applications.
• Up to 29 multifunction I/O pins
• One 12-bit/10-bit ADC
• Four 12-bit DACs with synchronization and
PWM capabilities
• Two low-current analog comparators with
built-in reference DACs
EFM8BB3 applications include the following:
• Internal temperature sensor
• Internal 49 MHz and 24.5 MHz oscillators
accurate to ±2%
• Consumer electronics
• Industrial control and automation
• Smart sensors
• Precision instrumentation
• Power management and control
• Four channels of Configurable Logic
• 6-channel PWM / PCA
• Six 16-bit general-purpose timers
Core / Memory
Clock Management
Energy Management
High Frequency
49 MHz RC
Oscillator
CIP-51 8051 Core
(50 MHz)
External
Oscillator
Internal LDO
Power-On Reset
Regulator
Flash Program
RAM Memory
Memory
High Frequency
24.5 MHz RC
Oscillator
Debug Interface
with C2
Low Frequency
RC Oscillator
Brown-Out Detector
(up to 4352 bytes)
(up to 64 KB)
8-bit SFR bus
Serial Interfaces
I/O Ports
Timers and Triggers
Analog Interfaces
Security
Timers
PCA/PWM
0/1/2/5
16-bit CRC
External
Interrupts
2 x
ADC
2 x UART
I2C / SMBus
SPI
Pin Reset
Comparators
Watchdog
Timer 3/4
Timer
Internal
Up to 4 x
High-Speed
I2C Slave
General
Purpose I/O
Voltage
Pin Wakeup
Voltage DAC
Reference
4 x Configurable Logic Units
Lowest power mode with peripheral operational:
Normal Idle Suspend
Snooze
Shutdown
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This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Preliminary Rev. 0.2
EFM8BB3 Data Sheet
Feature List
1. Feature List
The EFM8BB3 device family are fully integrated, mixed-signal system-on-a-chip MCUs. Highlighted features are listed below.
• Core:
• Analog:
• Pipelined CIP-51 Core
• 12/10-Bit Analog-to-Digital Converter (ADC)
• Fully compatible with standard 8051 instruction set
• Internal temperature sensor
• 70% of instructions execute in 1-2 clock cycles
• 4 x 12-Bit Digital-to-Analog Converters (DAC)
• 50 MHz maximum operating frequency
• 2 x Low-current analog comparators with adjustable refer-
• Memory:
ence
• Up to 64 kB flash memory (63 kB user-accessible), in-sys-
tem re-programmable from firmware in 512-byte sectors
• Communications and Digital Peripherals:
• 2 x UART, up to 3 Mbaud
• Up to 4352 bytes RAM (including 256 bytes standard 8051
RAM and 4096 bytes on-chip XRAM)
• SPI™ Master / Slave, up to 12 Mbps
• SMBus™/I2C™ Master / Slave, up to 400 kbps
• Power:
I2C High-Speed Slave, up to 3.4 Mbps
•
• Internal LDO regulator for CPU core voltage
• Power-on reset circuit and brownout detectors
• I/O: Up to 29 total multifunction I/O pins:
• Up to 25 pins 5 V tolerant under bias
• 16-bit CRC unit, supporting automatic CRC of flash at 256-
byte boundaries
• 4 Configurable Logic Units
• Timers/Counters and PWM:
• Selectable state retention through reset events
• Flexible peripheral crossbar for peripheral routing
• 5 mA source, 12.5 mA sink allows direct drive of LEDs
• Clock Sources:
• 6-channel programmable counter array (PCA) supporting
PWM, capture/compare, and frequency output modes
• 6 x 16-bit general-purpose timers
• Independent watchdog timer, clocked from the low frequen-
cy oscillator
• Internal 49 MHz oscillator with accuracy of ±2%
• Internal 24.5 MHz oscillator with ±2% accuracy
• Internal 80 kHz low-frequency oscillator
• External CMOS clock option
• On-Chip, Non-Intrusive Debugging
• Full memory and register inspection
• Four hardware breakpoints, single-stepping
• External crystal/RC/C Oscillator (up to 25 MHz)
With on-chip power-on reset, voltage supply monitor, watchdog timer, and clock oscillator, the EFM8BB3 devices are truly standalone
system-on-a-chip solutions. The flash memory is reprogrammable in-circuit, providing nonvolatile data storage and allowing field up-
grades of the firmware. The on-chip debugging interface (C2) allows non-intrusive (uses no on-chip resources), full speed, in-circuit
debugging using the production MCU installed in the final application. This debug logic supports inspection and modification of memory
and registers, setting breakpoints, single stepping, and run and halt commands. All analog and digital peripherals are fully functional
while debugging. Device operation is specified from 2.2 V up to a 3.6 V supply. Devices are AEC-Q100 qualified (pending) and availa-
ble in 4x4 mm 32-pin QFN, 3x3 mm 24-pin QFN, 32-pin QFP, or 24-pin QSOP packages. All package options are lead-free and RoHS
compliant.
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Preliminary Rev. 0.2 | 1
EFM8BB3 Data Sheet
Ordering Information
2. Ordering Information
EFM8 BB3 1 F 64 G – A – QFN32 R
Tape and Reel (Optional)
Package Type
Revision
Temperature Grade G (-40 to +85)
Flash Memory Size – 64 KB
Memory Type (Flash)
Family Feature Set
Busy Bee 3 Family
Silicon Labs EFM8 Product Line
Figure 2.1. EFM8BB3 Part Numbering
All EFM8BB3 family members have the following features:
• CIP-51 Core running up to 49 MHz
• Three Internal Oscillators (49 MHz, 24.5 MHz and 80 kHz)
• SMBus
• I2C Slave
• SPI
• 2 UARTs
• 6-Channel Programmable Counter Array (PWM, Clock Generation, Capture/Compare)
• Six 16-bit Timers
• Four Configurable Logic Units
• 12-bit Analog-to-Digital Converter with integrated multiplexer, voltage reference, temperature sensor, channel sequencer, and direct-
to-XRAM data transfer
• Two Analog Comparators
• 16-bit CRC Unit
• AEC-Q100 qualified (pending)
In addition to these features, each part number in the EFM8BB3 family has a set of features that vary across the product line. The
product selection guide shows the features available on each family member.
Table 2.1. Product Selection Guide
EFM8BB31F64G-A-QFN32
EFM8BB31F64G-A-QFP32
EFM8BB31F64G-A-QFN24
EFM8BB31F64G-A-QSOP24
64
64
64
64
4352
4352
4352
4352
29
28
20
21
4
4
4
4
20
20
12
13
10
10
6
9
9
6
7
Yes
Yes
Yes
Yes
-40 to +85 °C
-40 to +85 °C
-40 to +85 °C
-40 to +85 °C
QFN32
QFP32
QFN24
QSOP24
6
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Preliminary Rev. 0.2 | 2
EFM8BB3 Data Sheet
Ordering Information
EFM8BB31F32G-A-QFN32
EFM8BB31F32G-A-QFP32
EFM8BB31F32G-A-QFN24
EFM8BB31F32G-A-QSOP24
EFM8BB31F16G-A-QFN32
EFM8BB31F16G-A-QFP32
EFM8BB31F16G-A-QSOP24
32
32
32
32
16
16
16
2304
2304
2304
2304
2304
2304
2304
29
28
20
21
29
28
21
2
2
2
2
2
2
2
20
20
12
13
20
20
13
10
10
6
9
9
6
7
9
9
7
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-40 to +85 °C
QFN32
QFP32
-40 to +85 °C
-40 to +85 °C
-40 to +85 °C
-40 to +85 °C
-40 to +85 °C
-40 to +85 °C
QFN24
QSOP24
QFN32
QFP32
6
10
10
6
QSOP24
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Preliminary Rev. 0.2 | 3
EFM8BB3 Data Sheet
System Overview
3. System Overview
3.1 Introduction
Port I/O Configuration
Digital Peripherals
CIP-51 8051 Controller
Core
Debug /
Programming
Hardware
C2D
UART0
64 KB ISP Flash
Program Memory
VIO
UART1
C2CK/RSTb
Reset
Timers 0,
1, 2, 3, 4, 5
Power-On
Reset
256 Byte SRAM
4096 Byte XRAM
Port 0
Drivers
P0.n
Priority
Crossbar
Decoder
6-ch PCA
I2C Slave
Supply
Monitor
I2C /
Port 1
Drivers
SMBus
P1.n
P2.n
P3.n
VDD
SPI
Power
Net
CRC
Independent
Watchdog
Timer
SYSCLK
Voltage
Regulator
Config.
Logic
Units (4)
Port 2
Drivers
VREGIN
GND
Crossbar
Control
SFR
Bus
System Clock
Configuration
Port 3
Drivers
Analog Peripherals
Internal
Reference
Low Freq.
Oscillator
Up to 4 12-
bit DACs
VDD VREF
CMOS Clock
Input
EXTCLK
XTAL1
XTAL2
VDD
External Crystal /
RC Oscillator
12/10-
bit ADC
Temp
Sensor
49 MHz 2%
Oscillator
24.5 MHz 2%
Oscillator
+
+
-
2 Comparators
Figure 3.1. Detailed EFM8BB3 Block Diagram
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Preliminary Rev. 0.2 | 4
EFM8BB3 Data Sheet
System Overview
3.2 Power
All internal circuitry draws power from the VDD supply pin. External I/O pins are powered from the VIO supply voltage (or VDD on devi-
ces without a separate VIO connection), while most of the internal circuitry is supplied by an on-chip LDO regulator. Control over the
device power can be achieved by enabling/disabling individual peripherals as needed. Each analog peripheral can be disabled when
not in use and placed in low power mode. Digital peripherals, such as timers and serial buses, have their clocks gated off and draw little
power when they are not in use.
Table 3.1. Power Modes
Power Mode
Normal
Details
Mode Entry
Wake-Up Sources
Core and all peripherals clocked and fully operational
Idle
• Core halted
Set IDLE bit in PCON0
Any interrupt
• All peripherals clocked and fully operational
• Code resumes execution on wake event
Suspend
• Core and peripheral clocks halted
1. Switch SYSCLK to
HFOSC0
• Timer 4 Event
• HFOSC0 and HFOSC1 oscillators stopped
• Regulator in normal bias mode for fast wake
• Timer 3 and 4 may clock from LFOSC0
• Code resumes execution on wake event
• SPI0 Activity
2. Set SUSPEND bit in
PCON1
• I2C0 Slave Activity
• Port Match Event
• Comparator 0 Rising
Edge
• CLUn Interrupt-Enabled
Event
Stop
• All internal power nets shut down
• Pins retain state
1. Clear STOPCF bit in
REG0CN
Any reset source
2. Set STOP bit in
PCON0
• Exit on any reset source
Snooze
• Core and peripheral clocks halted
1. Switch SYSCLK to
HFOSC0
• Timer 4 Event
• HFOSC0 and HFOSC1 oscillators stopped
• SPI0 Activity
2. Set SNOOZE bit in
PCON1
• Regulator in low bias current mode for energy sav-
ings
• I2C0 Slave Activity
• Port Match Event
• Timer 3 and 4 may clock from LFOSC0
• Code resumes execution on wake event
• Comparator 0 Rising
Edge
• CLUn Interrupt-Enabled
Event
Shutdown
• All internal power nets shut down
• Pins retain state
1. Set STOPCF bit in
REG0CN
• RSTb pin reset
• Power-on reset
2. Set STOP bit in
PCON0
• Exit on pin or power-on reset
3.3 I/O
Digital and analog resources are externally available on the device’s multi-purpose I/O pins. Port pins P0.0-P2.3 can be defined as gen-
eral-purpose I/O (GPIO), assigned to one of the internal digital resources through the crossbar or dedicated channels, or assigned to an
analog function. Port pins P2.4 to P3.7 can be used as GPIO. Additionally, the C2 Interface Data signal (C2D) is shared with P3.0 or
P3.7, depending on the package option.
The port control block offers the following features:
• Up to 29 multi-functions I/O pins, supporting digital and analog functions.
• Flexible priority crossbar decoder for digital peripheral assignment.
• Two drive strength settings for each port.
• State retention feature allows pins to retain configuration through most reset sources.
• Two direct-pin interrupt sources with dedicated interrupt vectors (INT0 and INT1).
• Up to 24 direct-pin interrupt sources with shared interrupt vector (Port Match).
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Preliminary Rev. 0.2 | 5
EFM8BB3 Data Sheet
System Overview
3.4 Clocking
The CPU core and peripheral subsystem may be clocked by both internal and external oscillator resources. By default, the system
clock comes up running from the 24.5 MHz oscillator divided by 8.
The clock control system offers the following features:
• Provides clock to core and peripherals.
• 24.5 MHz internal oscillator (HFOSC0), accurate to ±2% over supply and temperature corners.
• 49 MHz internal oscillator (HFOSC1), accurate to ±2% over supply and temperature corners.
• 80 kHz low-frequency oscillator (LFOSC0).
• External Crystal / RC / C Oscillator.
• External CMOS clock input (EXTCLK).
• Clock divider with eight settings for flexible clock scaling:
• Divide the selected clock source by 1, 2, 4, 8, 16, 32, 64, or 128.
• HFOSC0 and HFOSC1 include 1.5x pre-scalers for further flexibility.
3.5 Counters/Timers and PWM
Programmable Counter Array (PCA0)
The programmable counter array (PCA) provides multiple channels of enhanced timer and PWM functionality while requiring less CPU
intervention than standard counter/timers. The PCA consists of a dedicated 16-bit counter/timer and one 16-bit capture/compare mod-
ule for each channel. The counter/timer is driven by a programmable timebase that has flexible external and internal clocking options.
Each capture/compare module may be configured to operate independently in one of five modes: Edge-Triggered Capture, Software
Timer, High-Speed Output, Frequency Output, or Pulse-Width Modulated (PWM) Output. Each capture/compare module has its own
associated I/O line (CEXn) which is routed through the crossbar to port I/O when enabled.
• 16-bit time base
• Programmable clock divisor and clock source selection
• Up to six independently-configurable channels
• 8, 9, 10, 11 and 16-bit PWM modes (center or edge-aligned operation)
• Output polarity control
• Frequency output mode
• Capture on rising, falling or any edge
• Compare function for arbitrary waveform generation
• Software timer (internal compare) mode
• Can accept hardware “kill” signal from comparator 0 or comparator 1
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EFM8BB3 Data Sheet
System Overview
Timers (Timer 0, Timer 1, Timer 2, Timer 3, Timer 4, and Timer 5)
Several counter/timers are included in the device: two are 16-bit counter/timers compatible with those found in the standard 8051, and
the rest are 16-bit auto-reload timers for timing peripherals or for general purpose use. These timers can be used to measure time inter-
vals, count external events and generate periodic interrupt requests. Timer 0 and Timer 1 are nearly identical and have four primary
modes of operation. The other timers offer both 16-bit and split 8-bit timer functionality with auto-reload and capture capabilities.
Timer 0 and Timer 1 include the following features:
• Standard 8051 timers, supporting backwards-compatibility with firmware and hardware.
• Clock sources include SYSCLK, SYSCLK divided by 12, 4, or 48, the External Clock divided by 8, or an external pin.
• 8-bit auto-reload counter/timer mode
• 13-bit counter/timer mode
• 16-bit counter/timer mode
• Dual 8-bit counter/timer mode (Timer 0)
Timer 2, Timer 3, Timer 4, and Timer 5 are 16-bit timers including the following features:
• Clock sources for all timers include SYSCLK, SYSCLK divided by 12, or the External Clock divided by 8
• LFOSC0 divided by 8 may be used to clock Timer 3 and Timer 4 in active or suspend/snooze power modes
• Timer 4 is a low-power wake source, and can be chained together with Timer 3
• 16-bit auto-reload timer mode
• Dual 8-bit auto-reload timer mode
• External pin capture
• LFOSC0 capture
• Comparator 0 capture
• Configurable Logic output capture
Watchdog Timer (WDT0)
The device includes a programmable watchdog timer (WDT) running off the low-frequency oscillator. A WDT overflow forces the MCU
into the reset state. To prevent the reset, the WDT must be restarted by application software before overflow. If the system experiences
a software or hardware malfunction preventing the software from restarting the WDT, the WDT overflows and causes a reset. Following
a reset, the WDT is automatically enabled and running with the default maximum time interval. If needed, the WDT can be disabled by
system software or locked on to prevent accidental disabling. Once locked, the WDT cannot be disabled until the next system reset.
The state of the RST pin is unaffected by this reset.
The Watchdog Timer has the following features:
• Programmable timeout interval
• Runs from the low-frequency oscillator
• Lock-out feature to prevent any modification until a system reset
3.6 Communications and Other Digital Peripherals
Universal Asynchronous Receiver/Transmitter (UART0)
UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support
allows a wide range of clock sources to generate standard baud rates. Received data buffering allows UART0 to start reception of a
second incoming data byte before software has finished reading the previous data byte.
The UART module provides the following features:
• Asynchronous transmissions and receptions
• Baud rates up to SYSCLK/2 (transmit) or SYSCLK/8 (receive)
• 8- or 9-bit data
• Automatic start and stop generation
• Single-byte buffer on transmit and receive
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EFM8BB3 Data Sheet
System Overview
Universal Asynchronous Receiver/Transmitter (UART1)
UART1 is an asynchronous, full duplex serial port offering a variety of data formatting options. A dedicated baud rate generator with a
16-bit timer and selectable prescaler is included, which can generate a wide range of baud rates. A received data FIFO allows UART1
to receive multiple bytes before data is lost and an overflow occurs.
UART1 provides the following features:
• Asynchronous transmissions and receptions
• Dedicated baud rate generator supports baud rates up to SYSCLK/2 (transmit) or SYSCLK/8 (receive)
• 5, 6, 7, 8, or 9 bit data
• Automatic start and stop generation
• Automatic parity generation and checking
• Single-byte buffer on transmit and receive
• Auto-baud detection
• LIN break and sync field detection
• CTS / RTS hardware flow control
Serial Peripheral Interface (SPI0)
The serial peripheral interface (SPI) module provides access to a flexible, full-duplex synchronous serial bus. The SPI can operate as a
master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and slaves on a single SPI bus. The slave-select
(NSS) signal can be configured as an input to select the SPI in slave mode, or to disable master mode operation in a multi-master
environment, avoiding contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can also be
configured as a firmware-controlled chip-select output in master mode, or disabled to reduce the number of pins required. Additional
general purpose port I/O pins can be used to select multiple slave devices in master mode.
• Supports 3- or 4-wire master or slave modes
• Supports external clock frequencies up to 12 Mbps in master or slave mode
• Support for all clock phase and polarity modes
• 8-bit programmable clock rate (master)
• Programmable receive timeout (slave)
• Two byte FIFO on transmit and receive
• Can operate in suspend or snooze modes and wake the CPU on reception of a byte
• Support for multiple masters on the same data lines
System Management Bus / I2C (SMB0)
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specifica-
tion, version 1.1, and compatible with the I2C serial bus.
The SMBus module includes the following features:
• Standard (up to 100 kbps) and Fast (400 kbps) transfer speeds
• Support for master, slave, and multi-master modes
• Hardware synchronization and arbitration for multi-master mode
• Clock low extending (clock stretching) to interface with faster masters
• Hardware support for 7-bit slave and general call address recognition
• Firmware support for 10-bit slave address decoding
• Ability to inhibit all slave states
• Programmable data setup/hold times
• Transmit and receive buffers to help increase throughput in faster applications
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EFM8BB3 Data Sheet
System Overview
I2C Slave (I2CSLAVE0)
The I2C Slave interface is a 2-wire, bidirectional serial bus that is compatible with the I2C Bus Specification 3.0. It is capable of transfer-
ring in high-speed mode (HS-mode) at speeds of up to 3.4 Mbps. Firmware can write to the I2C interface, and the I2C interface can
autonomously control the serial transfer of data. The interface also supports clock stretching for cases where the core may be tempora-
rily prohibited from transmitting a byte or processing a received byte during an I2C transaction. This module operates only as an I2C
slave device.
The I2C module includes the following features:
• Standard (up to 100 kbps), Fast (400 kbps), Fast Plus (1 Mbps), and High-speed (3.4 Mbps) transfer speeds
• Support for slave mode only
• Clock low extending (clock stretching) to interface with faster masters
• Hardware support for 7-bit slave address recognition
• Hardware support for multiple slave addresses with the option to save the matching address in the receive FIFO
16-bit CRC (CRC0)
The cyclic redundancy check (CRC) module performs a CRC using a 16-bit polynomial. CRC0 accepts a stream of 8-bit data and posts
the 16-bit result to an internal register. In addition to using the CRC block for data manipulation, hardware can automatically CRC the
flash contents of the device.
The CRC module is designed to provide hardware calculations for flash memory verification and communications protocols. The CRC
module supports the standard CCITT-16 16-bit polynomial (0x1021), and includes the following features:
• Support for CCITT-16 polynomial
• Byte-level bit reversal
• Automatic CRC of flash contents on one or more 256-byte blocks
• Initial seed selection of 0x0000 or 0xFFFF
Configurable Logic Units (CLU0, CLU1, CLU2, and CLU3)
The Configurable Logic block consists of multiple Configurable Logic Units (CLUs). CLUs are flexible logic functions which may be used
for a variety of digital functions, such as replacing system glue logic, aiding in the generation of special waveforms, or synchronizing
system event triggers.
• Four configurable logic units (CLUs), with direct-pin and internal logic connections
• Each unit supports 256 different combinatorial logic functions (AND, OR, XOR, muxing, etc.) and includes a clocked flip-flop for syn-
chronous operations
• Units may be operated synchronously or asynchronously
• May be cascaded together to perform more complicated logic functions
• Can operate in conjunction with serial peripherals such as UART and SPI or timing peripherals such as timers and PCA channels
• Can be used to synchronize and trigger multiple on-chip resources (ADC, DAC, Timers, etc.)
• Asynchronous output may be used to wake from low-power states
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EFM8BB3 Data Sheet
System Overview
3.7 Analog
12/10-Bit Analog-to-Digital Converter (ADC0)
The ADC is a successive-approximation-register (SAR) ADC with 12- and 10-bit modes, integrated track-and hold and a programmable
window detector. The ADC is fully configurable under software control via several registers. The ADC may be configured to measure
different signals using the analog multiplexer. The voltage reference for the ADC is selectable between internal and external reference
sources.
• Up to 20 external inputs
• Single-ended 12-bit and 10-bit modes
• Supports an output update rate of up to 400 ksps in 12-bit mode
• Channel sequencer logic with direct-to-XDATA output transfers
• Operation in a low power mode at lower conversion speeds
• Asynchronous hardware conversion trigger, selectable between software, external I/O and internal timer and configurable logic sour-
ces
• Output data window comparator allows automatic range checking
• Support for output data accumulation
• Conversion complete and window compare interrupts supported
• Flexible output data formatting
• Includes a fully-internal fast-settling 1.65 V reference and an on-chip precision 2.4 / 1.2 V reference, with support for using the sup-
ply as the reference, an external reference and signal ground
• Integrated temperature sensor
12-Bit Digital-to-Analog Converters (DAC0, DAC1, DAC2, DAC3)
The DAC modules are 12-bit Digital-to-Analog Converters with the capability to synchronize multiple outputs together. The DACs are
fully configurable under software control. The voltage reference for the DACs is selectable between internal and external reference
sources.
• Voltage output with 12-bit performance
• Supports an update rate of 200 ksps
• Hardware conversion trigger, selectable between software, external I/O and internal timer and configurable logic sources
• Outputs may be configured to persist through reset and maintain output state to avoid system disruption
• Multiple DAC outputs can be synchronized together
• DAC pairs (DAC0 and 1 or DAC2 and 3) support complementary output waveform generation
• Outputs may be switched between two levels according to state of configurable logic / PWM input trigger
• Flexible input data formatting
• Supports references from internal supply, on-chip precision reference, or external VREF pin
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EFM8BB3 Data Sheet
System Overview
Low Current Comparators (CMP0, CMP1)
An analog comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is higher.
External input connections to device I/O pins and internal connections are available through separate multiplexers on the positive and
negative inputs. Hysteresis, response time, and current consumption may be programmed to suit the specific needs of the application.
The comparator includes the following features:
• Up to 10 (CMP0) or 9 (CMP1) external positive inputs
• Up to 10 (CMP0) or 9 (CMP1) external negative inputs
• Additional input options:
• Internal connection to LDO output
• Direct connection to GND
• Direct connection to VDD
• Dedicated 6-bit reference DAC
• Synchronous and asynchronous outputs can be routed to pins via crossbar
• Programmable hysteresis between 0 and ±20 mV
• Programmable response time
• Interrupts generated on rising, falling, or both edges
• PWM output kill feature
3.8 Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur:
• The core halts program execution.
• Module registers are initialized to their defined reset values unless the bits reset only with a power-on reset.
• External port pins are forced to a known state.
• Interrupts and timers are disabled.
All registers are reset to the predefined values noted in the register descriptions unless the bits only reset with a power-on reset. The
contents of RAM are unaffected during a reset; any previously stored data is preserved as long as power is not lost. By default, the Port
I/O latches are reset to 1 in open-drain mode, with weak pullups enabled during and after the reset. Optionally, firmware may configure
the port I/O, DAC outputs, and precision reference to maintain state through system resets other than power-on resets. For Supply
Monitor and power-on resets, the RSTb pin is driven low until the device exits the reset state. On exit from the reset state, the program
counter (PC) is reset, and the system clock defaults to an internal oscillator. The Watchdog Timer is enabled, and program execution
begins at location 0x0000.
Reset sources on the device include the following:
• Power-on reset
• External reset pin
• Comparator reset
• Software-triggered reset
• Supply monitor reset (monitors VDD supply)
• Watchdog timer reset
• Missing clock detector reset
• Flash error reset
3.9 Debugging
The EFM8BB3 devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow flash programming and in-system debug-
ging with the production part installed in the end application. The C2 interface uses a clock signal (C2CK) and a bi-directional C2 data
signal (C2D) to transfer information between the device and a host system. See the C2 Interface Specification for details on the C2
protocol.
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EFM8BB3 Data Sheet
System Overview
3.10 Bootloader
All devices come pre-programmed with a UART0 bootloader. This bootloader resides in the code security page, which is the last page
of code flash; it can be erased if it is not needed.
The byte before the Lock Byte is the Bootloader Signature Byte. Setting this byte to a value of 0xA5 indicates the presence of the boot-
loader in the system. Any other value in this location indicates that the bootloader is not present in flash.
When a bootloader is present, the device will jump to the bootloader vector after any reset, allowing the bootloader to run. The boot-
loader then determines if the device should stay in bootload mode or jump to the reset vector located at 0x0000. When the bootloader
is not present, the device will jump to the reset vector of 0x0000 after any reset.
0xFFFF
Read-Only
64 Bytes
0xFFC0
0xFFBF
Reserved
0xFC00
Lock Byte
0xFBFF
Bootloader Signature Byte
0xFBFE
0xFBFD
Code Security Page
512 Bytes
0xFA00
Bootloader Vector
0xF9FF
62.5 KB Code
(125 x 512 Byte pages)
0x0000
Reset Vector
Figure 3.2. Flash Memory Map with Bootloader — 62.5 KB Devices
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EFM8BB3 Data Sheet
Electrical Specifications
4. Electrical Specifications
4.1 Electrical Characteristics
All electrical parameters in all tables are specified under the conditions listed in Table 4.1 Recommended Operating Conditions on page
13, unless stated otherwise.
4.1.1 Recommended Operating Conditions
Table 4.1. Recommended Operating Conditions
Parameter
Symbol
Test Condition
Min
2.2
Typ
—
Max
3.6
Unit
V
Operating Supply Voltage on VDD VDD
Operating Supply Voltage on VIO2,
3
VIO
TBD
—
VDD
V
System Clock Frequency
fSYSCLK
TA
0
—
—
50
85
MHz
°C
Operating Ambient Temperature
-40
Note:
1. All voltages with respect to GND
2. In certain package configurations, the VIO and VDD supplies are bonded to the same pin.
3. GPIO levels are undefined whenever VIO is less than 1 V.
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EFM8BB3 Data Sheet
Electrical Specifications
4.1.2 Power Consumption
Table 4.2. Power Consumption
Test Condition
Parameter
Symbol
Min
Typ
Max
Unit
Digital Core Supply Current
FSYSCLK = 49 MHz2
FSYSCLK = 24.5 MHz2
FSYSCLK = 1.53 MHz2
FSYSCLK = 80 kHz3
FSYSCLK = 49 MHz2
FSYSCLK = 24.5 MHz2
FSYSCLK = 1.53 MHz2
Normal Mode-Full speed with code IDD
executing from flash
—
—
—
—
—
—
—
—
TBD
4.2
TBD
5
mA
mA
μA
625
155
TBD
3.14
520
135
800
300
TBD
3.8
μA
Idle Mode-Core halted with periph- IDD
erals running
mA
mA
μA
700
280
FSYSCLK = 80 kHz3
LFO Running
μA
Suspend Mode-Core halted and
high frequency clocks stopped,
Supply monitor off.
IDD
—
—
125
120
285
270
μA
μA
LFO Stopped
Snooze Mode-Core halted and IDD
high frequency clocks stopped.
Regulator in low-power state, Sup-
ply monitor off.
LFO Running
LFO Stopped
—
—
23
19
165
160
μA
μA
Stop Mode—Core halted and all
clocks stopped,Internal LDO On,
Supply monitor off.
IDD
—
—
120
0.2
270
μA
μA
Shutdown Mode—Core halted and IDD
all clocks stopped,Internal LDO
Off, Supply monitor off.
0.65
Analog Peripheral Supply Currents
High-Frequency Oscillator 0
High-Frequency Oscillator 1
Low-Frequency Oscillator
IHFOSC0
Operating at 24.5 MHz,
TA = 25 °C
—
—
—
120
1080
3.7
135
1200
6
μA
μA
μA
IHFOSC1
Operating at 49 MHz,
TA = 25 °C
ILFOSC
Operating at 80 kHz,
TA = 25 °C
ADC04
IADC
High Speed Mode
Low Power Mode
High Speed Mode
Low Power Mode
—
—
—
—
—
—
—
TBD
TBD
700
170
75
TBD
TBD
790
210
—
μA
μA
μA
μA
µA
μA
µA
Internal ADC0 Reference5
IVREFFS
On-chip Precision Reference
Temperature Sensor
IVREFP
ITSENSE
IDAC
68
120
—
Digital-to-Analog Converters
(DAC0, DAC1)6
125
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EFM8BB3 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
CPMD = 11
CPMD = 10
CPMD = 01
CPMD = 00
Min
—
Typ
0.5
3
Max
—
Unit
μA
μA
μA
μA
μA
μA
Comparators (CMP0, CMP1)
ICMP
—
—
—
10
—
—
25
—
Comparator Reference
Voltage Supply Monitor (VMON0)
Note:
ICPREF
IVMON
—
TBD
15
—
—
20
1. Currents are additive. For example, where IDD is specified and the mode is not mutually exclusive, enabling the functions increa-
ses supply current by the specified amount.
2. Includes supply current from internal LDO regulator, supply monitor, and High Frequency Oscillator.
3. Includes supply current from internal LDO regulator, supply monitor, and Low Frequency Oscillator.
4. ADC0 power excludes internal reference supply current.
5. The internal reference is enabled as-needed when operating the ADC in low power mode. Total ADC + Reference current will
depend on sampling rate.
6. DAC supply current for each enabled DA and not including external load on pin.
4.1.3 Reset and Supply Monitor
Table 4.3. Reset and Supply Monitor
Parameter
Symbol
Test Condition
Min
1.85
—
Typ
1.95
1.4
—
Max
2.1
—
Unit
V
VDD Supply Monitor Threshold
VVDDM
Power-On Reset (POR) Threshold VPOR
Rising Voltage on VDD
Falling Voltage on VDD
Time to VDD > 2.2 V
V
0.75
10
1.36
—
V
VDD Ramp Time
tRMP
tPOR
—
μs
ms
μs
Reset Delay from POR
Relative to VDD > VPOR
3
10
31
Reset Delay from non-POR source tRST
RST Low Time to Generate Reset tRSTL
Time between release of reset
source and code execution
—
50
—
15
—
—
—
μs
Missing Clock Detector Response tMCD
Time (final rising edge to reset)
FSYSCLK >1 MHz
0.625
1.2
ms
Missing Clock Detector Trigger
Frequency
FMCD
—
—
7.5
2
13.5
—
kHz
μs
VDD Supply Monitor Turn-On Time tMON
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EFM8BB3 Data Sheet
Electrical Specifications
4.1.4 Flash Memory
Table 4.4. Flash Memory
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Write Time1 ,2
tWRITE
One Byte,
19
20
21
μs
FSYSCLK = 24.5 MHz
One Page,
Erase Time1 ,2
tERASE
5.2
5.35
5.5
ms
FSYSCLK = 24.5 MHz
VDD Voltage During Programming3
Endurance (Write/Erase Cycles)
Note:
VPROG
NWE
2.2
—
3.6
—
V
20k
100k
Cycles
1. Does not include sequencing time before and after the write/erase operation, which may be multiple SYSCLK cycles.
2. The internal High-Frequency Oscillator 0 has a programmable output frequency, which is factory programmed to 24.5 MHz. If
user firmware adjusts the oscillator speed, it must be between 22 and 25 MHz during any flash write or erase operation. It is
recommended to write the HFO0CAL register back to its reset value when writing or erasing flash.
3. Flash can be safely programmed at any voltage above the supply monitor threshold (VVDDM).
4. Data Retention Information is published in the Quarterly Quality and Reliability Report.
4.1.5 Power Management Timing
Table 4.5. Power Management Timing
Parameter
Symbol
Test Condition
Min
2
Typ
—
Max
3
Units
SYSCLKs
ns
Idle Mode Wake-up Time
Suspend Mode Wake-up Time
tIDLEWK
tSUS-
SYSCLK = HFOSC0
CLKDIV = 0x00
—
170
—
PENDWK
Snooze Mode Wake-up Time
tSLEEPWK SYSCLK = HFOSC0
CLKDIV = 0x00
—
12
—
µs
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EFM8BB3 Data Sheet
Electrical Specifications
4.1.6 Internal Oscillators
Table 4.6. Internal Oscillators
Test Condition
Parameter
Symbol
Min
Typ
Max
Unit
High Frequency Oscillator 0 (24.5 MHz)
Oscillator Frequency
fHFOSC0
Full Temperature and Supply
Range
24
—
24.5
0.5
25
—
MHz
%/V
Power Supply Sensitivity
PSSHFOS TA = 25 °C
C0
Temperature Sensitivity
TSHFOSC0 VDD = 3.0 V
—
40
—
ppm/°C
High Frequency Oscillator 1 (49 MHz)
Oscillator Frequency
fHFOSC1
Full Temperature and Supply
Range
48.02
—
49
49.98
—
MHz
%/V
Power Supply Sensitivity
PSSHFOS TA = 25 °C
TBD
C1
Temperature Sensitivity
TSHFOSC1 VDD = 3.0 V
—
TBD
80
—
ppm/°C
kHz
Low Frequency Oscillator (80 kHz)
Oscillator Frequency
fLFOSC
Full Temperature and Supply
Range
75
85
Power Supply Sensitivity
Temperature Sensitivity
PSSLFOSC TA = 25 °C
—
—
0.05
65
—
—
%/V
TSLFOSC
VDD = 3.0 V
ppm/°C
4.1.7 External Clock Input
Table 4.7. External Clock Input
Test Condition
Parameter
Symbol
Min
Typ
Max
Unit
External Input CMOS Clock
Frequency (at EXTCLK pin)
fCMOS
0
—
50
MHz
External Input CMOS Clock High
Time
tCMOSH
9
9
—
—
—
—
ns
ns
External Input CMOS Clock Low
Time
tCMOSL
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EFM8BB3 Data Sheet
Electrical Specifications
4.1.8 Crystal Oscillator
Table 4.8. Crystal Oscillator
Test Condition
Parameter
Symbol
fXTAL
Min
0.02
—
Typ
—
Max
25
—
Unit
MHz
µA
Crystal Frequency
Crystal Drive Current
IXTAL
XFCN = 0
XFCN = 1
XFCN = 2
XFCN = 3
XFCN = 4
XFCN = 5
XFCN = 6
XFCN = 7
0.5
1.5
4.8
14
—
—
µA
—
—
µA
—
—
µA
—
40
—
µA
—
120
550
2.6
—
µA
—
—
µA
—
—
mA
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EFM8BB3 Data Sheet
Electrical Specifications
4.1.9 ADC
Table 4.9. ADC
Parameter
Symbol
Test Condition
Min
Typ
12
Max
Unit
Bits
Resolution
Nbits
12 Bit Mode
10 Bit Mode
10 Bit Mode
10
Bits
Throughput Rate
(High Speed Mode)
Throughput Rate
(Low Power Mode)
Tracking Time
fS
—
—
1.125
Msps
fS
12 Bit Mode
—
—
—
—
—
—
—
—
—
0.7
350
1.125
—
ksps
Msps
ns
10 Bit Mode
tTRK
High Speed Mode
Low Power Mode
230
450
1.2
—
—
ns
Power-On Time
tPWR
fSAR
—
μs
SAR Clock Frequency
High Speed Mode
Low Power Mode
12-Bit Conversion,
SAR Clock =18 MHz,
System Clock = 49 MHz
10-Bit Conversion,
SAR Clock =18 MHz,
System Clock = 49 MHz
Gain = 1
18
MHz
MHz
μs
—
TBD
Conversion Time1
tCNV
0.59
μs
Sample/Hold Capacitor
CSAR
—
—
—
—
—
—
1
5.2
3.9
2.6
1.3
20
—
—
pF
pF
pF
pF
pF
Ω
Gain = 0.75
Gain = 0.5
—
Gain = 0.25
—
Input Pin Capacitance
Input Mux Impedance
Voltage Reference Range
CIN
—
RMUX
VREF
VIN
550
—
—
VIO
V
Input Voltage Range2
Gain = 1
0
—
VREF
Gain
/
V
Power Supply Rejection Ratio
DC Performance
PSRRADC
INL
—
TBD
—
dB
Integral Nonlinearity
12 Bit Mode
10 Bit Mode
12 Bit Mode
10 Bit Mode
12 Bit Mode
10 Bit Mode
-1.9
-0.6
-0.9
-0.5
-2
-0.35 / 1
±0.2
±0.3
±0.2
0
1.9
0.6
0.9
0.5
2
LSB
LSB
LSB
LSB
LSB
LSB
Differential Nonlinearity (Guaran-
teed Monotonic)
DNL
Offset Error
EOFF
-1
0
1
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EFM8BB3 Data Sheet
Electrical Specifications
Parameter
Symbol
TCOFF
EM
Test Condition
Min
—
Typ
TBD
—
Max
—
Unit
LSB/°C
%
Offset Temperature Coefficient
Slope Error
12 Bit Mode
10 Bit Mode
-2.5
-1.1
2.5
1.1
—
%
Dynamic Performance 10 kHz Sine Wave Input 1 dB below full scale, Max throughput, using AGND pin
Signal-to-Noise
SNR
12 Bit Mode
10 Bit Mode
12 Bit Mode
10 Bit Mode
12 Bit Mode
10 Bit Mode
12 Bit Mode
10 Bit Mode
64
59
64
59
—
—
—
—
68
61
68
61
-72
-69
74
71
—
—
—
—
—
—
—
—
dB
dB
dB
dB
dB
dB
dB
dB
Signal-to-Noise Plus Distortion
SNDR
THD
Total Harmonic Distortion (Up to
5th Harmonic)
Spurious-Free Dynamic Range
SFDR
Note:
1. Conversion Time does not include Tracking Time. Total Conversion Time is:
Total Conversion Time = RPT × (ADTK + NUMBITS + 1) × T(SARCLK) + (T(ADCCLK) × 4)
where RPT is the number of conversions represented by the ADRPT field and ADCCLK is the clock selected for the ADC.
2. Absolute input pin voltage is limited by the VIO supply.
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EFM8BB3 Data Sheet
Electrical Specifications
4.1.10 Voltage Reference
Table 4.10. Voltage Reference
Test Condition
Parameter
Symbol
Min
Typ
Max
Unit
Internal Fast Settling Reference
Output Voltage
VREFFS
1.62
1.65
1.68
V
(Full Temperature and Supply
Range)
Temperature Coefficient
Turn-on Time
TCREFFS
tREFFS
—
—
—
50
—
—
1.5
—
ppm/°C
μs
Power Supply Rejection
PSRRREF
400
ppm/V
FS
On-chip Precision Reference
Valid Supply Range
VDD
1.2 V Output
2.4 V Output
2.2
2.7
—
—
3.6
3.6
V
V
V
Output Voltage
VREFP
1.2 V Output, VDD = 3.3 V, T = 25
°C
1.195
1.2
1.205
1.2 V Output
1.18
2.39
1.2
2.4
1.22
2.41
V
V
2.4 V Output, VDD = 3.3 V, T = 25
°C
2.4 V Output
2.36
—
2.4
3
2.44
—
V
Turn-on Time, settling to 0.5 LSB
tVREFP
4.7 µF tantalum + 0.1 µF ceramic
bypass on VREF pin
ms
0.1 µF ceramic bypass on VREF
pin
—
100
—
µs
Load Regulation
LRVREFP
CVREFP
Load = 0 to 200 µA to GND
Load = 0 to 200 µA to GND
—
0.1
—
TBD
—
—
—
8
µV/µA
µF
Load Capacitor
Short-circuit current
Power Supply Rejection
ISCVREFP
—
mA
PSRRVRE
—
TBD
—
ppm/V
FP
External Reference
Input Current
IEXTREF
ADC Sample Rate = 800 ksps;
VREF = 3.0 V
—
5
—
μA
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EFM8BB3 Data Sheet
Electrical Specifications
4.1.11 Temperature Sensor
Table 4.11. Temperature Sensor
Parameter
Symbol
VOFF
Test Condition
TA = 0 °C
Min
—
Typ
749
19
Max
—
Unit
mV
mV
Offset
Offset Error1
Slope
EOFF
TA = 0 °C
—
—
M
—
—
2.835
25
—
—
mV/°C
μV/°C
Slope Error1
Linearity
EM
—
—
TBD
TBD
—
—
°C
μs
Turn-on Time
Note:
1. Represents one standard deviation from the mean.
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EFM8BB3 Data Sheet
Electrical Specifications
4.1.12 DACs
Table 4.12. DACs
Parameter
Symbol
Nbits
fS
Test Condition
Min
Typ
12
Max
Unit
Bits
Resolution
Throughput Rate
Integral Nonlinearity
Differential Nonlinearity
Output Noise
—
TBD
TBD
—
—
200
TBD
TBD
—
ksps
LSB
INL
TBD
—
DNL
LSB
VREF
2.4 V
=
110
μVRMS
fS = 0.1
Hz to 300
kHz
Slew Rate
SLEW
—
—
±1
—
5
V/μs
μs
Output Settling Time to 1 LSB
tSETTLE
VOUT change between 25% and
75% Full Scale
2.6
Power-on Time
tPWR
VREF
PSRR
THD
—
1.15
—
—
—
78
—
10
VDD
—
μs
V
Voltage Reference Range
Power Supply Rejection Ratio
Total Harmonic Distortion
DC, VOUT = 50% Full Scale
dB
dB
VOUT = 10 kHz sine wave, 10% to
90%
TBD
—
Offset Error
EOFF
EFS
RLOAD
CLOAD
VREF = 2.4 V
VREF = 2.4 V
-8
-13
2
0
±5
—
8
LSB
LSB
kΩ
Full-Scale Error
13
External Load Impedance
External Load Capacitance
Load Regulation
—
TBD
—
—
100
TBD
pF
VOUT = 50% Full Scale
IOUT = -2 to 2 mA
100
μV/mA
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EFM8BB3 Data Sheet
Electrical Specifications
4.1.13 Comparators
Parameter
Table 4.13. Comparators
Symbol
Test Condition
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Typ
100
150
1.5
3.5
0.4
8
Max
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
ns
Response Time, CPMD = 00
(Highest Speed)
tRESP0
+100 mV Differential
-100 mV Differential
+100 mV Differential
-100 mV Differential
CPHYP = 00
CPHYP = 01
CPHYP = 10
CPHYP = 11
CPHYN = 00
CPHYN = 01
CPHYN = 10
CPHYN = 11
CPHYP = 00
CPHYP = 01
CPHYP = 10
CPHYP = 11
CPHYN = 00
CPHYN = 01
CPHYN = 10
CPHYN = 11
CPHYP = 00
CPHYP = 01
CPHYP = 10
CPHYP = 11
CPHYN = 00
CPHYN = 01
CPHYN = 10
CPHYN = 11
CPHYP = 00
CPHYP = 01
CPHYP = 10
CPHYP = 11
ns
Response Time, CPMD = 11 (Low- tRESP3
est Power)
μs
μs
Positive Hysteresis
HYSCP+
HYSCP-
HYSCP+
HYSCP-
HYSCP+
HYSCP-
HYSCP+
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
Mode 0 (CPMD = 00)
16
32
Negative Hysteresis
Mode 0 (CPMD = 00)
-0.4
-8
-16
-32
0.5
6
Positive Hysteresis
Mode 1 (CPMD = 01)
12
24
Negative Hysteresis
Mode 1 (CPMD = 01)
-0.5
-6
-12
-24
0.7
4.5
9
Positive Hysteresis
Mode 2 (CPMD = 10)
18
Negative Hysteresis
Mode 2 (CPMD = 10)
-0.6
-4.5
-9
-18
1.5
4
Positive Hysteresis
Mode 3 (CPMD = 11)
8
16
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EFM8BB3 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
CPHYN = 00
CPHYN = 01
CPHYN = 10
CPHYN = 11
Min
—
Typ
-1.5
-4
Max
Unit
mV
mV
mV
mV
V
Negative Hysteresis
Mode 3 (CPMD = 11)
HYSCP-
—
—
—
—
—
-8
—
-16
—
—
Input Range (CP+ or CP-)
Input Pin Capacitance
VIN
-0.25
—
VIO+0.25
—
CCP
7.5
6
pF
Internal Reference DAC Resolution Nbits
bits
dB
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Input Offset Voltage
CMRRCP
—
—
70
72
0
—
—
10
—
PSRRCP
VOFF
dB
TA = 25 °C
-10
—
mV
μV/°
Input Offset Tempco
TCOFF
3.5
4.1.14 Configurable Logic
Table 4.14. Configurable Logic
Parameter
Symbol
tDLY
Test Condition
Min
—
Typ
—
Max
35.3
Unit
ns
Propagation Delay
Clocking Frequency
Through single CLU
1 or 2 CLUs Cascaded
3 or 4 CLUs Cascaded
FCLK
—
—
73.5
MHz
MHz
—
—
36.75
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EFM8BB3 Data Sheet
Electrical Specifications
4.1.15 Port I/O
Table 4.15. Port I/O
Parameter
Symbol
Test Condition
Min
Typ
—
Max
—
Unit
V
Output High Voltage (High Drive)
VOH
IOH = -7 mA, VIO ≥ 3.0 V
VIO - 0.7
VIO x 0.8
IOH = -3.3 mA, 2.2 V ≤ VIO < 3.0 V
IOH = -1.8 mA, 1.71 V ≤ VIO < 2.2 V
IOL = 13.5 mA, VIO ≥ 3.0 V
—
—
V
Output Low Voltage (High Drive)
Output High Voltage (Low Drive)
Output Low Voltage (Low Drive)
VOL
VOH
VOL
—
—
—
—
0.6
V
V
IOL = 7 mA, 2.2 V ≤ VIO < 3.0 V
IOL = 3.6 mA, 1.71 V ≤ VIO < 2.2 V
IOH = -4.75 mA, VIO ≥ 3.0 V
VIO x 0.2
VIO - 0.7
—
—
—
—
V
V
IOH = -2.25 mA, 2.2 V ≤ VIO < 3.0 V VIO x 0.8
IOH = -1.2 mA, 1.71 V ≤ VIO < 2.2 V
IOL = 6.5 mA, VIO ≥ 3.0 V
—
—
—
—
0.6
V
V
IOL = 3.5 mA, 2.2 V ≤ VIO < 3.0 V
IOL = 1.8 mA, 1.71 V ≤ VIO < 2.2 V
VIO x 0.2
Input High Voltage
Input Low Voltage
VIH
0.7 x
VIO
—
—
—
—
V
V
VIL
0.3 x
VIO
—
Pin Capacitance
Weak Pull-Up Current
(VIN = 0 V)
CIO
IPU
—
7
pF
μA
VDD = 3.6
-30
-20
-10
Input Leakage (Pullups off or Ana- ILK
log)
GND < VIN < VIO
TBD
0
—
5
TBD
150
μA
μA
Input Leakage Current with VIN
above VIO
ILK
VIO < VIN < VIO+2.5 V
Any pin except P3.0, P3.1, P3.2, or
P3.3
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EFM8BB3 Data Sheet
Electrical Specifications
4.2 Thermal Conditions
Table 4.16. Thermal Conditions
Parameter
Symbol
Test Condition
Min
—
Typ
TBD
TBD
80
Max
—
Unit
°C/W
°C/W
°C/W
°C/W
Thermal Resistance
θJA
QFN24 Packages
QFN32 Packages
QFP32 Packages
QSOP24 Packages
—
—
—
—
—
65
—
Note:
1. Thermal resistance assumes a multi-layer PCB with any exposed pad soldered to a PCB pad.
4.3 Absolute Maximum Ratings
Stresses above those listed in Table 4.17 Absolute Maximum Ratings on page 27 may cause permanent damage to the device. This
is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation
listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. For
more information on the available quality and reliability data, see the Quality and Reliability Monitor Report at http://www.silabs.com/
support/quality/pages/default.aspx.
Table 4.17. Absolute Maximum Ratings
Parameter
Symbol
TBIAS
TSTG
VDD
Test Condition
Min
-55
Max
125
Unit
°C
°C
V
Ambient Temperature Under Bias
Storage Temperature
Voltage on VDD
-65
150
GND-0.3
GND-0.3
4.2
Voltage on VIO2
VIO
VDD+0.3
V
Voltage on I/O pins or RSTb, excluding VIN
P2.0-P2.3 (QFN24 and QSOP24) or
P3.0-P3.3 (QFN32 and QFP32)
VIO > TBD V
VIO < TBD V
GND-0.3
GND-0.3
GND-0.3
TBD
TBD
V
V
V
Voltage on P2.0-P2.3 (QFN24 and
QSOP24) or P3.0-P3.3 (QFN32 and
QFP32)
VIN
VDD+0.3
Total Current Sunk into Supply Pin
IVDD
IGND
—
400
—
mA
mA
Total Current Sourced out of Ground
Pin
400
Current Sourced or Sunk by any I/O
Pin or RSTb
IIO
-100
100
mA
Note:
1. Exposure to maximum rating conditions for extended periods may affect device reliability.
2. In certain package configurations, the VIO and VDD supplies are bonded to the same pin.
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EFM8BB3 Data Sheet
Typical Connection Diagrams
5. Typical Connection Diagrams
5.1 Power
Figure 5.1 Power Connection Diagram on page 28 shows a typical connection diagram for the power pins of the device.
EFM8BB3 Device
1.8 - VDD V
VIO
2.2 - 3.6 V
4.7 µF and 0.1 µF bypass
capacitors required for
VDD
each power pin placed as
close to the pins as
possible.
GND
Figure 5.1. Power Connection Diagram
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EFM8BB3 Data Sheet
Typical Connection Diagrams
5.2 Debug
The diagram below shows a typical connection diagram for the debug connections pins. The pin sharing resistors are only required if
the functionality on the C2D (a GPIO pin) and the C2CK (RSTb) is routed to external circuitry. For example, if the RSTb pin is connec-
ted to an external switch with debouncing filter or if the GPIO sharing with the C2D pin is connected to an external circuit, the pin shar-
ing resistors and connections to the debug adapter must be placed on the hardware. Otherwise, these components and connections
can be omitted.
For more information on debug connections, see the example schematics and information available in AN127: "Pin Sharing Techniques
for the C2 Interface." Application notes can be found on the Silicon Labs website (http://www.silabs.com/8bit-appnotes) or in Simplicity
Studio.
VIO
External
System
EFM8BB3 Device
1 k
(if pin sharing)
C2CK
1 k
1 k
1 k
(if pin sharing)
C2D
1 k
GND
Debug Adapter
Figure 5.2. Debug Connection Diagram
5.3 Other Connections
Other components or connections may be required to meet the system-level requirements. Application Note AN203: "8-bit MCU Printed
Circuit Board Design Notes" contains detailed information on these connections. Application Notes can be accessed on the Silicon
Labs website (www.silabs.com/8bit-appnotes).
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Preliminary Rev. 0.2 | 29
EFM8BB3 Data Sheet
Pin Definitions
6. Pin Definitions
6.1 EFM8BB3x-QFN32 Pin Definitions
1
24
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P0.0
2
3
4
5
6
7
8
23
22
21
20
19
18
17
VIO
VDD
RSTb / C2CK
P3.7 / C2D
P3.4
32 pin QFN
(Top View)
P3.3
GND
P3.2
Figure 6.1. EFM8BB3x-QFN32 Pinout
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EFM8BB3 Data Sheet
Pin Definitions
Table 6.1. Pin Definitions for EFM8BB3x-QFN32
Pin
Number
1
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
Analog Functions
P0.0
Multifunction I/O
Yes
P0MAT.0
INT0.0
VREF
INT1.0
CLU0A.8
CLU2A.8
CLU3B.8
2
3
4
VIO
VDD
RSTb /
C2CK
P3.7 /
C2D
I/O Supply Power Input
Supply Power Input
Active-low Reset /
C2 Debug Clock
Multifunction I/O /
C2 Debug Data
5
6
7
P3.4
Multifunction I/O
Multifunction I/O
Multifunction I/O
Multifunction I/O
Multifunction I/O
Multifunction I/O
P3.3
DAC3
8
P3.2
DAC2
9
P3.1
DAC1
10
11
P3.0
DAC0
P2.6
ADC0.19
CMP1P.8
CMP1N.8
ADC0.18
CMP1P.7
CMP1N.7
ADC0.17
CMP1P.6
CMP1N.6
ADC0.16
CMP1P.5
CMP1N.5
12
13
14
P2.5
P2.4
P2.3
Multifunction I/O
Multifunction I/O
Multifunction I/O
CLU3OUT
Yes
P2MAT.3
CLU1B.15
CLU2B.15
CLU3A.15
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EFM8BB3 Data Sheet
Pin Definitions
Pin
Number
15
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
Analog Functions
P2.2
Multifunction I/O
Yes
P2MAT.2
CLU2OUT
CLU1A.15
CLU2B.14
CLU3A.14
P2MAT.1
I2C0_SCL
CLU1B.14
CLU2A.15
CLU3B.15
P2MAT.0
I2C0_SDA
CLU1A.14
CLU2A.14
CLU3B.14
P1MAT.7
CLU0B.15
CLU1B.13
CLU2A.13
P1MAT.6
CLU0A.15
CLU1B.12
CLU2A.12
P1MAT.5
CLU0B.14
CLU1A.13
CLU2B.13
CLU3B.11
P1MAT.4
CLU0A.14
CLU1A.12
CLU2B.12
CLU3B.10
ADC0.15
CMP1P.4
CMP1N.4
16
P2.1
Multifunction I/O
Yes
ADC0.14
CMP1P.3
CMP1N.3
17
P2.0
Multifunction I/O
Yes
CMP1P.2
CMP1N.2
18
19
20
P1.7
P1.6
P1.5
Multifunction I/O
Multifunction I/O
Multifunction I/O
Yes
Yes
Yes
ADC0.13
CMP0P.9
CMP0N.9
ADC0.12
ADC0.11
21
P1.4
Multifunction I/O
Yes
ADC0.10
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EFM8BB3 Data Sheet
Pin Definitions
Pin
Number
22
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
Analog Functions
P1.3
Multifunction I/O
Yes
P1MAT.3
CLU0B.13
CLU1B.11
CLU2B.11
CLU3A.13
P1MAT.2
CLU0A.13
CLU1A.11
CLU2B.10
CLU3A.12
CLU3B.13
P1MAT.1
CLU0B.12
CLU1B.10
CLU2A.11
CLU3B.12
P1MAT.0
CLU1OUT
CLU0A.12
CLU1A.10
CLU2A.10
P0MAT.7
INT0.7
ADC0.9
23
P1.2
Multifunction I/O
Yes
ADC0.8
CMP0P.8
CMP0N.8
24
25
26
P1.1
P1.0
P0.7
Multifunction I/O
Multifunction I/O
Multifunction I/O
Yes
Yes
Yes
ADC0.7
CMP0P.7
CMP0N.7
ADC0.6
CMP0P.6
CMP0N.6
CMP1P.1
CMP1N.1
ADC0.5
CMP0P.5
CMP0N.5
CMP1P.0
CMP1N.0
INT1.7
CLU0B.11
CLU1B.9
CLU3A.11
P0MAT.6
CNVSTR
INT0.6
27
P0.6
Multifunction I/O
Yes
ADC0.4
CMP0P.4
CMP0N.4
INT1.6
CLU0A.11
CLU1B.8
CLU3A.10
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EFM8BB3 Data Sheet
Pin Definitions
Pin
Number
28
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
Analog Functions
P0.5
Multifunction I/O
Yes
P0MAT.5
INT0.5
ADC0.3
CMP0P.3
CMP0N.3
INT1.5
UART0_RX
CLU0B.10
CLU1A.9
P0MAT.4
INT0.4
29
P0.4
Multifunction I/O
Yes
ADC0.2
CMP0P.2
CMP0N.2
INT1.4
UART0_TX
CLU0A.10
CLU1A.8
P0MAT.3
EXTCLK
INT0.3
30
P0.3
Multifunction I/O
Yes
XTAL2
INT1.3
CLU0B.9
CLU2B.10
CLU3A.9
P0MAT.2
INT0.2
31
P0.2
Multifunction I/O
Yes
XTAL1
ADC0.1
INT1.2
CMP0P.1
CMP0N.1
CLU0OUT
CLU0A.9
CLU2B.8
CLU3A.8
P0MAT.1
INT0.1
32
P0.1
Multifunction I/O
Yes
ADC0.0
CMP0P.0
CMP0N.0
AGND
INT1.1
CLU0B.8
CLU2A.9
CLU3B.9
Center
GND
Ground
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EFM8BB3 Data Sheet
Pin Definitions
6.2 EFM8BB3x-QFP32 Pin Definitions
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
P0.0
GND
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
VIO
VDD
32 Pin QFP
RSTb / C2CK
P3.7 / C2D
P3.3
P3.2
Figure 6.2. EFM8BB3x-QFP32 Pinout
Table 6.2. Pin Definitions for EFM8BB3x-QFP32
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
Analog Functions
Number
1
P0.0
Multifunction I/O
Yes
P0MAT.0
INT0.0
VREF
INT1.0
CLU0A.8
CLU2A.8
CLU3B.8
2
3
4
5
GND
VIO
Ground
I/O Supply Power Input
Supply Power Input
Active-low Reset /
C2 Debug Clock
VDD
RSTb /
C2CK
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EFM8BB3 Data Sheet
Pin Definitions
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
Analog Functions
Number
6
P3.7 /
C2D
P3.3
P3.2
P3.1
P3.0
P2.6
Multifunction I/O /
C2 Debug Data
Multifunction I/O
Multifunction I/O
Multifunction I/O
Multifunction I/O
Multifunction I/O
7
DAC3
8
DAC2
9
DAC1
10
11
DAC0
ADC0.19
CMP1P.8
CMP1N.8
ADC0.18
CMP1P.7
CMP1N.7
ADC0.17
CMP1P.6
CMP1N.6
ADC0.16
CMP1P.5
CMP1N.5
12
13
14
P2.5
P2.4
P2.3
Multifunction I/O
Multifunction I/O
Multifunction I/O
CLU3OUT
Yes
Yes
P2MAT.3
CLU1B.15
CLU2B.15
CLU3A.15
P2MAT.2
CLU2OUT
CLU1A.15
CLU2B.14
CLU3A.14
P2MAT.1
I2C0_SCL
CLU1B.14
CLU2A.15
CLU3B.15
P2MAT.0
I2C0_SDA
CLU1A.14
CLU2A.14
CLU3B.14
15
16
17
P2.2
P2.1
P2.0
Multifunction I/O
Multifunction I/O
Multifunction I/O
ADC0.15
CMP1P.4
CMP1N.4
Yes
ADC0.14
CMP1P.3
CMP1N.3
Yes
CMP1P.2
CMP1N.2
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EFM8BB3 Data Sheet
Pin Definitions
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
Analog Functions
Number
18
P1.7
Multifunction I/O
Yes
P1MAT.7
CLU0B.15
CLU1B.13
CLU2A.13
P1MAT.6
CLU0A.15
CLU1B.12
CLU2A.12
P1MAT.5
CLU0B.14
CLU1A.13
CLU2B.13
CLU3B.11
P1MAT.4
CLU0A.14
CLU1A.12
CLU2B.12
CLU3B.10
P1MAT.3
CLU0B.13
CLU1B.11
CLU2B.11
CLU3A.13
P1MAT.2
CLU0A.13
CLU1A.11
CLU2B.10
CLU3A.12
CLU3B.13
P1MAT.1
CLU0B.12
CLU1B.10
CLU2A.11
CLU3B.12
ADC0.13
CMP0P.9
CMP0N.9
19
20
P1.6
P1.5
Multifunction I/O
Multifunction I/O
Yes
Yes
ADC0.12
ADC0.11
21
22
23
P1.4
P1.3
P1.2
Multifunction I/O
Multifunction I/O
Multifunction I/O
Yes
Yes
Yes
ADC0.10
ADC0.9
ADC0.8
CMP0P.8
CMP0N.8
24
P1.1
Multifunction I/O
Yes
ADC0.7
CMP0P.7
CMP0N.7
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EFM8BB3 Data Sheet
Pin Definitions
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
Analog Functions
Number
25
P1.0
Multifunction I/O
Yes
P1MAT.0
CLU1OUT
CLU0A.12
CLU1A.10
CLU2A.10
P0MAT.7
INT0.7
ADC0.6
CMP0P.6
CMP0N.6
CMP1P.1
CMP1N.1
ADC0.5
26
P0.7
Multifunction I/O
Yes
CMP0P.5
CMP0N.5
CMP1P.0
CMP1N.0
INT1.7
CLU0B.11
CLU1B.9
CLU3A.11
P0MAT.6
CNVSTR
INT0.6
27
P0.6
Multifunction I/O
Yes
ADC0.4
CMP0P.4
CMP0N.4
INT1.6
CLU0A.11
CLU1B.8
CLU3A.10
P0MAT.5
INT0.5
28
P0.5
Multifunction I/O
Yes
ADC0.3
CMP0P.3
CMP0N.3
INT1.5
UART0_RX
CLU0B.10
CLU1A.9
P0MAT.4
INT0.4
29
P0.4
Multifunction I/O
Yes
ADC0.2
CMP0P.2
CMP0N.2
INT1.4
UART0_TX
CLU0A.10
CLU1A.8
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EFM8BB3 Data Sheet
Pin Definitions
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
Analog Functions
Number
30
P0.3
Multifunction I/O
Yes
P0MAT.3
EXTCLK
INT0.3
XTAL2
INT1.3
CLU0B.9
CLU2B.10
CLU3A.9
P0MAT.2
INT0.2
31
P0.2
Multifunction I/O
Yes
XTAL1
ADC0.1
CMP0P.1
CMP0N.1
INT1.2
CLU0OUT
CLU0A.9
CLU2B.8
CLU3A.8
P0MAT.1
INT0.1
32
P0.1
Multifunction I/O
Yes
ADC0.0
CMP0P.0
CMP0N.0
AGND
INT1.1
CLU0B.8
CLU2A.9
CLU3B.9
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EFM8BB3 Data Sheet
Pin Definitions
6.3 EFM8BB3x-QFN24 Pin Definitions
1
19
P0.1
P0.0
P0.7
P1.0
P1.1
P1.2
2
3
4
5
6
18
17
16
15
14
GND
24 pin QFN
VDD / VIO
RSTb / C2CK
P3.0 / C2D
P2.3
(Top View)
GND
P1.3
P1.4
GND
7
13
Figure 6.3. EFM8BB3x-QFN24 Pinout
Table 6.3. Pin Definitions for EFM8BB3x-QFN24
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Analog Functions
Functions
Number
1
P0.1
Multifunction I/O
Yes
P0MAT.1
INT0.1
ADC0.0
CMP0P.0
CMP0N.0
AGND
INT1.1
CLU0B.8
CLU2A.9
CLU3B.9
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EFM8BB3 Data Sheet
Pin Definitions
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
Analog Functions
Number
2
P0.0
Multifunction I/O
Yes
P0MAT.0
INT0.0
VREF
INT1.0
CLU0A.8
CLU2A.8
CLU3B.8
3
4
5
GND
Ground
VDD / VIO
RSTb /
C2CK
P3.0 /
C2D
Supply Power Input
Active-low Reset /
C2 Debug Clock
Multifunction I/O /
C2 Debug Data
Multifunction I/O
6
7
P2.3
Yes
Yes
Yes
Yes
Yes
P2MAT.3
CLU1B.15
CLU2B.15
CLU3A.15
P2MAT.2
CLU1A.15
CLU2B.14
CLU3A.14
P2MAT.1
CLU1B.14
CLU2A.15
CLU3B.15
P2MAT.0
CLU1A.14
CLU2A.14
CLU3B.14
P1MAT.6
CLU3OUT
CLU0A.15
CLU1B.12
CLU2A.12
DAC3
DAC2
DAC1
DAC0
8
P2.2
P2.1
P2.0
P1.6
Multifunction I/O
Multifunction I/O
Multifunction I/O
Multifunction I/O
9
10
11
ADC0.11
CMP1P.5
CMP1N.5
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EFM8BB3 Data Sheet
Pin Definitions
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
Analog Functions
Number
12
P1.5
Multifunction I/O
Yes
P1MAT.5
CLU2OUT
CLU0B.14
CLU1A.13
CLU2B.13
CLU3B.11
P1MAT.4
I2C0_SCL
CLU0A.14
CLU1A.12
CLU2B.12
CLU3B.10
P1MAT.3
I2C0_SDA
CLU0B.13
CLU1B.11
CLU2B.11
CLU3A.13
ADC0.10
CMP1P.4
CMP1N.4
13
P1.4
Multifunction I/O
Yes
ADC0.9
CMP1P.3
CMP1N.3
14
P1.3
Multifunction I/O
Yes
CMP1P.2
CMP1N.2
15
16
GND
P1.2
Ground
Multifunction I/O
Yes
P1MAT.2
CLU0A.13
CLU1A.11
CLU2B.10
CLU3A.12
CLU3B.13
P1MAT.1
CLU0B.12
CLU1B.10
CLU2A.11
CLU3B.12
P1MAT.0
CLU0A.12
CLU1A.10
CLU2A.10
ADC0.8
17
P1.1
Multifunction I/O
Yes
ADC0.7
18
P1.0
Multifunction I/O
Yes
ADC0.6
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EFM8BB3 Data Sheet
Pin Definitions
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
Analog Functions
Number
19
P0.7
Multifunction I/O
Yes
P0MAT.7
INT0.7
ADC0.5
CMP0P.5
CMP0N.5
CMP1P.1
CMP1N.1
INT1.7
CLU1OUT
CLU0B.11
CLU1B.9
CLU3A.11
P0MAT.6
CNVSTR
INT0.6
20
P0.6
Multifunction I/O
Yes
ADC0.4
CMP0P.4
CMP0N.4
CMP1P.0
CMP1N.0
INT1.6
CLU0A.11
CLU1B.8
CLU3A.10
P0MAT.5
INT0.5
21
22
23
P0.5
P0.4
P0.3
Multifunction I/O
Multifunction I/O
Multifunction I/O
Yes
Yes
Yes
ADC0.3
CMP0P.3
CMP0N.3
INT1.5
UART0_RX
CLU0B.10
CLU1A.9
P0MAT.4
INT0.4
ADC0.2
CMP0P.2
CMP0N.2
INT1.4
UART0_TX
CLU0A.10
CLU1A.8
P0MAT.3
EXTCLK
INT0.3
XTAL2
INT1.3
CLU0B.9
CLU2B.10
CLU3A.9
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EFM8BB3 Data Sheet
Pin Definitions
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
Analog Functions
Number
24
P0.2
Multifunction I/O
Yes
P0MAT.2
INT0.2
XTAL1
ADC0.1
CMP0P.1
CMP0N.1
INT1.2
CLU0OUT
CLU0A.9
CLU2B.8
CLU3A.8
Center
GND
Ground
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EFM8BB3 Data Sheet
Pin Definitions
6.4 EFM8BB3x-QSOP24 Pin Definitions
1
2
24
23
22
21
20
19
18
17
16
15
14
13
P0.3
P0.2
P0.1
P0.0
GND
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
3
4
5
6
24 pin QSOP
VDD / VIO
(Top View)
7
RSTb / C2CK
8
P3.0 / C2D
P2.3
9
10
11
12
P2.2
P2.1
P1.6
P1.7
P2.0
Figure 6.4. EFM8BB3x-QSOP24 Pinout
Table 6.4. Pin Definitions for EFM8BB3x-QSOP24
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
Analog Functions
Number
1
P0.3
Multifunction I/O
Yes
P0MAT.3
EXTCLK
INT0.3
XTAL2
INT1.3
CLU0B.9
CLU2B.10
CLU3A.9
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EFM8BB3 Data Sheet
Pin Definitions
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
Analog Functions
Number
2
P0.2
Multifunction I/O
Yes
P0MAT.2
INT0.2
XTAL1
ADC0.1
CMP0P.1
CMP0N.1
INT1.2
CLU0OUT
CLU0A.9
CLU2B.8
CLU3A.8
P0MAT.1
INT0.1
3
P0.1
Multifunction I/O
Yes
ADC0.0
CMP0P.0
CMP0N.0
AGND
INT1.1
CLU0B.8
CLU2A.9
CLU3B.9
P0MAT.0
INT0.0
4
P0.0
Multifunction I/O
Yes
VREF
INT1.0
CLU0A.8
CLU2A.8
CLU3B.8
5
6
7
GND
Ground
VDD / VIO
RSTb /
C2CK
P3.0 /
C2D
Supply Power Input
Active-low Reset /
C2 Debug Clock
Multifunction I/O /
C2 Debug Data
Multifunction I/O
8
9
P2.3
Yes
Yes
P2MAT.3
CLU1B.15
CLU2B.15
CLU3A.15
P2MAT.2
CLU1A.15
CLU2B.14
CLU3A.14
DAC3
DAC2
10
P2.2
Multifunction I/O
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EFM8BB3 Data Sheet
Pin Definitions
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
Analog Functions
Number
11
P2.1
Multifunction I/O
Yes
P2MAT.1
CLU1B.14
CLU2A.15
CLU3B.15
P2MAT.0
CLU1A.14
CLU2A.14
CLU3B.14
P1MAT.7
CLU0B.15
CLU1B.13
CLU2A.13
P1MAT.6
CLU3OUT
CLU0A.15
CLU1B.12
CLU2A.12
P1MAT.5
CLU2OUT
CLU0B.14
CLU1A.13
CLU2B.13
CLU3B.11
P1MAT.4
I2C0_SCL
CLU0A.14
CLU1A.12
CLU2B.12
CLU3B.10
P1MAT.3
I2C0_SDA
CLU0B.13
CLU1B.11
CLU2B.11
CLU3A.13
DAC1
12
13
14
P2.0
P1.7
P1.6
Multifunction I/O
Multifunction I/O
Multifunction I/O
Yes
Yes
Yes
DAC0
ADC0.12
CMP1P.6
CMP1N.6
ADC0.11
CMP1P.5
CMP1N.5
15
16
17
P1.5
P1.4
P1.3
Multifunction I/O
Multifunction I/O
Multifunction I/O
Yes
Yes
Yes
ADC0.10
CMP1P.4
CMP1N.4
ADC0.9
CMP1P.3
CMP1N.3
CMP1P.2
CMP1N.2
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EFM8BB3 Data Sheet
Pin Definitions
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
Analog Functions
Number
18
P1.2
Multifunction I/O
Yes
P1MAT.2
CLU0A.13
CLU1A.11
CLU2B.10
CLU3A.12
CLU3B.13
P1MAT.1
CLU0B.12
CLU1B.10
CLU2A.11
CLU3B.12
P1MAT.0
CLU0A.12
CLU1A.10
CLU2A.10
P0MAT.7
INT0.7
ADC0.8
19
P1.1
Multifunction I/O
Yes
ADC0.7
20
21
P1.0
P0.7
Multifunction I/O
Multifunction I/O
Yes
Yes
ADC0.6
ADC0.5
CMP0P.5
CMP0N.5
CMP1P.1
CMP1N.1
INT1.7
CLU1OUT
CLU0B.11
CLU1B.9
CLU3A.11
P0MAT.6
CNVSTR
INT0.6
22
P0.6
Multifunction I/O
Yes
ADC0.4
CMP0P.4
CMP0N.4
CMP1P.0
CMP1N.0
INT1.6
CLU0A.11
CLU1B.8
CLU3A.10
P0MAT.5
INT0.5
23
P0.5
Multifunction I/O
Yes
ADC0.3
CMP0P.3
CMP0N.3
INT1.5
UART0_RX
CLU0B.10
CLU1A.9
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Preliminary Rev. 0.2 | 48
EFM8BB3 Data Sheet
Pin Definitions
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
Analog Functions
Number
24
P0.4
Multifunction I/O
Yes
P0MAT.4
INT0.4
ADC0.2
CMP0P.2
CMP0N.2
INT1.4
UART0_TX
CLU0A.10
CLU1A.8
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Preliminary Rev. 0.2 | 49
EFM8BB3 Data Sheet
QFN32 Package Specifications
7. QFN32 Package Specifications
7.1 QFN32 Package Dimensions
Figure 7.1. QFN32 Package Drawing
Table 7.1. QFN32 Package Dimensions
Dimension
Min
0.45
0.00
0.15
Typ
0.50
Max
0.55
0.05
0.25
A
A1
b
0.035
0.20
D
4.00 BSC.
2.90
D2
e
2.80
3.00
0.40 BSC.
4.00 BSC.
2.90
E
E2
L
2.80
0.20
—
3.00
0.40
0.10
0.10
0.08
0.10
0.10
0.05
0.30
aaa
bbb
ccc
ddd
eee
ggg
—
—
—
—
—
—
—
—
—
—
—
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Preliminary Rev. 0.2 | 50
EFM8BB3 Data Sheet
QFN32 Package Specifications
Dimension
Note:
Min
Typ
Max
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Solid State Outline MO-220.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
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Preliminary Rev. 0.2 | 51
EFM8BB3 Data Sheet
QFN32 Package Specifications
7.2 QFN32 PCB Land Pattern
Figure 7.2. QFN32 PCB Land Pattern Drawing
Table 7.2. QFN32 PCB Land Pattern Dimensions
Dimension
Min
—
—
—
—
—
—
—
Max
4.00
4.00
0.2
C1
C2
X1
X2
Y1
Y2
e
2.8
0.75
2.8
0.4
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Preliminary Rev. 0.2 | 52
EFM8BB3 Data Sheet
QFN32 Package Specifications
Dimension
Note:
Min
Max
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabri-
cation Allowance of 0.05mm.
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
9. A 2 x 2 array of 1.10 mm square openings on a 1.30 mm pitch should be used for the center pad.
10. A No-Clean, Type-3 solder paste is recommended.
11. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
7.3 QFN32 Package Marking
EFM8
PPPPPPPP
YYWW
TTTTTT #
Figure 7.3. QFN32 Package Marking
The package marking consists of:
• PPPPPPPP – The part number designation.
• TTTTTT – A trace or manufacturing code.
• YY – The last 2 digits of the assembly year.
• WW – The 2-digit workweek when the device was assembled.
• # – The device revision (A, B, etc.).
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EFM8BB3 Data Sheet
QFP32 Package Specifications
8. QFP32 Package Specifications
8.1 QFP32 Package Dimensions
Figure 8.1. QFP32 Package Drawing
Table 8.1. QFP32 Package Dimensions
Dimension
Min
—
Typ
—
Max
1.20
0.15
1.05
0.45
0.20
A
A1
A2
b
0.05
0.95
0.30
0.09
—
1.00
0.37
c
—
D
9.00 BSC
7.00 BSC
0.80 BSC
9.00 BSC
7.00 BSC
0.60
D1
e
E
E1
L
0.50
0.70
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Preliminary Rev. 0.2 | 54
EFM8BB3 Data Sheet
QFP32 Package Specifications
Dimension
aaa
Min
Typ
0.20
0.20
0.10
0.20
3.5°
Max
bbb
ccc
ddd
theta
0°
7°
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MS-026.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Preliminary Rev. 0.2 | 55
EFM8BB3 Data Sheet
QFP32 Package Specifications
8.2 QFP32 PCB Land Pattern
Figure 8.2. QFP32 PCB Land Pattern Drawing
Table 8.2. QFP32 PCB Land Pattern Dimensions
Dimension
Min
Max
8.50
8.50
C1
C2
E
8.40
8.40
0.80 BSC
0.55
X1
Y1
1.5
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
7. A No-Clean, Type-3 solder paste is recommended.
8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
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EFM8BB3 Data Sheet
QFP32 Package Specifications
8.3 QFP32 Package Marking
EFM8
PPPPPPPPPPP
YYWWTTTTTT#
e3
Figure 8.3. QFP32 Package Marking
The package marking consists of:
• PPPPPPPP – The part number designation.
• TTTTTT – A trace or manufacturing code.
• YY – The last 2 digits of the assembly year.
• WW – The 2-digit workweek when the device was assembled.
• # – The device revision (A, B, etc.).
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EFM8BB3 Data Sheet
QFN24 Package Specifications
9. QFN24 Package Specifications
9.1 QFN24 Package Dimensions
Figure 9.1. QFN24 Package Drawing
Table 9.1. QFN24 Package Dimensions
Dimension
Min
0.8
Typ
0.85
Max
0.9
A
A1
A2
A3
b
0.00
—
—
0.05
—
0.65
0.203 REF
0.2
0.15
0.25
0.25
0.35
b1
D
0.3
3.00 BSC
3.00 BSC
E
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EFM8BB3 Data Sheet
QFN24 Package Specifications
Dimension
Min
Typ
0.40 BSC
0.45 BSC
1.70
Max
e
e1
J
1.60
1.60
0.35
0.25
—
1.80
1.80
0.45
0.35
—
K
1.70
L
0.40
L1
0.30
aaa
bbb
ccc
ddd
eee
Note:
0.10
—
0.10
—
—
0.08
—
—
0.1
—
—
0.1
—
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Solid State Outline MO-248 but includes custom features which are toleranced per supplier
designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Preliminary Rev. 0.2 | 59
EFM8BB3 Data Sheet
QFN24 Package Specifications
9.2 QFN24 PCB Land Pattern
c
X1
Y3
Y1
e
f
Y2
C2
c
X2
C1
Figure 9.2. QFN24 PCB Land Pattern Drawing
Table 9.2. QFN24 PCB Land Pattern Dimensions
Dimension
Min
Max
C1
C2
e
3.00
3.00
0.4 REF
0.20
X1
X2
Y1
Y2
Y3
f
1.80
0.80
1.80
0.4
2.50 REF
c
0.25
0.35
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Preliminary Rev. 0.2 | 60
EFM8BB3 Data Sheet
QFN24 Package Specifications
Dimension
Note:
Min
Max
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-SM-782 guidelines.
4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
6. The stencil thickness should be 0.125 mm (5 mils).
7. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
8. A 2 x 1 array of 1.20 mm x 0.95 mm openings on a 1.15 mm pitch should be used for the center pad.
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
9.3 QFN24 Package Marking
PPPP
PPPPPP
TTTTTT
YYWW #
Figure 9.3. QFN24 Package Marking
The package marking consists of:
• PPPPPPPP – The part number designation.
• TTTTTT – A trace or manufacturing code.
• YY – The last 2 digits of the assembly year.
• WW – The 2-digit workweek when the device was assembled.
• # – The device revision (A, B, etc.).
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EFM8BB3 Data Sheet
QSOP24 Package Specifications
10. QSOP24 Package Specifications
10.1 QSOP24 Package Dimensions
Figure 10.1. QSOP24 Package Drawing
Table 10.1. QSOP24 Package Dimensions
Dimension
Min
—
Typ
Max
1.75
0.25
0.30
0.25
A
—
—
A1
b
0.10
0.20
0.10
—
c
—
D
8.65 BSC
6.00 BSC
3.90 BSC
0.635 BSC
—
E
E1
e
L
0.40
0º
1.27
8º
theta
—
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EFM8BB3 Data Sheet
QSOP24 Package Specifications
Dimension
aaa
Min
Typ
0.20
0.18
0.10
0.10
Max
bbb
ccc
ddd
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-137, variation AE.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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EFM8BB3 Data Sheet
QSOP24 Package Specifications
10.2 QSOP24 PCB Land Pattern
Figure 10.2. QSOP24 PCB Land Pattern Drawing
Table 10.2. QSOP24 PCB Land Pattern Dimensions
Dimension
Min
Max
C
5.20
5.30
E
0.635 BSC
X
0.30
0.40
1.60
Y
1.50
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This land pattern design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
7. A No-Clean, Type-3 solder paste is recommended.
8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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EFM8BB3 Data Sheet
QSOP24 Package Specifications
10.3 QSOP24 Package Marking
EFM8
PPPPPPPP #
YYWWTTTTTT
Figure 10.3. QSOP24 Package Marking
The package marking consists of:
• PPPPPPPP – The part number designation.
• TTTTTT – A trace or manufacturing code.
• YY – The last 2 digits of the assembly year.
• WW – The 2-digit workweek when the device was assembled.
• # – The device revision (A, B, etc.).
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EFM8BB3 Data Sheet
Revision History
11. Revision History
11.1 Revision 0.1
Initial release.
11.2 Revision 0.2
Added information on the bootloader to 3.10 Bootloader.
Updated some characterization TBD values.
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Preliminary Rev. 0.2 | 66
Table of Contents
1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.3 I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.4 Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.5 Counters/Timers and PWM . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.6 Communications and Other Digital Peripherals . . . . . . . . . . . . . . . . . . . 7
3.7 Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.8 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.9 Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.10 Bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
4. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .13
4.1.1 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . .13
4.1.2 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4.1.3 Reset and Supply Monitor . . . . . . . . . . . . . . . . . . . . . . . . .15
4.1.4 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.1.5 Power Management Timing . . . . . . . . . . . . . . . . . . . . . . . .16
4.1.6 Internal Oscillators. . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.1.7 External Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.1.8 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.1.9 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.1.10 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.1.11 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.1.12 DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.1.13 Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.1.14 Configurable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.1.15 Port I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.2 Thermal Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . .27
5. Typical Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . 28
5.1 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
5.2 Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
5.3 Other Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
6. Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.1 EFM8BB3x-QFN32 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . .30
6.2 EFM8BB3x-QFP32 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . .35
Table of Contents 67
6.3 EFM8BB3x-QFN24 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . .40
6.4 EFM8BB3x-QSOP24 Pin Definitions . . . . . . . . . . . . . . . . . . . . . .45
7. QFN32 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . . 50
7.1 QFN32 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . .50
7.2 QFN32 PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . .52
7.3 QFN32 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . .53
8. QFP32 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . . 54
8.1 QFP32 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . .54
8.2 QFP32 PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . .56
8.3 QFP32 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . .57
9. QFN24 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . . 58
9.1 QFN24 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . .58
9.2 QFN24 PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . .60
9.3 QFN24 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . .61
10. QSOP24 Package Specifications . . . . . . . . . . . . . . . . . . . . . . 62
10.1 QSOP24 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . .62
10.2 QSOP24 PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . .64
10.3 QSOP24 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . .65
11. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
11.1 Revision 0.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
11.2 Revision 0.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table of Contents 68
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Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers
using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific
device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories
reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy
or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply
or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products must not be used within any Life Support System without the specific
written consent of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected
to result in significant personal injury or death. Silicon Laboratories products are generally not intended for military applications. Silicon Laboratories products shall under no
circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.
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