SI2107-D-FMR_技术文档

Si2107/08/09/10

SATELLITE RECEIVER FOR DVB-S/DSS

Features

ꢀ Single-chip tuner, demodulator, ꢀ Automatic acquisition and fade

and LNB controller

recovery

ꢀ DVB-S- and DSS-compliant ꢀ Automatic gain control

ꢀ QPSK/BPSK demodulation

ꢀ Integrated step-up dc-dc

ꢀ On-chip blind scan accelerator

(Si2109/10 only)

converter for LNB power supply ꢀ DiSEqC™ 2.2 support

(Si2108/10 only)

ꢀ Power, C/N, and BER estimators

ꢀ I2C bus interface

Pin Assignments

ꢀ Input signal level:

–81 to –18 dBm

Si2107/08/09/10

ꢀ 3.3/1.8 V supply, 3.3 V I/O

ꢀ Symbol rate range:

ꢀ Lead-free/RoHS-compliant

1 to 45 MBaud

package

44 43 42 41 40 39 38 37 36

1

VDD_LNA

REXT

35 XTAL1

Applications

2

3

4

5

6

7

8

9

GND

34 XTAL2

ADDR

33 VDD_XTAL

32 XTOUT

ꢀ

Set-top boxes

Digital video recorders

Digital televisions

ꢀ

Satellite PC-TV

SMATV trans-modulators

(Satellite Master Antenna TV)

VDD_MIX

VDD_BB

VDD_ADC

VSEN/TDET

LNB1/TGEN

ISEN

31 VDD_PLL33

30 INT/RLK/GPO

29 TS_ERR

Top

View

28

TS_VAL

27 TS_SYNC

26 SDA

LNB2/DRC 10

Description

RESET 11

PWM/DCS 12

VDD_DIG18 13

25 SCL

24 TS_DATA[7]

GND

TS_DATA[6]

23

The Si2107/08/09/10 are a family of pin-compatible, complete front-end solutions

for DSS and DVB-S digital satellite reception. The IC family incorporates a tuner,

demodulator, and LNB controller into a single device resulting in significantly

reduced board space and external component count. The device supports symbol

rates of 1 to 45 MBaud over a 950 to 2150 MHz range. A full suite of features

including automatic acquisition, fade recovery, blind scanning, performance

monitoring, and DiSEqC Level 2.2 compliant signaling are supported. The Si2108/

10 further add short circuit protection, overcurrent protection, and a step-up dc-dc

controller to implement a low-cost LNB supply solution. Si2110/09 versions

include a hardware channel scan accelerator for fast “blindscan”. An I2C bus

interface is used to configure and monitor all internal parameters.

14 15 16 17 18 19 20 21 22

Functional Block Diagram

Acquisition Control

AGC

TS_CLK

TS_DATA[7:0]

TS_VAL

RS

Decoder

Viterbi

Decoder

Tuner

Demodulator

RFIP

TS_SYNC

TS_ERR

VSEN/TDET

LNB2/DRL

ISEN/NC

LNB1/TGEN

PWM/DCS

LNB Control

RF Sythesizer

I2C Interface

SCL SDA

INT/RLK/GPO

XOUT

Preliminary Rev. 0.7 3/06

Si2107/08/09/10

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

Si2107/08/09/10

2

Preliminary Rev. 0.7

Si2107/08/09/10

TABLE OF CONTENTS

Section

Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

4. Part Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

5.1. Tuner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

5.2. Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

5.3. DVB-S/DSS Channel Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

5.4. On-Chip Blindscan Accelerator (Si2109/10 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . .18

5.5. LNB Signaling Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

5.6. On-Chip LNB DC-DC Step-Up Controller (Si2108/10 Only) . . . . . . . . . . . . . . . . . . .18

5.7. Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

6. Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

6.1. System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

6.2. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

6.3. Receiver Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

6.4. Tuning Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

6.5. Channel Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

6.6. Automatic Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

6.7. LNB Signaling Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

6.8. On-Chip LNB DC-DC Step-Up Controller (Si2108/10 Only) . . . . . . . . . . . . . . . . . . .28

7. I2C Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

8. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

9. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

10. Ordering Guide1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

11. Package Outline: 44-pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

Preliminary Rev. 0.7

3

Si2107/08/09/10

1. Electrical Specifications

Table 1. Recommended Operating Conditions

Parameter

Ambient temperature

Symbol

Min

0

Typ

—

Max

70

Unit

°C

V

T

A

DC supply voltage, 3.3 V

DC supply voltage, 1.8 V

V

3.0

1.71

3.3

1.8

3.6

3.3

1.8

1.89

V

Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.

Table 2. Absolute Maximum Ratings^{1, 2}

Parameter

Symbol

Min

–0.3

–10

–55

—

Max

3.9

Unit

V

DC supply voltage, 3.3 V

DC supply voltage, 1.8 V

Input voltage - pins 2, 3, 7, 9, 11

Input current - pins 2, 3, 7, 9, 11

Operating ambient temperature

Storage temperature

V

3.3

1.8

2.19

V

+ 0.3

3.3

V

IN

I

+10

+70

150

10

1

mA

°C

dBm

kV

T

OP

T

STG

RF input level

ESD protection - pins 39–40, 42–43

ESD protection - pins 1–38, 41, 44

Notes:

2

1. Permanent damage may occur if the absolute maximum ratings are exceeded. Functional operation should be

restricted to the conditions as specified in the operations sections of this data sheet. Exposure to absolute maximum

rating conditions for extended periods may affect device reliability.

2. The Si2107/08/09/10 is a high-performance RF integrated circuit. Handling and assembly of these devices should

only be done at ESD-protected workstations.

4

Preliminary Rev. 0.7

Si2107/08/09/10

Table 3. DC Characteristics

(V_3.3= 3.3 V ±10%, V_1.8= 1.8 V ±10%, T_A= 0–70 ºC)

Parameter

Symbol

Test Condition

45 Msps, CR 7/8*

20 Msps, CR 2/3*

45 Msps, CR 7/8*

20 Msps, CR 2/3*

SCL(25), SDA(26)

Min

—

2.3

0

Typ

313

298

292

217

—

Max

—

Unit

mA

V

Supply Current, 3.3 V

I

3.3

—

Supply Current, 1.8 V

I

—

1.8

—

Input high voltage

Input low voltage

Input leakage

V

5.5

0.8

±10

—

IH

V

I

—

V

IL

I

—

2.4

—

µA

V

Output high voltage

Output low voltage

Output leakage

V

—

OH

V

I

—

0.4

±10

V

OL

—

µA

OL

*Note: LNB dc-dc converter disabled; LNB_EN (CEh[2]) = 0.

Table 4. RF Electrical Characteristics

Parameter

Input power, single channel

Aggregate input power

Input impedance, balanced

Return Loss

Symbol

Test Condition

Min

–81

—

Typ

—

Max

–23

–7

Unit

dBm

Ω

P

i,ch

P

—

i,agg

Z

= 75 Ω

—

75

—

in

SOURCE

—

–10

75

—

dB

Dynamic voltage gain range

Maximum voltage gain

Noise figure

Δ

—

dB

GV

G

—

55

—

dB

V(max)

1

NF

Max gain

—

+9.5

+15

—

+12.5

—

dB

2

3

IP3

Min gain

+5

—

dBm

dBc/Hz

°rms

LO leakage

L

950 to 2150 MHz

100 kHz offset

1 MHz offset

–70

–94

2.8

LO

—

–97

2.1

LO SSB phase noise

N

LO

—

LO DSB phase noise (integrated)

10 kHz to 1/2 Baud

Rate

—

RF synthesizer spurious

At 20 MHz offset

At 2 kHz offset

—

–40

–130

100

—

dBc/Hz

µs

Reference oscillator phase noise

LO oscillator settling time

t

s,LO

Notes:

1. Max gain = +55 dB.

2. IM3 can be calculated as follows: IM3 = 2 x (IP3 – P_in).

3. Min gain = –35 dB.

Preliminary Rev. 0.7

5

Si2107/08/09/10

Table 5. Receiver Characteristics

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

RF input frequency range

f

950

—

2150

MHz

in

Fine tune step size

f

—

1

125

—

45

—

kHz

MBaud

MHz

step

Symbol rate range

R

S

Carrier offset correction range

f

—

±6

car_off

Table 6. LNB Supply Characteristics (Si2108/10 Only)

Parameter

Supply Voltage

Symbol

Test Condition

Min

8

Typ

12

Max

13.2

290

19.5

19.0

14.0

1

Unit

V

LNB_IN

Converter Switch Frequency

237

17.75

17.0

12.75

12.5

—

264

kHz

V

VHIGH = 1010

VHIGH = 0000

VLOW = 0110

VLOW = 0100

13 to 18 V

18.625

18.0

13.375

13.25

—

Output HIGH voltage

V

Output LOW voltage

V

Low to High Transition Time

High to Low Transition Time

Line Regulation

ms

ΔmV

18 to 13 V

—

1

V

= 8 to

—

200

CC

13.2 V

I = 500 mA

o

Load Regulation

I = 50 to

—

200

ΔmV

o

500 mA

V

= 12 V

CC

Load Capacitance Tolerance

Output current limiting

DiSEqC 1.x

DiSEqC 2.x

ILIM = 00

ILIM = 01

ILIM = 10

ILIM = 11

—

1.6

22

650

50

6

0.75

0.25

550

650

850

1000

1.92

24

µF

400

500

650

800

1.4

20

mA

A

Maximum LNB Supply Current

Tone Frequency

IMAX = 01

f

kHz

mV

%

tone

Tone Amplitude

500

40

800

60

Tone Duty Cycle

Tone Rise and Fall Time

3

10

µs

Tone Detector Frequency Capture

Range

17.6

—

26.4

kHz

Tone Detector Input Amplitude

200

—

1000

mV

pp

Note: Specifications based on recommended schematics in Figure 5 and Figure 6.

6

Preliminary Rev. 0.7

Si2107/08/09/10

Table 7. I2C Bus Characteristics

Parameter

Symbol

Test Condition

Min

0

Typ

—

Max

400

—

Unit

kHz

µs

SCL Clock Frequency

f

SCL

BUF

Bus Free Time between START and

STOP Condition

t

1.3

—

Hold Time (repeated) START Condition.

(After this period, the first clock pulse is

generated.)

t

0.6

—

µs

HD, STA

LOW Period of SCL Clock

HIGH Period of SCL Clock

Data Setup Time

t

1.3

0.6

100

0

—

µs

ns

µs

ns

µs

LOW

t

HIGH

t

—

SU, DAT

HD, DAT

Data Hold Time

t

0.9

300

—

SCL and SDA Rise and Fall Time

t t

—

r, f

Setup Time for a Repeated START Con-

dition

t

0.6

SU, STA

Setup Time for STOP Condition

Capacitive Load for each Bus Line

t

0.6

—

µs

pF

SU,STO

C

400

B

SDA

t_r

t_BUF

t_SU;DAT

t_f

t_LOW

t_r

t_HD;STA

t_SP

SCL

t_SU;STO

t_HD;STA

t_HD;DAT

t_HIGH

t_SU;STA

S_r

S

P

S

2

Figure 1. I C Timing Diagram

Preliminary Rev. 0.7

7

Si2107/08/09/10

Table 8. MPEG-TS Specifications (Rising Launch and Capture)

Parameter

Symbol

Test Condition

Serial mode

Min

11.3

77

Typ

—

Max

28.6

8000

6.9

Unit

ns

Clock cycle time

t

cycle

Parallel mode

—

ns

Clock low time

Clock high time

Hold time

t

Serial mode (TSSCR = 11)

Serial mode (TSSCR = 00)

Parallel mode

5.1

—

ns

clow

12.0

39

—

15.8

4000

ns

—

ns

t

Serial mode (TSSCR = 01)

Serial mode (TSSCR = 11)

Parallel mode

5.1

12.0

39

—

6.9

15.8

4000

—

ns

chigh

—

t

Normal operation

0

hold

Data delayed (TSDD = 1)

Clock Delayed (TSCD = 1)

Normal operation

—

1.5

–1.5

—

Setup time

t

—

t

– 1.5

—

setup

cycle

Data delayed (TSDD = 1)

Clock Delayed (TSCD = 1)

—

– 3.0

—

t

—

cycle

Access time

t

—

1.5

—

access

t_cycle

C

L

TS_CLK

TS_DATA

t_hold

t_setup

t_access

Figure 2. MPEG-TS (Rising Launch and Capture) Timing Diagram

8

Preliminary Rev. 0.7

Si2107/08/09/10

Table 9. MPEG-TS Specifications (Rising Launch, Falling Capture)

Parameter

Symbol

Test Condition

Serial mode

Min

11.3

77

Typ

—

Max

28.6

8000

6.9

Unit

ns

Clock cycle time

t

cycle

Parallel mode

—

ns

Clock low time

Clock high time

Hold time

t

Serial mode (TSSCR = 11)

Serial mode (TSSCR = 00)

Parallel mode

5.1

—

ns

clow

12.0

39

—

15.8

4000

ns

—

ns

t

Serial mode (TSSCR = 01)

Serial mode (TSSCR = 11)

Parallel mode

5.1

12.0

39

—

6.9

15.8

4000

—

ns

chigh

t

Normal operation

t

/2

cycle

hold

Data delayed (TSDD = 1)

Clock Delayed (TSCD = 1)

Normal operation

—

t

/2 + 1.5

/2 – 1.5

/2 – 3.0

—

cycle

—

Setup time

t

—

setup

Data delayed (TSDD = 1)

Clock Delayed (TSCD = 1)

—

t

—

cycle

—

t

/2

—

cycle

Access time

t

—

1.5

—

access

t_cycle

C

L

TS_CLK

TS_DATA

t_hold

t_setup

t_access

Figure 3. MPEG-TS (Rising Launch, Falling Capture) Timing Diagram

Preliminary Rev. 0.7

9

Si2107/08/09/10

2. Typical Application Schematic

2

V D D _ L N A

A L 1 X T

A L 2 X T

1

3 5

3 4

R E X T

2

A D D R

A L

V D D _ X T

3

3 3

V D D _ M I X

O U X T T

4

3 2

V D D _ P L L 3 3

3 1

/ R L K I N / G T P O

V D D _ B B

5

V D D _ A D C

6

3 0

T S _ E R R

2 9

/ V S E E T D N T

7

1

/ L N N E B T G

N C / I S E N

D R C / L N B 2

T S _ V A L

2 8

8

T S _ S Y N C

2 7

9

S D A

1 0

1 1

1 2

1 3

2 6

R E S E T

S C L

2 5

D C S / P W M

V D D _ D I G

A 7

A 6

_ D S T A T

2 4

2 3

1 8

_ D S T A T

10

Preliminary Rev. 0.7

Si2107/08/09/10

Si2110 LNB Control

Preliminary Rev. 0.7

11

Si2107/08/09/10

Si2110 LNB Control

12

Preliminary Rev. 0.7

Si2107/08/09/10

3. Bill of Materials

Table 10. Si2107/08/09/10 Bill of Materials

Component

Description

Vendor

C1,C2,C4,C6,C10,C8,C9,

C10,C13,C14,C15,C16

0.1 µF, X7R, ±20%

C5

0.01 µF, X7R, ±20%

33 pF, 6 V, NP0, ±10%

C3,C7,C11,C12

C19,C36

33 pF, 50 V, NP0, ±10%

2

D4

Transient voltage suppressor, 20 V

Littlefuse SMCJ20CA

J1

Connector, F-type, 75 Ω, 950-2150 MHz

4.53 kΩ, 62.5 mW, ±1%

See Note 1

R2

TC1-5

X1

Balun transformer

Anaren B0922J7575A00

Silicon Laboratories

Y1

20 MHz, 20 pF, 50 ppm, 20 Ω ESR

Si2107/08/09/10

U1

Notes:

1. Tuning component values depend on the balun selected and layout. Contact Silicon Laboratories for

assistance reviewing layouts and selecting matching components.

2. The transient voltage suppression device should be selected to match the surge requirements of the

application.

Preliminary Rev. 0.7

13

Si2107/08/09/10

Table 11. DiSEqC 1.x LNB Supply Bill of Materials (Si2108/10 Only)

Component

C30

Description

Vendor

47 µF, 25 V,Electrolytic,± 20%

0.47 µF, 25 V, X7R,± 20%

22 nF, 25 V, X7R, ± 20%

0.22 µF, 25 V, X7R, ± 20%

4.7 µF, 25 V, X7R, ± 20%

C31

C32

C33

C34

D1

CMPSH1-4, 40 V, 1 A

ZHCS750TA, 40 V, 750 mA

Central Semiconductor

Zetex

D3

L2

MMBD1705, Dual diode, 20 V, 25 mA

Fairchild

DR78098,33 µH,1.2 A, 20%

SD0705-330K-R-SL

Datatronic

ACT

Q1

ZXMN3B14

FDN337N

Zetex

Fairchild

Q2

Q3,Q5,Q6

Q4

FMMT618

Zetex

Fairchild

Zetex

MMBT3904

FMMT718

R5

1.3 Ω, 500 mW, ±5%

33 Ω, 250 mW, ±5%

10 kΩ, 62.5 mW, ±5%

1 kΩ, 250 mW, ±5%

680 Ω, 125 mW, ±5%

0.22 Ω, 1 W, ±5%

22 kΩ, 62.5 mW, ±1%

20 kΩ, 62.5 mW, ±5%

33 Ω, 62.5 mW, ±5%

43 kΩ, 62.5 mW, ±5%

3 kΩ, 100 mW, ±5%

2 kΩ, 250 mW, ±5%

2.2 kΩ, 62.5 mW, ±1%

R6

R7

R8

R9

R10

R11

R12,R20

R13

R14

R15

R16

R17

14

Preliminary Rev. 0.7

Si2107/08/09/10

Table 12. DiSEqC 2.x LNB Supply Bill of Materials (Si2108/10 Only)

Component

C17

Description

Vendor

1200 pF, 25 V, X7R, ± 20%

47 µF, 25 V,Electrolytic,± 20%

0.47 µF, 25 V, X7R,± 20%

22 nF, 25 V, X7R, ± 20%

0.22 µF, 25 V, X7R, ± 20%

4.7 µF, 25 V, X7R, ± 20%

C30

C31,C35

C32

C33

C34

D1

CMPSH1-4, 40 V, 1 A

ZHCS750TA, 40 V, 750 mA

Central Semiconductor

Zetex

D3

L2

MMBD1705, Dual diode, 20 V, 25 mA

Fairchild

DR78098,33 µH,1.2 A, 20%

SD0705-330K-R-SL

Datatronic

ACT

L3

DR78097,100 µH, 500 mA, 20%

SD0504-101K-R-SL

Datatronic

ACT

Q1

ZXMN3B14

FDN337N

Zetex

Fairchild

Q2

Q3,Q5,Q6

Q4

FMMT618

Zetex

Fairchild

Zetex

MMBT3904

FMMT718

R5

1.3 Ω, 500 mW, ±5%

33 Ω, 250 mW, ±5%

10 kΩ, 62.5 mW, ±5%

1 kΩ, 250 mW, ±5%

680 Ω, 125 mW, ±5%

0.22 Ω, 1 W, ±5%

22 kΩ, 62.5 mW, ±1%

20 kΩ, 62.5 mW, ±5%

33 Ω, 62.5 mW, ±5%

43 kΩ, 62.5 mW, ±5%

3 kΩ, 100 mW, ±5%

2 kΩ, 250 mW, ±5%

2.2 kΩ, 62.5 mW, ±1%

16 Ω, 250 mW, ±5%

R6

R7

R8

R9

R10

R11

R12,R20

R13

R14

R15

R16

R17

R18

Preliminary Rev. 0.7

15

Si2107/08/09/10

4. Part Versions

There are four pin- and software-compatible versions of

this device. All versions include the L-band tuner, DVB-

S/DSS demodulator and channel decoder, and LNB

signaling controller. Furthermore, the Si2108 and

Si2110 integrate an efficient LNB supply regulator while

allowing operation with an external LNB supply

regulator circuit. The LNB supply controller utilizes a

step-up converter architecture. In case operation with

an external regulator is desired, Si2107 and Si2109 can

be used; these do not integrate the LNB step-up dc-dc

controller.

On the other hand, the Si2109 and Si2110 integrate an

on-chip “blindscan” accelerator, which allows the

implementation of a very fast channel scan, an

important feature for end products targeted to free-to-air

(FTA) applications in which channel locations are

unknown. Si2107 and Si2108 do not integrate this

accelerator and are a good fit when symbol rates and

frequencies of satellite channels are known, as in the

case of pay-TV receivers or for FTA receivers in which

the embedded firmware contains the channel tuning

information. Table 13 summarizes the differences

between part versions.

Table 13. Device Versions

Part

DVB-S/DSS

LNB Supply

Regulator

On-Chip

Blindscan

Accelerator

Number Integrated Tuner/

Demodulator with

Integrated LNB

Messaging

Si2110

Si2109

Si2108

Si2107

Y

N

Y

N

Y

N

16

Preliminary Rev. 0.7

Si2107/08/09/10

solution for the free-to-air (FTA) and common interface

(CI) market. Automatic acquisition and fade recovery

5. Functional Description

The Si2107/08/09/10 is a family of highly-integrated sequencers are also included to reduce the required

CMOS RF satellite receivers for DVB-S and DSS amount of software interaction and to simplify the

applications. The device is an ideal solution for satellite overall design. The output of the demodulator is

set-top boxes, digital video recorders, digital televisions, quantized into a 4-bit number by the soft-decision

and satellite PC-TV. The IC incorporates a tuner, decoder. The use of soft-decision decoding improves

demodulator, and LNB controller into a single device the error correction capabilities of the channel decoder.

resulting in a significant reduction in board space and

5.3. DVB-S/DSS Channel Decoder

external component count. The device supports symbol

rates of 1 to 45 Msym/s over a 950 to 2150 MHz range. The Si2107/08/09/10 integrates a full-channel decoder,

A full suite of features including automatic acquisition, which can be configured in either DSS or DVB-S mode

fade recovery, blind scanning, performance monitoring, and consists of a soft-decision Viterbi decoder, de-

and DiSEqC™ Level 2.2 compliant signaling are interleaver, Reed-Solomon decoder, and energy-

supported. The Si2110 and Si2108 further add short- dispersal descrambler.

circuit protection, overcurrent protection, and a step-up

5.3.1. Viterbi decoder

dc-dc controller to implement a low-cost LNB supply.

The Viterbi decoder performs maximum likelihood

Furthermore, the Si2109 and Si2110 have an on-chip

estimation of convolutional codes in compliance with

blindscan accelerator. An I2C bus interface is used to

DVB-S and DSS standards. The decoder is capable of

configure and monitor all internal parameters.

detecting code rate, puncturing pattern phase, 90°

phase rotation, and I/Q interchange. Supported code

rates are listed in Table 14

5.1. Tuner

The tuner is designed to accept RF signals within a 950

to 2150 MHz frequency range. The inputs are matched

to a 75 Ω coaxial cable in a single-ended configuration.

Table 14. Viterbi Code Rates

The tuner block consists of a low-noise amplifier (LNA),

DVB-S

1/2

DSS

—

variable gain attenuators, a local oscillator, quadrature

downconverters, and anti-aliasing filters. The LNA and

variable gain stages provide balance between the noise

figure and linearity characteristics of the system. When

all gain stages are combined, the device provides more

than 80 dB of gain range. The desired tuning frequency

can be adjusted in intervals of 125 kHz, without the aid

of external varactors, using a unique two-stage tuning

algorithm that is supplied with the software driver. The

rapid settling time of the local oscillator improves

channel acquisition and switching performance. The

PLL loop filter has been completely integrated into the

2/3

—

3/4

5/6

—

6/7

—

7/8

device resulting in low tuner phase noise, improved The device allows monitoring of the Viterbi bit-error rate

spurious response, and reduced BOM cost. An external (BER) over a finite or infinite measurement window.

20 MHz crystal unit generates the reference frequency

for the system.

5.3.2. Convolutional De-Interleaver

The deinterleaver disassembles the Reed-Solomon

(RS) code words, which were interleaved by the

modulator, to provide better resilience against burst

errors. The Si2110/09 performs deinterleaving

according to DVB-S and DSS standards.

5.2. Demodulator

The demodulator supports QPSK and BPSK

demodulation of channels between 1 to 45 Msym/s. It

incorporates the following functional blocks: analog-to-

digital converters (ADCs), dc notch filters, I/Q imbalance

5.3.3. Reed-Solomon decoder

corrector, decimation filters, matched filters, equalizer, The Si2109/10 supports RS codes in compliance with

digital automatic gain controls, and a soft-decision DVB-S and DSS specifications. Both standards use a

decoder. The demodulator supports rapid channel shortened Reed-Solomon code, which can correct up to

acquisition using an advanced carrier offset estimation eight byte errors per information packet. DVB-S utilizes

algorithm. When combined with the Si2209/10’s blind 204 byte codes. DSS utilizes 146 byte codes.

scanning capabilities, the device becomes an ideal

Preliminary Rev. 0.7

17

Si2107/08/09/10

The device allows monitoring of correctable bit,

correctable byte, and uncorrectable packet errors over a

finite or infinite measurement window. The device also

includes a total BER monitor, which compares received

data from a modulated PRBS sequence against the

same sequence generated from an on-chip PRBS

generator.

5.6. On-Chip LNB DC-DC Step-Up Control-

ler (Si2108/10 Only)

Next to the LNB message signaling controller, the

device also integrates the LNB supply regulator

controller. The supported LNB supply regulator

architecture consists of a step-up dc-dc (boost)

converter followed by an efficient filter, linefeed, and

DiSEqC transmit/receive circuit, which implements a

very power-efficient LNB supply solution. This facilitates

a complete LNB supply circuit with only a minimal

number of external components.

5.3.4. Energy-dispersal descrambler

The descrambler removes the energy dispersal

scrambling introduced by the DVB-S process. The

descrambler is automatically bypassed in DSS mode.

5.4. On-Chip Blindscan Controller

(Si2109/10 Only)

5.7. Crystal Oscillator

The crystal oscillator requires a crystal with a resonant

The device includes on-chip circuitry to facilitate fundamental frequency of 20 MHz to generate the

extremely fast detection of available satellite channels. reference frequency for the local oscillator. A single

For each valid DVB-S/DSS channel, the tuning crystal can be shared between two devices by utilizing

frequency and symbol rate, which can be stored by the the master-slave configuration shown in Figure 6.

host for subsequent tuning, are determined. On Si2107/

08 devices, the host needs to provide the channel

tuning frequency and symbol rate to the device.

C11

XTAL1

5.5. LNB Signaling Controller

Y1

The device supports several LNB signaling methods

including dc voltage selection, continuous tone, tone

burst, DiSEqC 1.x- and DiSEqC 2.x-compliant

messaging, and several combinations of these to allow

simultaneous operation with legacy tone/burst and

DiSEqC-capable peripherals.

XTAL2

C12

XTOUT

Si2107/09 includes the capability to convert I2C

signaling commands to signals that interface to an

external LNB supply regulator circuit. In the case of (bi-

directional) DiSEqC operation, the device modulates

(and demodulates) the PWK data to (and from) an

internal message FIFO, which the host uses to write

(and read) DiSEqC messages. In the case of

transmission, the device can generate either the 22 kHz

tone burst directly or generate a tone envelope for when

an external LNB supply controller is used, which

includes the 22 kHz oscillator.

Figure 6. Master-Slave Crystal Sharing

18

Preliminary Rev. 0.7

Si2107/08/09/10

All signals on the MPEG-TS output interface can be

individually tri-stated using bits TSE_OE, TSV_OE,

6. Operational Description

The following sections discuss the user-programmable TSS_OE, TSC_OE, and TSD_OE.

functionality offered by the corresponding register map

Transport stream data can be output in a parallel byte-

sections. Refer to Table 19, “Register Summary,” on

page 31 and detailed register descriptions starting on

page 35.

wide mode or a serial bit-wide mode for system-level

flexibility. Selection of the interface mode is controlled

via the TSM bit. In serial mode, data is output on

TS_DATA[0] while TS_DATA[7:1] are held low. The

direction of the serial data stream may be programmed

to output in an MSB or LSB first direction using the

TSDF bit. Parity data may be optionally zeroed by

setting the TSPG bit. To support board-level timing

modifications, the data stream may be delayed by

setting TSDD.

6.1. System Configuration

The MPEG Transport Stream (TS) output interface

carries the decoded satellite data to external devices for

further processing. Both DVB-S and DSS receiver

modes and associated output data packet formats are

supported. Mode selection is controlled via the system

mode register, SYSM. QPSK or BPSK demodulation is

set via the modulation type (MOD) register.

The transport stream clock can be programmed such

that data is transitioning on its rising or falling edge

using the TSCE bit. When operating in serial mode, the

transport stream clock mode bit, TSCM, can be used to

select either a gapped or continuous clock mode. In the

gapped mode, the clock is active only when data is

being output. For this, parity information is not

considered data when the TSPG is set to output zero

data during parity. In the continuous mode, the clock

runs without regard to data being output, and the user

uses TS_VAL as a data strobe. To support board-level

timing modifications, the clock stream may be delayed

by register bit TSCD.

The MPEG-TS output interface consists of the following

output pins:

ꢀ TS_DATA[7:0]

ꢀ TS_CLK

Data

Clock

ꢀ TS_SYNC

ꢀ TS_VAL

Sync/Frame Start Indicator

Valid Data Indicator

Uncorrectable Packet Error

ꢀ TS_ERR

The start of a TS frame is indicated by the TS_SYNC

signal. The TS_SYNC signal is a pulse that is active

during the sync byte in a DVB-S frame or during the first

byte of a DSS frame and is active only while TS

synchronization exists. In serial mode, the TS_SYNC

pulse can be programmed to be active for the whole

byte, or the first bit only, by setting the TSSL bit. The

polarity of the TS_SYNC pulse can be programmed to

be either active high or active low using the TSSP bit.

In serial mode, the transport stream clock rate range is

determined by the TSSCR register. The exact rate is

determined during the acquisition process. The range

that minimizes the difference between the effective

transport stream data rate and the clock rate should be

chosen. The recommended settings are listed in

Table 15.

The TS_VAL output is used to indicate when valid data

is present. TS_VAL is active during the MPEG-TS frame

packet data and inactive while parity data is being

output or when there is no TS synchronization. The

polarity of the TS_VAL output can be programmed to be

active high or active low using the TSVP bit.

Table 15. Serial MPEG-TS Clock Frequency

TSSCR

00

Baud Rate

40–50 Msps

30–40 Msps

19–30 Msps

1–19 Msps

Serial Clock Rate

80–88.5 MHz

The TS_ERR output indicates that an uncorrectable

error has been detected in the RS decoding stage and

that the current TS data packet contains uncorrectable

errors. The TS_ERR output is active during the entire

erred TS frame. The polarity of TS_ERR can be

programmed to be active high or active low using the

TSEP bit.

01

76.8–82.8 MHz

54.9–59.2 MHz

35–37.7 MHz

10

11

Figure 7 illustrates the parallel data mode. Figure 8

illustrates the continuous and gapped serial data

modes.

Preliminary Rev. 0.7

19

Si2107/08/09/10

Parallel Data Mode

TS_CLK, rising edge

TS_DATA[7:0]

TS1 (sync)

TS188

TS2

RS1

TS_SYNC active high

TS_VAL active high

TS_ERR active high

Figure 7. MPEG-TS Parallel Mode

Continuous Serial Data Mode

TS_CLK rising edge

TS1 (sync)

TS2

TS188

RS1

TS1 (sync)

TS2

TS_DATA[0]

TS_SYNC, active low/1-bit wide

TS_VAL active low

TS_ERR, active low

Gapped Serial Data Mode

TS_CLK falling edge/ gapped

TS1 (sync)

RS1

TS2

TS188

TS2

TS1 (sync)

TS_DATA[0]

TS_SYNC active high

TS_VAL active high

TS_ERR active high

Figure 8. MPEG-TS Serial Modes

The device has one output pin (pin 30), which can be

configured as either a receiver lock indicator, general

purpose output, or interrupt output, using the pin select

register, PSEL. The receiver lock indicator provides a

signal output for register bit RCVL. The general purpose

output reflects the polarity of register bit GPO. The

interrupt output is discussed further in “6.2. Interrupts”.

6.2. Interrupts

The device is equipped with several sticky interrupt bits

to provide precise event tracking and monitoring.

Next to interrupts being signaled via the I2C register

map, the user can program one of the device terminals

(INT) as a dedicated interrupt pin via the pin select

register bit, PSEL. The device contains an extensive

collection of interrupt sources that can be individually

masked from the INT pin using the corresponding

interrupt enable register bits, labeled with suffix “_E”.

Thus, the INT output is a logical-OR of all enabled

interrupts. Generation of the channel interrupt on pin

INT can be masked off by using the interrupt enable bit,

INT_EN. Note that interrupt reporting in the register

map is not affected by INT_EN.

The user can configure the device such that

components of the channel decoder are bypassed. This

is controlled by the energy-dispersal descrambler

bypass bit, DS_BP, the Reed-Solomon decoder bypass

bit, RS_BP, and the convolutional de-interleaver bypass

bit, DI_BP. The use of these bypass options is defined

for the implementation of a BER test on a known

modulated PRBS data sequence as explained later in

"6.5. Channel Decoder" on page 24.

20

Preliminary Rev. 0.7

Si2107/08/09/10

The interrupt signal polarity can be configured to be Interrupt bits are set by the device to 1 when an

active high or active low using the interrupt polarity bit, interrupt occurs. The host clears an interrupt bit by

INTP. The interrupt signal type can be configured to be writing a 1 again, at which time the device resets the

CMOS output or open-drain/source output using the interrupt bit to zero. Table 16 illustrates the interrupt

interrupt type bit, INTT.

sources and their associated status, enable, and

interrupt bits.

Table 16. Events, Interrupts, and Status Bits

Event

Interrupt Bit

RCVL_I

RCVU_I

TUNL_I

AGCL_I

AGCTS_I

CEL_I

Enable Bit

RCVL_E

RCVU_E

TUNL_E

AGCL_E

AGCTS_E

CEL_E

Status Bit

RCVL (0 –>1)

RCVL (1 –> 0)

TUNL (0 –> 1)

AGCL (0 –> 1)

AGCTS (0 –> 1)

CEL (0 –> 1)

SRL (0 –> 1)

STL (0 –> 1)

STL (1 –> 0)

CRL (0 –> 1)

CRL (1 –> 0)

VTL (0 –> 1)

VTL (1 –> 0)

FSL (0 –> 1)

FSL (1 –> 0)

AQF (0 –> 1)

CNS (1 –> 0)

VTBRS (1 –> 0)

RSERS (1 –> 0)

FE (0 –> 1)

Receiver lock

Receiver unlock

Tuner lock

AGC lock

AGC threshold

Carrier estimation lock

Symbol rate estimation lock

Symbol timing lock

Symbol timing unlock

Carrier recovery lock

Carrier recovery unlock

Viterbi lock

SRL_I

SRL_E

STL_I

STL_E

STU_I

STU_E

CRL_I

CRL_E

CRU_I

VTL_I

CRU_E

VTL_E

Viterbi unlock

VTU_I

VTU_E

Frame synchronizer lock

Frame synchronizer unlock

Acquisition fail

FSL_I

FSL_E

FSU_I

FSU_E

AQF_I

AQF_E

CN_E

C/N measurement complete

Viterbi BER measurement complete

RS measurement complete

Message FIFO empty

Message FIFO full

Message received

Message parity error

Message receive timeout

Short-circuit detect

Overcurrent detect

CN_I

VTBR_I

RSER_I

FE_I

VTBR_E

RSER_E

FE_E

FF_I

FF_E

FF (0 –> 1)

MSGR_I

MSGPE_

MSGTO_I

SCD_I

OCD_I

MSGPE_E

MSGR_

MSGTO_E

SCD_E

OCD_E

MSGR (0 –> 1)

MSGPE (0 –> 1)

MSGTO (0 –> 1)

SCD (0 –> 1)

OCD (0 –> 1)

Preliminary Rev. 0.7

21

Si2107/08/09/10

6.3. Receiver Status

During receive operation, the host can retrieve

information on the status of AGC lock (AGCL), carrier

estimation lock (CEL), symbol rate estimation lock

(SRL), symbol timing lock (STL), carrier recovery lock

(CRL), Viterbi decoder lock (VTL), frame sync lock

(FSL), and overall receiver lock (RCVL).

Acquisition Start

Calibration

done

LO Tuning

During channel acquisition, the host can retrieve

information on error conditions due to: AGC search

(AGCF), carrier estimation (CEF), symbol rate search

(SRF), symbol timing search (STF), carrier recovery

search (CRF), Viterbi code rate search (VTF), frame

sync search (FSF), and overall receiver acquisition

(AQF),

done

Analog AGC Search

done

Stage fail

CFO Estimation¹

lock

6.4. Tuning Control

Symbol Rate Estimation¹

lock

The Si2107/08/09/10 utilizes a unique two-stage tuning

algorithm to provide optimal RF reception. The input

signal is first mixed down to a low-IF frequency by a

coarse tuning stage and then down to baseband by a

fine-tune mixer. The user programs both coarse and

fine-tuning frequencies using the CTF and FTF

registers.

Stage fail but

STL is locked

Stage fail

Symbol Timing Loop¹

Stage fail

and STL

unlocked

lock

Carrier Frequency Loop¹

An algorithm (supplied with the reference software

driver) is used to automatically calculate the required

values. As part of the tuning process, the sample rate,

fs, should also be programmed via the ADCSR register.

Values between 192 and 207 MHz are supported. An

algorithm is supplied with the reference software driver

to automatically select the optimal sampling rate.

Stage fail

Viterbi Search²

Frame Search²

Receiver locked

6.4.1. Automatic Acquisition

The receiver acquisition sequence consists of the

following stages: Analog AGC Search, Carrier Offset

Estimation, Symbol Rate Estimation, Symbol Timing

Recovery, Carrier Recovery, Viterbi Search, and Frame

Synchronization. For the receiver to lock, each stage

must run to completion or declare lock as shown in

Figure 9. If a given stage is unable to achieve lock after

exhausting a parameter search range or exceeding the

timeout period, it asserts a fail signal.

1. Acquisition fail if stage fails n times in a row.

2. Acquisition fail if stage completes parameter range

without locking.

Figure 9. Acquisition Sequence (Symbol Rate

Estimation Available on Si2109/10 Only)

6.4.2. Carrier Offset Estimation

The desired carrier frequency may be offset from its

nominal position due to the imperfections and

temperature dependencies of the LNB. The carrier

offset estimator uses a search procedure to identify,

track, and remove this frequency offset from the system.

To initiate the acquisition sequence, the user should

program the acquisition start bit, AQS. All search

parameters must be specified before initiating the

acquisition. Upon completion of the acquisition

sequence, the AQS bit is automatically cleared. The

acquisition sequence can be aborted at any time by

clearing the AQS bit.

Seven different carrier offset estimation search ranges

can be programmed from 0.10 to ~6.0 MHz with register

CESR. Smaller search ranges result in faster search

times.

The status of the acquisition sequence can be

monitored via the registers in the receiver status register

map section. A successful acquisition is reported by the

assertion of the receiver lock bit, RCVL. A failed

acquisition is reported by the assertion of the acquisition

fail bit, AQF.

When carrier offset estimation is complete, the CEL bit

is asserted. If an error is detected during carrier offset

estimation, the CEF bit is set. Carrier offset estimation

commences under the control of the acquisition

22

Preliminary Rev. 0.7

Si2107/08/09/10

sequencer.

The symbol timing recovery loop is responsible for

acquiring and tracking the symbol timing of the

incoming data signal. When lock is achieved, the

symbol timing loop lock indicator, STL, is asserted. If

symbol timing lock is not achieved within a predefined

timeout period, the device declares symbol timing loop

failure by asserting the STF bit. The symbol timing

recovery loop commences under the control of the

acquisition sequencer.

After the completion of a search, the estimated carrier

offset is stored in the carrier frequency error register,

CFER. If no signal is found, the CEF bit is asserted. The

value contained in CFER may be optionally transferred

to the CFO register to adjust the search center

frequency and permit the utilization of a smaller search

range for subsequent acquisitions. This relationship can

be expressed by the following equation:

6.4.6. Automatic Fade Recovery

f_s

2¹⁵

The device is designed to automatically recover lock in

the event of a fade condition. Fade recovery is

performed when any stage loses synchronization after

receiver lock has been achieved. It is assumed that

symbol rate, code rate, and puncturing pattern have not

changed; so, these parameters remain fixed during the

attempted reacquisition. The fade recovery sequence is

shown in Figure 10.

--------

Search center frequency = f_desired+ CFO ×

Hz

6.4.3. Symbol Rate Estimation (Si2109/10 Only)

The Si2109/10 supports the ability to automatically

detect the symbol rate of a channel when it is unknown.

This feature is ideal for FTA/CI applications where it is

often desirable to rapidly scan (blind scan) and detect

the available channels of a given satellite. If symbol rate

estimation is not required, the user should program the

symbol rate explicitly into the SR register. This is the

only mode of operation for Si2107/08.

The fade recovery sequence continues until either

receiver lock is achieved or a new acquisition is

initiated.

On Si2109/10, the symbol rate unknown bit, SRUK, can

be changed from its default value to activate symbol

rate estimation. The search range must then be

bounded by programming the symbol rate maximum

and minimum registers, SRMX and SRMN. If the

symbol rate search is successful, the estimated symbol

rate is automatically written to the SR register. Smaller

search ranges result in faster search times. Note that

the values stored in the symbol rate, symbol rate

maximum, and symbol rate minimum registers are

sample rate-dependent. This relationship is described

by the following equation:

Calibration

LO Tuning

Analog AGC Search

Fail

Done

CFO Estimation

Done

Symbol Rate Estimation

Unlock

f_s

2²⁴

--------

Actual Symbol Rate = Symbol Rate ×

MHz

Symbol Timing Loop

When symbol rate estimation is complete, the SRL bit is

asserted. If an error is detected during symbol rate

estimation, the SRF bit is also set. The symbol rate

estimator commences under the control of the

acquisition sequencer.

lock

Unlock

Carrier Frequency Loop

lock

Viterbi Search

(Limited)

6.4.4. Carrier Recovery Loop

Unlock

lock

Frame Search

lock

The carrier recovery loop is responsible for acquiring

frequency and phase lock to the incoming signal. When

lock is achieved, the carrier recovery lock indicator,

CRL, is asserted. If carrier recovery lock is not achieved

within a predefined timeout period, the device declares

carrier recovery failure by asserting the CRF bit. The

carrier recovery loop commences under the control of

the acquisition sequencer.

Receiver locked

Figure 10. Fade Recovery Sequence

6.4.5. Symbol Timing Loop

Preliminary Rev. 0.7

23

Si2107/08/09/10

6.4.7. C/N Estimator

6.5.3. Reed-Solomon Error Monitor

A carrier-to-noise estimator is provided to aid in satellite The Reed-Solomon error monitor is capable of counting

antenna positioning. The C/N measurement mode bit, bit, byte, and uncorrectable packet errors. The error

CNM, controls whether the count is performed over a type to be counted is controlled by the Reed-Solomon

fixed-length or infinite window. With a fixed-length error type register, RSERT. The Reed-Solomon error

window, the window size is defined by register CNW. mode bit, RSERM, controls whether the count is to be

Measurements are stored in a 16-bit saturating register, performed over a fixed length or infinite window. The

CNL. Setting the C/N estimator start bit, CNS clears the window size is defined by RSERW. The BER count is

CNL register and initiates the C/N measurement. When stored in a 16-bit saturating register, RSERC. Setting

operating in the finite window mode, the CNS bit is the RS BER measurement start bit, RSERS, clears the

automatically cleared when the measurement is RSERC register and initiates the measurement. When

complete. The CNS bit must be cleared manually in the operating in the finite window mode, the RSERS bit is

infinite mode to stop the count. An external lookup table automatically cleared when the measurement is

is used to translate the measurement into a C/N complete. The RSERS bit must be cleared manually in

estimate for a given setting of the C/N threshold, CNET, the infinite mode, to stop the count.

and a given digital AGC setting.

6.5.4. PRBS BER Tester

To facilitate in-system pseudo random bit sequence

(PRBS) BER testing, the device provides the ability to

6.5. Channel Decoder

6.5.1. Viterbi Decoder

synchronize and track test sequences contained in the

The Viterbi decoder performs maximum likelihood

payload (i.e. not SYNC bytes) of the MPEG data

estimation of convolutional codes in compliance with

stream. A PRBS test pattern must be encoded,

DVB-S and DSS standards. When lock is achieved, the

Viterbi lock indicator, VTL, is asserted. If Viterbi lock is

not achieved after exhausting the specified parameter

space, the device declares Viterbi search failure by

modulated, and injected into the channel to be

23

monitored. The device supports a PRBS 2 – 1 bits

long described by the following polynomial:

G(x) = x²³+ x¹⁸+ 1

asserting the VTF bit. The Viterbi search commences

under the control of the acquisition sequencer.

To enable PRBS testing, the Reed-Solomon error type

The device can be programmed to attempt to

register, RSERT, must be appropriately programmed.

automatically acquire Viterbi lock using all, one, or a

After the device has synchronized to the incoming

subset of the supported code rates using the VTCS

PRBS test pattern, errors are reported in the RSERC

register.

If lock is achieved, the status of the search, including

Measurements can be performed at the output of the

code rate, puncturing pattern phase, 90-degree phase

Viterbi or Reed-Solomon decoder. To record errors at

rotation, and I/Q swap, can be monitored in the Viterbi

the output of the Viterbi decoder, the Reed-Solomon

search status registers, VTRS, VTPS, and VTIQS.

decoder and interleaver must be bypassed by setting

6.5.2. Viterbi BER Estimator

RS_BP and DI_BP in the “System Configuration”

The Viterbi BER estimator measures the frequency of

bit errors at the input of the Viterbi decoder. The Viterbi

BER mode bit, VTERM, controls whether the count is to

be performed over a fixed length or infinite window. The

window size is defined by VTERW. The BER count is

stored in a 16-bit saturating register, VTBRC. Setting

the Viterbi BER measurement start bit, VTERS, clears

the VTBRC register and initiates the measurement.

When operating in the finite window mode, the VTERS

bit is automatically cleared when the measurement is

complete. The VTERS bit must be cleared manually in

the infinite mode to stop the count.

section of the register map. To record errors at the

output of the Reed-Solomon block, the RS_BP bit must

be cleared.

6.5.5. Frame Synchronizer

The output of the Viterbi decoder is aligned into bytes by

detecting sync patterns within the data stream. In DVB-

S systems, the sync byte, 47h, occurs during the first

byte of a 204 byte RS code block. In DSS systems, a

sync byte, 1Dh, is appended to the beginning of each

RS encoded 146-byte block, resulting in 147-byte RS

code blocks. In DSS mode, sync bytes are discarded

before the byte stream is output to subsequent

decoding stages. When lock is achieved, the frame

synchronization lock bit, FSL, is asserted. If lock is not

achieved, the frame synchronizer fail bit, FSF, is

asserted.

24

Preliminary Rev. 0.7

Si2107/08/09/10

The frame synchronizer commences under the control

of the acquisition sequencer.

f_s

-------------------

AGC measurement frequency =

Hz

AGCW

Following frame synchronization lock, the device

examines the byte stream for a possible 180-degree When gain adjustments are made, the device allows up

phase shift. If an inversion is detected, data are inverted to 100 µs for the gain changes to settle before

prior to being output.

beginning the next measurement.

To facilitate a rapid initial acquisition, Si2107/08/09/10

includes an acquisition mode wherein the measurement

window size is reduced by a factor of 64 when

compared to the normal tracking mode.

6.6. Automatic Gain Control

The Si2107/08/09/10 is equipped with the ability to

adjust signal levels via an automatic gain control (AGC)

loop. This ensures that the noise and linearity

characteristics of the signal path are optimized at all

times. AGC settings can be set at 4 points in the analog

signal chain and 2 points in the digital signal chain.

During the AGC search, the device is in acquisition

mode, and the gain is adjusted until the measured

signal power crosses the desired threshold or a limit is

reached. If the signal power crosses the threshold

before reaching a limit, the search completes, and the

6.6.1. Analog AGC

System gain is distributed into four independent stages AGCL bit is asserted. If a gain limit is reached, the

as shown in Figure 11. The gain range of all stages device asserts both the AGCL bit and the AGCF bit.

combined is over 80 dB. When the AGC search

In the normal tracking mode, the device continuously

completes, the AGCL bit is asserted. If an error is

measures the input signal power according to the AGC

encountered during the AGC search, the AGCF bit is

measurement window size. If the absolute value of the

also set. The AGC search commences under the

difference between the AGCTH and AGCPWR exceeds

the value of the AGC tracking threshold, AGCTR, the

control of the acquisition sequencer.

The AGC loop works to automatically adjust the gain of AGC loop adjusts gain settings until the AGCPWR level

each stage to minimize the error between a measured matches AGCTH.

signal power and a desired output level. Signal power is

The AGC gain offset register, AGCO, provides the

measured at the output of the ADC using an internal

ability to apply a static gain offset to the input channel.

rms power calculator. The result is stored in a 7-bit

Silicon Laboratories will provide the recommended

saturating register, AGCPWR. The desired output level

values for this register. It is possible to read out the

is stored in the AGC threshold register, AGCTH. Signal

instantaneous settings of each of the four VGAs from

power measurements occur at a frequency dictated by

the AGC<n>, <n = 1..4>, registers.

the AGC measurement window size, AGCW. This

frequency can be described using the following

equation, where fs equals the ADC sampling rate,

ADCSR.

LPF

OFFSET

LNA

VGA1

VGA2

MIXER

A/D

rms calculator

AGC

AGC Threshold

Figure 11. Analog AGC Control Loop

Preliminary Rev. 0.7

25

Si2107/08/09/10

6.6.2. Digital AGC

When an external LNB supply regulator is used, the

DCS pin is driven high or low depending on the

selection of high or low voltage.

Downstream of the analog VGAs, after A/D conversion

of the signal, there are two points at which the digital

gain can be programmed. Digital AGC1 is used to 6.7.2. Tone Generation

change signal power after removal of adjacent channels

by the (digital) anti-aliasing filter.

Tone-related information is communicated to external

devices via the TGEN pin. The tone format select bit,

By default, DAGC1 is enabled and periodically adjusts TFS, specifies whether the output of TGEN is an

the gain of the I & Q data streams based on a internally-generated tone or a tone envelope. The

comparison of the measured complex RMS level and a frequency of the internal tone generator is governed by

target value. The target value can be selected with the the following equation:

DAGC1T register. Two levels are provided to allow

operation with additional headroom for signal peaks

during signal acquisition. The gain function of DAGC1

can be disabled using DAGC1_EN; then, no gain is

applied to I & Q data streams. The signal measurement

and gain adjustment normally operate continuously,

allowing the gain to track the input level. The

measurement window can be adjusted by register

DAGC1W. The automatic updating of the gain can be

frozen by register bit DAGC1HOLD. This holds the gain

to the last setting. The value of the gain can be read

from the DAGC1 register. It is possible to override the

internal AGC algorithm and provide host-based control

of AGC1 by appropriately programming register bit

DAGC1HOST.

100

----------------------------------------------------------

MHz

f_tone

=

[32 × (TFQ[7:0] + 1)]

Frequencies between 20 and 24 kHz are supported.

The default value of TFQ results in a nominal tone

frequency of 22 kHz. When tone envelope output is

selected, a high signal on TGEN corresponds to "tone

on" while a low signal corresponds to "tone off." When

operating in the “Manual LNB messaging mode”, the TT

bit directly controls the output of the tone or tone

envelope.

6.7.2.1. Continuous Tone

A continuous tone is typically used to select between

the high and low band of an incoming satellite signal.

The LNBCT bit can be set to one to generate a

continuous tone.

Digital AGC2 (DAGC2) is intended to optimally scale the

soft decision outputs of the demodulator prior to Viterbi

decoding. This allows it to compensate for signal level

variations after matched filtering and equalization.

Normally, operation is continuous, but tracking can be

disabled using register bit DAGC2_TDIS. This holds the

gain to the last setting.

6.7.2.2. Tone Burst

The tone burst signaling method can be used to

facilitate the control of a simple two-way switch. Two

types of tone burst are available, as shown in Figure 12.

An unmodulated tone burst persists for 12.5 ms. A

modulated tone burst lasts for the same duration but

consists of a sequence of nine 0.5 ms pulses and 1 ms

gaps. Tone burst selection is controlled via the LNBB

bit. The tone burst command can optionally be disabled

to support systems that do not use tone burst signaling

by setting the burst disable bit, BRST_DS, to one. This

disables the tone/burst generation as part of the

DiSEqC signaling sequence when the device uses

“Automatic LNB messaging mode” as described below.

During AGC operation, the average power of the signal

is compared to a threshold set by register DAGC2T. The

signal power is measured over a finite window specified

by DAGC2W. The gain applied to the signal to make the

input match the programmed threshold can be read

from register DAGC2GA.

6.7. LNB Signaling Controller

All device versions provide LNB signaling capability.

The device supports several LNB signaling methods

including dc voltage selection, continuous tone, tone

burst, DiSEqC 1.x- and DiSEqC 2.x-compliant

messaging. A description of each method follows.

'0' Tone Burst (Satellite A)

Envelope

Tone

'1' Tone Burst (Satellite B)

Envelope

6.7.1. DC Voltage Selection

A constant dc voltage of 18 or 13 V is typically used to

switch the LNB between horizontal and vertical polarity

or clockwise and counterclockwise polarization. The

LNBV bit is used to select the desired voltage.

Tone

12.5 ms

Figure 12. Tone Burst Modulation

26

Preliminary Rev. 0.7

Si2107/08/09/10

6.7.3. DiSEqC™

6.7.3.2. DiSEqC 2.x two-way communication

The DiSEqC signaling method extends the functionality Two-way communication is supported via DiSEqC 2.x-

of the legacy 22 kHz tone by superimposing a compliant messages. When the seventh bit in the

command protocol and adding an optional return framing byte of an outgoing message is set to 1, the

channel. A DiSEqC command normally consists of a device anticipates a response and monitors the line for

framing byte, an address byte, a command byte, and, up to 150 ms for an incoming message. If no message

optionally, one or more data bytes. This format is is detected during the 150 ms monitoring period, the

illustrated in Figure 13.

MSGTO bit is asserted to indicate the time-out

condition. A DiSEqC reply message typically consists of

a single framing byte and optionally one or more data

bytes as shown in Figure 15.

P

FRAMING

ADDRESS

P

COMMAND

DATA

Figure 13. DiSEqC Message Format

The length of a message is specified by MSGL. When

the message length is set to one byte, the message is

modulated using tone burst modulation. When the

message length is set to two or more bytes, the

message is modulated using DiSEqC-compliant

modulation, and the odd parity bit is automatically

added. The DiSEqC modulation scheme is illustrated in

Figure 14.

DATA

FRAMING

P

Figure 15. DiSEqC Reply Format

When a complete message has been received (one or

more bytes followed by 4 ms of silence), the MSGR bit

is asserted. Should parity errors exist in the received

message, the MSGPE flag is also asserted. If the

received message is longer than 6 bytes, the FIFO full

bit, FF, is asserted to indicate that a byte has been

written to FIFO6. The LNB control module writes the

next byte to FIFO1. The length of the received message

is recorded in the MSGRL register.

'1' Data Bit

'0' Data Bit

6.7.4. LNB Signaling Modes

6.7.4.1. Automatic LNB Messaging Mode

1.0 ms

0.5 ms

1.0 ms

0.5 ms

The Si2107/08/09/10 LNB Signaling Controller can fully

manage the generation and sequencing of all LNB

commands. The device is configured in this mode by

appropriately programming the LNB Messaging mode

register, LNBM. To initiate a message sequence, the

user should first program LNB voltage selection (LNBV),

continuous tone enable (LNBCT), tone burst type

(LNBB), and DiSEqC message parameters (MMSG,

MSGL, and FIFO1..6). Subsequently, the LNB

sequence start bit, LNBS, must be set to start the

automated transmission sequence. The device

automatically allocates the required delays between

each signaling method. Prior dc voltage levels and

continuous tones, if present, persist until the sequence

is initiated. A typical sequence is shown in Figure 16.

Figure 14. DiSEqC Compliant Modulation

6.7.3.1. DiSEqC 1.x One-Way Communication

Messages are programmed directly into the device

using a message FIFO that consists of six byte wide

registers, FIFO1–6. The messages must be written in a

first-in-first-out manner such that the first byte of a

message is stored in FIFO1; the second byte is stored

in FIFO2, and so on. If messages are longer than six

bytes, the device asserts the FIFO empty indicator, FE,

as soon as the sixth byte has been read. The LNB

control module then takes its next byte from FIFO1 and

continues the process. The message length must also

be reprogrammed to indicate how many more bytes

remain to be sent. The interval between FIFO reads is

typically 13.5 ms.

Multiple messages can be sent in a sequential manner

by setting the MMSG bit. When this bit is set, the LNB

control module delays continuous tone and tone burst

commands until all messages in the sequence have

been sent. After the current message is transmitted, the

MMSG bit is automatically cleared. The tone burst can

be disabled as part of this sequence depending on the

setting of BRST_DS.

To support cascaded DiSEqC devices, it may be

necessary to repeat commands. Repeated commands

should be separated by at least 100 ms to ensure that

the far-end device is connected to the signaling path. To

facilitate the required 100 ms delay, a four byte

command can be inserted between repeated

commands.

Preliminary Rev. 0.7

27

Si2107/08/09/10

When the sequence has completed, the device clears 6.7.4.2. Step-by-Step LNB Messaging Mode

the LNB sequence start bit, LNBS, automatically. Note By appropriately programming the LNB Messaging

that, when operating in this mode, the DRC pin is high Mode register, LNBM, the device allows for individual

while transmitting and low while receiving.

control of each signaling method by the host. In this

mode, the LNB voltage, LNBV, and LNB continuous

tone enable, LNBCT, take effect once they are set

without waiting for the user to set the LNB sequence

start bit, LNBS.

End of continuous

tone (if present)

Change of voltage

(if required)

1st message (no

reply requested)

2nd message

(reply requested)

Reply to 2nd

message

Start of continuous

tone (if present)

Tone Burst

> 15ms

> 25ms

< 150ms

> 15ms

Figure 16. LNB Signaling Sequence

The DiSEqC message uses the LNBS bit to start When the tone format select bit, TFS, is programmed to

transmission and behaves the same as in Automatic use an external oscillator, the TT bit directly controls the

LNB Messaging Mode. However, the guard intervals output of the TGEN pin, and the TR bit directly reflects

between each signaling method (LNB voltage change, the input of the TDET pin. In this mode, the tone

DiSEqC message, tone burst, and continuous tone direction control bit, TDIR, directly controls the output of

resumption) are controlled by the host.

the DRC pin.

In this mode, the tone burst should be implemented by

using a 1-byte DiSEqC message of all 0s or all 1s

programmed into FIFO1. The device uses appropriate

modulation for the tone burst; i.e., when FIFO1 is

programmed to 00h (rather than a DiSEqC-compliant

modulation for a '00h' byte), no tone is generated. Also,

the device does not expect a reply if FIFO1 is

programmed to FFh; i.e., the assertion of bit7 is not

considered a request for the peripheral to reply in step-

by-step LNB messaging mode.

6.8. On-Chip LNB DC-DC Step-Up

Controller (Si2108/10 Only)

In addition to the LNB signaling controller present on all

device versions, Si2108 and Si2110 devices contain an

internal supply controller circuit. This internal dc-dc

controller can be enabled via register bit LNB_EN. The

internal circuit requires the connection of an external

circuit with a specified bill-of-materials, and this

combination generates the selected LNB voltage with

superimposed one-way or two-way LNB signaling

communications. Si2108/10 devices include short-

circuit protection, overcurrent protection, and a step-up

dc-dc controller to implement a low-cost LNB power

supply using minimal external components. The

required circuit for DiSEqC1.x operation is illustrated in

Figure 5 on page 11. A circuit for DiSEqC2.x operation

is shown in Figure 6 on page 12.

6.7.4.3. Manual LNB Messaging Mode

The manual LNB messaging mode provides the

maximum level of signaling flexibility but at the expense

of increased software interaction. The device is

configured in this mode by appropriately programming

the LNBM register. The continuous tone, tone burst, and

messaging controls are not functional in this mode.

When the tone format bit, TFS, is programmed for use

of the internal oscillator, assertion of the TT bit

modulates the output of the internal tone generator on

the TGEN pin, and the TR bit records the envelope of a

tone presented to the TDET pin.

When the LNB supply circuit is populated, the Si2108/

10 detects a connection to ground on the ISEN pin via

R10 during reset and configures the LNB pins for dc-dc

converter control instead of providing the interfaces to

an external LNB supply regulator discussed in the

previous section. See Table 17.

28

Preliminary Rev. 0.7

Si2107/08/09/10

The nominal level of both the low- and high-output

voltages can be further fine-tuned using the VLOW and

VHIGH registers. Register bit LNBV selects whether to

output high or low dc voltage to the LNB. During

operation, the voltage level of the line can be monitored

via the VMON register.

Table 17. LNB Pin Configuration

LNB Supply Circuit

Connected Unconnected

7

10

9

VSEN

LNB2

ISEN

LNB1

PWM

TDET

DRC

NC

The maximum current draw of the LNB supply can be

set using the IMAX register. The overcurrent threshold

of the LNB supply may be set via the ILIM register. If the

output current exceeds this value, the external LNB

power supply is automatically disabled, and the

overcurrent detect bit, OCD, is asserted. The device

attempts to restore normal operation after 1 s by

supplying power to the line. During the recovery period,

overcurrent detection is disabled for the time specified

by the OLOT register.

8

TGEN

DCS

12

The LNB supply controller is disabled by default. To use

the supply, it must be enabled by setting the LNB enable

bit, LNB_EN. If the LNB supply circuit is connected, the

TFS bit is ignored; the internal LNB supply controller

uses its internal oscillator to generate the 22 kHz tone.

The TFQ setting can still be used to modify the nominal

frequency as explained earlier.

Short circuit protection circuitry operates in conjunction

with overcurrent detection to rapidly identify short-circuit

conditions. If the output is shorted to ground, the

external LNB power supply is automatically disabled,

and the short-circuit detect bit, SCD, is asserted. The

device attempts to restore normal operation after one

second by supplying power to the line. During the

recovery period, short-circuit detection is disabled for

the time specified by the SLOT register.

Selection of high or low voltage outputs the

corresponding PWM control signal for the boost

converter. Since Japan uses a different LNB supply

voltage than the rest of the world (R.O.W.), the device

can be configured to either generate 13 V/18 V

(R.O.W.) or 12 V/15 V (Japan) dc levels via register bit

LNBLVL. To compensate for long cable lengths, a 1 V

boost can be applied to both levels by setting the COMP

bit.

The LNB supply circuit is protected from an overvoltage

condition by design. In the event that the LNB supply

circuit is accidentally connected to a voltage source

greater than the intended output voltage, it remains

operational. The LNB supply circuit resumes normal

operation when the connection to the external voltage

source has been removed.

Preliminary Rev. 0.7

29

Si2107/08/09/10

master. During a write, data is sent from the bus master

to the device. The field labeled “DATA (ADR)” must

7. I2C Control Interface

The I2C bus interface is provided for configuration and contain the 8-bit address of the target register. The data

monitoring of all internal registers. The Si2107/08/09/10 to be transferred to or from the target register must be

supports the 7-bit addressing procedure and is capable placed in the following 8-bit “DATA” field. When the

of operating at rates up to 400 kbps. Individual data auto-increment feature is enabled, INC_DS, the target

transfers to and from the device are 8-bits. The I2C bus register address, is automatically incremented for

consists of two wires: a serial clock line (SCL) and a subsequent data transfers until a STOP condition ends

serial data line (SDA). The device always operates as a the operation.

bus slave. Read and write operations are performed in

accordance with the I2C-bus specification and the

DATA field permitted by I2C. These registers are split

following sequences.

Some registers in the device are larger than the 8-bit

into 8-bit addressable chunks that are uniquely

The first byte after the START condition consists of the identified by a positional suffix. The suffix L indicates the

slave address (SLAVE ADR, 7-bits) of the target device. low-byte; the suffix M indicates the middle-byte (for 24-

The slave address is configured during a hard reset by bit registers only), and the suffix H indicates the high-

setting the voltage on the ADDR pin. Possible slave byte.

addresses and their corresponding ADDR voltages are

listed in Table 18.

To read a multibyte register as a single unit, the low byte

must be read first. This forces the device to sample and

hold the contents of the remaining bytes until the

multibyte read is complete. If a STOP condition occurs

Table 18. I2C Slave Address Selection

before the operation is complete, the buffered data is

discarded.

Fixed Address

11010

LSBs

00

ADDR Voltage (V)

(pullup)

To write a multibyte register as a single unit, the low

byte must be written first. All bytes must be transferred

to the device before the multibyte value is recorded. If a

STOP condition occurs before the operation is

complete, the buffered data is discarded.

V

3.3

11010

01

2/3 x V ±10%

3.3

11010

10

1/3 x V ±10%

3.3

The slave address consists of a fixed part and a

programmable part. The voltage of the ADDR pin is

used to set the two least significant bits of the address

during device power-up according to the table below.

This enables up to four devices to share the same I2C

bus.

11010

11

0 (pulldown)

Four addresses are available, allowing up to four

devices to share the same I2C bus. The R/W bit

determines the direction of data transfer. During a read

operation, data is sent from the device to the bus

Read Operation

S

SLAVE ADR

W

A

DATA (ADR)

A

S_ror P

SLAVE ADR

R

A

DATA

A/A

P

n bytes + ack

Write Operation

SLAVE ADR

S

S_ror P

W

DATA

n bytes + ack

Master

Slave

A = Acknowledge

R = Read (1)

S = START condition

P = STOP condition

W= Write (0)

S_r= Repeated START condition

Figure 17. I2C Interface Protocol

30

Preliminary Rev. 0.7

Si2107/08/09/10

8. Control Registers

The control registers can be divided into three main classes: Initialization, Run-time, and Status. Initialization

registers (“I”) need only be programmed once following device power-up. Run-time registers (“RT”) are the primary

registers for device control. Status registers (“S”) provide device state information. The corresponding category of

each register is indicated in the rightmost column of Table 19.

Table 19. Register Summary

Name

I2C

D7

D6

D5

D4

D3

D2

D1

D0

Addr.

System Configuration

Device ID

System Mode

TS Ctrl 1

00h

01h

02h

03h

DEV[3:0]

INC_DS

REV[3:0]

S

I

MOD[1:0]

SYSM[2:0]

TSDF

TSEP

TSVP

TSSP

TSPCS

INTP

TSSL

TSCD

TSCM

TSDD

TSCE

TSPG

TSM

I

TS Ctrl 2

TSSCR[1:0]

I

Pin Ctrl 1

Pin Ctrl 2

Bypass

04h INT_EN

INTT

TSE_OE TSV_OE

TSS_OE

GPO

TSC_OE

TSD_OE

I

05h

06h

PSEL[1:0]

I

DS_BP

RS_BP

Interrupts

SRL_E

DI_BP

I

Int En 1

Int En 2

Int En 3

Int En 4

Int Stat 1

Int Stat 2

Int Stat 3

Int Stat 4

07h RCVL_E

AGCL_E

CEL_E

STL_E

VTU_E

FE_E

CRL_E

FSU_E

FF_E

VTL_E

FSL_E

AQF_E

MSGTD_E

OCD_E

FSL_I

I

08h RCVU_E AGCTS_E STU_E

CRU_E

09h

0Ah

CN_E

VTBER_E RSER_E MSGPE_E

MSGR_E

SCD_E

VTL_I

I

0Bh RCVL_I

AGCL_I

CEL_I

STU_I

SRL_I

CRU_I

STL_I

VTU_I

FE_I

CRL_I

FSU_I

FF_I

S

0Ch RCVU_I AGCTS_I

AQF_I

0Dh

0Eh

CN_I

VTBR_I

RSER_I MSGPE_I

MSGR_I

SCD_I

MSGTO_I

OCD_I

Receiver Status

Lock Stat 1

Lock Stat 2

Acq Stat

0Fh

10h

11h

AGCL

AGCF

CEL

CEF

SRL

STL

STF

CRL

CRF

VTL

VTF

FSL

FSF

S

RCVL

AQF

SRF

Tuning Control

Acq Ctrl 1

ADC SR

14h

15h

16h

AQS

RT

ADCSR[7:0]

CTF[7:0]

Coarse Tune

Preliminary Rev. 0.7

31

Si2107/08/09/10

Table 19. Register Summary (Continued)

Name

I2C

D7

D6

D5

D4

D3

D2

D1

D0

Addr.

Fine Tune L

Fine Tune H

CE Ctrl

17h

18h

29h

36h

37h

38h

39h

3Ah

3Fh

40h

41h

42h

43h

7Ch

7Dh

7Eh

7Fh

FTF[7:0]

RT

I

FTF[14:8]

CESR[2:0]

CE Offset L

CE Offset H

CE Err L

CE Err H

SR Ctrl

CFO[7:0]

CFO[15:8]

CFER[7:0]

CFER[15:8]

RT

I

SRUK

Sym Rate L

Sym Rate M

Sym Rate H

SR Max

SR[7:0]

SR[15:8]

SR[23:16]

SRMX[7:0]

SRMN[7:0]

SR Min

CN Ctrl

CNS

CNM

CNW[1:0]

CN TH

CNET[7:0]

CNL[7:0]

I

CN L

RT

CN H

CNL[15:8]

Channel Decoder

VT Ctrl 1

VT Ctrl 2

VT Stat

A0h

A2h

A3h

VTCS[5:0]

VTERM

I

VTERS

VTERW[1:0]

RT

S

VTRS[2:0]

VTPS

VTIQS

VT BER Cnt L ABh

VT BER Cnt H ACh

VTBRC[7:0]

VTBRC[15:8]

RSERM

RT

I

RS Err Ctrl

RS Err Cnt L

RS Err Cnt H

DS Ctrl

B0h

B1h

B2h

B3h

B5h

RSERS

RSERW

RSERT[1:0]

RSERC[7:0]

RSERC[15:8]

DST_DS

DSO_DS

PRBS Ctl

PRBS_

START

PRBS_

INVERT

PRBS_

SYNC

PRBS_HEADER_SIZE

RT

32

Preliminary Rev. 0.7

Si2107/08/09/10

Table 19. Register Summary (Continued)

Name

I2C

D7

D6

D5

D4

D3

D2

D1

D0

Addr.

Automatic Gain Control

AGC Ctrl 1

AGC Ctrl 2

23h

24h

AGCW[1:0]

I

AGCTR[3:0]

AGCO[3:0]

AGC 1–2 Gain 25h

AGC 3–4 Gain 26h

AGC2[3:0]

AGC4[3:0]

AGC1[3:0]

AGC3[3:0]

I

AGC TH

AGC PL

27h

28h

75h

76h

77h

78h

79h

7Ah

7Bh

AGCTH[6:0]

AGCPWR[6:0]

I

S

I

DAGC 1 Ctrl

DAGC1 L

DAGC1_EN

DAGC1W[1:0]

DAGC1T DAGC1HOLD DAGC1HOST

DAGC1[7:0]

I

DAGC1 H

DAGC1[15:8]

I

DAGC2 Ctrl

DAGC2 TH

DAGC2Lvl L

DAGC2Lvl H

DAGC2[3:0]

DAGC2W[1:0]

DAGC2TDIS

I

DAGC2T[7:0]

I

DAGC2GA[7:0]

I

DAGC2GA[15:8]

I

LNB Supply Controller

LNB Ctrl 1

LNB Ctrl 2

LNB Ctrl 3

LNB Ctrl 4

LNB Stat

C0h

C1h

C2h

C3h

C4h

C5h

C6h

C7h

C8h

C9h

CAh

CBh

CCh

CDh

LNBS

LNBV

TT

LNBCT

LNBB

MMSG

MSGL[2:0]

TFS

RT

S

LNBM[1:0]

BRST_DS

TDIR

TR

TFQ[7:0]

MSGTO

FE

FF

MSGPE

MSGR

MSGRL[2:0]

Msg FIFO 1

Msg FIFO 2

Msg FIFO 3

Msg FIFO 4

Msg FIFO 5

Msg FIFO 6

LNB S Ctrl1

LNB S Ctrl2

LNB S Ctrl3

FIFO1[7:0]

FIFO2[7:0]

FIFO3[7:0]

FIFO4[7:0]

FIFO5[7:0]

FIFO6[7:0]

RT

I

VLOW[3:0]

VHIGH[3:0]

ILIM[1:0]

IMAX[1:0]

SLOT[1:0]

VMON[7:0]

OLOT[1:0]

I

S

Preliminary Rev. 0.7

33

Si2107/08/09/10

Table 19. Register Summary (Continued)

Name

I2C

D7

D6

D5

D4

D3

D2

D1

D0

Addr.

LNB S Ctrl4

LNB S Stat

CEh

CFh

LNBL

LNB_EN

COMP

LNBLVL

SCD

LNBMD

OCD

I

S

34

Preliminary Rev. 0.7

Si2107/08/09/10

Register 00h. Device ID Register

Bit

D7

D6

D5

D4

D3

D2

REV[3:0]

D1

D0

Name

DEV[3:0]

Bit

Name

Function

7:4

DEV[3:0]

REV[3:0]

Device ID.

0h = Si2110

1h = Si2109

2h = Si2108

3h = Si2107

3:0

Revision.

Current revision = 3h

Register 01h. System Mode

Bit

D7

D6

D5

INC_DS

D4

D3

D2

D1

D0

Name

0

MOD[1:0]

SYSM[2:0]

Bit

7:6

5

Name

Function

Reserved

INC_DS

Program to zero.

I2C Automatic Address Increment Disable.

0 = Enabled (default)

1 = Disabled

4:3

2:0

MOD[1:0]

Modulation Selection.

00 = BPSK Demodulation

01 = QPSK Demodulation (default)

10 = Reserved

11 = Reserved

SYSM[2:0]

System Mode.

000 = DVB-S (default)

001 = DSS

010–111 = Reserved

Preliminary Rev. 0.7

35

Si2107/08/09/10

Register 02h. Transport Stream Control 1

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

TSEP

TSVP

TSSP

TSSL

TSCM

TSCE

TSDF

TSM

Bit

Name

Function

7

TSEP

Transport Stream Error Polarity.

0 = Active high (default)

1 = Active low

6

5

4

TSVP

TSSP

TSSL

Transport Stream Valid Polarity.

0 = Active high (default)

1 = Active low

Transport Stream Sync Polarity.

0 = Active high (default)

1 = Active low

Transport Stream Start Length.

0 = Byte wide (default)

1 = Bit wide

Note: This bit is ignored in parallel mode.

3

2

1

TSCM

TSCE

TSDF

Transport Stream Clock Mode.

0 = Gapped mode (default)

1 = Continuous mode

Transport Stream Clock Edge.

0 = Data transitions on rising edge (default)

1 = Data transitions on falling edge

Transport Stream Serial Data Format.

0 = MSB first (default)

1 = LSB first

Note: This bit is ignored in parallel mode

0

TSM

Transport Stream Mode.

0 = Serial (default)

1 = Parallel

36

Preliminary Rev. 0.7

Si2107/08/09/10

Register 03h. Transport Stream Control 2

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

0

TSPCS

TSCD

TSDD

TSPG

TSSCR[1:0]

Bit

7:6

5

Name

Function

Reserved

TSPCS

Program to zero.

Transport Stream Parallel Clock Smoother.

Smoothens TS_CLK to ~50% duty cycle.

0 = Smoothing disabled

1 = Smoothen clock to ~50% duty cycle (default)

4

3

TSCD

TSDD

Transport Stream Clock Delay.

Adds delay to TS_CLK to adjust clock-data timing relationship.

0 = Normal operation (default)

1 = Delay clock relative to data

Transport Stream Data Delay.

Adds delay to TS_DATA, TS_SYNC, TS_VAL, TS_ERR output to adjust

clock-data timing relationship.

0 = Normal operation (default)

1 = Delay data relative to clock

2

TSPG

Transport Stream Parity Gate.

0 = Normal operation (default)

1 = Zero data lines during parity

1:0

TSSCR[1:0]

Transport Stream Serial Clock Rate.

00 = 80–88.5 MHz (default)

01 = 76.8–82.8 MHz

10 = 54.9–59.2 MHz

11 = 35–37.7 MHz

Preliminary Rev. 0.7

37

Si2107/08/09/10

Register 04h. Pin Control 1

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

INT_EN

INTT

INTP

TSE_OE

TSV_OE

TSS_OE

TSC_OE

TSD_OE

Bit

Name

Function

7

INT_EN

Interrupt Pin Enable.

0 = Disabled (default)

1 = Enabled

6

5

4

3

2

1

0

INTT

Interrupt Pin Type.

0 = CMOS (default)

1 = Open drain/source

INTP

Interrupt Polarity.

0 = Active low (default)

1 = Active high

TSE_OE

TSV_OE

TSS_OE

TSC_OE

TSD_OE

Transport Stream Error Output Enable.

0 = Enabled

1 = Tri-state (default)

Transport Stream Valid Output Enable.

0 = Enabled

1 = Tri-state (default)

Transport Stream Sync Output Enable.

0 = Enabled

1 = Tri-state (default)

Transport Stream Clock Output Enable.

0 = Enabled

1 = Tri-state (default)

Transport Stream Data Output Enable.

0 = Enabled

1 = Tri-state (default)

38

Preliminary Rev. 0.7

Si2107/08/09/10

Register 05h. Pin Control 2

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

0

1

0

GPO

PSEL[1:0]

Bit

7:3

2

Name

Function

Reserved

GPO

Program to zero (except bit D5, which is programmed to 1).

General Purpose Output Control.

Controls output of pin 30 when PSEL = 10

0 = Output logic zero. (default)

1 = Output logic 1.

1:0

PSEL[1:0]

Pin Select (Pin 30).

00 = Interrupt (default)

01 = Receiver lock indicator

10 = General Purpose Output

11 = Reserved

Register 06h. Bypass

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

0

DS_BP

RS_BP

DI_BP

0

Bit

7:6

5

Name

Reserved

DS_BP

Function

Program to zero.

Descrambler Bypass.

0 = Normal operation (default)

1 = Bypass

Note: This bit is ignored in DSS mode; the descrambler is automatically

bypassed.

4

3

RS_BP

DI_BP

Reed-Solomon Bypass.

0 = Normal operation (default)

1 = Bypass

Deinterleaver Bypass.

0 = Normal operation (default)

1 = Bypass

2:0

Reserved

Program to zero.

Preliminary Rev. 0.7

39

Si2107/08/09/10

Register 07h. Interrupt Enable 1

Bit

D7

D6

D5

D4

D3

D2

D1

Name

RCVL_E

AGCL_E

CEL_E

SRL_E

STL_E

CRL_E

VTL_E

FSL_E

Bit

Name

Function

7

RCVL_E

AGCL_E

CEL_E

Receiver Lock Interrupt Enable.

0 = Disabled (default)

1 = Enabled

6

5

4

AGC Lock Interrupt Enable.

0 = Disabled (default)

1 = Enabled

Carrier Estimator Lock Interrupt Enable.

0 = Disabled (default)

1 = Enabled

SRL_E

Symbol Rate Lock Interrupt Enable.

0 = Disabled (default)

1 = Enabled

Note: Available on Si2109/10 only.

3

2

1

0

STL_E

CRL_E

VTL_E

FSL_E

Symbol Timing Lock Interrupt Enable.

0 = Disabled (default)

1 = Enabled

Carrier Recovery Lock Interrupt Enable.

0 = Disabled (default)

1 = Enabled

Viterbi Search Lock Interrupt Enable.

0 = Disabled (default)

1 = Enabled

Frame Sync Lock Interrupt Enable.

0 = Disabled (default)

1 = Enabled

40

Preliminary Rev. 0.7

Si2107/08/09/10

Register 08h. Interrupt Enable 2

Bit

D7

D6

D5

D4

D3

D2

D1

Name

RCVU_E

AGCTS_E

STU_E

CRU_E

VTU_E

FSU_E

0

AQF_E

Bit

Name

Function

7

RCVU_E

AGCTS_E

STU_E

Receiver Unlock Interrupt Enable.

0 = Disabled (default)

1 = Enabled

6

5

4

3

2

AGC Tracking Threshold Interrupt Enable.

0 = Disabled (default)

1 = Enabled

Symbol Timing Unlock Interrupt Enable.

0 = Disabled (default)

1 = Enabled

CRU_E

VTU_E

Carrier Recovery Unlock Interrupt Enable.

0 = Disabled (default)

1 = Enabled

Viterbi Search Unlock Interrupt Enable.

0 = Disabled (default)

1 = Enabled

FSU_E

Frame Sync Unlock Interrupt Enable.

0 = Disabled (default)

1 = Enabled

1

0

Reserved

AQF_E

Program to zero.

Acquisition Fail Interrupt Enable.

0 = Disabled (default)

1 = Enabled

Preliminary Rev. 0.7

41

Si2107/08/09/10

Register 09h. Interrupt Enable 3

Bit

D7

D6

D5

D4

D3

D2

D1

Name

CN_E

VTBER_E RSER_E

MSGPE_E

FE_E

FF_E

MSGR_E

MSGTD_E

Bit

Name

Function

7

CN_E

VTBER_E

RSER_E

MSGPE_E

FE_E

C/N Estimator Interrupt Enable.

0 = Disabled (default)

1 = Enabled

6

5

4

3

2

1

0

Viterbi BER Interrupt Enable.

0 = Disabled (default)

1 = Enabled

Reed-Solomon Error Measurement Interrupt Enable.

0 = Disabled (default)

1 = Enabled

LNB Message Parity Error Interrupt Enable.

0 = Disabled (default)

1 = Enabled

LNB Transmit FIFO Empty Interrupt Enable.

0 = Disabled (default)

1 = Enabled

FF_E

LNB Receive FIFO Full Interrupt Enable.

0 = Disabled (default)

1 = Enabled

MSGR_E

MSGTD_E

LNB Receive Message Interrupt Enable.

0 = Disabled (default)

1 = Enabled

LNB Receive Timeout Interrupt Enable.

0 = Disabled (default)

1 = Enabled

42

Preliminary Rev. 0.7

Si2107/08/09/10

Register 0Ah. Interrupt Enable 4

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

0

SCD_E

OCD_E

Bit

7:2

1

Name

Function

Reserved

SCD_E

Program to zero.

Short Circuit Detect Interrupt Enable.

0 = Disabled (default)

1 = Enabled

0

OCD_E

Over Current Detect Interrupt Enable.

0 = Disabled (default)

1 = Enabled

Preliminary Rev. 0.7

43

Si2107/08/09/10

Register 0Bh. Interrupt Status 1

Bit

D7

D6

D5

D4

D3

D2

D1

Name

RCVL_I

AGCL_I

CEL_I

SRL_I

STL_I

CRL_I

VTL_I

FSL_I

Bit

Name

Function

7

RCVL_I

AGCL_I

CEL_I

Receiver Lock Interrupt.

0 = Disabled (default)

1 = Enabled

6

5

4

AGC Lock Interrupt.

0 = Disabled (default)

1 = Enabled

Carrier Estimator Lock Interrupt.

0 = Disabled (default)

1 = Enabled

SRL_I

Symbol Rate Lock Interrupt.

0 = Disabled (default)

1 = Enabled

Note: Available on Si2109/10 only.

3

2

1

0

STL_I

CRL_I

VTL_I

FSL_I

Symbol Timing Lock Interrupt.

0 = Disabled (default)

1 = Enabled

Carrier Recovery Lock Interrupt.

0 = Disabled (default)

1 = Enabled

Viterbi Search Lock Interrupt.

0 = Disabled (default)

1 = Enabled

Frame Sync Lock Interrupt.

0 = Disabled (default)

1 = Enabled

44

Preliminary Rev. 0.7

Si2107/08/09/10

Register 0Ch. Interrupt Status 2

Bit

D7

D6

D5

D4

D3

D2

D1

Name

RCVU_I

AGCTS_I

STU_I

CRU_I

VTU_I

FSU_I

0

AQF_I

Bit

7

Name

RCVU_I

AGCTS_I

Function

Receiver Unlock Interrupt.

6

AGC Tracking Threshold Interrupt.

0 = Normal operation (default)

1 = Event recorded

5

4

3

2

STU_I

CRU_I

VTU_I

FSU_I

Symbol Timing Unlock Interrupt.

0 = Normal operation (default)

1 = Event recorded

Carrier Recovery Unlock Interrupt.

0 = Normal operation (default)

1 = Event recorded

Viterbi Search Unlock Interrupt.

0 = Normal operation (default)

1 = Event recorded

Frame Sync Unlock Interrupt.

0 = Normal operation (default)

1 = Event recorded

1

0

Reserved

AQF_I

Program to zero.

Acquisition Fail Interrupt.

0 = Normal operation (default)

1 = Event recorded

Preliminary Rev. 0.7

45

Si2107/08/09/10

Register 0Dh. Interrupt Status 3

Bit

D7

D6

D5

D4

D3

D2

D1

Name

CN_I

VTBR_I

RSER_I MSGPE_I

FE_I

FF_I

MSGR_I

MSGTO_I

Bit

Name

Function

7

CN_I

C/N Estimator Interrupt.

0 = Normal operation (default)

1 = Event recorded

6

5

4

3

2

1

0

VTBR_I

RSER_I

MSGPE_I

FE_I

Viterbi BER Interrupt.

0 = Normal operation (default)

1 = Event recorded

Reed-Solomon Error Measurement Complete Interrupt.

0 = Normal operation (default)

1 = Event recorded

LNB Message Parity Error Interrupt.

0 = Normal operation (default)

1 = Event recorded

LNB Transmit FIFO Empty Interrupt.

0 = Normal operation (default)

1 = Event recorded

FF_I

LNB Receive FIFO Full Interrupt.

0 = Normal operation (default)

1 = Event recorded

MSGR_I

MSGTO_I

LNB Receive Message Interrupt.

0 = Normal operation (default)

1 = Event recorded

LNB Receive Timeout Interrupt.

0 = Normal operation (default)

1 = Event recorded

46

Preliminary Rev. 0.7

Si2107/08/09/10

Register 0Eh. Interrupt Status 4

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

0

SCD_I

OCD_I

Bit

7:2

1

Name

Function

Reserved

SCD_I

Program to zero.

Short Circuit Detect Interrupt.

0 = Normal operation (default)

1 = Event recorded

0

OCD_I

Over Current Detect Interrupt.

0 = Normal operation (default)

1 = Event recorded

Preliminary Rev. 0.7

47

Si2107/08/09/10

Register 0Fh. Lock Status 1

Bit

D7

D6

D5

D4

D3

D2

D1

D0

0

AGCL

CEL

SRL

STL

CRL

VTL

FSL

Name

Bit

7

Name

Reserved

AGCL

Function

Program to zero.

6

AGC Lock Status.

0 = Pending (default)

1 = Complete

5

4

CEL

SRL

Carrier Estimation Status.

0 = Pending (default)

1 = Complete

Symbol Rate Estimation Status.

0 = Pending (default)

1 = Complete

Note: Available on Si2109/10 only.

3

2

1

0

STL

CRL

VTL

FSL

Symbol Timing Lock Status.

0 = Unlocked (default)

1 = Locked

Carrier Lock Status.

0 = Unlocked (default)

1 = Locked

Viterbi Lock Status.

0 = Unlocked (default)

1 = Locked

Frame Sync Lock Status.

0 = Unlocked (default)

1 = Locked

Register 10h. Lock Status 2

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

RCVL

0

Bit

Name

Function

7

RCVL

Receiver Lock Status.

0 = Unlocked (default)

1 = Locked

6:0

Reserved

Program to zero.

48

Preliminary Rev. 0.7

Si2107/08/09/10

Register 11h. Acquisition Status

Bit

D7

D6

D5

D4

D3

D2

D1

Name

AQF

AGCF

CEF

SRF

STF

CRF

VTF

FSF

Bit

Name

Function

7

AQF

Receiver Acquisition Status.

0 = Normal operation (default)

1 = Acquisition failed

6

5

4

AGCF

CEF

AGC Search Status.

0 = Normal operation (default)

1 = Gain control limit reached

Carrier Estimation Search Status.

0 = Normal operation (default)

1 = Carrier offset not found

SRF

Symbol Rate Search Status.

0 = Normal operation (default)

1 = Search failed

Note: Available on Si2109/10 only.

3

2

1

0

STF

CRF

VTF

FSF

Symbol Timing Search Status.

0 = Normal operation (default)

1 = Search failed

Carrier Search Status.

0 = Normal operation (default)

1 = Search failed

Viterbi Search Status.

0 = Normal operation (default)

1 = Search failed

Frame Sync Search Status.

0 = Normal operation (default)

1 = Search failed

Preliminary Rev. 0.7

49

Si2107/08/09/10

Register 14h. Acquisition Control 1

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

AQS

0

Bit

Name

Function

Automatic Acquisition Start.

7

AQS

Writing a one to this bit initiates the acquisition sequence. This bit is

automatically cleared when the acquisition sequence completes.

6:0

Reserved

Program to zero.

Register 15h. ADC Sampling Rate

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

ADCSR[7:0]

Bit

Name

ADCSR[7:0]

Function

7:0

ADC Sampling Rate.

f = ADCSR x 1 MHz

s

Default: C8h (200 MHz)

Register 16h. Coarse Tune Frequency

Bit

D7

D6

D5

D4

CTF[7:0]

D3

D2

D1

D0

Name

Bit

Name

CTF[7:0]

Function

7:0

Coarse Tune Frequency.

Calculation of the coarse tune value is determined by the reference

software driver.

f

= CTF x 10 MHz

coarse

Default: 00h

50

Preliminary Rev. 0.7

Si2107/08/09/10

Register 17h. Fine Tune Frequency L

Bit

D7

D6

D5

D4

FTF[7:0]

D3

D2

D1

D0

Name

Bit

Name

FTF[7:0]

Function

Fine Tune Frequency (Low Byte).

7:0

f_s

2¹⁴

--------

f_fine= FTF ×

where FTF is stored as a 2s complement value.

Calculation of the fine tune value is determined by the reference soft-

ware driver.

Default: 00h

Register 18h. Fine Tune Frequency H

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

0

FTF[14:8]

Bit

7

Name

Function

Reserved

FTF[14:8]

Program to zero.

6:0

Fine Tune Frequency (High Byte).

See Register 17h.

Register 23h. Analog AGC Control 1

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

0

AGCW[1:0]

0

Bit

7:6

5:4

Name

Function

Reserved

AGCW[1:0]

Program to zero.

AGC Measurement Window.

Acquisition

00 = 1024 (default)

01 = 2048

Tracking

65536 samples (default)

131072 samples

10 = 4096

262144 samples

11 = 8192

524288 samples

3:0

Reserved

Program to zero.

Preliminary Rev. 0.7

51

Si2107/08/09/10

Register 24h. AGC Control 2

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

AGCTR[3:0]

AGCO[3:0]

Bit

Name

Function

7:4

AGCTR[3:0]

AGC Tracking Threshold.

Specifies the maximum difference between AGCPWR (28h) and

AGCTH (27h) before making a gain adjustment.

Default: 1000.

3:0

AGCO[3:0]

AGC Gain Offset.

Applies a static gain offset to the input channel.

0000 = +0 dB (default)

0001 = +1 dB

…

1110 = +14 dB

1111 = +15 dB

Register 25h. Analog AGC 1–2 Gain

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

AGC2[3:0]

AGC1[3:0]

Bit

Name

Function

7:4

AGC2[3:0]

Analog Gain stage 2 setting.

Default: 0h

3:0

AGC1[3:0]

Analog Gain stage 1 setting.

Default: 0h

Register 26h. Analog AGC 3–4 Gain

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

AGC4[3:0]

AGC3[3:0]

Bit

Name

Function

7:4

AGC4[3:0]

Analog Gain stage 4 setting

Default: 0h

3:0

AGC3[3:0]

Analog Gain stage 3 setting

Default: 0h

52

Preliminary Rev. 0.7

Si2107/08/09/10

Register 27h. AGC Threshold

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

0

AGCTH[6:0]

Bit

7

Name

Function

Reserved

Program to zero.

6:0

AGCTH[6:0]

AGC Threshold.

The value specified in this register corresponds to the desired AGC

power level. The AGC loop adjusts the gain of the system to drive the

AGC power level to this value.

Default: 20h.

Register 28h. AGC Power Level

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

0

AGCPWR[6:0]

Bit

7

Name

Function

Reserved

Program to zero.

6:0

AGCPWR[6:0]

AGC Power Level.

Represents the measured input power level after the ADC in rms format.

The measurement window is set by AGCW (23h[6:4]). This register sat-

urates at full scale.

Default: 00h.

Preliminary Rev. 0.7

53

Si2107/08/09/10

Register 29h. Carrier Estimation Control

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

0

1

CESR[2:0]

Bit

7:4

3

Name

Function

Reserved

CESR[2:0]

Program to zero.

Program to one.

2:0

Carrier Estimation Search Range.

000 = Reserved

001 = ± f / 32

(± 6.3 MHz typ.) (default)

(± 3.1 MHz typ.)

(± 1.6 MHz typ.)

(± 0.8 MHz typ.)

(± 0.4 MHz typ.)

(± 0.2 MHz typ.)

(± 0.1 MHz typ.)

s

010 = ± f / 64

s

011 = ± f / 128

s

100 = ± f / 256

s

101 = ± f / 512

s

110 = ± f / 1024

s

111 = ± f / 2048

s

Register 36h. Carrier Estimator Offset L

Bit

D7

D6

D5

D4

CFO[7:0]

D3

D2

D1

D0

Name

Bit

Name

CFO[7:0]

Function

Carrier Frequency Offset (Low Byte).

7:0

Designed to store a residual carrier frequency offset for future acquisi-

tions. Used during carrier offset estimation to adjust the center fre-

quency.

f_s

2¹⁵

--------

Search center frequency = f_desired+ CFO ×

Hz

Note: CFO is a 16-bit Twos complement number.

Default: 00h

54

Preliminary Rev. 0.7

Si2107/08/09/10

Register 37h. Carrier Estimator Offset H

Bit

D7

D6

D5

D4

CFO[15:8]

D3

D2

D1

D0

Name

Bit

Name

CFO[15:8]

Function

7:0

Carrier Frequency Offset (High Byte).

See register 36h.

Register 38h. Carrier Frequency Offset Error L

Bit

D7

D6

D5

D4

CFER[7:0]

D3

D2

D1

D0

Name

Bit

Name

CFER[7:0]

Function

Carrier Frequency Offset Error (Low Byte).

7:0

Stores the carrier frequency offset that is identified during the carrier

offset estimation stage.

f_s

--------

Offset = –CFER ×

Hz

2¹⁵

Note: CFER is a 16-bit Twos complement number.

Default: 00h

Register 39h. Carrier Frequency Offset Error H

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

CFER[15:8]

Bit

Name

CFER[15:8]

Function

7:0

Carrier Frequency Offset Error (High Byte).

See register 38h.

Preliminary Rev. 0.7

55

Si2107/08/09/10

Register 3Ah. Symbol Rate Control (Si2109 and Si2110 only)

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

0

SRUK

0

Bit

7

Name

Function

Reserved

SRUK

Program to zero.

6

Symbol Rate Unknown.

0 = Symbol rate is known. (default)

1 = Symbol rate is unknown.

5:0

Reserved

Program to zero.

Register 3Fh. Symbol Rate L

Bit

D7

D6

D5

D4

SR[7:0]

D3

D2

D1

D0

Name

Bit

Name

SR[7:0]

Function

7:0

Symbol Rate (Low Byte).

Symbol rate = SR ×

f_s

2²⁴

--------

Hz

Default: 00h.

Register 40h. Symbol Rate M

Bit

D7

D6

D5

D4

SR[15:8]

D3

D2

D1

D0

Name

Bit

Name

SR[15:8]

Function

7:0

Symbol Rate (Mid Byte).

See register 3Fh.

56

Preliminary Rev. 0.7

Si2107/08/09/10

Register 41h. Symbol Rate H

Bit

D7

D6

D5

D4

SR[23:16]

D3

D2

D1

D0

Name

Bit

Name

SR[23:16]

Function

7:0

Symbol Rate (High Byte).

See register 3F.

Register 42h. Symbol Rate Maximum (Si2109 and Si2110 only)

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

SRMX[7:0]

Bit

Name

SRMX[7:0]

Function

Symbol Rate Estimation Maximum.

Max symbol rate = SRMX ×

7:0

f_s

2¹⁶

--------

Hz

Default: 00h.

Register 43h. Symbol Rate Minimum (Si2109 and Si2110 only)

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

SRMN[7:0]

Bit

Name

SRMN[7:0]

Function

Symbol Rate Estimation Minimum.

7:0

f_s

2¹⁶

--------

Min symbol rate = SRMN ×

Hz

Default: 00h.

Preliminary Rev. 0.7

57

Si2107/08/09/10

Register 75h. Digital AGC 1 Control

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

0

DAGC1_EN

DAGC1W[1:0]

DAGC1T DAGC1HOLD

DAGC1HOST

0

Bit

Name

Function

7

Reserved

Program to 0 (device may change the value of this bit during opera-

tion)

6

DAGC1_EN

Enable digital AGC 1

0 = Disabled

1 = Enabled (default)

5:4

DAGC1W[1:0]

Digital AGC Measurement Window

00 = 256 samples

01 = 512 samples

10 = 1024 samples (default)

11 = 2048 samples

3

2

1

DAGC1T

Select AGC threshold

0 = –15 dBFS (default)

1 = –9 dBFS

DAGC1HOLD

DAGC1HOST

Hold previous computed gain value on DAGC1

0 = Update gain after each calculation (default)

1 = Do not update gain value

Host-controlled DAGC1

0 = Gain is determined by DAGC1 module. Digital AGC1 gain regis-

ter is read-only. (Default)

1 = Gain is determined by host and specified in Digital AGC1 Gain

Register (76h & 77h).

0

Reserved

Program to 0.

Register 76h. Digital AGC 1 Gain L

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

DAGC1[7:0]

Bit

Name

DAGC1[7:0]

Function

7:0

Gain of digital AGC 1 (low-byte).

Default: 00h

58

Preliminary Rev. 0.7

Si2107/08/09/10

Register 77h. Digital AGC 1 Gain H

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

DAGC1[15:8]

Bit

Name

DAGC1[15:8]

Function

7:0

Gain of digital AGC 1 (high-byte).

Default: 00h

Register 78h. Digital AGC 2 Control

Bit

D7

D6

D5

D4

D3

D2

D1

D0

DAGC2TDIS

Name

Reserved

DAGC2[3:0]

DAGC2W[1:0]

Bit

Name

Reserved

Function

7

Program to 0 (device may change the value of this bit during opera-

tion)

6:3

2:1

DAGC2[3:0]

Digital AGC2 gain factor

Default: 0h

DAGC2W[1:0]

Digital AGC2 Measurement window

Acquisition

Tracking

00 = 16 samples (default)

01 = 32 samples

10 = 64 samples

11 = 128 samples

1024 samples (default)

2048 samples

4096 samples

8192 samples

0

DAGC2TDIS

Digital AGC2 Automatic Tracking Disable

1 = Disable automatic tracking. Freeze applied to gain.

0 = Enable automatic tracking. (default)

Register 79h. Digital AGC 2 Threshold

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

DAGC2T[7:0]

Bit

Name

DAGC2T[7:0]

Function

7:0

Digital AGC2 Threshold

Default: B5h

Preliminary Rev. 0.7

59

Si2107/08/09/10

Register 7Ah. Digital AGC 2 Level L

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

DAGC2GA[7:0]

Bit

Name

DAGC2GA[7:0]

Function

7:0

Digital AGC2 Gain Auto (low byte).

Digital AGC2 gain applied to meet threshold

Default: 00h

Register 7Bh. Digital AGC 2 Level H

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

DAGC2GA[15:8]

Bit

Name

DAGC2GA[15:8]

Function

7:0

Digital AGC2 Gain Auto (high byte).

See register 7Ah.

Default: 00h

Register 7Ch. C/N Estimator Control

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

CNS

0

CNM

CNW[1:0]

0

Bit

Name

Function

7

CNS

C/N Estimator Start.

Writing a one to this bit initiates an C/N estimator and clears the result

stored in CNE_LEVEL. This bit is automatically cleared to zero when the

measurement period elapses.

6:3

2

Reserved

CNM

Program to zero.

C/N Estimator Mode.

0 = Finite window

1 = Infinite window (default)

1:0

CNW[1:0]

C/N Measurement Window.

00 = 1024 samples

01 = 4096 samples (default)

10 = 16384 samples

11 = 65536 samples

60

Preliminary Rev. 0.7

Si2107/08/09/10

Register 7Dh. C/N Estimator Threshold0

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

CNET[7:0]

Bit

Name

CNET[7:0]

Function

7:0

C/N Estimator Threshold.

This value defines a noise threshold for the C/N estimator.

Default 13h.

Register 7Eh. C/N Estimator Level L

Bit

D7

D6

D5

D4

CNL[7:0]

D3

D2

D1

D0

Name

Bit

Name

CNL[7:0]

Function

C/N Estimator Level (Low Byte).

7:0

The value in this register is to be used with an external lookup table to

estimate the C/N of the input signal.

Default: 00h.

Register 7Fh. C/N Estimator Level H

Bit

D7

D6

D5

D4

CNL[15:8]

D3

D2

D1

D0

Name

Bit

Name

CNL[15:8]

Function

7:0

C/N Estimator Level (High Byte).

See Register 7Eh.

Preliminary Rev. 0.7

61

Si2107/08/09/10

Register A0h. Viterbi Search Control 1

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

0

VTCS[5:0]

Bit

7:6

5:0

Name

Function

Reserved

VTCS[5:0]

Program to zero.

Viterbi Code Rate Search Parameter Enable.

The code rates to be used in the Viterbi search are selected by writing a

one into the appropriate bit position. The list below illustrates the rela-

tionship between bit position and code rate.

Bit 5 = 7/8 code rate (MSB)

Bit 4 = 6/7 code rate

Bit 3 = 5/6 code rate

Bit 2 = 3/4 code rate

Bit 1 = 2/3 code rate

Bit 0 = 1/2 code rate (LSB)

Default: All code rates selected (3Fh).

Register A2h. Viterbi Search Control 2

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Reserved

VTERS

VTERM

VTERW[1:0]

Bit

Name

Function

Viterbi BER Measurement Start

3

VTERS

Writing a 1 to this bit initiates the Viterbi BER measurement.

2

VTERM

Viterbi BER Measurement Mode

0 = finite window (default)

1 = infinite window

1:0

VTERW[1:0]

Viterbi BER Measurement Window

13

00 = 2 bits (default)

17

01 = 2 bits

21

10 = 2 bits

25

11 = 2 bits

62

Preliminary Rev. 0.7

Si2107/08/09/10

Register A3h. Viterbi Search Status

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

VTRS[2:0]

Reserved

VTPS

VTIQS

Bit

Name

Function

7:5

VTRS[2:0]

Viterbi Current Code Rate Indicator.

000 = 1/2 code rate (default)

001 = 2/3 code rate

010 = 3/4 code rate

011 = 5/6 code rate

100 = 6/7 code rate

101 = 7/8 code rate

11x = Undefined

4:2

1

Reserved

VTPS

Program to 0.

Viterbi Constellation Rotation Phase Status.

0 = Not rotated (default)

1 = Rotated by 90 degrees

Viterbi I/Q Swap Status.

0

VTIQS

0 = Not swapped (default)

1 = Swapped

Register ABh. Viterbi BER Count L

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

VTBRC[7:0]

Bit

Name

VTBRC[7:0]

Function

Viterbi BER Counter (Low Byte).

7:0

Stores the number of the Viterbi bit errors detected within the specified

measurement window. This register saturates when it reaches the limit

of its range.

Default: 00h

Preliminary Rev. 0.7

63

Si2107/08/09/10

Register ACh. Viterbi BER Count H

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

VTBRC[15:8]

Bit

Name

VTBRC[15:8]

Function

7:0

Viterbi BER Counter (High Byte).

See Register ABh.

Register B0h. Reed-Solomon BER Error Monitor Control

Bit

D7

D6

D5

D4

D3

D2

RSERW

Function

D1

D0

Name

Reserved

RSERS

RSERM

RSERT[1:0]

Bit

7:5

4

Name

Reserved

RSERS

Program to zero.

Reed-Solomon BER Measurement Start.

Writing a 1 to this bit initiates the Reed-Solomon BER measurement.

3

2

RSERM

RSERW

Reed-Solomon Measurement Mode.

0 = Finite window (default)

1 = Infinite window

Reed-Solomon Measurement Window.

12

0 = 2 frames (default)

16

1 = 2 frames

1:0

RSERT[1:0]

Reed-Solomon Error Type.

00 = Corrected bit errors (default)

01 = Corrected byte errors

10 = Uncorrected packets

11 = PRBS errors

64

Preliminary Rev. 0.7

Si2107/08/09/10

Register B1h. Reed-Solomon Error Monitor Count L

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

RSERC[7:0]

Bit

Name

RSERC[7:0]

Function

Reed-Solomon Error Counter (Low Byte).

7:0

Stores the number of RS or PRBS errors detected within the specified

window. This register saturates when it reaches the limit of its range.

Default: 00h

Register B2h. Reed-Solomon Error Monitor Count H

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

RSERC[15:8]

Bit

Name

RSERC[15:8]

Function

7:0

Reed-Solomon Error Counter (High Byte).

See Register B1h.

Register B3h. Descrambler Control

Bit

D7

D6

D5

D4

D3

D2

D1

D0

DSO_DS

Name

0

DST_DS

Bit

7:2

1

Name

Function

Reserved

DST_DS

Program to zero.

Descrambler Transport Error Insertion Disable.

0 = Enabled (default)

1 = Disabled

0

DSO_DS

Descrambler Inverted SYNC Overwrite Disable.

0 = Enabled (default)

1 = Disabled

Preliminary Rev. 0.7

65

Si2107/08/09/10

Register B5h. PRBS Control

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name PRBS_START PRBS_INVERT PRBS_SYNC

0

PRBS_HEADER_SIZE

Bit

Name

Function

7

PRBS_START

Start PRBS synchronization.

1 = Start PRBS synchronization

Default = 0

6

5

PRBS_INVERT

PRBS_SYNC

Invert PRBS output.

1 = PRBS inverted.

Default = 0

Synchronization achieved for PRBS test.

0 = Not synchronized.

1 = Synchronized

Default = 0

4:2

1:0

Reserved

Read returns zero.

PRBS_HEADER_SIZE

Packet header size (DVB-S/DSS)

00 = 1/0 (Default)

01 = 2/1

10 = 3/2

11 = 4/3

66

Preliminary Rev. 0.7

Si2107/08/09/10

Register C0h. LNB Control 1

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

LNBS

LNBV

LNBCT

LNBB

MMSG

MSGL[2:0]

Bit

Name

Function

7

LNBS

LNB Start.

Writing a 1 to this bit initiates an LNB signaling sequence. This bit is

automatically cleared to zero when the sequence is complete.

Note: Not available in manual LNB mode.

6

LNBV

LNB DC Voltage Selection.

0 = 11/13 V (Japan/R.O.W.) (default)

1 = 15/18 V (Japan/R.O.W.)

Selection between Japan and R.O.W. LNB supply levels via register

LNBLVL(CEh[1])

Note: Available on Si2108/10 only.

5

4

LNBCT

LNBB

Continuous Tone Selection.

0 = Normal operation (default)

1 = Send continuous tone

Note: Not available in manual LNB mode.

Tone Burst Selection.

0 = Unmodulated tone burst (default)

1 = Modulated tone burst

Note: For use in automatic LNB mode only. Use a 1-byte DiSEqC message for

tone burst implementation in step-by-step LNB mode.

3

MMSG

More Messages.

0 = Normal operation (default)

1 = Indicates more DiSEqC messages to be sent

This bit is automatically cleared to zero when the sequence is complete.

Note: For use in automatic LNB mode only.

2:0

MSGL[2:0]

Message Length.

000 = No message (default)

001 = One byte

010 = Two bytes

011 = Three bytes

100 = Four bytes

101 = Five bytes

110 = Six bytes

111 = Longer than six bytes.

Notes:

1. When message length is set to one byte, tone burst modulation is used.

When message length is set to two or more bytes, DiSEqC modulation is

used.

2. Not available in manual LNB mode.

Preliminary Rev. 0.7

67

Si2107/08/09/10

Register C1h. LNB Control 2

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

LNBM[1:0]

0

BRST_DS

TFS

0

Bit

Name

Function

7:6

LNBM[1:0]

LNB Signaling Mode.

00 = Automatic (default)

01 = Step-by-step

10 = Manual

11 = Reserved

5:3

2

Reserved

BRST_DS

Program to zero.

Tone Burst Disable.

0 = Enabled (default)

1 = Disabled

Note: For use in automatic LNB mode only, in conjunction with LNBB (C0h[4])

1

0

TFS

Tone Format Select.

0 = Tone generation/detection (default)

1 = Envelope generation/detection

Reserved

Program to zero.

Register C2h. LNB Control 3

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

TDIR

TT

TR

0

Bit

Name

Function

7

TDIR

Tone Direction Control.

Controls output of DRC pin.

0 = Low (logic zero) (default)

1 = High (logic one)

Note: This bit is only active in manual LNB mode.

6

5

TT

TR

Tone Transmit.

Controls output of TGEN pin.

0 = Tone off / Low (logic zero) (default)

1 = Tone on / High (logic one)

Note: This bit is only active in manual LNB mode.

Tone Receive.

Detects input on TDET pin.

0 = No tone or low signal detected (default)

1 = Tone or high signal detected

Note: This bit is only active in manual LNB mode.

4:0

Reserved

Program to zero.

68

Preliminary Rev. 0.7

Si2107/08/09/10

Register C3h. LNB Control 4

Bit

D7

D6

D5

D4

D3

TFQ[7:0]

D2

D1

Name

Bit

Name

TFQ[7:0]

Function

7

LNB Tone Frequency Control.

Used to set the frequency of the LNB tone according to the following

equation:

Frequency = 100 MHz/[32 x (TFQ+1)]

00000000–01111011 = Reserved

01111100–10011011 = valid range

10011100–11111111 = Reserved

Default: 8Dh = 22 kHz

Preliminary Rev. 0.7

69

Si2107/08/09/10

Register C4h. LNB Status

Bit

D7

FE

D6

FF

D5

D4

D3

D2

D1

D0

MSGPE

MSGR

MSGTO

MSGRL[2:0]

Name

Bit

Name

Function

7

FE

Message FIFO Empty.

0 = Normal operation (default)

1 = Message FIFO empty

6

FF

Message FIFO Full

0 = Normal operation (default)

1 = Message FIFO full

5

MSGPE

MSGR

Message Parity Error

0 = Normal operation (default)

1 = Parity error detected

4

Message Received

0 = Normal operation (default)

1 = Message received

3

MSGTO

Message Timeout

0 = Normal operation (default)

1 = Message reply not received within 150 ms

2:0

MSGRL[2:0]

Received Message Length

000 = No message (default)

001 = One byte

010 = Two bytes

011 = Three bytes

100 = Four bytes

101 = Five bytes

110 = Six bytes

111 = Longer than six bytes

Register C5-CAh. Message FIFO 1–6

Bit

D7

D6

D5

D4

FIF0x[7:0]

D3

D2

D1

D0

Name

Bit

Name

FIFO1–6[7:0]

Function

7:0

Message FIFO

Contains message to be transmitted or message received

70

Preliminary Rev. 0.7

Si2107/08/09/10

Register CBh. LNB Supply Control 1 (Si2108 and Si2110 only)

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

VLOW[3:0]

VHIGH[3:0]

Bit

Name

Function

7:4

VLOW[3:0]

LNB Supply Low Voltage

Low voltage = Vlow_nom + VLOW[3:0] x 0.0625V + Vboost, where

Vlow_nom is determined by the LNBLVL(CEh[1]) register bit, and

Vboost is determined by the COMP(CEh[2]) register bit.

Default: 8h resulting in low voltage = Vlow_nom + 0.5 V + Vboost.

3:0

VHIGH[3:0]

LNB Supply High Voltage

High voltage = Vhigh_nom + VHIGH[3:0] x 0.0625V + Vboost, where

Vhigh_nom is determined by the LNBLVL(CEh[1]) register bit, and

Vboost is determined by the COMP(CEh[2]) register bit.

Default: 8h resulting in High voltage = Vhigh_nom + 0.5 V + Vboost.

Preliminary Rev. 0.7

71

Si2107/08/09/10

Register CCh. LNB Supply Control 2 (Si2108 and Si2110 only)

Bit

D7

D6

D5

D4

D3

SLOT[1:0]

Function

D2

D1

D0

Name

ILIM[1:0]

IMAX[1:0]

OLOT[1:0]

Bit

Name

7:6

ILIM[1:0]

IMAX[1:0]

SLOT[1:0]

Average Current Limit.

00 = 400 – 550 mA (default)

01 = 500 – 650 mA

10 = 650 – 850 mA

11 = 800 – 1000 mA

5:4

3:2

Peak Current Limit.

00 = 1.2 A (default)

01 = 1.6 A

10 = 2.4 A

11 = 3.2 A

Short Circuit Lockout Time.

00 = 15 µs

01 = 20 µs (default)

10 = 30 µs

11 = 40 µs

Overcurrent Lockout Time.

00 = 2.5 ms

1:0

OLOT[1:0]

01 = 3.75 ms

10 = 5.0 ms (default)

11 = 7.5 ms

Note: Register CCh is lockable via LNBL (CEh[7]). When locked, this register is read-only.

Register CDh. LNB Supply Control 3 (Si2110 only)

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

VMON[7:0]

Bit

Name

VMON[7:0]

Function

7:0

LNB Voltage Monitor.

LNB output voltage = VMON x 0.0625 + 6 V

72

Preliminary Rev. 0.7

Si2107/08/09/10

Register CEh. LNB Supply Control 4 (Si2108 and Si2110 only)

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

LNBL

Reserved

LNB_EN

COMP

LNBLVL

LNBMD

Bit

Name

Function

7

LNBL

LNB Supply Lock.

Writing a one to this bit locks the contents of Register CCh. This bit

can only be cleared by a device reset.

6:4

3

Reserved

LNB_EN

Program to zero.

LNB Supply Enable.

0 = Disabled (default)

1 = Enabled

2

1

COMP

LNB Cable Compensation Boost.

0 = Normal operation (default)

1 = LNB output voltage increased +1 V

LNBLVL

Select LNB supply levels for Japan or R.O.W.

0 = high voltage levels for R.O.W. i.e. Vhigh_nom = 17.5 V &

Vlow_nom = 11.5 V (default)

1 = low voltage levels for Japan i.e.

Vhigh_nom = 14.5 V & Vlow_nom = 11.5 V.

Note: The resulting nominal output voltages are: 12/15 V (Japan) and

13/18 V (R.O.W.) when using the default settings for the VLOW

(CBh[7:4]) and VHIGH (CBh[3:0]) register bits.

0

LNBMD

LNB Mode Detect.

Detected supply mode (read-only)

0 = External LNB supply circuit

1 = Internal LNB supply circuit

Preliminary Rev. 0.7

73

Si2107/08/09/10

Register CFh. LNB Supply Status (Si2108 and Si2110 only)

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

0

SCD

OCD

Bit

Name

Reserved

SCD

Function

7:2

1

Program to zero.

Short-Circuit Detect Flag.

0 = Normal operation (default)

1 = Short-circuit detected

0

OCD

Overcurrent Detect Flag.

0 = Normal operation (default)

1 = Overcurrent detected.

74

Preliminary Rev. 0.7

Si2107/08/09/10

9. Pin Descriptions

Si2108/10

Si2107/09

44 43 42 41 40 39 38 37 36

1

2

3

4

5

6

7

8

9

VDD_LNA

REXT

1

2

3

4

5

6

7

8

9

35 XTAL1

VDD_LNA

REXT

35 XTAL1

XTAL2

GND

34 XTAL2

34

ADDR

33 VDD_XTAL

32 XTOUT

ADDR

33 VDD_XTAL

32 XTOUT

VDD_MIX

VDD_BB

VDD_ADC

VSEN/TDET

LNB1/TGEN

ISEN

VDD_MIX

VDD_BB

VDD_ADC

TDET

31 VDD_PLL33

30 INT/RLK/GPO

29 TS_ERR

31 VDD_PLL33

30 INT/RLK/GPO

29 TS_ERR

Top

View

Top

View

TGEN

28

27

28

TS_VAL

NC

27 TS_SYNC

26 SDA

TS_SYNC

LNB2/DRC 10

RESET 11

DRC 10

11

26 SDA

RESET

25 SCL

PWM/DCS

DCS 12

12

24 TS_DATA[7]

GND

TS_DATA[6]

23

TS_DATA[6]

23

VDD_DIG18 13

14 15 16 17 18 19 20 21 22

Name

I/O

Description

Number

Supply Voltage.

1

VDD_LNA

I

LNA power supply. Connect to 3.3 V.

External Reference Resistor.

Connect 4.53 kΩ to GND.

2

3

4

REXT

ADDR

I/O

I/O I2C Address Select.

Supply Voltage.

Mixer power supply. Connect to 3.3 V

VDD_MIX

I

Supply Voltage.

Baseband power supply. Connect to 1.8 V.

5

6

VDD_BB

I

Supply Voltage.

ADC power supply. Connect to 3.3 V.

VDD_ADC

I

Voltage Sense/Tone Detect.

7

8

9

VSEN/TDET

LNB1/TGEN

ISEN

I

O

I

VSEN (Si2108/10 only)—Line voltage of LNB supply circuit.

TDET—Detect input of external tone or tone envelope.

LNB Control 1/Tone Generation.

LNB1 (Si2108/10 only)—Required connection to LNB supply circuit.

TGEN—Outputs tone or tone envelope.

Current Sense (Si2108/10 only).

Monitors current of LNB supply circuit. When LNB supply circuit is not populated or

when using Si2107/09, leave pin unconnected.

LNB Control 2/Direction Control.

LNB2 (Si2108/10 only)—required connection to LNB supply circuit.

DRC—Outputs signal to indicate message transmission (HIGH) or reception

(LOW).

10

11

LNB2/DRC

RESET

I/O

I

Device Reset.

Active low.

Preliminary Rev. 0.7

75

Si2107/08/09/10

PWM/DC Voltage Select.

PWM (Si2108/10 only)—Connected to gate of power MOSFET for LNB supply cir-

12

PWM/DCS

O

cuit.

DCS—Outputs signal to indicate 18 V (HIGH) or 13 V (LOW) LNB supply voltage

selection.

Supply voltage.

13

VDD_DIG18

TS_DATA[7:0]

VDD_DIG33

I

O

I

Digital power supply. Connect to 1.8 V.

Transport Stream Data Bus.

Serial data is output on TS_DATA[0].

Supply Voltage.

Digital power supply. Connect to 3.3 V.

Transport Stream Clock.

I2C Clock.

14–17,

21–24

18, 20

19

25

26

27

28

29

TS_CLK

SCL

O

I

SDA

I/O I2C Data.

TS_SYNC

TS_VAL

TS_ERR

O

Transport Stream Sync.

Transport Stream Valid.

Transport Stream Error.

Multi Purpose Output Pin.

This pin can be configured to one of the following outputs using the Pin Ctrl 2 (05h)

register.

INT = Interrupt

INT / RLK /

GPO

30

O

RLK = Receiver lock indicator

GPO = General purpose output

Supply Voltage.

Analog PLL power supply. Connect to 3.3 V.

31

32

VDD_PLL33

XTOUT

I

No Connect/Crystal oscillator output.

If this device is to be used as the clock master in a multi-channel design, this pin

should be connect to the XTAL1 pin of a clock slave device. (Otherwise, this pin

should be left unconnected.)

O

Supply Voltage.

Crystal Oscillator power supply. Connect to 3.3 V.

Crystal Oscillator.

Connect to 20 MHz crystal unit.

Crystal Oscillator.

Connect to 20 MHz crystal unit.

Supply Voltage.

Synth power supply. Connect to 3.3 V.

Supply Voltage.

Local Oscillator power supply. Connect to 3.3 V.

Ground.

33

34

VDD_XTAL

XTAL2

I

O

I

35

XTAL1

36

VDD_SYNTH

VDD_LO

GND

I

37

I

38,41,44

I

Reference ground.

RF Input.

39, 43 RFIP1, RFIP2

40, 42 RFIN1, RFIN2

I

These pins must be connected together on the board.

RF Input.

These pins must be connected together on the board.

Ground.

I

ePad

GND

I

Reference ground.

76

Preliminary Rev. 0.7

Si2107/08/09/10

10. Ordering Guide^1,2

Ordering Part #

Description

Temperature

Si2110-X-FM

Si2109-X-FM

Si2108-X-FM

Si2107-X-FM

Satellite receiver for DVB-S/DSS with LNB step-up dc-dc controller

and on-chip blindscan accelerator, Lead-free and RoHS Compliant

0 to 70 °C

Satellite receiver for DVB-S/DSS with on-chip blindscan accelerator,

Lead-free and RoHS Compliant

Satellite receiver for DVB-S/DSS with step-up dc-dc controller, Lead-

free and RoHS Compliant

Satellite receiver for DVB-S/DSS, Lead-free and RoHS Compliant

Notes:

1. “X” denotes product revision.

2. Add an “R” at the end of the device to denote tape and reel option; 2500 quantity per reel.

Preliminary Rev. 0.7

77

Si2107/08/09/10

11. Package Outline: 44-pin QFN

Figure 18 illustrates the package details for the Si2110. Table 20 lists the values for the dimensions shown in the

illustration.

Figure 18. 44-Pin QFN

Table 20. Package Diagram Dimensions

Millimeters

Nom

Millimeters

Nom

Dimension

Min

Max

Min

Max

A

0.80

0.00

0.18

0.90

0.02

1.00

0.05

0.30

E2

L

6.00

0.45

0.03

6.10

0.55

0.05

0.10

0.08

0.10

6.20

0.65

0.08

A1

b

0.25

L1

D

D2

6.00 BSC.

2.80

aaa

bbb

ccc

ddd

2.70

2.90

e

0.50 BSC.

8.00 BSC.

E

Notes:

1. Dimensioning and tolerancing per ANSI Y14.5M-1994.

2. This drawing conforms to the JEDEC Solid State Outline MO-220, Variation VJLD.

3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for small body Components.

4. The pin 1 I.D. pad is for component orientation only and is not to be soldered to the PCB.

78

Preliminary Rev. 0.7

Si2107/08/09/10

DOCUMENT CHANGE LIST

Revision 0.4 to Revision 0.5

ꢀ Package dimensions changed to 6 x 8 mm.

ꢀ Updated pin numbering and pin descriptions.

ꢀ Schematics updated.

ꢀ I2C interface description added.

ꢀ MPEG-TS timing specifications added.

Revision 0.5 to revision 0.6

ꢀ Data sheet for Si2107/08/09/10.

ꢀ Added detailed operational description.

ꢀ Register map changed for Rev. C silicon.

ꢁ Various editorial changes and corrections.

Revision 0.6 to revision 0.7

ꢀ Updated application diagram and BOM.

ꢀ Added table for multi-device I2C address support.

Preliminary Rev. 0.7

79

Si2107/08/09/10

CONTACT INFORMATION

Silicon Laboratories Inc.

4635 Boston Lane

Austin, TX 78735

Tel: 1+(512) 416-8500

Fax: 1+(512) 416-9669

Toll Free: 1+(877) 444-3032

Email: DBSinfo@silabs.com

Internet: www.silabs.com

The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.

Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from

the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features

or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-

resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-

quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to

support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-

sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-

plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.

Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.

Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.

80

Preliminary Rev. 0.7


型号：	SI2107-D-FMR
厂家：	SILICON
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SI2107-D-FMR [SILICON]

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