SI3010-F-FS_技术文档

Si2401

®

V.22BIS ISOMODEM WITH INTEGRATED GLOBAL DAA

Features

Data modem formats

z 2400 bps: V.22bis

Integrated third-generation DAA

z Fewer external components required

z Over 5000 V capacitive isolation

z Parallel phone detect

z 1200 bps: V.22, V.23, Bell 212A

z 300 bps: V.21, Bell 103

z Fast connect and V.23 reversing

z SIA and other security protocols

27 MHz CLKIN support

Caller ID detection and decoding

UART with flow control

z Globally-compliant line interface

AT command set support

Call progress support

3.3 V Power

Ordering Information

Lead-free, RoHS-compliant

See page 72.

packages

Applications

Pin Assignments

Si2401

Set-top boxes

Point-of-sale

ATM terminals

Security systems

Medical monitoring

Power meters

1

16 GPIO1/EOFR

15 GPIO2/CD

14 GPIO3/ESC

CLKIN/XTALI

XTALO

Description

2

3

The Si2401 ISOmodem^®is a complete, two-chip 2400 bps modem integrating

Silicon Labs’ third-generation direct access arrangement (DAA), which provides a

globally-programmable telephone line interface with an unprecedented level of

integration. Available in two 16-pin SOIC packages, this compact solution

eliminates the need for a separate DSP data pump, modem controller, codec,

isolation transformer, relay, opto-isolators, and 2–4 wire hybrid. The Si2401

provides conventional data formats at connect rates of up to 2400 bps with full-

duplex operation over the Public Switched Telephone Network (PSTN).

Additionally, the Si2401 is fully-programmable to meet global standards with a

single design. Other features include fast connect times for electronic point-of-

sale (EPOS) applications and alarm protocols for security systems. The device is

ideal for embedded modem applications due to its small size, low external

component count, and low power consumption.

GPIO5/RI

V_D

4

5

6

7

8

13

12

V_A

GND

RXD

TXD

CTS

11 GPIO4/INT/AOUT

10 C1A

9

C2A

RESET

Si3010

1

16

DCT2

QE

2

3

DCT

15 IGND

14 DCT3

RX

IB

4

5

6

7

8

13

12

QB

QE2

C1B

C2B

Functional Block Diagram

11 SC

VREG

10 VREG2

9

RNG2

RNG1

Si2401

Si3010

RX

RXD

TXD

µ Controller

(AT Decoder,

Call Progress)

U.S. Patent #5,870,046

U.S. Patent #6,061,009

Other patents pending

IB

SC

CTS

Hybrid, AC

and DC

Terminations

DCT

VREG

RESET

VREG2

DCT2

DCT3

Isolation

Interface

EOFR/GPIO1

DSP

(Data Pump)

CD/GPIO2

ESC/GPIO3

INT/GPIO4

RI/GPIO5

Control

Interface

RNG1

RNG2

QB

QE

QE2

Ring Detect

Off-Hook

XTALI

XOUT

Clock

Interface

Rev. 1.0 12/05

Si2401

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

Si2401

2

Rev. 1.0

Si2401

TABLE OF CONTENTS

Section

Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3. Bill of Materials: Si2401/10 Chipset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

4.1. Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

4.2. Configurations and Data Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

4.3. Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

4.4. Global DAA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

4.5. Parallel Phone Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4.6. Interrupt Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

4.7. V.23 Operation/V.23 Reversing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

4.8. V.42 HDLC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

4.9. Fast Connect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

4.10. Clock Generation Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

5. AT Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

5.1. Command Line Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

5.2. <CR> End-Of-Line Character . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

5.3. AT Command Set Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

5.4. Alarm Industry AT Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

5.5. Modem Result Codes and Call Progress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

6. Low Level DSP Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

6.1. DSP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

6.2. Call Progress Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

7. S Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

8. Pin Descriptions: Si2401 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

9. Pin Descriptions: Si3010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

10. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

11. Package Outline: 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Rev. 1.0

3

Si2401

1. Electrical Specifications

Table 1. Recommended Operating Conditions

1

2

Symbol

Test Condition

Typ

Unit

Parameter

Min

Max

70

Ambient Temperature

Si2401 Supply Voltage, Digital

Notes:

T

F-Grade

0

25

°C

V

A

3

V

3.0

3.3

3.6

D

1. The Si2401 specifications are guaranteed when the typical application circuit (including component tolerance) and Si2401

and Si3010 are used. See "2. Typical Application Schematic" on page 10.

2. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical

values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.

3. The digital supply, V , operates from 3.0 to 3.6 V. The Si2401 interface supports 5 V logic (CLKIN/XTALI supports 3.3 V

D

logic only).

4

Rev. 1.0

Si2401

Table 2. Loop Characteristics

(V_D= 3.0 to 3.6 V, T_A= 0 to 70 °C for F-Grade, see Figure 1 on page 6)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

DC Termination Voltage

V

I = 20 mA, ILIM = 0

DCV = 00, MINI = 11, DCR = 0

—

6.0

V

TR

L

DC Termination Voltage

I = 120 mA, ILIM = 0

9

—

V

L

DCV = 00, MINI = 11, DCR = 0

I = 20 mA, ILIM = 0

—

9

7.5

—

L

DCV = 11, MINI = 00, DCR = 0

I = 120 mA, ILIM = 0

L

DCV = 11, MINI = 00, DCR = 0

I = 20 mA, ILIM = 1

—

40

—

7.5

—

L

DCV = 11, MINI = 00, DCR = 0

I = 60 mA, ILIM = 1

L

DCV = 11, MINI = 00, DCR = 0

I = 50 mA, ILIM = 1

40

L

DCV = 11, MINI = 00, DCR = 0

On-Hook Leakage Current

Operating Loop Current

DC Ring Current

I

V

= –48 V

TR

—

10

—

5

120

60

3

µA

mA

µA

LK

LP

MINI = 00, ILIM = 0

MINI = 00, ILIM = 1

—

dc current flowing through ring

detection circuitry

1.5

*

Ring Detect Voltage

V

RT = 0

RT = 1

12

18

15

—

15

21

—

18

25

68

0.2

V

RD

RMS

*

Ring Detect Voltage

V

Ring Frequency

F

Hz

R

Ringer Equivalence Number

REN

*Note: The ring signal is guaranteed to not be detected below the minimum. The ring signal is guaranteed to be detected

above the maximum.

Rev. 1.0

5

Si2401

Table 3. DC Characteristics^*

(V_D= 3.0 to 3.6 V, T_A= 0 to 70°C for F-Grade)

Parameter

Symbol Test Condition

Min

Typ

Max

Unit

High Level Input Voltage

V

2.0

—

100

10

8

—

0.8

—

V

IH

Low Level Input Voltage

V

IL

High Level Output Voltage

V

I = –2 mA

2.4

—

V

OH

O

Low Level Output Voltage

V

I = 1 mA

0.35

0.6

10

V

OL

O

Low Level Output Voltage, GPIO1–4

Input Leakage Current

I = 10 mA

—

V

O

I

–10

50

—

µA

kΩ

mA

µA

L

Pullup Resistance Pins 5, 7, 11, 14

Power Supply Current, Digital

Power Supply Current, DSP Powerdown

Power Supply Current, Wake-On-Ring

Power Supply Current, Total Powerdown

R

200

15

PU

I

V pin

D

V pin

—

12

D

V pin

—

7

10

D

V pin

—

100

—

D

*Note: Measurements are taken with inputs at rails and no loads on outputs.

TIP

+

600 Ω

Si3010

V^TR

I_L

10 µF

–

RING

Figure 1. Test Circuit for Loop Characteristics

6

Rev. 1.0

Si2401

Table 4. AC Characteristics

(V_D= 3.0 to 3.6 V, TA = 0 to 70 °C for F-Grade, Fs = 8 kHz)

Parameter

Sample Rate

Symbol

Test Condition

Min

—

Typ

8

Max

—

Unit

kHz

Fs

Clock Input Frequency

F

default

—

4.9152

27

—

MHz

XTL

F

<10 kΩ resistor between DCD

—

and GND

Receive Frequency Response

Low –3 dBFS Corner, FILT = 0

Low –3 dBFS Corner, FILT = 1

—

5

—

Hz

200

1.1

80

1

Transmit Full Scale Level

V

PEAK

FS

1,2

Receive Full Scale Level

V

PEAK

DR

ILIM = 0, DCV = 11, MINI = 00

dB

3

Dynamic Range

DCR = 0, I = 100 mA

L

DR

ILIM = 0, DCV = 00, MINI = 11

—

80

—

dB

3

Dynamic Range

DCR = 0, I = 20 mA

L

DR

ILIM = 1, DCV = 11, MINI = 00

3

Dynamic Range

DCR = 0, I = 50 mA

L

Transmit Total Harmonic

THD

ILIM = 0, DCV = 11, MINI = 00

–72

–78

50

4

Distortion

DCR = 0, I = 100 mA

L

Transmit Total Harmonic

ILIM = 0, DCV = 00, MINI = 11

4

Distortion

DCR = 0, I = 20 mA

L

Receive Total Harmonic

ILIM = 0, DCV = 00, MINI = 11

4

Distortion

DCR = 0, I = 20 mA

L

Receive Total Harmonic

ILIM = 1,DCV = 11, MINI=00

4

Distortion

DCR = 0, I = 50 mA

L

Dynamic Range (Caller ID Mode)

DR

VIN = 1 kHz, –13 dBm

CID

Notes:

1. Measured at TIP and RING with 600 Ω termination at 1 kHz, as shown in Figure 1 on page 6.

2. Receive full scale level produces –0.9 dBFS at DTX.

3. DR = 20 x log |Vin| + 20 x log (rms signal/rms noise). Applies to both transmit and receive paths. Vin = 1 kHz, –3 dBFS.

4. Vin = 1 kHz, –3 dBFS. THD = 20 x log (rms distortion/rms signal).

Rev. 1.0

7

Si2401

Table 5. Absolute Maximum Ratings

Parameter

Symbol

Value

–0.5 to 4.1

±10

Unit

V

DC Supply Voltage

V

D

Input Current, Si2401 Digital Input Pins

Digital Input Voltage

I

mA

V

IN

V

–0.3 to 5.3

IND

CLKIN/XTALI Input Voltage

Operating Temperature Range

Storage Temperature Range

V

–0.3 to (V + 0.3)

V

XIND

D

T

–10 to 100

–40 to 150

°C

A

T

STG

Note: Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be

restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum

rating conditions for extended periods may affect device reliability.

8

Rev. 1.0

Si2401

Table 6. Switching Characteristics

(V_D= 3.0 to 3.6 V, T_A= 0 to 70 °C for F-Grade)

Parameter

Symbol

Min

Typ

Max

Unit

Baud Rate Accuracy

CTS ↓ Active to Start Bit↓

RESET Pulse Width

RESET ↑ to TXD ↓

–1

10

1

—

1

%

ns

t

—

csb

t

ms

rl

t

3

rs

Note: All timing is referenced to the 50% level of the waveform. Input test levels are V_IH= 2.0 V, V_IL= 0.8 V

Receive Timing

RXD

8-Bit Data

Mode (Default)

Start

D0

D1

D2

D3

D4

D5

D6

D7

Stop

RXD

9-Bit Data

Mode

D8

Stop

Transmit Timing

TXD

8-Bit Data

Mode (Default)

Start

D0

D1

D2

D3

D4

D5

D6

D7

Stop

D8

TXD

9-Bit Data

Mode

D2

D3

D4

Stop

t_csb

t_sbc

CTS

RESET

t_rl

TXD

t_rs

Note: Baud rates (programmed through register SE0) are as follows: 300,1200, 2400, 9600, 19200,

38400, 115200, and 307200 Hz.

Figure 2. Asynchronous UART Serial Interface Timing Diagram

Rev. 1.0

9

Si2401

2. Typical Application Schematic

+

S C

1 1

1 5

I G N D

1

2

V A

1 3

1 2

D

G N

V D

4

10

Rev. 1.0

Si2401

3. Bill of Materials: Si2401/10 Chipset

Component

C1, C2

C3

Value

33 pF, Y2, X7R, ±20%

10 nF, 250 V, X7R, ±20%

1.0 µF, 50 V, Tant/Elect, ±20%

0.1 µF, 16 V, X7R, ±20%

2.7 nF, 50 V, X7R, ±20%

680 pF, Y2, X7R, ±10%

0.01 µF, 16 V, X7R, ±20%

33 pF, 16 V, NP0, ±5%

0.22 µF, 16 V, X7R, ±20%

Dual Diode, 225 mA, 300 V, CMPD2004S

Ferrite Bead, BLM21AG601SN1

NPN, 300 V, MMBTA42

PNP, 300 V, MMBTA92

NPN, 80 V, 330 mW, MMBTA06

Sidactor, 275 V, 100 A

1.07 kΩ, 1/2 W, 1%

Supplier(s)

Panasonic, Murata, Vishay

Venkel, SMEC

C4

Venkel, SMEC

C5, C6, C50

C7

Venkel, SMEC

C8, C9

C10

Panasonic, Murata, Vishay

Venkel, SMEC

1

C40, C41

Venkel, SMEC

C51

Venkel, SMEC

2

D1, D2

Central Semiconductor

Murata

FB1, FB2

Q1, Q3

Q2

OnSemi, Fairchild

Q4, Q5

RV1

OnSemi, Fairchild

Teccor, Protek, ST Micro

Venkel, SMEC, Panasonic

Silicon Labs

R1

R2

150 Ω, 1/16 W, 5%

R3

3.65 kΩ, 1/2 W, 1%

R4

2.49 kΩ, 1/2 W, 1%

R5, R6

R7, R8

R9

100 kΩ, 1/16 W, 5%

20 MΩ, 1/16 W, 5%

1 MΩ, 1/16 W, 1%

R10

536 Ω, 1/4 W, 1%

R11

73.2 Ω, 1/2 W, 1%

R12, R13

56 Ω, 1/16 W, 1%

3

R15, R16

0 Ω, 1/16 W

U1

U2

Si2401

Si3010

Silicon Labs

1,4

Y1

4.9152 MHz, 20 pF, 100 ppm, 150 Ω ESR

Zener Diode, 43 V, 1/2 W, BZT52C43

ECS Inc., Siward

Z1

On Semi

Notes:

1. In STB applications, C40, C41, and Y1 can be removed when using the 27 MHz clock input feature. See

"4.10. Clock Generation Subsystem" on page 23.

2. Several diode bridge configurations are acceptable. For example, a single DF04S or four 1N4004 diodes may be

used.

3. Murata BLM21AG601SN1 may be substituted for R15–R16 (0 Ω) to decrease emissions.

4. To ensure compliance with ITU specifications, frequency tolerance must be less than 100 ppm including initial

accuracy, 5-year aging, 0 to 70 °C, and capacitive loading. 50 ppm initial accuracy crystals typically satisfy this

requirement.

Rev. 1.0

11

Si2401

can be programmed using the Si3010 to meet

worldwide PTT specifications for ac termination, dc

4. Functional Description

The Si2401 is a complete modem chipset with termination, ringer impedance, and ringer threshold.

integrated direct access arrangement (DAA) that The DAA can also monitor line status for parallel

provides a programmable line interface to meet global handset detection and overcurrent conditions.

telephone line requirements. Available in two 16-pin

small-outline packages, this solution includes a DSP

existing modem applications. The device interfaces

data pump, modem controller, codec, and DAA.

The Si2401 is designed for rapid assimilation into

directly through a UART to a microcontroller. The

The modem accepts simple modem AT commands and Si2401URT-EVB evaluation board connects directly to a

provides connect rates up to 2400 bps full-duplex over standard RS-232 interface. This allows for evaluation of

the Public Switched Telephone Network (PSTN) with the modem immediately upon powerup via

V.42 hardware support through HDLC framing. To HyperTerminal or any standard terminal software.

minimize handshake times, the Si2401 can implement a

V.22-based fast connect. The modem also supports the

international telephone line interface requirements with

V.23 reversing protocol and standard alarm formats

The chipset can be fully programmed to meet

full compliance to FCC, TBR21, JATE, and other

country-specific PTT specifications. In addition, the

including SIA.

This device is ideal for embedded modem applications Si2401 has been designed to meet the most stringent

due to its small board space, low power consumption, worldwide requirements for out-of-band energy, billing-

and global compliance. The Si2401 solution integrates a tone immunity, high-voltage surges, and safety

silicon DAA using Silicon Laboratories’ proprietary third- requirements.

generation DAA technology. This highly-integrated DAA

Table 7. Selectable Configurations

Carrier

Frequency (Hz)

Data Rate

(bps)

Standard

Compliance

Configuration

Modulation

V.21

V.22

FSK

DPSK

QAM

1080/1750

1200/2400

1300/2100

1300/1700

1170/2125

1200/2400

—

300

1200

Full

*

V.22bis

V.23

2400

No retrain

1200/75

600/75

300

Full; plus reversing

(Europe)

FSK

V.23

Bell 103

FSK

DPSK

DTMF

Pulse

FSK

Full

Bell 212A

Security

1200

40

Full

SIA—Pulse

SIA Format

—

Low

Full

1170/2125

300 half-duplex

300 bps only

*Note: The Si2401 only adjusts its DCE rate from 2400 bps to 1200 bps if it is connecting to a V.22-only (1200 bps only)

modem. Because the V.22bis specification does not outline a fallback procedure, the host should implement a

fallback mechanism consisting of hanging up and connecting at a lower baud rate. Retraining to accommodate

changes in line conditions that occur during a call must be implemented by terminating the call and redialing.

12

Rev. 1.0

Si2401

4.1. Serial Interface

Table 9. Modem Configuration Examples

(S07[7] (HDEN) = 0, S07[6] (BD) = 0)

The Si2401 has a universal asynchronous receiver/

transmitter (UART) serial interface compatible with

standard microcontroller serial interfaces. After powerup

or reset, the speed of the serial (Data Terminal

Equipment—DTE) interface is set by default to

2400 bps with the 8-bit, no parity, and one-stop bit (8N1)

format described below.

Modem Protocol

V.22bis

Register S07 Values

0x06

0x02

0x03

0x00

0x01

0x16

0x26

0x10

0x20

V.22

V.21

Bell 212A

The serial interface DTE rate can be modified by writing

SE0[2:0] (SD) with the value corresponding to the

desired DTE rate. (See Table 8.) This is accomplished

with the command, ATSE0=xx, where xx is the

hexadecimal value of the SE0 register.

Bell 103

V.23 (1200 tx, 75 rx)

V.23 (75 tx, 1200 rx)

V.23 (600 tx, 75 rx)

V.23 (75 tx, 600 rx)

Table 8. DTE Rates

DTE Rate (bps)

300

SE0[2:0] (SD)

As shown in Figure 3, 8-bit and 9-bit data modes refer to

the DTE format over the UART. Line data formats are

configured through registers S07 (MF1) and S15 (MLC).

If the number of bits specified by the format differs from

the number of bits specified by the DCE data

communications equipment or line (DTE) format, the

MSBs are either dropped or bit-stuffed, as appropriate.

For example, if the DTE format is 9 data bits (9N1), and

the line data format is 8 data bits (8N1), the MSB from

the DTE is dropped as the 9-bit word is passed from the

DTE side to the DCE (line) side. In this case, the

dropped ninth bit can then be used as an escape

mechanism. However, if the DTE format is 8N1, and the

line data format is 9N1, an MSB equal to 0 is added to

the 8-bit word as it is passed from the DTE side to the

DCE side.

000

001

010

011

100

101

110

111

1200

2400

9600

19200

38400

115200

307200

Immediately after the ATSE0=xx string is sent, the host

UART must be reprogrammed to the new DTE rate in

order to communicate with the Si2401.

The carriage return character following the ATSE0=xx

string must be sent at the new DTE rate to observe the

“O” response code. See Table 12 on page 24 for the

response code summary.

The Si2401 UART does not continuously check for stop

bits on the incoming digital data. Therefore, if the TXD

pin is not high, the RXD pin may echo meaningless

characters to the host UART. This requires the host

UART to flush its receiver FIFO upon initialization.

4.2. Configurations and Data Rates

The Si2401 can be configured to any of the Bell and

CCITT operation modes listed in Table 9. When

configured for V.22bis, the modem connects at

1200 bps if the far end modem is configured for V.22.

This device also supports SIA and other protocols for

the security industry. Table 7 provides the modulation

method, carrier frequencies, data rate, baud rate, and

notes on standard compliance for each modem

configuration of the Si2401. Table 9 shows example

register settings (S07) for some of the modem

configurations.

Si2401

Si3010

TXD

RXD

RJ11

DTE Interface

Data Rate: SE0[2:0] (SD)

Data Format: SE0[3] (ND)

DCE (Line) Interface

Data Rate: S07 (MF1)

Data Format: S15 (MLC)

Figure 3. Link and Line Data Formats

Rev. 1.0

13

Si2401

4.2.1. Command/Data Mode

After the middle of the stop bit time, the Si2401 begins

looking for a logic 1 to logic 0 transition signaling the

start of the next character on TXD to be sent to the line

(remote modem).

Upon reset, the modem is in command mode and

accepts AT-style commands. An outgoing modem call

can be made using the “ATDT#” (tone dial) or “ATDP#”

(pulse dial) command after the device is configured. If 4.2.3. 9-Bit Data Mode (9N1)

the handshake is successful, the modem responds with

The 9-bit data mode is set by SE0[3] (ND) = 1. It is

the “c”, “d”, or “v” string and enters data mode. (The

byte following the “c”, “d”, or “v” is the first data byte.) At

this point, AT-style commands are not accepted. There

are three methods that may be used to return the

Si2401 to command mode:

asynchronous, full duplex, and uses a total of 11 bits

including a start bit (logic 0), 9 data bits, and a stop bit

(logic 1). Data received from the line (remote modem) is

transferred from the Si2401 to the host on the RXD pin.

Data transfer to the host begins when the Si2401

asserts a logic 0 start bit on RXD. Data is shifted out of

the Si2401 LSB first at the DTE rate determined by the

SE0[2:0] (SD) setting and terminates with a stop bit.

Use the ESC pin—To program the GPIO3 pin to

function as an ESCAPE input, set GPIO3

SE2[5:4] = 11. In this setting, a positive edge

detected on this pin returns the modem to command Data from the host for transmission to the line (remote

mode. The “ATO” string can be used to reenter data modem) is shifted to the Si2401 on TXD beginning with

mode.

a start bit, LSB, first at the DTE rate determined by the

S-Register SE0[2:0] (SD) setting, and terminates with a

stop bit. After the middle of the stop bit time, the Si2401

begins looking for a logic 1 to logic 0 transition signaling

the start of the next character on TXD to be sent to the

line (remote modem).

Use 9-bit data mode—If 9-bit data format with

escape is programmed, a 1 detected on bit 9 returns

the modem to command mode. (See Figure 2 on

page 9.) This is enabled by setting SE0[3] (ND) = 1

and S15[0] (NBE) = 1. The ATO string can be used

to reenter data mode. Ninth bit escape does not

work in the security modes.

The ninth data bit may be used to indicate an escape by

setting S15[0] (NBE) = 1. In this mode, the ninth data bit

is normally set to 0 when the modem is online. When

the ninth data bit is set to 1, the modem goes offline into

command mode, and the next frame is interpreted as an

AT command. Data mode can be reentered using the

ATO command.

Use “+++”—The escape sequence is a sequence of

three escape characters that are set in S-register

®

S0F (“+” characters by default). If the ISOmodem

chipset detects the “+++” sequence and detects no

activity on the UART before or after the “+++”

sequence for a time period set by S-register S10, it

returns to command mode. To disable this escape

sequence, set S-register S10 = FF. To remove the

time-dependent behavior, set S-register S10 = 00.

4.2.4. Flow Control

No flow control is needed if the DTE rate and DCE rate

are the same. If the serial link (DTE) data rate is set

higher than the line (DCE) rate of the modem, flow

control is required to prevent loss of data to the

transmitter.

Whether using an escape method or not, when the

carrier is lost, the modem automatically returns to

command mode and reports “N”.

To control data flow, the clear-to-send (CTS) pin is used.

When CTS is asserted, the Si2401 is ready to accept a

character. While CTS is negated, no data should be

sent to the Si2401 on TXD. To simplify flow control, the

Si2401 has an integrated ten character transmit FIFO

and allows for two different CTS reporting methods. By

default, the CTS pin is negated as soon as a start bit is

detected on the TXD pin and remains negated until the

modem is ready to accept another character (see

Figure 2 on page 9.) By setting SFC7[7] = 1 (CTSM),

CTS is negated when the FIFO is 70% full and is

reasserted when the FIFO is 30% full.

4.2.2. 8-Bit Data Mode (8N1)

The 8-bit data mode is the default mode after powerup

or reset and is set by SE0[3] (ND) = 0 . It is

b

asynchronous, full duplex, and uses a total of 10 bits

including a start bit (logic 0), eight data bits, and a stop

bit (logic 1). Data received from the remote modem is

transferred from the Si2401 to the host on the RXD pin.

Data transfer to the host begins when the Si2401

asserts a logic 0 start bit on RXD. Data is shifted out of

the Si2401 LSB first at the DTE rate determined by the

SE0[2:0] (SD) setting and terminates with a stop bit.

Data from the host for transmission to the remote

modem is shifted to the Si2401 on TXD beginning with a

start bit, LSB, first at the DTE rate determined by the

SE0[2:0] setting, and terminates with a stop bit.

14

Rev. 1.0

Si2401

(WOR) = 1 (WOR = 0 by default).

4.3. Low Power Modes

b

Total Powerdown. Setting SF1[5] = 1 and SF1[6] = 1

places the Si2401 into a total powerdown mode. All

logic is powered down including the crystal oscillator

and clock-out pin. Only a hardware reset can restart

the Si2401.

The Si2401 has three low-power modes:

DSP Powerdown. The DSP processor can be

powered down by setting register

SEB[3] (PDDE) = 1.

In this mode, the serial interface still functions, and

the modem detects ringing and intrusion. However,

no modem modes or tone detection features

function.

4.4. Global DAA Operation

The Si2401 chipset contains an integrated silicon direct

access arrangement (silicon DAA) that provides a

programmable line interface to meet international

telephone line requirements. Table 10 gives the DAA

register settings required to meet various country PTT

standards.

Wake-Up-On-Ring. By issuing the ATz command,

the Si2401 goes into a low-power mode where both

the microcontroller and DSP are powered down.

Only an incoming ring, a low TXD signal, or a total

reset will power up the chip again. Return from

wake-on-ring triggers the INT pin if S09[6]

Table 10. Country-Specific Register Settings

Si2401 Register

Country

SF5

ILIM

SF6

OHS

RZ

RT MINI[1:0] DCV[1:0] ACT[3:0]

AT Command

String

Algeria

Argentina

Armenia

10

00

01

10

00

10

00

10

00

10

00

1

0

1

0

1

0

1

0

1

0

00

10

00

10

01

10

0011

0000

0011

0000

0011

0000

0011

0000

0011

0000

ATSF5=28SF6=23

ATSF5=00SF6=20

ATSF5=10SF6=93

ATSF5=28SF6=23

ATSF5=00SF6=20

ATSF5=28SF6=23

ATSF5=00SF6=20

ATSF5=28SF6=23

ATSF5=00SF6=20

ATSF5=28SF6=23

ATSF5=00SF6=20

Australia

Austria (EU)

Bahamas

Bahrain

Belarus

Belgium (EU)

Bermuda

Brazil

Brunei

Bulgaria

Canada

Caribbean

Chile

China - People's Republic

Colombia

Costa Rica

Rev. 1.0

15

Si2401

Table 10. Country-Specific Register Settings

Si2401 Register

SF5

ILIM

SF6

Country

OHS

RZ

RT MINI[1:0] DCV[1:0] ACT[3:0]

AT Command

String

Croatia

Cyprus (EU)

Czech Republic (EU)

Denmark (EU)

Dominican Republic

Dubai

10

00

10

00

10

00

10

00

10

00

10

00

1

0

1

0

1

0

1

0

1

0

1

0

1

0

00

01

00

10

00

10

01

10

01

10

0011

0000

0011

0000

0011

0000

0011

0000

0011

0000

0011

0000

ATSF5=28SF6=23

ATSF5=00SF6=20

ATSF5=28SF6=23

ATSF5=00SF6=20

ATSF5=28SF6=23

ATSF5=00SF6=20

ATSF5=28SF6=23

ATSF5=00SF6=20

ATSF5=28SF6=23

ATSF5=00SF6=20

ATSF5=28SF6=23

ATSF5=20SF6=53

ATSF5=28SF6=23

ATSF5=00SF6=90

ATSF5=00SF6=20

Equador

Egypt

El Salvador

Estonia (EU)

Finland (EU)

France (EU)

Georgia

Germany (EU)

Ghana

Greece (EU)

Guadeloupe

Guam

Hong Kong

Hungary (EU)

Iceland (CTR-21)

India

Indonesia

Ireland (EU)

Israel

Italy (EU)

Japan

Jordan

Kazakhstan

16

Rev. 1.0

Si2401

Table 10. Country-Specific Register Settings

Si2401 Register

Country

SF5

ILIM

SF6

OHS

RZ

RT MINI[1:0] DCV[1:0] ACT[3:0]

AT Command

String

Korea

Kuwait

00

10

00

10

00

10

00

10

00

10

00

10

00

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

00

10

00

10

00

10

00

10

01

10

01

10

01

10

0000

0011

0000

0011

0000

0011

0100

0011

0000

0011

0000

ATSF5=04SF6=20

ATSF5=00SF6=20

ATSF5=28SF6=23

ATSF5=04SF6=23

ATSF5=28SF6=23

ATSF5=00SF6=20

ATSF5=00SF6=90

ATSF5=28SF6=23

ATSF5=00SF6=20

ATSF5=28SF6=23

ATSF5=00SF6=24

ATSF5=28SF6=23

ATSF5=00SF6=90

ATSF5=00SF6=20

ATSF5=00SF6=90

ATSF5=28SF6=23

ATSF5=00SF6=20

Kyrgyzstan

Latvia (EU)

Lebanon

Lesotho

Liechtenstein (CTR-21)

Lithuania (EU)

Luxembourg (EU)

Macao

Malaysia

Malta (EU)

Martinique

Mexico

Moldova

Morocco

Netherlands (EU)

New Zealand

Nigeria

Norway (CTR-21)

Oman

Pakistan

Paraguay

Peru

Philippines

Poland (EU)

Polynesia (French)

Portugal (EU)

Puerto Rico

Rev. 1.0

17

Si2401

Table 10. Country-Specific Register Settings

Si2401 Register

SF5

ILIM

SF6

Country

OHS

RZ

RT MINI[1:0] DCV[1:0] ACT[3:0]

AT Command

String

Qatar

Reunion

00

10

00

10

00

10

00

10

00

10

00

10

00

10

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

10

00

10

00

01

10

01

10

01

10

01

10

0000

0011

0000

0011

0000

0011

0000

0011

0000

0011

0000

0011

ATSF5=00SF6=90

ATSF5=28SF6=23

ATSF5=00SF6=10

ATSF5=00SF6=20

ATSF5=28SF6=23

ATSF5=04SF6=23

ATSF5=28SF6=23

ATSF5=00SF6=20

ATSF5=28SF6=23

ATSF5=00SF6=90

ATSF5=00SF6=20

ATSF5=00SF6=10

ATSF5=00SF6=20

ATSF5=28SF6=23

ATSF5=00SF6=20

ATSF5=28SF6=23

ATSF5=00SF6=20

ATSF5=28SF6=23

Romania

Russia

Saudi Arabia

Singapore

Slovakia (EU)

Slovenia (EU)

South Africa

Spain (EU)

Sri Lanka

Sweden (EU)

Switzerland (CTR-21)

Syria

Taiwan

Thailand

Tunisia

Turkey

UAE

Ukraine

United Kingdom (EU)

Uruguay

USA

Uzbekistan

Venezuela

Yemen

Zambia

18

Rev. 1.0

Si2401

directly through the LCS register. Upon detecting an

intrusion, an "i" result code is sent to the host if it is in

the call negotiation stage or command mode.

Otherwise, the modem can be programmed to generate

an interrupt to notify the host of the intrusion.

4.5. Parallel Phone Detection

®

The ISOmodem chipset is able to detect when another

telephone, modem, or other device is using the phone

line. This allows the host to avoid interrupting another

phone call when the phone line is already in use and to

intelligently handle an interruption when the ISOmodem

chipset is using the phone line.

The off-hook intrusion algorithm monitors the value of

LCS (SF3) at a sample rate determined by the DGSR

(SDF, bits 6:0) register (40 ms units). The algorithm

compares each LCS sample to the reference value in

the ACL register (S12). If LCS is lower than ACL by an

amount greater than DCL (S11, bits 4:0), the algorithm

waits for another LCS sample, and if the next LCS

sample is also lower than ACL by an amount greater

than DCL, an interrupt occurs. This helps the

ISOmodem chipset avoid a false parallel phone

detection (PPD) interrupt due to glitches on the phone

line. The ACL is continually updated with the value of

LCS as outlined below. The algorithm can be outlined

as follows:

4.5.1. On-Hook Intrusion Detection

When the ISOmodem chipset is sharing the telephone

line with other devices, it is important that it not interrupt

a call in progress. To detect when another device is

using the shared telephone line, the host can use the

ISOmodem chipset to monitor the TIP-RING dc voltage

with the LVS[7:0] bits (SDB). The LVS[7:0] bits have a

resolution of 1 V per bit with an accuracy of

approximately ±10%. Bits 0 through 6 of this 8-bit signed

2s complement number indicate the value of the line

voltage, and the sign bit (bit 7) indicates the polarity of

TIP and RING.

If LCS(t) = LCS(t – 40 ms x DGSR)

When all devices on a particular telephone line are on-

hook, there is no loop current flowing through TIP and

RING. Therefore, the voltage across TIP and RING is at

and

LCS(t) – ACL > DCL

a maximum. (On most telephone lines, this on-hook then ACL = LCS(t)

voltage is a minimum of 40 V.) Once a device goes off-

If (ACL – LCS[t – 40 ms x DGSR]) > DCL)

hook, current flows through TIP and RING on that

device, and the TIP-RING voltage drops appreciably.

(On most telephone lines, this off-hook voltage is a

maximum of 20 V.)

and

(ACL – LCS[t]) > DCL)

Then, an intrusion is sent to the host.

If the host checks the TIP-RING voltage via LVS before The very first sample of LCS the algorithm uses after

causing the ISOmodem chipset to dial out or go off- going off-hook does not have any previous samples for

hook, the host can determine if another device is using comparison. If LCS was measured during a previous

the telephone line. One way to do this is to verify that call, this value of LCS may be used as an initial

the voltage represented in LVS is above some fixed reference. ACL may be written by the host with this

threshold, such as 30 V.

known value of LCS. If ACL is non-zero, the ISOmodem

chipset uses ACL as the first valid LCS sample in the

off-hook intrusion algorithm. If ACL is 0 (default after

reset), the ISOmodem chipset ignores the register and

does not begin operating the algorithm until two LCS

samples have been received. Additionally, immediately

after a modem call, ACL is updated automatically with

the last valid LCS value before a parallel phone

detection (PPD) intrusion or going back on-hook.

4.5.2. Off-Hook Intrusion Detection

After it has been determined that it is safe to use the

phone line without interrupting a call, the host can

instruct the ISOmodem chipset to begin a call or go off-

hook. However, once the call has begun and the

ISOmodem chipset is in data mode, the serial port is

used for modem data making it difficult for the host to

monitor registers. Therefore, when the ISOmodem

chipset is off-hook, an algorithm is implemented to

automatically monitor the TIP-RING loop current via the

LCS register (SF3). Because the TIP-RING voltage

drops significantly when off-hook, TIP-RING current is a

better indicator of another device using the phone line.

The LCS[7:0] bits have a resolution of 1.1 mA per bit.

An LCS register value of 0x00 indicates less than the

required loop current is present, and a value of 0xFF

indicates excessive current draw (>120 mA if ILIM = 0

or >60 mA if ILIM = 1). The user can read these bits

The off-hook intrusion algorithm does not begin to

operate immediately after going off-hook. This is to

avoid triggering an interrupt due to transients resulting

from the ISOmodem chipset itself going from on-hook to

off-hook. The time that elapses between the ISOmodem

chipset going off-hook and the intrusion algorithm

starting defaults to one second and may be adjusted via

the IST register (S82, bits 7:4). If ACL is written to a

non-zero value before going off-hook, a parallel phone

intrusion that occurs during this IST interval and

Rev. 1.0

19

Si2401

sustains through the end of the interval triggers an S09[1] interrupt status. As long as GPIO4 is

interrupt.

programmed as INT and the overcurrent mask bit is

enabled by setting S08[1](OCDM) = 1, INT asserts

during an overcurrent situation. The host may then

check S09[1] (OCD) via the AT:I command to confirm

that an overcurrent condition occurred.

The off-hook intrusion algorithm may additionally be

disabled for a period of time after dialing begins via the

IB register (S82, bits 2:1). This avoids triggering an

interrupt due to pulse dialing, open-switch intervals, or

line transients from central office switching. Intrusion 4.6.4. Caller ID Decoding Operation

may be disabled from the start of dialing to the end of

The Si2401 supports full caller ID detection and decode

dialing (IB = 01 ), from the start of dialing to the timeout

b

for US Bellcore and UK standards. To use the caller ID

decoding feature, the following configuration is

necessary:

of the IS (S29, bits 7:0) by setting IB = 10 (IB = 2), or

b

from the start of dialing to carrier detect by setting

IB = 11b. The off-hook intrusion algorithm is only

suspended (not disabled) during this IB interval.

Therefore, any intrusion that occurs during the IB

interval and sustains through the end of the interval

triggers a PPD interrupt.

1. Set SE0[3] (ND) = 0 (set modem to 8N1

b

configuration).

2. Set S0C[6:5] (CIDM) = 01 (set modem to Bellcore

type caller ID) or S13[2] (CIDB) = 1 (set modem to

UK type caller ID).

4.6. Interrupt Detection

4.6.5. Caller ID Monitor/Bellcore Caller ID

The INT interrupt pin can be programmed to alert the

host of loss of carrier, loss of phone line voltage/current,

parallel phone detection, and other interrupts listed in

the interrupt status mask (S08). After the host receives

an interrupt via the INT pin, the host should issue the

AT:I command. This command causes a read-clear of

the WOR, PPD, NLD, RI, OCD, and REV bits of the S09

register and raises (deactivates) the INT pin. All the

interrupt status bits in register S09 remain high after

being set until cleared by the AT:I command.

The Si2401 continuously monitors the phone line for the

caller ID mark signals. This can be useful in systems

that require detection of caller ID data before the ring

signal, voice mail indicator signals, and Type II caller ID

monitor support. To force the Si2401 into caller ID

monitor mode, set SOC[6:5] (CIDM) = 11.

Note: CIDM should be disabled before going off-hook.

4.6.6. UK Caller ID Operation

The Si2401 starts searching for the Idle State Tone Alert

Signal. When this signal has been detected, the Si2401

transmits an “a” to the host. After the Idle State Tone

Alert Signal is completed, the Si2401 applies the

wetting pulse for the required 15 ms by quickly going

off-hook and on-hook. From this point on, the algorithm

is identical to that of Bellcore in that it searches for the

channel seizure signal and the marks before echoing an

“m” and then reports the decoded caller ID data.

4.6.1. Loop Current Detection

In addition to monitoring parallel phone intrusion, it is

possible to monitor the loss of loop current. This feature

can be enabled by setting S08[4] (NLDM) = 1. This

feature is disabled by default. If the loop current is too

low for normal DAA operation, S09[4] (NLD) is set.

During this event, if the NLR result code is enabled by

setting S62[1](NLR) = 1, the “l” result code is sent. Once

the loop current returns to a normal current state, the “L”

result code is sent. The INT pin is also asserted if

enabled.

4.7. V.23 Operation/V.23 Reversing

The Si2401 supports full V.23 operation including the

V.23 reversing procedure. V.23 operation is enabled by

4.6.2. Loss-of-Carrier Detection

setting S07 (MF1) = xx10x110 or xx01x110 . If

b

S07[5] (V23R) = 1 , the Si2401 transmits data at 75 bps

and receives data at 600 or 1200 bps. If

The Si2401 has two methods of implementing a loss-of-

carrier function. If GPIO4 is programmed as INT, and if

S08[7](CDM) = 1, INT asserts in data mode when a

loss-of-carrier is detected. The carrier detect function

may also be implemented on GPIO2 by setting SE2[3:2]

(GPIO2) = 01 and SOC[7](CDE) = 1.

b

S07[4] (V23T) = 1 , the Si2401 receives data at 75 bps

b

and transmits data at 600 or 1200 bps. S07[2] (BAUD)

is the 1200 or 600 bps indicator. BAUD = 1 enables the

b

1200/600 V.23 channel to run at 1200 bps, while

BAUD = 0 enables 600 bps operation.

b

4.6.3. Overcurrent Detection

When a V.23 connection is successfully established, the

modem responds with a “c” character if the connection

is made with the modem transmitting at 1200/600 bps

and receiving at 75 bps. The modem responds with a

“v” character if a V.23 connection is established with the

The Si2401 has an integrated overcurrent detection

feature. The Si2401 begins monitoring for an

overcurrent condition at a programmable time set by

S32 (OCDT) after going off-hook (default = 20 ms). If an

overcurrent condition is detected, the Si2401 sets

20

Rev. 1.0

Si2401

modem transmitting at 75 bps and receiving at 1200/ Successful completion of a turnaround procedure in

600 bps.

master or slave mode automatically updates

S07[4] (V23T) and S07[5] (V23R) to indicate the new

status of the V.23 connection.

The Si2401 supports the V.23 turnaround procedure.

This allows a modem that is transmitting at 75 bps to

initiate a “turnaround” procedure so that it can begin

transmitting data at 1200/600 bps and receiving data at

75 bps. The modem is defined as being in V.23 master

mode if it is transmitting at 75 bps, and it is defined as

being in slave mode if the modem is transmitting at

1200/600 bps. The following paragraphs give a detailed

description of the V.23 turnaround procedure.

To avoid using the INT pin, the host may also be notified

of the INT condition by using 9-bit data mode. Setting

S15[0] (NBE) = 1 and S0C[3] (9BF) = 0 configures

b

the ninth bit on the Si2401 TXD path to function exactly

as the INT pin has been described.

4.8. V.42 HDLC Mode

The Si2401 supports V.42 through hardware HDLC

framing in all modem data modes. Frame packing and

unpacking including opening and closing flag generation

and detection, CRC computation and checking, zero

insertion and deletion, and modem data transmission

and reception are all performed by the Si2401. V.42

error correction and V.42bis data compression must be

performed by the host.

4.7.1. Modem in Master Mode

To perform a direct turnaround once a modem

connection is established, the master host goes into

online-command-mode by sending an escape

command (Escape pin activation, TIES, or ninth bit

escape) to the master modem.

Note: The host can initiate a turnaround only if the Si2401 is

the master.

The digital link interface in this mode uses the same

UART interface (8-bit data and 9-bit data formats) as in

the asynchronous modes, and the ninth data bit may be

The host then sends the ATRO command to the Si2401

to initiate a V.23 turnaround and return to the online

(data) mode.

used as an escape by setting S15[0] (NBE) = 1 . When

b

The Si2401 then changes its carrier frequency (from

390 Hz to 1300 Hz) and waits to detect a 390 Hz carrier

for 440 ms. If the modem detects more than 40 ms of a

390 Hz carrier in a time window of 440 ms, it echoes the

“c” response character. If the modem does not detect

more than 40 ms of a 390 Hz carrier in a time window of

440 ms, it hangs up and echoes the “N” (no carrier)

character as a response.

using HDLC in 9-bit data mode, if the ninth bit is not

used as an escape, it is ignored.

To use the HDLC feature on the Si2401, the host must

enable HDLC operation by setting S13[1] (HDEN) = 1 .

b

The host may initiate the call or answer the call using

either the “ATDT#”, the “ATA” command or the auto-

answer mode. (The auto-answer mode is implemented

by setting register S00 (NR) to a non-zero value.) When

the call is connected, a “c”, “d”, or “v” is echoed to the

host controller. The host may now send/receive data

across the UART using either the 8-bit data or 9-bit data

formats with flow control.

4.7.2. Modem in Slave Mode

Configure GPIO4 as INT (SE2[7:6] [GPIO4] = 11 ). The

b

Si2401 performs a reverse turnaround when it detects a

carrier drop longer than 20 ms. The Si2401 then

reverses (changes its carrier from 1300 Hz to 390 Hz)

and waits to detect a 1300 Hz carrier for 400 ms. If the

Si2401 detects more than 40 ms of a 1300 Hz carrier in

a time window of 400 ms, it sets the S09[7] bit, and the

next character echoed by the Si2401 is a “v”.

At this point, the Si2401 begins framing data into the

HDLC format. On the transmit side, if no data is

available from the host, the HDLC flag pattern is sent

repeatedly. When data is available, the Si2401

computes the CRC code throughout the frame, and the

data is sent with the HDLC zero-bit insertion algorithm.

If the Si2401 does not detect more than 40 ms of the

1300 Hz carrier in a time window of 400 ms, it reverses

again and waits to detect a 390 Hz carrier for 440 ms.

Then, if the Si2401 detects more than 40 ms of a

390 Hz carrier in a time window of 220 ms, it sets the

S09[7] bit, and the next character echoed by the Si2401

is a “c”.

HDLC flow control operates in a similar manner to

normal asynchronous flow control across the UART and

is shown in Figure 4. To operate flow control (using the

CTS pin to indicate when the Si2401 is ready to accept

a character), a DTE rate higher than the line rate should

be selected.

At this point, if the Si2401 does not detect more than

40 ms of the 390 Hz carrier in a time window of 440 ms,

it hangs up, sets the S09[7] bit, and the next character

echoed by the Si2401 is an “N” (no carrier).

Rev. 1.0

21

Si2401

The method of transmitting HDLC frames is as follows:

2. When the Si2401 detects the stop flag, it sends the

last data word in the frame as well as the two CRC

bytes and determines if the CRC checksum

matches. Thus, the last two bytes are not frame data

but are the CRC bytes, which can be discarded by

the host. If the checksum matches, the Si2401

echoes “G” (good). If the checksum does not match,

the Si2401 echoes “e” (error). Additionally, if the

Si2401 detects an abort (seven or more contiguous

ones), it echoes an “A”.

1. After the call is connected, the host should begin

sending the frame data to the Si2401 using the CTS

flow control to ensure data synchronicity.

2. When the frame is complete, the host should simply

stop sending data to the Si2401. Since the Si2401

does not yet recognize the end-of-frame, it expects

an extra byte and asserts CTS as shown in

Figure 4A. If CTS is used to cause a host interrupt,

this final interrupt should be ignored by the host.

When the “G”, “e”, or “A” (referred to as a frame

result word) is sent, the Si2401 raises the EOFR

(end of frame receive) pin (see Figure 4B). The

GPIO1 pin must be configured as EOFR by setting

3. When the Si2401 is ready to send the next byte, if it

has not yet received any data from the host, it

recognizes this as an end-of-frame, raises CTS,

calculates the final CRC code, transmits the code,

and begins transmitting stop flags.

SE4[3] (GPE) = 1 . In addition to using the EOFR

b

pin to indicate that the byte is a frame result word, if

4. After transmitting the first stop flag, the Si2401

lowers CTS indicating that it is ready to receive the

next frame from the host. At this point, the process

repeats as in Step 1.

in 9-bit data mode (set S15[0] (NBE) = 1 ), the ninth

bit is raised if the byte is a frame result word. To

b

program this mode, set S0C[3] (9BF) = 1 and

b

SE0[3] (ND) = 1.

The method of receiving HDLC frames is as follows:

3. When the next frame of data is detected, EOFR is

lowered, and the process repeats at Step 1 .

b

1. After the call is connected, the Si2401 searches for

flag data. Then, once the first non-flag word is

detected, the CRC is continuously computed, and

the data is sent across the UART (8-bit data or 9-bit

data mode) to the host after removing the HDLC

zero-bit insertion. The DTE rate of the host must be

at least as high as that of data transmission. HDLC

mode only works with 8-bit data words; the ninth bit

is used only for escape on TXD and end-of-frame

received (EOFR) on RXD.

To summarize, when receiving HDLC frames, the host

begins receiving data asynchronously from the Si2401.

When each byte is received, the host should check the

EOFR pin (or the ninth bit). If the EOFR pin (or the ninth

bit) is low, the data is valid frame data. If the EOFR pin

(or the ninth bit) is high, the data is a frame result word.

Host begins frame N

Host finished sending frame N

Stop

Host begins frame N + 1

Start

TXD

Start

Frame N

Frame N + 1

Si2401 detects end of frame N.

(CTS used as normal flow control.)

Si2400 ready for byte 1 of frame N

Si2401 ready for byte 1

of frame N + 1.

CTS

Note: Figure not to scale.

A. Frame Transmit

RXD

Start

Receive Data

Stop

Start

CRC Byte 1

Stop

Start

CRC Byte 2

Stop

Start

Frame Result Word Stop

EOFR

(or bit 9)

B. Frame Receive

Figure 4. HDLC Timing

22

Rev. 1.0

Si2401

4.9. Fast Connect

4.10. Clock Generation Subsystem

In modem applications that require fast connection The Si2401 contains an on-chip clock generator. Using

times, it is possible to reduce the length of the a single master clock input, the Si2401 can generate all

handshake.

modem sample rates necessary to support V.22bis,

V.22/Bell212A, and V.21/Bell103 standards and a

9.6 kHz rate for audio playback. Either a 27 MHz or

4.9152 MHz clock on XTALI or a 4.9152 MHz crystal

across XTALI and XTALO form the master clock for the

Si2401. This clock source is sent to an internal phase-

locked loop (PLL) that generates all necessary internal

system clocks. The PLL has a settling time of ~1 ms.

Data on RXD should not be sent to the device prior to

settling of the PLL. By default, the Si2401 assumes a

4.9152 MHz clock input. If a 27 MHz clock on XTALI is

used, a pulldown resistor <10 kΩ must be placed

between GPIO4 (Si2401, pin 11) and GND.

Additional modem handshaking control can be adjusted

through the registers shown in Table 11. These registers

are most useful if the user has control of both the

originating and answering modems.

When the fast connect settings are used, there may be

unintended data received initially. The host must

tolerate these bytes.

Table 11. V.22/Bell212 Handshaking Control Registers

Register Name

Function

Units

Default

Fast

Connect

S1E

S1F

S20

S21

S22

S23

S24

S34

TATL Transmit Answer Tone Length

1 s

0x03

0x2D

0x5D

0x09

0xA2

0xCB

0x08

0x5A

00

F0

ATTD Answer Tone to Transmit Delay

UNL Unscrambled Ones Length—V.22

TSOD Transmit Scrambled Ones Delay—V.22

TSOL Transmit Scrambled Ones Length—V.22

VDDL V.22/22b Data Delay Low

5/3 ms

53.3 ms

5/3 ms

VDDH V.22/22b Data Delay High

(256) 5/3 ms

5/3 ms

TASL Answer Tone Length

(only used in S1E [TATL] = 0x00)

S35

RSOL Receive V.22 Scrambled Ones Length

5/3 ms

0xA2

00

Rev. 1.0

23

Si2401

are no characters between AT and <CR>, the modem

responds with “O” after the carriage return.

5. AT Command Set

The controller provides several vital functions including

AT command parsing, DAA control, connect sequence

5.1. Command Line Execution

control, DCE protocol control, intrusion detection, The characters in a command line are executed one at

parallel phone off-hook detection, escape control, caller a time. Unexpected command characters are ignored,

ID control and formatting, ring detect, DTMF control, call but unexpected data characters may be interpreted

progress monitoring, and HDLC framing. The controller incorrectly.

also writes to the control registers that configure the

After the modem has executed a command line, the

modem. Virtually all interaction between the host and

result code corresponding to the last command

the modem is done via the controller. The controller

executed is returned to the terminal or host. In addition

uses AT (ATtention) commands and S-Registers to

to the “ATH” and “ATZ” commands, the commands that

warrant a response (e.g., “ATSR?” or “ATI”) must be the

configure and control the modem.

The modem has two modes of operation: command last in the string and followed by a <CR>. All other

mode and data mode. The Si2401 is asynchronous in commands may be concatenated on a single line. To

both command mode and data mode. The modem is in echo command line characters, set the Si2401 to echo

command mode at powerup, after a reset, before a mode using the E1 command.

connection is made, after a connection is dropped, and

All numeric arguments, including the address and value

during a connection after successfully “Escaping” from

of an S-register, are in hexidecimal format, and two

the data mode back to the command mode using one of

digits must always be entered.

the methods previously described. The following section

5.2. <CR> End-Of-Line Character

describes the AT command set available in command

This character is typed to end a command line. The

value of the <CR> character is 13 in decimal, the ASCII

carriage return character. When the <CR> character is

entered, the modem executes the commands in the

command line.

mode.

The Si2401 supports a subset of the typical modem AT

command set since it is intended for use with a

dedicated microcontroller instead of general terminal

applications. AT commands begin with the letters AT

and are followed directly (no space) by the command.

(These commands are also case-sensitive.) All AT

commands must be entered in upper case including AT,

except w##, r#, m#, q#, and z (wakeup-on-ring).

Note: Commands that do not require a response are exe-

cuted immediately and do not need a <CR>.

Table 12. AT Command Set Summary

AT commands can be divided into two groups: control

commands and configuration commands. Control

commands, such as ATD, cause the modem to perform

an action (going off-hook and dialing). The value of this

type of command is changed at a particular time to

Command

Function

Answer line immediately with modem

Tone dial number

A

DT#

DP#

E

perform

a

particular action. For example, the

Pulse dial number

ATDT1234<CR> command causes the modem to go

off-hook and dial the number, 1234, via DTMF. This

action exists only during a connection attempt. No

enduring change in the modem configuration exists

after the connection or connection attempt has ended.

Local echo on/off

H0

H1

I

Go on-hook (hang up modem)

Go off-hook

Chip revision

Configuration

commands

change

modem

:I

Interrupt read and clear

Speaker control options

Return online

characteristics until they are modified or reversed by a

subsequent configuration command or the modem is

reset. Modem configuration status can be determined

with the use of “ATSR?<CR>” where “R” is the two-

character hexadecimal address of an S-register.

M

O

RO

S

V.23 reverse

Read/write S-Registers

Write S-Register in binary

Read S-Register in binary

Monitor S-Register in binary

A command line is defined as a string of characters

starting with AT and ending with an end-of-line

character, <CR> (13 decimal). Command lines may

contain several commands, one after another. If there

w##

r#

m#

24

Rev. 1.0

Si2401

character is interpreted as an abort, and the Si2401

returns to command mode ready to accept AT

commands. A line feed character immediately following

the <CR> is treated as an “extra character” and aborts

the call.

Table 12. AT Command Set Summary

q#

V0

V1

Read S-Register in binary

Result code with no carriage return

Result code with added carriage

returns

If the modem does not have to dial (i.e., “ATDT<CR>” or

“ATDP<CR>” with no dial string), the Si2401 assumes

the call was manually established and attempts to make

a connection.

Z

z

Software reset

Wakeup on ring

5.3.1. Automatic Tone/Pulse Dialing

5.3. AT Command Set Description

The Si2401 can be configured to attempt DTMF dialing

and automatically revert to pulse dialing if it determines

that the line is not DTMF-capable. This feature is best

explained by the following example.

A

Answer

The “A” command makes the modem go off-hook and

respond to an incoming call. This command is to be

executed after the Si2401 has indicated a ring has If it is desired that the telephone number, 12345, be

occurred. (The Si2401 indicates an incoming ring by dialed, it is normally accomplished through either the

echoing an “R”.)

ATDT12345 or the ATDP12345 command. In the force

pulse dialing mode of operation, the following string

should be issued instead: ATDT1,p12345

This command is aborted if any other character is

transmitted to the Si2401 before the answer process is

completed.

If the result code returned is “t,”, this indicates that the

dialing was accomplished using DTMF dialing. If the

result code returned is “tt,”, it indicates that the dialing

was accomplished using pulse dialing.

Auto answer mode is entered by setting S00 (NR) to a

non-zero value. NR indicates the number of rings before

answering the line.

In the above example, the Si2401 dials the first digit “1”

using DTMF dialing. The “,” is used to pause in order to

ensure that the central office has had time to accept the

DTMF digit “1”. When the Si2401 processes the “p”

command, it attempts to detect a dial tone. If a dial tone

is detected, the DTMF digit “1” was not effective; hence,

the line does not support DTMF dialing. Conversely, if

the dial tone is not detected, the DTMF digit “1” was

effective, and the line supports DTMF dialing. The

character after the “p” may or may not be dialed

depending on whether the DTMF digit “1” was effective.

If the “1” was effective (DTMF mode), the character after

the “p” is skipped. The next DTMF digit to be dialed is

“2”. Subsequent digits are all DTMF. If the “1” was not

effective, the first character after the “p” (the “1”) is

pulse-dialed, and subsequent digits are all pulse-dialed.

Upon answering, the modem communicates by

whatever protocol has been determined via the modem

control registers in S07 (MF1).

If no transmit carrier signal is received from the calling

modem within the time specified in S39 (CDT), the

modem hangs up and enters the idle state.

D

Dial

DT#

DP#

Tone Dial Number.

Pulse Dial Number.

The D commands make the modem dial a telephone

call according to the digits and dial modifiers in the dial

string following the command. A maximum of 64 digits is

allowed. A DT command performs tone dialing, and a

DP command performs pulse dialing.

The ATH1 command can be used to go off-hook without

detecting a dial tone or dialing.

E

Command Mode Echo

Tells the Si2401 whether or not to echo characters sent

from the terminal.

The dial string must contain only the digits “0–9”, “*”, “#”,

“A”, “B”, “C”, “D”, or the modifiers “;”, “/”, or “,”. Other

characters are interpreted incorrectly. The modifier “,”

EO

causes a two-second delay (added to the spacing value Does not echo characters sent from the terminal.

in S04) in dialing. The modifier “/” causes a 125 ms

delay (added to the spacing value in S04) in dialing. The

modifier “;” returns the device to command mode after

dialing and must be the last character.

E1

Echoes characters sent from the terminal.

H0

Hang up and go into command mode (go offline).

Off-hook

Go off-hook and remain in command mode.

Hangup

If any character is received by the Si2401 between the

ATDT#<CR> (or ATDP#<CR>) command and when the H1

connection is made (“c” or “d” is echoed), the extra

Rev. 1.0

25

Si2401

Note: Two digits must always be entered for R.

w## Write S Register in Binary

I

Chip Identification

This command causes the modem to echo the chip

revision for the Si2401 device.

This command writes a register in binary format. The

first byte following the “w” is the address in binary

format, and the second byte is the data in binary format.

This is a more rapid method to write registers than the

“SR=N” command and is recommended for use by a

host microcontroller.

A = Revision A

B = Revision B

C = Revision C, etc.

I6

®

Display the ISOmodem model number.

r#

Read S Register in Binary

This command reads a register in binary format. The

byte following the “r” is the address in binary format.

The modem echoes the contents of this register in

binary format. This is a more rapid method to read

registers than the “SR?” command and is

recommended for use by a host microcontroller. Modem

result codes should be disabled to avoid confusing a

result code with the value being read. (S62 = 40).

“2401” = Si2401.

:I

Interrupt Read

This command causes the ISOmodem chipset to report

the contents of the interrupt status register (S09). The

WOR, PPD, NLD, RI, OCD, and REV bits are also

cleared, and the INT is deactivated on this read.

M

Speaker On/Off Options

These options are used to control AOUT for use with a

call progress monitor speaker.

Notes:

1. w## and r# are not required to be on separate lines (i.e.,

no <CR> between them). Also, the result of an r# is

returned immediately without waiting for a <CR> at the end

of the AT command line.

M0

Speaker always off.

M1

2. Once a <CR> is encountered, “AT” is again required to

begin the next “AT” command.

Speaker on until carrier established. The modem sets

SF4[3:2] (ARL) = 11 and SF4[1:0] (ATL) = 11 after a

connection is established.

b

m#

Monitor S Register in Binary

This command monitors a register in binary format. The

byte following the “m” is the address in binary format.

The Si2401 constantly transmits the contents of the

register at the set baud rate until a new byte is

transmitted to the device. The new byte is ignored and

viewed as a stop command. The modem result codes

should be disabled (as described above in r#) before

M2

Speaker always on.

M3

Speaker on after last digit dialed, off at carrier detect.

Return to Online Mode

O

This command returns the modem to the online mode. It using this command.

is frequently used after an escape sequence to resume

communication with the remote modem.

q#

Read S Register in Binary

This command is exactly the same as the r# command;

however, the response from the Si2401 is formatted as

0x55 followed by the contents of the register in binary.

This guarantees that the register contents are always

preceded by 0x55 and allows the result codes to remain

enabled.

RO

Turn-Around

This command initiates a V.23 “direct turnaround”

sequence and returns online.

S

S Register Control

SR=N

V

Result Code Options

Write an S register. This command writes the value “N”

to the S-register specified by “R”. “R” is a hexidecimal

number, and “N” must also be a hexadecimal number

from 00–FF. This command does not wait for a carriage

return <CR> before taking effect.

V0

Result codes reported according to Table 14.

V1

Result codes reported with an additional carriage return

and line feed (default).

Note: Two digits must always be entered for both “R” and “N”.

SR?

Read an S register. This command causes the Si2401

to echo the value of the S-register specified by R in hex

format. R must be a hexidecimal number.

26

Rev. 1.0

Si2401

Z

Software Reset

5.4.1. !1

The “Z” command initiates a software reset causing all Dial number and follow the DTMF security protocol.

registers, with the exception of E0, which controls the

DTE settings, to default to their powerup value.

ATDT<phone number>!1<message 1><CR>

The hardware reset pin, RESET (Si2401, pin 8), is used

The format for this command is as follows:

K

to reset the Si2401 to factory default settings.

!<message 2><CR>

z

Wakeup on Ring (lower-case z)

K

The Si2401 enters a low-power mode in which the DSP

and microcontroller are powered down. In this mode,

only the line-side device (Si3010) and the isolation

capacitor communication link are functional. An

incoming ring signal or line transient causes the Si2401

to power up and echo an “R”. Any character received on

the RXD pin also causes the Si2401 to exit the wakeup-

on-ring state. Return from wake-on-ring can also be set

!<message 3><CR>

K

!<message n><CR>

The modem dials the phone number and echoes “r”

(ring), “b” (busy), and “c” (connect) as appropriate. “c”

echoes only after the Si2401 detects the Handshake

Tone. After a 250 ms delay, the modem sends the

DTMF tones containing the first message data and

listens for a Kissoff Tone. If a Kissoff Tone shorter than

or equal to the value stored in S36(KTL)

(default = 480 ms) is detected, the Si2401 echoes a “K”.

A “k” is echoed if the length of the Kissoff Tone is longer

than the S36(KTL) value. The controller can then send

the next message. All messages must be preceded by a

“!” and followed by a <CR> and received by the Si2401

within 250 ms after the “K” is echoed. Setting

to trigger the INT pin by setting S08[6] (WORM) = 1 .

b

5.4. Alarm Industry AT Commands

The Si2401 supports a complete set of commands

necessary for making connections in security industry

systems. The Si2401 is configurable in two modes for

these applications. The first mode uses DTMF

messaging and is selected with the “!1” command. The

second mode uses FSK transmit with

acknowledgement and is selected with “!2”.

a

tone

The following are a few general comments about the

use of “!” commands. Specific details for each command

are given below. The first instance of the “!” must be on

the same line as the ATDT or ATDP command. DRT

S0C[0] (MCH) = 1 causes a “.” to be echoed when the

b

DTMF tone is turned on and a “/” character to be

echoed when the DTMF tone is turned off. This helps

the host monitor the status of the message being sent.

The previous message can be resent if the host

responds with a “~” after the Si2401 echoes a “K”. Any

character other than a “!” or a “~” sent to the modem

immediately after the “K” causes the modem to escape

to the command mode and remain off-hook. Any

character except “!” and “~” sent during the transmission

of a message causes the message to be aborted and

the modem to return to the command mode.

must be set to data mode (SE4[5:4] (DRT) = 0 ) before

b

attempting to send tones after a “!” command. The three

data-mode escape sequences (“+++”, “escape” pin, and

“ninth-bit”) function in “!2” mode. However, using the

“+++” or “ninth-bit” is not recommended because

characters could be sent to and misinterpreted by the

remote modem. Only the “escape pin” (Si2401, pin 14)

is recommended for use in the “!2” mode. The “!1” mode

has a special escape provision described below. The AT

commands for Alarm Industry applications are

described in Table 13.

If the Kissoff Tone is not received within 1.25 seconds,

the modem echoes a “^”. A “~” from the host causes the

last message to be resent. Any character other than a

“!” or a “~” sent to the modem immediately after the “^”

causes the modem to escape to the command mode

and remain off-hook.

Table 13. AT Command Set Extensions

for the Alarm Industry

Command

Function

5.4.2. !2

!1

Dial and switch to DTMF security

mode

Dial the number and follow the “SIA Format” protocol for

Alarm System Communications.

!2

X1

X2

Dial and switch to “SIA Format”

SIA half-duplex mode search

SIA half-duplex return online as

transmitter

The modem dials the phone number and echoes “r”

(ring), “b” (busy), and “c” (connect) as appropriate. “c”

echoes only after the Si2401 detects the Handshake

Tone and the speed synchronization signal is sent. The

signaling is at 300 bps, half-duplex FSK. The host can

X3

SIA half-duplex return online as

receiver

Rev. 1.0

27

Si2401

send the first SIA block after the “c” is received. Once

the block is transmitted, the modem can monitor for the

acknowledge tone by completing the following

sequence:

Table 14. Modem Result Codes

Command Function

1. Place the Si2401 in command mode by pulsing the

ESCAPE pin (Si2401 pin 14). The “+++” and “ninth-

bit” escape modes operate in the “!2” mode but are

not recommended because they can send unwanted

characters to the remote modem.

a

British Telecom Caller ID Idle Tone

Alert Detected

b

c

d

Busy Tone Detected

Connect

2. Issue the “ATX1” command to turn the modem

transmitter off and begin monitoring for the

acknowledgment tones.

Connect 1200 bps (when pro-

grammed as V.22bis modem)

f

Hookswitch Flash or Battery Reversal

Detected

3. Monitor for a positive (negative) acknowledgment “P”

(“N”) after the tone has been detected for at least

400 ms.

H

Modem Automatically Hanging Up in

!2, !1

4. The modem, still in command mode, can be placed

online as a transmitter by issuing the “ATX2”

command or a receiver by issuing the “ATX3”

command. If tonal acknowledgement is not used, the

host can toggle the ESCAPE pin to place the Si2401

in the command mode and issue an “ATX2” or an

“ATX3” command to reverse data direction.

Intrusion Completed (parallel phone

back on-hook)

I

i

Intrusion Detected (parallel phone off-

hook on the line)

K

k

Kissoff Tone Detected

Contact ID Kissoff Tone too long (!1)

Phone Line Detected

This sequence can be repeated for long messages.

L

l

5.5. Modem Result Codes and Call

Progress

No Phone Line Detected

Caller ID Mark Signal Detected

No Carrier Detected

m

N

n

Table 14 shows the modem result codes that can be

used in call progress monitoring. All result codes are a

single character to speed up communication and ease

host processing.

No Dial tone (time-out set by CW

[S02])

O

R

r

Modem OK Response

Incoming Ring Signal Detected

Ringback Tone Detected

Dial Tone

t

v

Connect 75 bps TX (V.23 originate

only)

x

Overcurrent State Detected After an

Off-Hook Event

^

,

Kissoff tone detection required

Dialing Complete

28

Rev. 1.0

Si2401

5.5.1. Automatic Call Progress Detection

The call progress biquad filters can be programmed to

have a custom frequency response and detection level

(as described in "6. Low Level DSP Control" on page

31).

The Si2401 has the ability to detect dial, busy, and

ringback tones automatically. The following is a

description of the algorithms that have been

implemented for these three tones.

Four dedicated user-defined frequency detectors can

be programmed to search for individual tones. The four

detectors have center frequencies that can be set by

registers UDFD1–4 (see Table 18). SE5[6] [TDET]

[SE8 = 0x02] Read Only Definition can be monitored,

along with TONE, to detect energy at these user-

defined frequencies. The default trip-threshold for

UDFD1–4 is –43 dBm but can be modified with the DSP

register, UDFSL.

Dial Tone. The dial tone detector looks for a dial

tone after going off-hook and before dialing is

initiated. This can be bypassed by enabling blind

dialing (set S07[6] (BD) = 1 ). After going off-hook,

b

the Si2401 waits the number of seconds in S01

(DW) before searching for the dial tone.

In order for a dial tone to be detected, it must be

present for the length of time programmed in S1C

(DTT). Once the dial tone is detected, dialing

commences. If a dial tone is not detected within the

time programmed in S02 (CW), the Si2401 hangs up

and echoes an “n” to the user.

By issuing the “ATDT;” command, the modem goes off-

hook and returns to command mode. The user can then

put the DSP into call progress monitoring by first setting

SE8 = 0x02. Next, set SE5 (DSP2) = 0x00 so that no

tones are transmitted, and set SE6 (DSP3) to the

appropriate code, depending on which types of tones

are to be detected.

Busy/Ringback Tone. After dialing has completed,

the Si2401 monitors for Busy/Ringback and modem

answer tones. The busy and ringback tone detectors

both use the call progress energy detector. The

registers that set the cadence for busy and ringback

are listed in Table 15. Si2401 register settings for

global cadences for busy and ringback tones are

listed in Table 16.

At this point, users may program their own algorithm to

monitor the detected tones. If the host wishes to dial, it

should do so by blind dialing, setting the dial timeout

S01 (DW)

to

0

seconds,

and

issuing

an

“ATDT<Phone Number>;<CR>”

immediately causes the ISOmodem chipset to dial and

return to command mode.

command.

This

®

Table 15. Busy and Ringback Cadence

Registers

Once the host has detected an answer tone using

manual call progress, the host should immediately

execute the “ATDT” command in order to make a

connection. This causes the Si2401 to search for the

modem answer tone and begin the correct connect

sequence.

Register Name

Function

Units

10 ms

S16

S17

S18

S19

BTON

BTOF

BTOD

Busy tone on time

Busy tone off time

Busy tone delta time

In manual call progress, the DSP can be programmed

to detect specific tones. The result of the detection is

reported in SE5 (SE8 = 0x2) as explained above. The

output is priority-encoded such that if multiple tones are

detected, the one with the highest priority whose

detection is also enabled is reported (see SE5 [SE8=02]

Read Only.)

RTON Ringback tone on time

53.333

ms

S1A

S1B

RTOF Ringback tone off time

53.333

ms

RTOD Ringback tone delta time 53.333

ms

In manual call progress, the DSP can be programmed

to generate specific tones (see SE5[2:0] (TONC)

(SE8 = 02) Write Only). For example, setting

5.5.2. Manual Call Progress Detection

Because other call progress tones beyond those

described above may exist, the Si2401 supports manual

call progress. This requires the host to read and write

the low-level DSP registers and may require real time

control by the host. Manual call progress may be

required for detection of application-specific ringback,

dial tone, and busy signals. The section on DSP low-

level control should be read before attempting manual

call progress detection.

SE5[2:0] (TONC) = 110 generates the user-defined

b

tone (as indicated by UFRQ in Table 18) with an

amplitude of TGNL.

Table 17 shows the mappings of Si2401 DTMF values,

keyboard equivalents, and the related dual tones.

Rev. 1.0

29

Si2401

Table 16. Si2401 Global Ringer and Busy Tone Cadence Settings

Country

RTON

S19

RTOF

S1A

RTOD

S1B

BTON

S16

BTOF

S17

BTOD

S18

Australia

Austria

Belgium

Brazil

0x07

0x12

0x1C

0x12

0x0E

0x1C

0x12

0x07

0x12

0x07

0x17

0x16

0x07

0x12

0x03

0x5D

0x38

0x4B

0x38

0x4B

0x8C

0x5D

0x41

0x4B

0x03

0x4B

0x03

0x46

0x58

0x03

0x4B

0x01

0x0A

0x06

0x08

0x06

0x08

0x0F

0x0A

0x07

0x08

0x01

0x08

0x01

0x0F

0x09

0x01

0x08

0x25

0x1E

0x32

0x19

0x14

0x23

0x32

0x18

0x19

0x1E

0x32

0x25

0x1E

0x32

0x1E

0x19

0x4B

0x32

0x25

0x1E

0x32

0x19

0x32

0x23

0x32

0x24

0x19

0x1E

0x32

0x25

0x1E

0x32

0x1E

0x19

0x4B

0x32

0x04

0x03

0x05

0x03

0x05

0x04

0x05

0x0A

0x03

0x05

0x04

0x03

0x05

0x03

0x08

0x05

Bulgaria

China

Cyprus

Czech Republic

Denmark

Finland

France

Germany

Great Britain

Greece

Hong Kong, New Zealand

Hungary

Iceland

India

Ireland

Italy, Netherlands, Norway, Thai-

land, Switzerland, Israel

Japan, Korea

Luxembourg

Malaysia

0x12

0x07

0x00

0x12

0x07

0x1C

0x12

0x25

0x4B

0x03

0x00

0x4B

0x5D

0x03

0x38

0x5D

0x25

0x4B

0x04

0x08

0x01

0x00

0x08

0x10

0x0A

0x01

0x06

0x0A

0x04

0x08

0x32

0x30

0x23

0x00

0x19

0x32

0x4B

0x14

0x19

0x32

0x30

0x41

0x00

0x19

0x32

0x4B

0x14

0x19

0x32

0x05

0x07

0x00

0x03

0x05

0x08

0x02

0x03

0x05

Malta

Mexico

Poland

Portugal

Singapore

Spain

Sweden

Taiwan

U.S., Canada (default)

30

Rev. 1.0

Si2401

6. Low Level DSP Control

Table 17. DTMF Values

Contact

Although not necessary for most applications, the DSP

low-level control functions are available for users with

very specific applications requiring direct DSP control.

Tones

Low High

DTMF

Code

Keyboard

ID

Equivalent

Digit

6.1. DSP Registers

0

1

0

1

2

3

4

5

6

7

8

9

D

*

0

941

697

770

852

941

697

770

852

1336

1209

1336

1477

1209

1336

1477

1209

1336

1477

1633

1209

1477

1633

Several DSP registers are accessible through the

Si2401 microcontroller via S-registers SE5, SE6, and

SE8. SE5 and SE6 are used as conduits to write data to

specific DSP registers and read status. SE8 defines the

function of SE5 and SE6 depending on whether they

are being written to or read from. Care must be

exercised when writing to DSP registers. DSP registers

can only be written while the Si2401 is on-hook and in

the command mode. Writing to any register address not

listed in Tables 18 and 19 or writing out-of-range values

is likely to cause the DSP to exhibit unpredictable

behavior.

1

2

3

4

5

6

The DSP register address is 16-bits wide, and the DSP

data field is 14-bits wide. DSP register addresses and

data are written in hexadecimal. To write a value to a

DSP register, the register address is written, and then

the data is written. When SE8 = 0x00, SE5(DADL) is

written with the low bits [7:0] of the DSP register

address, and SE6 (DADH) is written with the high bits

[15:8] of the DSP address. When SE8 = 0x01,

SE5 (DDL) is written with the low bits [7:0] of the DSP

data word corresponding to the previously written

address, and SE6 (DDH) is written with the high bits

[15:8] of the data word corresponding to the previously

written address. Example 1 illustrates the proper

procedure for writing to DSP registers.

7

8

9

10

11

12

13

14

15

–

B

C

D

E

F

#

A

B

C

Example1: The user would like to program call

progress filter coefficient A2_k0 (0x15) to be 309

(0x135).

Host Command:

ATSE8=00SE6=00SE5=15SE8=01SE6=01SE5=35SE8=00

In this command, ATSE8=00 sets up registers SE5 and

SE6 as DSP address registers. SE6=00 sets the high

bits of the address, and SE5=15 sets the low bits.

SE8=01 sets up registers SE5 and SE6 as DSP data

registers for the previously-written DSP address (0x15).

SE6=01 sets the six high bits of the 14-bit data word,

and SE5=35 sets the eight low bits of the 14-bit data

word.

Rev. 1.0

31

Si2401

Table 18. Low-Level DSP Parameters

Description

Name

Function

Default

(dec)

DSP Reg. Addr.

0x0002

XMTL DAA modem full-scale transmit level,

default = –10 dBm.

Level = 20log (XTML/4096)

–10 dBm

4096

4868

3277

10

0x0003

0x0004

DTML DTMF high-tone transmit level,

default = –5.5 dBm.

Level = 20log (DTML/4868)

10

–5.5 dBm

DTMT DTMF twist ratio (low/high),

default = –2 dBm.

Level = 20log (DTMT/3277) –

10

2 dB

0x0005

0x0006

0x0007

0x0008

0x0009

0x000A

0x000B

UFRQ User-defined transmit tone frequency. See f = (9600/512) UFRQ (Hz)

register SE5 (SE8=0x02 (Write Only)).

91

CPDL Call progress detect level (see Figure 5), Level = 20log (4096/CPDL)

4096

4987

536

10

default = –43 dBm.

–43 dBm

UDFD1 User-defined frequency detector 1. Center UDFD1 = 8192 cos (2π f/9600)

frequency for detector 1.

UDFD2 User-defined frequency detector 2. Center UDFD2 = 8192 cos (2π f/9600)

frequency for detector 2.

UDFD3 User-defined frequency detector 3. Center UDFD3 = 8192 cos (2π f/9600)

4987

536

frequency for detector 3.

UDFD4 User-defined frequency detector 4. Center UDFD4 = 8192 cos (2π f/9600)

frequency for detector 4.

TGNL Tone generation level associated with

Level = 20log (TGNL/2896)

2896

10

TONC (SE5 (SE8 = 0x02) Write Only Defi- – 10 dBm

nition), default = –10 dBm.

0x000E

0x0024

0x0025

0x0026

0x0027

UDFSL Sensitivity setting for UDFD1–4 detectors, Sensitivity = 10log (UDFSL/

4096

2620

3300

67

10

default = –43 dBm.

4096) –43 dBm

CONL Carrier ON level. Carrier is valid once it

reaches this level.

Level = 20log (2620/CONL) –

43 dBm

10

COFL Carrier OFF level. Carrier is invalid once it Level = 20log (3300/COFL) –

10

falls below this level.

45.5 dBm

AONL Answer ON level. Answer tone is valid

once it reaches this level.

Level = 10log (AONL/107) –

43 dBm

10

AOFL Answer OFF level. Answer tone is invalid Level = 10log (AOFL/58) –

37

10

once it falls below this level.

45.5 dBm

32

Rev. 1.0

Si2401

Table 19 defines the relationship between SE5, SE6, and SE8.

Table 19. SE5, SE6, and SE8 Relationship

SE8

SE6

Description

SE5

Description

R/W

W

Name

DADH

DDH

Name

DADL

DDL

0x00

0x01

0x02

DSP register address bits [7:0]

DSP register data bits [7:0]

DSP register address bits [15:8]

DSP register data bits [15:8]

W

R

DSP1

7 = DSP data available

6 = Tone detected

5 = Reserved

4:0 = Tone type

0x02

W

DSP3

DSP2

7 = Reserved

6:3 = DTMF tone to transmit

2:0 = Tone type

7 = Enable squaring function

6 = Call progress cascade disable

5 = Reserved

4 = User tone 3 and 4 reporting

3 = User tone 1 and 2 reporting

2 = V.23 tone reporting

1 = Answer tone reporting

0 = DTMF tone reporting

6.2. Call Progress Filters

The programmable call progress filter coefficients are located in DSP address locations 0x0010 through 0x0023.

There are two independent 4th order filters, A and B, each consisting of two biquads, for a total of 20 coefficients.

Coefficients are 14 bits (–8192 to 8191) and are interpreted as, for example, b0 = value/4096, thus giving a floating

point value of approximately –2.0 to 2.0. Output of each biquad is calculated as follows:

w[n] = k0 × x[n] + a1 × w[n – 1] + a2 × w[n – 2]

y[n] = w[n] + b1 × w[n – 1] + b2 × w[n – 2]

The output of the filters is input to an energy detector and then compared to a fixed threshold with hysteresis (DSP

register CPDL). Defaults shown are a bandpass filter from 290–630 Hz (–3 dB). These registers are located in the

DSP and, thus, must be written in the same manner described in “DSP Registers”.

The filters may be configured in either parallel or cascade through SE6[6] (CPCD) with SE8 = 0x02, and the output

of filter B may be squared by selecting SE6[7] (CPSQ) = 1. Figure 5 shows a block diagram of the call progress

filter structure.

Table 20. Call Progress Filters

DSP Register

Coefficient Default (dec)

Address

0x0010

0x0011

0x0012

0x0013

0x0014

0x0015

A1_k0

A1_b1

A1_b2

A1_a1

A1_a2

A2_k0

256

–8184

4096

7737

–3801

1236

Rev. 1.0

33

Si2401

Table 20. Call Progress Filters

0x0016

0x0017

0x0018

0x0019

0x001A

0x001B

0x001C

0x001D

0x001E

0x001F

0x0020

0x0021

0x0022

0x0023

A2_b1

A2_b2

A2_a1

A2_a2

B1_k0

B1_b1

B1_b2

B1_a1

B1_a2

B2_k0

B2_b1

B2_b2

B2_a1

B2_a2

133

4096

7109

–3565

256

–8184

4096

7737

–3801

1236

133

4096

7109

–3565

0

CPCD

1

Filter Input

Energy

Detect

Filter B

0

2

y = x

1

0

B

A

B

Max

(A,B)

Hysteresis

TDET

A > B?

1

0

CPCD

CPSQ

Energy

Detect

Filter A

20log₁₀(4096/CPDL) –43 dBm

Figure 5. Programmable Call Progress Filter Architecture

34

Rev. 1.0

Si2401

7. S Registers

Any register not documented here is reserved and should not be written. Bold selection in bit-mapped registers

indicates default values.

Table 21. S-Register Summary

“S”

Register

Name Function

Reset

Register Address

(hex)

S00

S01

0x00

0x01

NR

Number of rings before answer; 0 suppresses auto answer.

0x00

0x02

DW

Number of seconds modem waits before dialing after going off-

hook (maximum of 109 seconds).

S02

S03

0x02

0x03

CW

CLW

TD

Number of seconds modem waits for a dial tone before hang-up

added to time specified by DW (maximum of 109 seconds).

0x03

0x0E

Duration that the modem waits (53.33 ms units) after loss of car-

rier before hanging up.

S04

S05

S06

S07

S08

S09

S0C

S0D

S0E

0x04

0x05

0x06

0x07

0x08

0x09

0x0C

0x0D

0x0E

Both duration and spacing (5/3 ms units) of DTMF dialed tones.

0x30

0x18

0x24

0x06

0x00

0x46

OFFPD Duration of off-hook time (5/3 ms units) for pulse dialing.

ONPD Duration of on-hook time (5/3 ms units) for pulse dialing.

*

MF1

INTM

INTS

MF2

MF3

DIT

This is a bit-mapped register.

*

Pulse dialing Interdigit time (10 ms units added to a minimum

time of 64 ms).

S0F

S10

S11

S12

0x0F

0x10

0x11

0x12

TEC

TDT

OFHI

ACL

TIES escape character. Default = +.

TIES delay time (53.33 ms units).

0x2B

0x13

0x04

0x00

*

This is a bit-mapped register.

Absolute Current Level. When S13[4] (OFHD) = 0 , ACL

b

represents the absolute current threshold used by the off-hook

intrusion algorithm (1 mA units.)

*

S13

S15

S16

0x13

0x15

0x16

MF4

MLC

This is a bit-mapped register.

0x10

0x04

0x32

*

This is a bit-mapped register.

BTON Busy tone on. Time that the busy tone must be on (10 ms units)

for busy tone detector.

S17

0x17

BTOF Busy tone off. Time that the busy tone must be off (10 ms units)

for busy tone detector.

0x32

*Note: These registers are explained in detail in the following section.

Rev. 1.0

35

Si2401

Table 21. S-Register Summary (Continued)

Name Function

“S”

Register

Reset

Register Address

(hex)

S18

0x18

BTOD Busy tone delta time (10 ms units). A busy tone is detected to be

valid if (BTON – BTOD < on time < BTON + BTOD) and (BTOF –

BTOD < off time < BTOF + BTOD).

0x0F

S19

S1A

S1B

0x19

0x1A

0x1B

RTON Ringback tone on. Time that the ringback tone must be on

(53.333 ms units) for ringback tone detector.

0x26

0x4B

0x07

RTOF Ringback tone off. Time that the ringback tone must be off

(53.333 ms units) for ringback tone detector.

RTOD Detector time delta (53.333 ms units). A ringback tone is deter-

mined to be valid if (RTON – RTOD < on time < RTON + RTOD)

and (RTOF – RTOD < off time < RTOF + RTOD).

S1C

0x1C

DTT

Dial tone detect time. The time that the dial tone must be valid

before being detected

0x0A

(10 ms units).

S1E

S1F

S20

0x1E

0x1F

0x20

TATL

Transmit answer tone length. Answer tone length in seconds

when answering a call (1 s units).

0x03

0x2D

0x5D

ARM3 Answer tone to transmit delay. Delay between answer tone end

and transmit data start (5/3 ms units).

UNL

Unscrambled ones length. Minimum length of time required for

detection of unscrambled binary ones during V.22 handshaking

by a calling modem (5/3 ms units).

S21

0x21

TSOD Transmit scrambled ones delay. Time between unscrambled

binary one detection and scrambled binary one transmission by

a call mode V.22 modem (53.3 ms units).

0x09

S22

S23

0x22

0x23

TSOL Transmit scrambled ones length. Length of time scrambled ones

are sent by a call mode V.22 modem (5/3 ms units).

0xA2

0xCB

VDDL V.22X data delay low. Delay between handshake complete and

data connection for a V.22X call mode modem (5/3 ms units

added to the time specified by VDDH).

S24

0x24

VDDH V.22X data delay high. Delay between handshake complete and

data connection for a V.22X call mode modem (256 x 5/3 ms

units added to the time specified by VDDL).

0x08

S25

S26

0x25

0x26

SPTL S1 pattern time length. Amount of time the unscrambled S1 pat-

tern is sent by a call mode V.22bis modem (5/3 ms units).

0x3C

0x0C

VTSO V.22bis 1200 bps scrambled ones length. Minimum length of

time for transmission of 1200 bps scrambled binary ones by a

call mode V.22bis modem after the end of pattern S1 detection

(53.3 ms).

S27

0x27

VTSOL V.22bis 2400 bps scrambled ones length low. Minimum length of

time for transmission of 2400 bps scrambled binary ones by a

call mode V.22bis modem (5/3 ms units).

0x78

*Note: These registers are explained in detail in the following section.

36

Rev. 1.0

Si2401

Table 21. S-Register Summary (Continued)

Name Function

“S”

Register

Reset

Register Address

(hex)

S28

0x28

VTSOH V.22bis 2400 bps scrambled ones length high. Minimum length

0x08

of time for transmission of 2400 bps scrambled binary ones by a

call mode V.22bis modem (256 x 5/3 ms units added to the time

specified by VTSOL).

S29

S2A

0x29

0x2A

IS

Intrusion suspend. When S82[2:1] (IB) = 10 , this register sets

the length of time from when dialing begins that the off-hook

intrusion algorithm is blocked (suspended) (500 ms units).

0x00

0xD2

b

RSO

Receive scrambled ones V.22bis (2400 bps) length.

Minimum length of time required for detection of scrambled

binary ones during V.22bis handshaking by the answering

modem after S1 pattern conclusion (5/3 ms units).

S2B

S2C

S2D

S2E

S2F

S30

0x2B

0x2C

0x2D

0x2E

0x2F

0x30

DTL

V.23 direct turnaround carrier length. Minimum length of time that

a master mode V.23 modem must detect carrier when searching

for a direct turnaround sequence (5/3 ms units).

0x18

0x08

0x0C

0xF0

0x3C

0x00

DTTO V.23 direct turnaround timeout. Length of time that the modem

searches for a direct turnaround carrier (5/3 ms units added to a

minimum time of 426.66 ms).

SDL

V.23 slave carrier detect loss. Minimum length of time that a

slave mode V.23 modem must lose carrier before searching

for a reverse turnaround sequence (5/3 ms units).

RTCT V.23 reverse turnaround carrier timeout. Amount of time a slave

mode V.23 modem searches for carriers during potential reverse

turnaround sequences (5/3 ms units).

FCD

FSK connection delay low. Amount of time delay added

between end of answer tone handshake and actual modem

connection for FSK modem connections (5/3 ms units).

FCDH FSK connection delay high. Amount of time delay added

between end of answer tone handshake and actual modem con-

nection for FSK modem connections (256 x 5/3 ms units).

S31

S32

S34

S35

0x31

0x32

0x34

0x35

RATL Receive answer tone length. Minimum length of time required

for detection of a CCITT answer tone (5/3 ms units).

0x3C

0x0C

0x5A

0xA2

OCDT The time after going off-hook when the loop current sense bits

are checked for overcurrent status (5/3 ms units).

TASL

Answer tone length when answering a call (5/3 ms units). This

register is only used if TATL (1E) has a value of zero.

RSOL Receive scrambled ones V.22 length (5/3 ms units). Minimum

length of time that an originating V.22 (1200 bps) modem must

detect 1200 bps scrambled ones during a V.22 handshake.

S36

0x36

ARM1 Second kissoff tone detector length. The security modes, A1 and

!1, echo a “k” if a kissoff tone longer than the value stored in

SKDTL is detected (10 ms units).

0x30

*Note: These registers are explained in detail in the following section.

Rev. 1.0

37

Si2401

Table 21. S-Register Summary (Continued)

Name Function

“S”

Register

Reset

Register Address

(hex)

S37

0x37

CDR

Carrier detect return. Minimum length of time that a carrier must

return and be detected in order to be recognized after a carrier

loss is detected

0x20

(5/3 ms units).

S39

S3A

0x39

0x3A

CDT

ATD

Carrier detect timeout. Amount of time modem waits for carrier

detect before aborting call (1 second units).

0x3C

0x29

Delay between going off-hook and answer tone generation when

in answer mode (53.33 ms units).

*

S3C

S62

S82

SDB

0x3C

0x62

0x82

0xDB

CIDG This is a bit-mapped register.

0x01

0x41

0x08

*

RC

IST

LVS

This is a bit-mapped register.

*

Line Voltage Status. Eight bit signed, 2s complement number

representing the tip-ring voltage. Each bit represents 1 volt.

Polarity of the voltage is represented by the MSB (sign bit).

0000_0000 = Measured voltage is < 3 V.

*

SDF

SE0

SE1

SE2

SE3

SE4

SE5

0xDF

0xE0

0xE1

0xE2

0xE3

0xE4

0xE5

DGSR This is a bit-mapped register.

0x0C

0x22

0x0E

0x00

*

CF1

This is a bit-mapped register.

GPIO1 This is a bit-mapped register.

GPIO2 This is a bit-mapped register.

GPD

CF5

This is a bit-mapped register.

0x00

DADL (SE8 = 0x00) Write only definition. DSP register address lower

*

bits [7:0].

SE5

0xE5

DDL

(SE8 = 0x01) Write only definition. DSP data word lower bits

[7:0].

*

1

SE5

SE6

0xE5

0xE6

DSP1 (SE8 = 0x02) Read only definition. This is a bit-mapped register.

DSP2 (SE8 = 0x02) Write only definition. This is a bit-mapped register.

DADH (SE8 = 0x00) Write only definition. DSP register address upper

bits [15:8].

SE6

0xE6

DDH

(SE8 = 0x01) Write only definition. DSP data word upper bits

[13:8]

1

SE6

SE8

SEB

0xE6

0xE8

0xEB

DSP3 (SE8 = 0x02) Write only definition. This is a bit-mapped register.

DSPR4 Set the mode to define E5 and E6 for low-level DSP control.

*

TPD

This is a bit-mapped register.

0x00

*Note: These registers are explained in detail in the following section.

38

Rev. 1.0

Si2401

Table 21. S-Register Summary (Continued)

Name Function

“S”

Register

Reset

Register Address

(hex)

*

SEC

SED

SEE

SF0

SF1

SF2

SF3

0xEC

0xED

0xEE

0xF0

0xF1

0xF2

0xF3

RV1

RV2

RV3

This is a bit-mapped register.

0x88

0x19

0x16

0x40

0x0C

*

DAA0 This is a bit-mapped register.

DAA1 This is a bit-mapped register.

DAA2 This is a bit-mapped register.

DAA3

Line Current Status. Eight-bit value returning the loop current.

Each bit represents 1.1 mA of loop current.

0x00

Accuracy is not guaranteed if the loop current is less than

required for normal operation.

*

SF4

SF5

SF6

SF7

SF8

SF9

0xF4

0xF5

0xF6

0xF7

0xF8

0xF9

DAA4 This is a bit-mapped register.

DAA5 This is a bit-mapped register.

DAA6 This is a bit-mapped register.

DAA7 This is a bit-mapped register.

DAA8 This is a bit-mapped register.

DAA9 This is a bit-mapped register.

0x0F

0x00

0xF0

0x00

—

*

0x20

*Note: These registers are explained in detail in the following section.

Rev. 1.0

39

Si2401

Table 22. Bit-Mapped Register Summary

“S”

Register Register Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

Binary

Register Address Name

(hex)

S07

S08

S09

S0C

S0D

S11

0x07

0x08

0x09

0x0C

0x0D

0x11

0x13

0x15

0x3C

0x62

0x82

0xDF

0xE0

0xE1

0xE2

0xE3

0xE4

0xE5

0xE6

0xEB

0xEC

0xED

0xEE

0xF0

0xF1

0xF2

MF1

INTM

INTS

MF2

BD

V23R

V23T

BAUD CCITT

FSK

0000_0110

CDM WORM PPDM NVDM

RIM

RI

CIDM OCDM REVM 0000_0000

CD

WOR

PPD

NVD

RBTS

OFHD

CID

BDL

EHB

OCD

MLB

EHI

REV 0000_0000

0000_0000

CDE

CIDM[1:0]

9BF

EHR

MF3

RI

INTP

EHE 0000_0000

0000_0100

OFHI

MF4

DCL[3:0]

S13

S15

S3C

S62

S82

SDF

SE0

SE1

SE2

SE3

SE4

SE5

SE6

SEB

SEC

SED

SEE

SF0

SF1

SF2

BTID

CIDB HDEN

BDA[1:0]

0001_0000

MLC

ATPRE VCTE FHGE EHGE

STB

NBE 0000_0100

0000_0001

CIDG

RC

CIDG[2:0]

OCR

IR

NLR

IB[1:0]

RR

0100_0001

0000_1000

0000_1100

0010_0010

IST

IST[3:0]

LCLD

DGSR[6:0]

ND

DGSR

CF1

ICTS

SD[2:0]

GPIO1

GPIO2

GPD

CF5

GPD5 GPIO5 0000_1110

GPIO4[1:0]

GPIO3[1:0]

GPIO2[1:0]

GPIO1[1:0]

0000_0000

N/A

GPD4 GPD3 GPD2 GPD1

NBCK SBCK

DDAV TDET

DRT

GPE

xx00_0000

N/A

DSP1

DSP2

DSP3

TPD

TONE[4:0]

TONC[2:0]

DTM[3:0]

N/A

CPSQ CPCD

RNGV

USEN2 USEN1 V23E ANSE DTMFE 0000_0000

PDDE

0000_0000

1000_1000

0001_1001

0001_0110

0100_0000

0000_1100

xxxx_1xxx

RVC1

RVC2

RVC3

DAA0

DAA1

DAA2

RDLY[2:0]

RCC[2:0]

RAS[5:0]

RMX[3:0]

RTO[3:0]

FOH[1:0]

BTE PDN

LM[1:0]

PDL

LVFD

HBE

FDT

40

Rev. 1.0

Si2401

Table 22. Bit-Mapped Register Summary (Continued)

“S”

Register Register Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

Binary

Register Address Name

(hex)

SF4

SF5

SF6

SF8

SF9

SFC

0xF4

0xF5

0xF6

0xF8

0xF9

0xFC

DAA4

DAA5

DAA6

DAA8

DAA9

ARL[1:0]

ATL[1:0]

RT

0000_1111

0000_0000

1111_0000

N/A

OHS[1:0]

ILIM

RZ

MINI[1:0]

DCV[1:0]

ACT[3:0]

LRV[3:0]

DCR

ROV

BTD

OVL

0010_0000

N/A

DAAFC CTSM

Rev. 1.0

41

Si2401

S07 (MF1). Modem Functions 1

Bit

D7

D6

BD

D5

D4

D3

D2

D1

D0

Name

Type

V23R

R/W

V23T

R/W

BAUD

R/W

CCITT

R/W

FSK

R/W

Reset settings = 0000_0110 (0x06)

Bit

7

Name

Reserved

BD

Function

Read returns zero.

6

Blind Dialing.

0 = Disable.

1 = Enable (Blind dialing occurs immediately after “ATDT#” command).

5

4

V23R

V23T

V.23 Receive.*

V.23 75 bps send/600 (BAUD = 0) or 1200 (BAUD = 1) bps receive.

0 = Disable.

1 = Enable.

V.23 Transmit.*

V.23 600 (BAUD = 0) or 1200 (BAUD = 1) bps send/75 bps receive.

0 = Disable.

1 = Enable.

3

2

Reserved

BAUD

Read returns zero.

2400/1200 Baud Select.*

2400/1200 baud select (V23R = 0 and V23T = 0).

0 = 1200

1 = 2400

600/1200 baud select (V23R = 1 and V23T = 1).

0 = 600

1 = 1200

1

0

CCITT

FSK

CCITT/Bell Mode.*

0 = Bell.

1 = CCITT.

300 bps FSK.*

0 = Disable.

1 = Enable.

*Note: See Table 9 on page 13 for proper setting of modem protocols.

42

Rev. 1.0

Si2401

S08 (INTM). Interrupt Mask

Bit

D7

D6

WORM

R/W

D5

D4

D3

D2

D1

D0

Name

Type

CDM

R/W

PPDM

R/W

NVDM

R/W

RIM

R/W

CIDM

R/W

OCDM

R/W

REVM

R/W

Reset settings = 0000_0000 (0x00)

Bit

Name

Function

7

CDM

Carrier Detect Mask.

0 = Change in CD does not affect INT.

1 = A high to low transition in CD (S09, bit 7), which indicates loss of carrier, activates

INT.

6

5

4

3

2

1

0

WORM

PPDM

NVDM

RIM

Wake-on-Ring Mask.

0 = Change in CD does not affect INT.

1 = A low to high transition in WOR (S09, bit 6) activatesINT.

Parallel Phone Detect Mask.

0 = Change in PPD does not affect INT.

1 = A low to high transition in PPD (S09, bit 5) activates INT.

No Phone Line Detect Mask.

0 = Change in NLD does not affect INT.

1 = A low to high transition in NLD (S09, bit 4) activates INT.

Ring Indicator Mask.

0 = Change in RI does not affect INT.

1 = A low to high transition in RI (S09, bit 3) activates INT.

CIDM

OCDM

REVM

Caller ID Mask.

0 = Change in CID does not affect INT.

1 = A low to high transition in CID (S09, bit 2) activates INT.

Overcurrent Detect Mask.

0 = Change in OCD does not affect INT.

1 = A low to high transition in OCD (S09, bit 1) activates INT.

V.23 Reversal Detect Mask.

0 = Change in REV does not affect INT.

1 = A low to high transition in REV (S09, bit 0) activates INT.

Rev. 1.0

43

Si2401

S09 (INTS). Interrupt Status

Bit

D7

CD

D6

D5

D4

D3

RI

D2

CID

R/W

D1

D0

Name

Type

WOR

R/W

PPD

R/W

NVD

R/W

OCD

R/W

REV

R/W

Reset settings = 0000_0000 (0x00)

Bit

Name

Function

7

CD

Carrier Detect (sticky).

Active high bit indicates carrier detected (equivalent to inverse of CD pin). Clears on :1

read.

6

5

4

3

WOR

PPD

NVD

RI

Wake-on-Ring (sticky).

Wake-on-ring has occurred. Clears on :I read.

Parallel Phone Detect (sticky).

Parallel phone detected since last off-hook event. Clears on :I read.

No Phone Line Detect (sticky).

No line phone detected. Clears on :I read.

Ring Indicator (sticky).

Active high bit when the Si2403 is on-hook, indicates ring event has occurred. Clears on

:I read.

2

1

0

CID

OCD

REV

Caller ID (sticky).

Caller ID preamble has been detected; data soon follows. Clears on :I read.

Overcurrent Detect (sticky).

Overcurrent condition has occurred. Clears on :I read.

V.23 Reversal Detect (sticky).

V.23 reversal condition has occurred. Clears on :I read.

44

Rev. 1.0

Si2401

S0C (MF2). Modem Functions 2

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

CDE

R/W

CIDM[1:0]

9BF

R/W

BDL

R/W

MLB

R/W

Reset settings = 0000_0000 (0x00)

Bit

Name

Function

CDE

7

Carrier Detect Enable.

0 = Disable.

1 = Enable GPI02 as an active low carrier detect pin (must also set SE2[3:2]

[GPIO2] = 01).

6:5

CIDM[1:0]

Caller ID Monitor.

00 = Caller ID monitor disabled.

01 = Caller ID monitor enabled. Si2401 must detect channel seizure signal followed by

marks in order to report caller ID data. (Normal Bellcore caller ID)

10 = Reserved.

11 = Caller ID monitor enabled. Si2401 must only detect marks in order to report caller ID

data.

4

3

Reserved

9BF

Read returns zero.

Ninth Bit Function.

Only valid if the ninth bit escape is set S15[0] (NBE).

0 = Ninth bit equivalent to ALERT.

1 = Ninth bit equivalent to HDLC EOFR.

2

1

0

BDL

MLB

Blind Dialing.

0 = Blind dialing disabled.

1 = Enables blind dialing after dial timeout register S02 (CW) expires.

Modem Loopback.

0 = Not swapped.

1 = Swaps frequency bands in modem algorithm to do a loopback in a test mode.

Reserved

Read returns zero.

Rev. 1.0

45

Si2401

S0D (MF3). Modem Functions 3

Bit

Name

Type

D7

D6

RI

D5

D4

D3

D2

D1

EHI

R/W

D0

INTP

R/W

RBTS

R/W

EHR

R/W

EHB

R/W

EHE

R/W

Reset settings = 0000_0000 (0x00)

Bit

Name

Reserved Read returns zero.

Function

7

6

RI

Ring Indicator.

Specifies the functionality of pin3.

0 = Pin 3 functions as GPIO5 controlled by register SE1.

1 = Pin 3 functions as RI. RI asserts during a ring and negates when no

ring is present.

5

4

3

2

1

0

INTP

RBTS

EHR

EHB

EHI

INT Polarity.

Specifies the polarity of the INT function on pin 11.

0 = An interrupt forces pin 11 low.

1 = An interrupt forces pin 11 high.

Ringback Tone Selector

Controls the unit step size for registers S19, S1A and S1B.

0 = 53.33 ms units. Necessary for detecting a ringback tone.

1 = 10 ms units. Necessary for detecting a reorder tone.

Enable Hangup on Reorder.

Modem is placed on-hook if a ringback or reorder tone is detected. See S0D[4].

0 = Disable.

1 = Enable.

Enable Hangup on Busy.

Modem is placed on-hook if a busy signal is detected.

0 = Disable.

1 = Enable.

Enable Hangup on Intrusion.

Modem is placed on-hook if parallel intrusion is detected.

0 = Disable.

1 = Enable.

EHE

Enable Hangup on Escape.

Modem is placed on-hook if a ESC signal is detected.

0 = Disable.

1 = Enable.

46

Rev. 1.0

Si2401

S11 (OFHI). Off-Hook Intrusion

Bit

D7

D6

D5

D4

D3

D2

D1

DCL[3:0]

R/W

D0

Name

Type

Reset settings = 0000_0100 (0x04)

Bit

7:4

3:0

Name

Function

Reserved

DCL[3:0]

Read returns zero.

Differential Current Level.

Differential current level to detect intrusion event (1 mA units).

S13 (MF4). Modem Functions 4

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

BTID

R/W

OFHD

R/W

CIDB

R/W

HDEN

R/W

Reset settings = 0001_0000 (0x10)

Bit

7

Name

Reserved

BTID

Function

Read returns zero.

6

BT Caller ID Wetting Pulse.

0 = Enable.

1 = Disable.

5

4

Reserved

OFHD

Read returns zero.

Off-Hook Intrusion Detect Method.

0 = Absolute.

1 = Differential.

3

2

Reserved

CIDB

Read returns zero.

British Telecom Caller ID Decode.

0 = Disable.

1 = Enable.

When set, SOC[6:5] is overwritten by the modem, as needed.

1

0

HDEN

HDLC Framing.

0 = Disable.

1 = Enable.

Reserved

Read returns zero.

Rev. 1.0

47

Si2401

S15 (MLC). Modem Link Control

Bit

D7

ATPRE

R/W

D6

D5

D4

D3

D2

BDA[1:0]

R/W

D1

D0

Name

Type

VCTE

R/W

FHGE

R/W

EHGE

R/W

STB

R/W

NBE

R/W

Reset settings = 0000_0100 (0x04)

Bit

Name

Function

7

ATPRE

Answer Tone Phase Reversal.

0 = Disable.

1 = Enable answer tone phase reversal.

6

5

VCTE

FHGE

EHGE

STB

V.25 Calling Tone.

0 = Disable.

1 = Enable V.25 calling tone.

550 Hz Guardtone.

0 = Disable.

1 = Enable 550 Hz guardtone.

4

1800 Hz Guardtone.

0 = Disable.

1 = Enable 1800 Hz guardtone.

3

Stop Bits.

0 = 1 stop bit.

1 = 2 stop bits.

2:1

BDA[1:0]

Bit Data.

00 = 6 bit data.

01 = 7 bit data.

10 = 8 bit data.

11 = 9 bit data.

0

NBE

Ninth Bit Enable.

0 = Disable.

1 = Enable ninth bit as Escape and ninth bit function (register C).

48

Rev. 1.0

Si2401

S3C (CIDG). Caller ID Gain

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

CIDG[2:0]

R/W

Reset settings = 0000_0001 (0x01)

Bit

7:3

2:0

Name

Function

Reserved

CIDG[2:0]

Read returns 0.

Caller ID Gain.

The Si2400 dynamically sets the On-Hook Analog Receive Gain SF4[6:4] (ARG) to

CIDG during a caller ID event (or continuously if S0C[6:5] (CIDM = 11 ). This field should

b

be set prior to caller ID operation.

000 = 0 dB

001 = 3 dB

010 = 6 dB

011 = 9 dB

100 = 12 dB

Rev. 1.0

49

Si2401

S62 (RC). Result Codes Override

Bit

D7

D6

D5

D4

D3

D2

IR

D1

D0

RR

Name

Type

OCR

R/W

NLR

R/W

Reset settings = 0100_0001 (0x41)

Bit

7

Name

Reserved

OCR

Function

Read returns zero.

6

Overcurrent Result Code (“x”).

0 = Enable.

1 = Disable.

5:3

2

Reserved

IR

Read returns zero.

Intrusion Result Code (“I” and “i”).

0 = Disable.

1 = Enable.

1

0

NLR

RR

No Phone Line Result Code (“L” and “l”).

0 = Disable.

1 = Enable.

Ring Result Code (“R”).

0 = Disable.

1 = Enable.

50

Rev. 1.0

Si2401

S82 (IST). Intrusion

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

IST[3:0]

R/W

LCLD

R/W

IB[1:0]

R/W

Reset settings = 0000_1000 (0x08)

Bit

Name

Function

7:4

IST[3:0]

Intrusion Settling Time.

0000 = IST equals 1 second.

Delay between when the ISOmodem chipset goes off-hook and the off-hook intrusion

algorithm begins (250 ms units).

®

3

LCLD

Loop Current Loss Detect.

0 = Disable.

1 = Enables the reporting of “I” and “L” result codes while off-hook. Asserts INT if

GPIO4 (SE2[7:6]) is enabled as INT.

2:1

IB[1:0]

Intrusion Blocking.

This feature only works when SDF ≠ 0x00. Defines the method used to block the off-hook

intrusion algorithm from operating after dialing has begun.

00 = No intrusion blocking.

01 = Intrusion disabled from start of dial to end of dial.

10 = Intrusion disabled from start of dial to register S29 time out.

11 = Intrusion disabled from start of dial to carrier detect or to “N” or “n” result code.

0

Reserved

Read returns zero.

Rev. 1.0

51

Si2401

SDF (DGSR). Intrusion Deglitch

Bit

D7

D6

D5

D4

D3

DGSR[6:0]

R/W

D2

D1

D0

Name

Type

Reset settings = 0000_1100 (0x0C)

Bit

7

Name

Function

Reserved

DGSR[6:0]

Read returns zero.

Deglitch Sample Rate.

6:0

Sets the sample rate for the deglitch algorithm and the off-hook intrusion algorithm

(40 ms units).

0000000 = Disables the deglitch algorithm, and sets the off-hook intrusion sample rate to

200 ms and delay between compared samples to 800 ms.

SE0 (CF1). Chip Functions 1

Bit

D7

D6

D5

D4

D3

ND

D2

D1

D0

Name

Type

ICTS

R/W

SD[2:0]

R/W

Reset settings = 0010_0010 (0x22)

Bit

7:6

5

Name

Reserved

ITCS

Function

Read returns zero.

Invert CTS pin.

0 = Inverted (CTS).

1 = Normal (CTS).

4

3

Reserved

ND

Read returns zero.

0 = 8N1.

1 = 9N1 (hardware UART only).

2:0

SD[2:0]

Serial Dividers.

000 = 300 bps serial link.

001 = 1200 bps serial link.

010 = 2400 bps serial link.

011 = 9600 bps serial link.

100 = 19200 bps serial link.

101 = 38400 bps serial link

110 = 115200 bps serial link.

111 = 307200 bps serial link.

52

Rev. 1.0

Si2401

SE1 (GPIO1). General Purpose Input/Output 1

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

GPD5

R/W

GPIO5

R/W

Reset settings = 0000_1110 (0x0E)

Bit

7:2

1

Name

Reserved

GPD5

Function

Read returns zero.

GPIO5 Data.

Data = 0.

Data = 1.

0

GPIO5

GPIO5.

0 = Digital input.

1 = Digital output (relay drive).

SE2 (GPIO2). General Purpose Input/Output 2

Bit

D7

GPIO4[1:0]

R/W

D6

D5

GPIO3[1:0]

R/W

D4

D3

D2

D1

D0

Name

Type

GPIO2[1:0]

R/W

GPIO1[1:0]

R/W

Reset settings = 0000_0000 (0x00)

Bit Name

7:6 GPIO4[1:0] GPIO4.

00 = Digital input.

Function

01 = Digital output (relay drive).

10 = AOUT.

11 = INT function defined by S08.

5:4 GPIO3[1:0] GPIO3.

00 = Digital input.

01 = Digital output (relay drive).

10 = Reserved.

11 = ESC function (digital input).

3:2 GPIO2[1:0] GPIO2.

00 = Digital input.

01 = Digital output (relay drive; also used for CD function).

10 = Reserved.

11 = Digital input.

1:0 GPIO1[1:0] GPIO1*.

00 = Digital input.

01 = Digital output (relay drive).

10 = Reserved.

11 = Reserved.

*Note: To be used as a GPIO pin; SE4[3] (GPE) must equal zero.

Rev. 1.0

53

Si2401

SE3 (GPD). GPIO Data

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

GPD4

R/W

GPD3

R/W

GPD2

R/W

GPD1

R/W

Reset settings N/A

Bit

7:4

3

Name

Reserved

GPD4

Function

Read returns zero.

GPIO4 Data.

Data = 0

Data = 1

2

GPD3

GPIO3 Data.

Data = 0

Data = 1

1

0

GPD2

GPD1

GPIO2 Data.

Data = 0

Data = 1

GPIO1 Data.

Data = 0

Data = 1

SE4 (CF5). Chip Functions 5

Bit

D7

NBCK

R

D6

SBCK

R

D5

D4

D3

D2

D1

D0

Name

Type

DRT

R/W

GPE

R/W

Reset settings = xx00_0000 (0x00)

Bit

7

Name

NBCK

SBCK

DRT

Function

9600 Baud Clock (Read Only).

600 Baud Clock (Read Only).

Data Routing.

6

5

0 = Data mode, DSP output transmitted to line, line received by DSP input.

1 = Loopback mode, TXD through microcontroller (DSP) to RXD.

4

3

Reserved

GPE

Read returns zero.

GPIO1 Enable.

0 = Disable.

1 = Enable GPIO1 to be HDLC end-of-frame flag.

Read returns zero.

2:0

Reserved

54

Rev. 1.0

Si2401

SE5 (DSP1). (SE8 = 0x02) Read Only Definition

Bit

D7

DDAV

R

D6

TDET

R

D5

D4

D3

D2

TONE[4:0]

R

D1

D0

Name

Type

Reset settings N/A

Bit

7

Name

DDAV

TDET

Function

DSP Data Available.

Tone Detected.

6

Indicates a TONE (any of type 0–25 below) has been detected.

0 = Not detected.

1 = Detected.

5

Reserved

TONE[4:0]

Read returns zero.

4:0

Tone Type Detected.

When TDET goes high, TONE indicates which tone has been detected from the following:

TONE

Tone Type

Priority

1

00000–01111 DTMF 0–15 (DTMFE = 1) See Table 17 on page 31.

1

2

3

4

6

5

6

2

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

Answer tone detected 2100 Hz (ANSE = 1)

Bell 103 answer tone detected 2225 Hz (ANSE = 1)

V.23 forward channel mark 1300 Hz (V23E = 1)

V.23 backward channel mark 390 Hz (V23E = 1)

User defined frequency 1 (USEN1 = 1)

User defined frequency 2 (USEN1 = 1)

Call progress filter A detected

User defined frequency 3 (USEN2 = 1)

User defined frequency 4 (USEN2 = 1)

Call progress filter B detected

3

4

5

Notes:

1. SE6[0] (DTMFE) SE8 = 0x02.

2. SE6[1] (ANSE) SE8 = 0x02.

3. SE6[2] (V23E) SE8 = 0x02.

4. SE6[3] (USEN1) SE8 = 0x02.

5. SE6[4] (USEN2) SE8 = 0x02.

Rev. 1.0

55

Si2401

SE5 (DSP2). (SE8 = 0x02) Write Only Definition

Bit

D7

D6

D5

D4

D3

D2

D1

TONC[2:0]

W

D0

Name

Type

DTM[3:0]

W

Reset settings N/A

Bit

Name

Function

7

Reserved

DTM[3:0]

Always write zero.

Tone Type Generated.

6:3

DTMF tone (0–15) to transmit when selected by TONC = 001. See Table 17 on page 31.

2:0

TONC[2:0]

DTMF Tone Selector.

ToneTone Type

000

001

010

011

100

101

110

Mute

DTMF

2225 Hz Bell mode answer tone with phase reversal

2100 Hz CCITT mode answer tone with phase reversal

2225 Hz Bell mode answer tone without phase reversal

2100 Hz CCITT mode answer tone without phase reversal

User-defined programmable frequency tone (UFRQ)

(see Table 18 on page 32, default = 1700 Hz)

1300 Hz V.25 calling tone

111

56

Rev. 1.0

Si2401

SE6 (DSP3). (SE8 = 0x02) Write Only Definition

Bit

D7

CPSQ

W

D6

CPCD

W

D5

D4

USEN2

W

D3

USEN1

W

D2

V23E

W

D1

ANSE

W

D0

DTMFE

W

Name

Type

Reset settings = 0000_0000 (0x00)

Bit

Name

Function

7

CPSQ

Call Progress Squaring Filter.

0 = Disable.

1 = Enables a squaring function on the output of filter B before the input to A (cascade

only).

6

CPCD

Call Progress Cascade Disable.

0 = Call progress filter B output is input into call progress filter A. Output from fil-

ter A is used in the detector.

1 = Cascade disabled. Two independent fourth order filters available (A and B). The

largest output of the two is used in the detector.

5

4

Reserved

USEN2

User Tone Reporting Enable 2.

0 = Disable.

1 = Enable the reporting of user defined frequency tones 3 and 4 through TONE.

3

2

1

0

USEN1

V23E

User Tone Reporting Enable 1.

0 = Disable.

1 = Enable the reporting of user defined frequency tones 1 and 2.

V.23 Tone Reporting Enable.

0 = Disable.

1 = Enable the reporting of V.23 tones, 390 Hz and 1300 Hz.

ANSE

Answering Tone Reporting Enable.

0 = Disable.

1 = Enable the reporting of answer tones.

DTMFE

DTMF Tone Reporting Enable.

0 = Disable.

1 = Enable the reporting of DTMF tones.

Rev. 1.0

57

Si2401

SEB (TPD). Timer and Powerdown

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

PDDE

R/W

Reset settings = 0000_0000 (0x00)

Bit

7:4

3

Name

Reserved

PDDE

Function

Read returns zero.

Powerdown DSP Engine.

0 = Power on.

1 = Powerdown.

2:0

Reserved

Read returns zero.

58

Rev. 1.0

Si2401

SEC (RVC1). Ring Validation Control 1

Bit

D7

D6

D5

RDLY[2:0]

R/W

D4

D3

D2

RCC[2:0]

R/W

D1

D0

Name

Type

RNGV

R/W

Reset settings = 1000_1000 (0x88)

Bit

Name

Function

7

RNGV

Ring Validation Enable.

0 = Ring validation feature is disabled.

1 = Ring validation feature is enabled in both normal operating mode and low-

power mode.

6:4

RDLY[2:0]

Ring Delay.

These bits set the amount of time between when a ring signal is validated and when a

valid ring signal is indicated.

RDLY[2:0]

Delay

0 ms

256 ms

512 ms

000

001

010

.

111

1792 ms

3:1

RCC[2:0]

Ring Confirmation Count.

These bits set the amount of time that the ring frequency must be within the tolerances

set by the RAS[5:0] bits and the RMX[3:0] bits to be classified as a valid ring signal.

RCC[2:0]

000

001

010

011

100

101

110

111

Ring Confirmation Count Time

100 ms

150 ms

200 ms

256 ms

384 ms

512 ms

640 ms

1024 ms

0

Reserved

This bit must always be written to zero.

Rev. 1.0

59

Si2401

SED (RVC2). Ring Validation Control 2

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

RAS[5:0]

R/W

Reset settings = 0001_1001 (0x19)

Bit

7:6

5:0

Name

Function

Reserved

RAS[5:0]

Read returns zero.

Ring Assertion Time.

These bits set the minimum ring frequency for a valid ring signal. During ring qualification,

a timer is loaded with the RAS[5:0] field upon a TIP/RING event and decrements at a reg-

ular rate. If a second or subsequent TIP/RING event occurs after the timer has timed out,

the frequency of the ring is too low, and the ring is invalidated. The difference between

RAS[5:0] and RMX[5:0] identifies the minimum duration between TIP/RING events to qual-

ify as a ring, in binary-coded increments of 2.0 ms (nominal). A TIP/RING event typically

occurs twice per ring tone period. At 20 Hz, TIP/RING events would occur every

1/(2 x 20 Hz) = 25 ms. To calculate the correct RAS[5:0] value for a frequency range

[f_min, f_max], the following equation should be used: RAS[5:0] = 1 / (2 x f_min).

60

Rev. 1.0

Si2401

SEE (RVC3). Ring Validation Control 3

Bit

D7

D6

RTO[3:0]

R/W

D5

D4

D3

D2

D1

D0

Name

Type

RMX[3:0]

R/W

Reset settings = 0001_0110 (0x16)

Bit

Name

Function

7:4

RTO[3:0]

Ring Timeout.

These bits set when a ring signal is determined to be over after the most recent ring

threshold crossing.

RTO[3:0]

0000

Ring Timeout

80 ms

0001

128 ms

0010

256 ms

.

1111

1920 ms

3:0

RMX[3:0]

Ring Assertion Maximum Count.

These bits set the maximum ring frequency for a valid ring signal. During ring qualification,

a timer is loaded with the RAS[5:0] field upon a TIP/RING event and decrements at a reg-

ular rate. When a subsequent TIP/RING event occurs, the timer value is compared to the

RMX[3:0] field, and if it exceeds the value in RMX[3:0], the frequency of the ring is too

high, and the ring is invalidated. The difference between RAS[5:0] and RMX[3:0] identifies

the minimum duration between TIP/RING events to qualify as a ring, in binary-coded incre-

ments of 2.0 ms (nominal). A TIP/RING event typically occurs twice per ring tone period.

At 20 Hz, TIP/RING events would occur every 1/(2 x 20 Hz) = 25 ms. To calculate the cor-

rect RMX[3:0] value for a frequency range [f_min, f_max], the following equation should be

used: RMX[3:0] x 2 ms = RAS[5:0] – 2 ms – (1/(2 x f_max)).

Rev. 1.0

61

Si2401

SF0 (DAA0). DAA Low Level Functions 0

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

FOH[1:0]

R/W

LM[1:0]

R/W

Reset settings = 0100_0000 (0x40)

Bit

Name

FOH[1:0] Fast Off-Hook Selection.

Function

7:6

These bits determine the length of the off-hook counter. The default setting is 128 ms.

00 = 512 ms

01 = 128 ms

10 = 64 ms

11 = 8 ms

5:2 Reserved Read returns zero.

1:0

LM[1:0]

Line Mode.

These bits determine the line status of the Si2401.*

00 = On-hook

01 = Off-hook

10 = On-hook line monitor mode

11 = Reserved

*Note: Under normal operation, the Si2401 internal microcontroller automatically sets these bits appropriately.

62

Rev. 1.0

Si2401

SF1 (DAA1). DAA Low Level Functions 1

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

BTE

R/W

PDN

R/W

PDL

R/W

LVFD

R/W

HBE

R/W

Reset settings = 0000_1100 (0x0C)

Bit

Name

Function

7

BTE

Billing Tone Enable.

When the line-side device detects a billing tone, SF9[3] (BTD) is set.

0 = Disable.

1 = Enable.

6

5

4

PDN

PDL

Powerdown.

0 = Normal operation.

1 = Powers down the Si2401.

Powerdown Line-Side Chip (typically only used for board level debug.)

0 = Normal operation. Program the clock generator before clearing this bit.

1 = Places the line-side device in lower power mode.

LVFD

Line Voltage Force Disable.

0 = Normal operation.

1 = The circuitry that forces the LVS register to all 0s at 3 V or less is disabled. This reg-

ister may display unpredictable values at voltages between 0 to 2 V. All 0s are displayed

if the line voltage is 0 V.

3

2

Reserved

HBE

Do not modify.

Hybrid Transmit Path Connect.

0 = Disable.

1 = Enable.

1:0

Reserved

Do not modify.

Rev. 1.0

63

Si2401

SF2 (DAA2). DAA Low Level Functions 2

Bit

D7

D6

D5

D4

D3

FDT

R

D2

D1

D0

Name

Type

Reset settings = xxxx_1xxx

Bit

7:4

3

Name

Reserved

FDT

Function

Read only.

Frame Detect (Typically only used for board-level debug).

1 = Indicates isolation capacitor frame lock has been established.

0 = Indicates isolation capacitor frame lock has not been established.

2:0

Reserved

SF4 (DAA4). DAA Low Level Functions 4

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

ARL[1:0]

R/W

ATL[1:0]

R/W

Reset settings = 0000_1111 (0x0F)

Bit

7:4

3:2

Name

Function

Reserved

ARL[1:0]

Read returns zero.

AOUT Receive—Path Level.

DAA receive path signal AOUT gain.

00 = 0 dB

01 = –6 dB

10 = –12 dB

11 = Mute

1:0

ATL[1:0]

AOUT Transmit—Path Level.

DAA transmit path signal AOUT gain.

00 = –18 dB

01 = –24 dB

10 = –30 dB

11 = Mute

64

Rev. 1.0

Si2401

SF5 (DAA5). DAA Low Level Functions 5

Bit

D7

D6

D5

D4

D3

D2

RZ

D1

D0

RT

Name

Type

OHS[1:0]

R/W

ILIM

R/W

Reset settings = 0000_0000 (0x00)

Bit

Name

Function

7:6

5:4

Reserved

OHS[1:0]

Read returns zero.

On-Hook Speed.

These bits set the amount of time for the line-side device to go on-hook. The on-hook

speeds specified are measured from the time the register is written until loop current

equals zero.

OHS[1:0]

Mean On-Hook Speed

00

01

1X

Less than 0.5 ms

3 ms ±10% (Meets ETSI standard)

20 ms ±10% (Meets Australian spark quenching spec)

3

2

ILIM

RZ

Current Limiting Enable.

0 = Current limiting mode disabled.

1 = Current limiting mode enabled. This mode limits loop current to a maximum of 60 mA

per the TBR21 standard.

Ringer Impedance.

0 = Maximum (high) ringer impedance.

1 = Synthesized ringer impedance used to satisfy a maximum ringer impedance specifi-

cation in countries, such as Poland, South Africa, and Slovenia.

1

0

Reserved

RT

Do not modify.

Ringer Threshold Select.

Used to satisfy country requirements on ring detection. Signals below the lower level do

not generate a ring detection; Signals above the upper level are guaranteed to generated

a ring detection.

0 = 13.5 to 16.5 V

RMS

1 = 19.35 to 23.65 V

RMS

Rev. 1.0

65

Si2401

SF6 (DAA6). DAA Low Level Functions 6

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

MINI[1:0]

R/W

DCV[1:0]

R/W

ACT[3:0]

R/W

Reset settings = 1111_0000 (0xF0)

Bit

Name

Function

7:6

MINI[1:0]

Minimum Operational Loop Current.

Adjusts the minimum loop current at which the DAA can operate. Increasing the mini-

mum operational loop current can improve signal headroom at a lower TIP/RING volt-

age.

MINI[1:0] Min Loop Current

00

01

10

11

10 mA

12 mA

14 mA

16 mA

5:4

DCV[1:0]

TIP/RING Voltage Adjust.

These bits adjust the voltage on the DCT pin of the line-side device, which affects the

TIP/RING voltage on the line. Low voltage countries should use a lower TIP/RING volt-

age. Raising the TIP/RING voltage can improve signal headroom.

DCV[1:0] DCT Pin Voltage

00

01

10

11

3.1 V

3.2 V

3.35 V

3.5 V

3:0

ACT[3:0]

AC Termination Select.

ACT[3:0] AC Termination

0000

Real 600 Ω termination that satisfies the impedance requirements

of FCC part 68, JATE, and other countries.

0011

Global complex impedance. Complex impedance that satisfies global

impedance requirements EXCEPT New Zealand. May achieve higher

return loss for countries requiring complex ac termination.

[220 Ω + (820 Ω || 120 nF) and 220 Ω + (820 Ω || 115 nF)].

0100

1111

Complex impedance for use in New Zealand.

[370 Ω + (620 Ω || 310 nF)]

Complex impedance that satisfies global impedance requirements.

66

Rev. 1.0

Si2401

SF8 (DAA8). DAA Low Level Functions 8

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

LRV[3:0]

R

DCR

R/W

Reset settings vary with line-side vision

Bit

Name

Function

7:4

LRV[3:0]

Line-Side Device Revision Number.

0011 = Si3010 Rev C

0100 = Si3010 Rev D

0101 = Si3010 Rev E

0110 = Si3010 Rev F

3:2

1

Reserved

DCR

Read returns an indeterministic value.

DC Impedance Selection.

0 = 50 Ω dc termination is selected. This mode should be used for all standard

applications.

1 = 800 Ω dc termination is selected.

0

Reserved

Do not modify.

SF9 (DAA9). DAA Low Level Functions 9 Read Only

Bit

D7

D6

D5

D4

D3

D2

OVL

R

D1

D0

Name

Type

BTD

R/W

ROV

R/W

Reset settings = 0010_0000 (0x20)

Bit

7:4

3

Name

Reserved

BTD

Function

Do not modify.

Billing Tone Detect (sticky).

0 = No billing tone detected.

1 = Billing tone detected.

2

1

OVL

ROV

Receive overload.

Same as ROV, except not sticky.

Receive Overload (sticky).

0 = No excessive level detected.

1 = Excessive input level detected.

0

Reserved

Do not modify.

Rev. 1.0

67

Si2401

SFC (DAAFC). DAA Low Level Functions

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name

Type

CTSM

R/W

Reset settings N/A

Bit

Name

Function

7

CTSM

Clear-to-Send (CTS) Mode.

0 = CTS pin is negated as soon as a start bit is detected and reasserted when the

transmit FIFO is empty.

1 = CTS pin is negated when the FIFO is > 70% full and reasserted when the FIFO is <

30% full.

6:0

Reserved

Read value indeterminate.

68

Rev. 1.0

Si2401

8. Pin Descriptions: Si2401

1

16 GPIO1/EOFR

15 GPIO2/CD

CLKIN/XTALI

XTALO

2

3

14

13

12

11

GPIO3/ESC

GPIO5/RI

V_D

4

5

6

7

8

V_A

GND

RXD

TXD

CTS

GPIO4/INT/AOUT

10 C1A

9

C2A

RESET

Pin #

Pin Name

CLKIN/XTALI XTALI—Crystal Oscillator Pin.

Description

1

These pins provide support for parallel resonant AT cut crystals. XTALI also acts as an

input in the event that an external clock source is used in place of a crystal. A

4.9152 MHz crystal is required or a 4.9152 or 27 MHz clock on XTALI.

2

3

XTALO

XTALO—Crystal Oscillator Pin.

Serves as the output of the crystal amplifier.

GPI05/RI

General Purpose Input/RI.

This pin can be either a GPIO pin (digital in, digital out) or the RI pin. Default is digital

in. When programmed as RI, it indicates the presence of an ON segment of a ring

signal on the telephone line.

4

5

6

7

V

Supply Voltage.

D

Provides the 3.3 V supply voltage to the Si2401.

RXD

TXD

CTS

Receive Data.

Serial communication data from the Si2401.

Transmit Data.

Serial communication data to the Si2401.

Clear to Send.

Clear to send output used by the Si2401 to signal that the device is ready to receive

more digital data on the TXD pin.

8

RESET

Reset Input.

An active low input that is used to reset all control registers to a defined, initialized

state. Also used to bring the Si2401 out of sleep mode.

9

C2A

C1A

Isolation Capacitor 2A.

Connects to one side of the isolation capacitor C2.

10

Isolation Capacitor 1A.

Connects to one side of the isolation capacitor C1.

Rev. 1.0

69

Si2401

Pin #

Pin Name

Description

11

GPIO4/INT/

AOUT

General Purpose Input/INT.

This pin can be either a GPIO pin (digital in, digital out) or the INT pin. Default is digital

in. When programmed as INT, this pin provides five functions. While the modem is

connected, it asserts if the carrier is lost, a wake-on ring (using the “ATZ” command)

event is detected, a loss of loop current event is detected, V.23 reversal is detected, or

if an intrusion event has been detected. The INT pin is sticky and stays asserted until

the host clears it by writing to the correct S register. (See register SE2[7:6].)

12

13

GND

Ground.

Connects to the system digital ground.

V

Regulator Voltage Reference.

A

This pin connects to an external capacitor and serves as the reference for the internal

voltage regulator.

14

GPIO3/ESC

GPIO2/CD

General Purpose Input/Escape.

This pin can be either a GPIO pin (digital in, digital out) or the ESC pin. Default is digi-

tal in. When programmed as ESC, a positive edge on this pin causes the modem to go

from online (connected) mode to the offline (command) mode.

15

16

General Purpose Input/CD.

This pin can be either a GPIO pin (digital in, digital out) or the CD pin. Default is digital

in. When programmed as CD, it is the active low carrier detect pin.

GPIO1/EOFR General Purpose Input/EOFR.

This pin can be either a GPIO pin (digital in, digital out) or the EOFR pin. Default is

digital in. This pin can also be programmed to function as the EOFR (end-of-frame

receive) signal for HDLC framing.

70

Rev. 1.0

Si2401

9. Pin Descriptions: Si3010

1

16

DCT2

QE

DCT

2

3

15 IGND

14 DCT3

RX

IB

13

4

5

6

7

8

QB

QE2

SC

12

11

C1B

C2B

VREG

10 VREG2

RNG2

9

RNG1

Table 23. Si3010 Pin Descriptions

Description

Pin #

Pin Name

1

QE

Transistor Emitter.

Connects to the emitter of Q3.

DC Termination.

2

3

4

5

6

7

8

DCT

RX

Provides dc termination to the telephone network.

Receive Input.

Serves as the receive side input from the telephone network.

Internal Bias 1.

IB

Provides Internal Bias.

Isolation Capacitor 1B.

C1B

Connects to one side of isolation capacitor C1 and communicates with the Si2401.

Isolation Capacitor 2B.

C2B

Connects to one side of isolation capacitor C2 and communicates with the Si2401.

Voltage Regulator.

Connects to an external capacitor to provide bypassing for an internal power supply.

Ring 1.

VREG

RNG1

Connects through a capacitor to the RING lead of the telephone line. Provides the ring

and caller ID signals to the Si2401.

9

RNG2

Ring 2.

Connects through a capacitor to the TIP lead of the telephone line. Provides the ring

and caller ID signals to the Si2401.

10

11

12

13

14

15

16

VREG2

SC

Voltage Regulator 2.

Connects to an external capacitor to provide bypassing for an internal power supply.

Circuit Enable.

Enables transistor network.

Transistor Emitter 2.

QE2

Connects to the emitter of Q4.

Transistor Base.

QB

Connects to the base of transistor Q3. Used to go on- and off-hook.

DC Termination 3.

DCT3

IGND

DCT2

Provides the dc termination to the telephone network.

Isolated Ground.

Connects to ground on the line-side interface.

DC Termination 2.

Provides dc termination to the telephone network.

Rev. 1.0

71

Si2401

10. Ordering Guide

Chipset

Region

Digital

Line

Lead-Free

Temperature

Si2401

Global

Si2401-FS

Si3010-F-FS

Yes

0 to 70 °C

72

Rev. 1.0

Si2401

11. Package Outline: 16-Pin SOIC

Figure 6 illustrates the package details for the Si2401 and Si3010. Table 24 lists the values for the dimensions

shown in the illustration.

16

9

h

bbb B

E

H

-B-

θ

1

8

L

B

aaa C A B

Detail F

-A-

D

C

A

-C-

A1

e

See Detail F

γ

Seating Plane

Figure 6. 16-pin Small Outline Integrated Circuit (SOIC) Package

Table 24. Package Diagram Dimensions

Millimeters

Symbol

Min

1.35

.10

Max

1.75

.25

A

A1

B

.33

.51

C

.19

.25

D

E

9.80

3.80

10.00

4.00

e

1.27 BSC

H

h

5.80

.25

6.20

.50

L

.40

1.27

γ

0.10

θ

0º

8º

aaa

bbb

0.25

Rev. 1.0

73

Si2401

DOCUMENT CHANGE LIST

Revision 0.7 to Revision 0.9

Updated Table 5, “Absolute Maximum Ratings,” on

page 8.

Updated "3. Bill of Materials: Si2401/10 Chipset" on

page 11.

Updated SF3 description in Table 21, “S-Register

Summary,” on page 35.

Updated SE4 description in Register SE4 (CF5).,

“Chip Functions 5,” on page 54.

Updated "8. Pin Descriptions: Si2401" on page 69.

Removed Appendix A and Appendix B. This

information can be found in “AN94: Si2401 Modem

Designer’s Guide”.

Revision 0.9 to Revision 1.0

Updated features list to include lead-free, RoHS

compliant packages.

Updated ring detect voltage values in Table 2 on

page 5.

Updated transmit and receive values in Table 4 on

page 7.

Updated "3. Bill of Materials: Si2401/10 Chipset" on

page 11.

Updated country-specific register settings in

Table 10 on page 15.

Updated reset values in Table 21 on page 35.

Updated default binary values in Table 22 on page

40.

Updated "10. Ordering Guide" on page 72.

Updated "11. Package Outline: 16-Pin SOIC" on

page 73.

74

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Si2401

NOTES:

Rev. 1.0

75

Si2401

CONTACT INFORMATION

Silicon Laboratories Inc.

4635 Boston Lane

Austin, TX 78735

Tel: 1+(512) 416-8500

Fax: 1+(512) 416-9669

Toll Free: 1+(877) 444-3032

Email: productinfo@silabs.com

Internet: www.silabs.com

The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.

Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from

the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features

or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-

resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-

quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to

support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-

sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-

plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.

Silicon Laboratories, Silicon Labs, and ISOmodem are trademarks of Silicon Laboratories Inc.

Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders

76

Rev. 1.0


型号：	SI3010-F-FS
厂家：	SILICON
描述：	V.22BIS ISOMODEM㈢ WITH INTEGRATED GLOBAL DAA 与全球综合DAA的V.22bis ISOMODEM⑩
文件：	总76页 (文件大小：999K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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